Hafnium oxide-based ferroelectric capacitor and manufacturing method thereof

Abstract

The invention relates to a hafnium oxide-based ferroelectric capacitor and a manufacturing method thereof, belongs to the technical field of microelectronics, and solves the problem that a strong wake-up effect is caused by more antiferroelectric tetragonal phases generated due to the fact that a thermal budget is lower than an ideal annealing temperature of the capacitor when an existing storage unit is prepared in a back-end process. The method comprises the following steps of: forming a lower electrode layer above a substrate layer by adopting a first sputtering process, wherein the substrate layer is positioned above a substrate; performing oxidation treatment on the top part of the lower electrode layer by using an oxygen source so as to enable the top part of the lower electrode layer to form an interface layer; forming an HZO dielectric layer above the interface layer by adopting an ALD (Atomic Layer Deposition) process; and forming an upper electrode layer above the HZO dielectric layer by adopting a second sputtering process, and then forming a plurality of upper electrodes on the upper electrode layer by removing redundant metal. The TiN lower electrode is oxidized to generate the TiO2 interface layer, so that the tensile stress effect on the ferroelectric layer in the rapid thermal annealing process can be enhanced, and the annealing temperature of the capacitor is remarkably reduced on the premise that ferroelectric degradation of the capacitor is not caused.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic technology, and in particular to a hafnium oxide-based ferroelectric capacitor and a manufacturing method thereof. Background Art

[0002] Based on doped HfO 2 The new ferroelectric material is expected to be used in the next generation of memory devices, showing significant advantages including high speed, low power consumption and full CMOS compatibility. Since the first report of Si-doped HfO in 2011, 2 Since the ferroelectricity of thin films has been demonstrated, a series of different doping materials have been shown to be able to anneal HfO at appropriate doping concentrations and annealing temperatures. 2 Ferroelectricity is induced in the film.

[0003] It is generally believed that the stress clamping effect of the upper and lower electrodes on the ferroelectric dielectric layer during the rapid thermal annealing process of the capacitor is the key factor in inducing ferroelectricity in the film. 2 The annealing temperature required by different materials is also different. Usually the best annealing temperature is around 500-1000℃. 2 When ferroelectric capacitors are used as memory, CMOS back-end processes are usually used to integrate capacitors based on logic devices prepared in the front-end process, ultimately forming a storage unit structure such as "one transistor one capacitor" (1T1C). In order to ensure the reliability and yield of the logic devices prepared in the front-end process, the thermal budget of the back-end process is usually limited to below 400°C, which is lower than that of all existing doping types of HfO 2 The optimal annealing temperature required for HfO-based ferroelectric capacitors. 2 In order to ensure the compatibility of ferroelectric capacitors in the back-end CMOS process while ensuring the storage performance and reliability of the capacitors themselves, it is necessary to optimize and reduce the annealing temperature of the capacitors. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a hafnium oxide-based ferroelectric capacitor and a method for manufacturing the same, so as to solve the problem that when the existing memory cell is prepared using a back-end process, the thermal budget is lower than the ideal annealing temperature of the capacitor, thereby generating more antiferroelectric tetragonal phases and ultimately leading to a strong wake-up effect.

[0005] On the one hand, an embodiment of the present invention provides a method for manufacturing a hafnium oxide-based ferroelectric capacitor, comprising: forming a lower electrode layer above a substrate layer using a first sputtering process, wherein the substrate layer is located above a substrate; oxidizing the top portion of the lower electrode layer using an oxygen source to form the top portion of the lower electrode layer into an interface layer; forming a HZO dielectric layer above the interface layer using a deposition process; and forming an upper electrode layer above the HZO dielectric layer using a second sputtering process, and then forming the upper electrode layer into multiple upper electrodes by removing excess metal.

[0006] The beneficial effects of the above technical solution are as follows: TiO is produced by oxidizing the TiN lower electrode 2 The interface layer enhances the tensile stress on the ferroelectric layer during rapid thermal annealing, and can significantly reduce the annealing temperature of the capacitor without causing degradation of the ferroelectricity of the capacitor.

[0007] Based on a further improvement of the above method, the material of the lower electrode layer is TiN, wherein the top portion of the lower electrode layer is oxidized using an oxygen source to form the top portion of the lower electrode layer as an interface layer further comprises: placing the substrate on which the lower electrode layer is formed in an atomic layer deposition ALD chamber; and setting the temperature of the atomic layer deposition ALD chamber to 250-300° C. and providing O from above the substrate. 3 As an oxygen source, the top portion of the lower electrode layer is oxidized to form TiO within an oxidation time of 15-30 min. 2 Interface layer.

[0008] Based on the further improvement of the above method, when the oxidation time is greater than or equal to 20 min, the TiO 2 The thickness of the interfacial layer increases, where the thickness of TiO 2 The interface layer performs voltage division to reduce the operating voltage applied to the HZO dielectric layer so as to reduce the polarization strength of the capacitor.

[0009] Based on the further improvement of the above method, the first sputtering process and the second sputtering process are the same ion beam sputtering process, DC sputtering process or reactive sputtering process, wherein the sputtering process range of the first sputtering process and the second sputtering process is: TiN target, beam voltage of 700-900V, beam current of 40-60mA, acceleration voltage of 150-170V, gas of Ar / N 2 The mixed gas has a flow rate of 7~9sccm / 4~6sccm respectively.

[0010] Based on the further improvement of the above method, before forming the lower electrode layer above the substrate layer using the first sputtering process, it also includes: soaking and cleaning the substrate with acetone and anhydrous ethanol in sequence, and then blowing the substrate dry; soaking and rinsing the substrate with deionized water again, and blowing the substrate dry.

[0011] Based on the further improvement of the above method, forming the HZO dielectric layer above the interface layer by a deposition process further comprises: under the condition of a deposition temperature of 250-300° C., periodically growing ZrO above the interface layer by an atomic layer deposition ALD process in the atomic layer deposition ALD chamber; 2 Layer and HfO 2 layer and the last layer is HfO 2 layer, wherein the precursor of Zr and the precursor of Hf are heated to 100-140°C to form O 3 Keep room temperature and select carrier gas N 2 and setting the gas flow rate to 40-80 sccm to generate the ZrO 2 layer and the HfO 2 The precursor of Zr is tetrakis(ethylmethylamino)zirconium(IV) and the precursor of Hf is tetrakis(ethylmethylamino)hafnium(IV).

[0012] Based on the further improvement of the above method, after forming the HZO dielectric layer and before forming the upper electrode layer, it also includes: coating a negative resist on the HZO dielectric layer, and then pre-baking for 2 minutes at 150°C; exposing the negative resist, and then post-baking for 2 minutes at 120°C; soaking the negative resist in a developer for 40-50 seconds, and then developing the negative resist; and rinsing and drying the HZO dielectric layer with deionized water.

[0013] Based on the further improvement of the above method, the upper electrode layer is formed into a plurality of upper electrodes by removing the excess metal, further comprising: coating a photoresist on the upper electrode layer and exposing and developing the photoresist; etching the upper electrode layer with the developed photoresist to form the upper electrode layer into a plurality of upper electrodes, wherein a capacitor array is formed on the substrate; and after removing the remaining photoresist, annealing at a temperature of 300-400°C and an annealing atmosphere of N 2 The capacitor array is annealed for 30-60 seconds under the conditions of.

[0014] On the other hand, an embodiment of the present invention provides a hafnium oxide-based ferroelectric capacitor, comprising: a substrate layer located above a substrate; a lower electrode layer located above the substrate layer; and an interface layer located above a portion of the lower electrode layer, wherein the material of the interface layer is TiO formed by oxidizing the top portion of the lower electrode layer. 2 ; a HZO dielectric layer located above the interface layer; and a plurality of upper electrodes located above the HZO dielectric layer and formed into an upper electrode array, wherein the material of the lower electrode layer and the upper electrode is TiN.

[0015] Based on the further improvement of the above device, the thickness of the interface layer is 1-2nm; the thickness of the HZO dielectric layer is 6-8nm; the thickness of the lower electrode layer and the upper electrode is 10-60nm, wherein the TiO 2 The thermal expansion coefficient of TiN is smaller than that of TiN.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0017] 1. Produce TiO by oxidizing the TiN lower electrode 2 The interface layer enhances the tensile stress on the ferroelectric layer during rapid thermal annealing, which can significantly reduce the required annealing temperature without causing ferroelectric degradation of the capacitor;

[0018] 2. Before using atomic layer deposition (ALD) to prepare ferroelectric materials, an oxygen source (O 3 ) to oxidize the TiN lower electrode to form a uniform and stable TiO 2 Interface layer. After an appropriate period of oxidation treatment, the resulting interface layer will provide sufficiently strong tensile stress to the ferroelectric layer during the subsequent rapid thermal annealing process, thereby significantly reducing the required annealing temperature;

[0019] 3. After the TiN lower electrode is oxidized for an appropriate period of time, the resulting interface layer will provide a sufficiently strong tensile stress to the ferroelectric layer during the subsequent rapid thermal annealing process, so that the capacitor can produce a large amount of ferroelectric orthorhombic phase even after the ferroelectric layer thickness is reduced, and suppress the antiferroelectric tetragonal phase that should have been generated. Ultimately, the strong wake-up effect of the device caused by the film thickness reduction is eliminated, and the device has a large residual polarization strength in the initial state, while retaining the advantage of the device's reduced operating voltage when the film thickness is reduced.

[0020] 4. Under the premise that the coercive electric field strength required for the polarization reversal of the ferroelectric is a fixed value, the reduced thickness of the ferroelectric layer can reduce the operating voltage of the device and effectively reduce the write power consumption of the memory; the reminder-free feature of the device enables it to have a larger storage window at the initial stage, increasing the signal recognition margin of the storage chip during large-scale integration of the capacitor.

[0021] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be achieved and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0023] Figure 1 is a flow chart of a method for manufacturing a hafnium oxide-based ferroelectric capacitor according to an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of a capacitor structure according to an embodiment of the present invention;

[0025] Figure 3 PE hysteresis curve diagram of the capacitor at different annealing temperatures after oxygen treatment for 20 minutes according to an embodiment of the present invention;

[0026] Figure 4 It is a PE hysteresis curve diagram when the thickness of the HZO dielectric layer in the existing capacitor that has not been oxidized (that is, no interface layer is formed) is reduced (that is, from 10nm to 8nm);

[0027] Figure 5 is a PE hysteresis curve diagram of different oxidation treatment times according to an embodiment of the present invention;

[0028] Figure 6 PE hysteresis curves at different operating voltages after 20 minutes of oxygen treatment according to an embodiment of the present invention;

[0029] Figure 7 A partial cross-sectional view of a 1T1C ferroelectric memory chip according to an embodiment of the present invention;

[0030] Figure 8 1 is the chip yield of the ferroelectric capacitor on the wafer according to the embodiment of the present invention annealed at 500° C. and 350° C. respectively. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0032] refer to Figure 1 A specific embodiment of the present invention discloses a method for manufacturing a hafnium oxide-based ferroelectric capacitor, comprising: in step S101, forming a lower electrode layer above a substrate layer by a first sputtering process, wherein the substrate layer is located above a substrate; in step S102, oxidizing a top portion of the lower electrode layer using an oxygen source to form the top portion of the lower electrode layer into an interface layer; in step S103, forming a HZO dielectric layer above the interface layer by a deposition process; and in step S104, forming an upper electrode layer above the HZO dielectric layer by a second sputtering process, and then forming the upper electrode layer into a plurality of upper electrodes by removing excess metal.

[0033] Compared with the prior art, in the method for manufacturing the hafnium oxide-based ferroelectric capacitor provided in this embodiment, the TiO 2 The interface layer enhances the tensile stress on the ferroelectric layer during rapid thermal annealing, and can significantly reduce the annealing temperature of the capacitor without causing degradation of the ferroelectricity of the capacitor.

[0034] In the following, reference Figure 1 and Figure 2 , each step of the method for manufacturing a hafnium oxide-based ferroelectric capacitor according to an embodiment of the present invention is described in detail.

[0035] Before forming the lower electrode layer on the substrate layer by the first sputtering process, the substrate is soaked and cleaned by acetone and anhydrous ethanol in sequence, and then the substrate is blown dry; and the substrate is soaked and rinsed by deionized water again, and the substrate is blown dry.

[0036] In step S101, a lower electrode layer is formed on the substrate layer by a first sputtering process, wherein the substrate layer is located above the substrate. The first sputtering process and the second sputtering process are the same ion beam sputtering process, DC sputtering process or reactive sputtering process, wherein the sputtering process ranges of the first sputtering process and the second sputtering process are: TiN target, beam voltage of 700-900V, beam current of 40-60mA, acceleration voltage of 150-170V, gas of Ar / N 2 The mixed gas has a flow rate of 7~9sccm / 4~6sccm respectively.

[0037] In step S102, an oxygen source is used to perform an oxidation treatment on the top portion of the lower electrode layer to form the top portion of the lower electrode layer into an interface layer. The material of the lower electrode layer is TiN.

[0038] The method further comprises: placing the substrate on which the lower electrode layer is formed in an atomic layer deposition (ALD) chamber; and setting the temperature of the atomic layer deposition (ALD) chamber to 250-300° C. and providing O from above the substrate. 3 As an oxygen source, the top portion of the lower electrode layer was oxidized to form TiO within an oxidation time of 15-30 min. 2 The interface layer, i.e., the lower electrode layer, includes two parts, the bottom part is formed as the lower electrode and the top part is formed as the interface layer. The TiO 2 The thickness of the interface layer, that is, the thickness of TiO 2 The thickness of the interface layer increases accordingly. Specifically, when the oxidation time is greater than or equal to 20 min, TiO 2 The thickness of the interfacial layer increases, where the thickness of TiO 2 The interface layer performs voltage division, reducing the operating voltage applied to the HZO dielectric layer to reduce the polarization strength of the capacitor.

[0039] In step S103, a HZO dielectric layer is formed on the interface layer by a deposition process. Specifically, forming the HZO dielectric layer on the interface layer by a deposition process further includes: periodically growing ZrO on the interface layer by an atomic layer deposition ALD process in an atomic layer deposition ALD chamber at a deposition temperature of 250-300°C. 2 Layer and HfO 2 layer and the last layer is HfO 2 layer, wherein the precursor of Zr and the precursor of Hf are heated to 100-140°C to form O 3 Keep room temperature and select carrier gas N 2 And set the gas flow rate to 40-80sccm to generate ZrO 2 Layer and HfO 2 layer, the precursor of Zr is tetrakis(ethylmethylamino)zirconium(IV) and the precursor of Hf is tetrakis(ethylmethylamino)hafnium(IV).

[0040] Specifically, after forming the HZO dielectric layer and before forming the upper electrode layer, the process further includes: coating a negative photoresist on the HZO dielectric layer, and then pre-baking at 150°C for 2 minutes; exposing the negative photoresist, and then post-baking at 120°C for 2 minutes; soaking the negative photoresist in a developer for 40-50 seconds, preferably, soaking for 45 seconds, and then developing the negative photoresist; and rinsing and drying the HZO dielectric layer with deionized water. The thickness of the HZO dielectric layer can be reduced to less than 8nm, for example, 6-8nm, the annealing temperature can be reduced to 300°C, and the polarization intensity P r No degradation.

[0041] Optionally, for the oxidation process of the TiN lower electrode, the thickness of the ferroelectric layer (i.e., the thickness of the HZO dielectric layer) can be reduced to less than 8nm, and the polarization intensity of the capacitor tends to saturation at an operating voltage of 2V, and its initial residual polarization intensity 2P r >27μC / cm 2 , and there is almost no awakening effect.

[0042] In step S104, a second sputtering process is used to form an upper electrode layer on the HZO dielectric layer, and then the upper electrode layer is formed into a plurality of upper electrodes by removing excess metal.

[0043] The first sputtering process is the same as or different from the second sputtering process. The sputtering process includes an ion beam sputtering process, a DC sputtering process or a reactive sputtering process. The sputtering process range of the second sputtering process is: TiN target, beam voltage of 700-900V, beam current of 40-60mA, acceleration voltage of 150-170V, gas of Ar / N 2 The mixed gas has a flow rate of 7~9sccm / 4~6sccm respectively.

[0044] Specifically, the upper electrode layer is formed into a plurality of upper electrodes by removing excess metal, further comprising: coating a photoresist on the upper electrode layer and exposing and developing the photoresist; etching the upper electrode layer using the developed photoresist to form the upper electrode layer into a plurality of upper electrodes, wherein a capacitor array is formed on the substrate; and after removing the remaining photoresist, annealing at a temperature of 300-400° C. and an annealing atmosphere of N 2 The capacitor array is annealed for 30-60 seconds under the condition of . The capacitors in the capacitor array correspond to the transistors under the capacitors. Figure 7 The 1T1C ferroelectric memory chip includes a plurality of 1T1C memory cells, each of which includes a capacitor and a corresponding transistor located below the capacitor, and the capacitor in a 1T1C memory cell is connected to the transistor via a metal layer M1-M4 between the capacitor and the transistor.

[0045] refer to Figure 2 Another specific embodiment of the present invention discloses a hafnium oxide-based ferroelectric capacitor comprising: a substrate, a substrate layer (1), a lower electrode layer (2), an interface layer (3), a HZO dielectric layer (4) and a plurality of upper electrodes (5).

[0046] The substrate layer (1) is located above the substrate. The material of the substrate is Si, and the material of the substrate layer (1) is SiO 2 .

[0047] The lower electrode layer (2) is located above the substrate layer (1). The thickness of the lower electrode layer (2) is 10-60 nm and the material of the lower electrode layer (2) is TiN.

[0048] The interface layer (3) is located above a portion of the lower electrode layer (2). The material of the interface layer (3) is TiO formed by oxidizing the top portion of the lower electrode layer (2). 2 The thickness of the interface layer is 1-2nm. TiO 2 The thermal expansion coefficient (about 5×10 -6 / ℃) is smaller than the thermal expansion coefficient of TiN (the thermal expansion coefficient is about 9.4×10 -6 / ℃).

[0049] The HZO dielectric layer (4) is located above the interface layer (3). The molar composition ratio of Hf and Zr is close to 1:1, with the maximum residual polarization intensity. In addition, other composition ratios close to this value are also possible. The thickness of the HZO dielectric layer is 8-15nm, preferably, the thickness of the HZO dielectric layer is reduced to less than 8nm, for example, 6-8nm.

[0050] A plurality of upper electrodes (5) are located above the HZO dielectric layer (4) and form an upper electrode array. The material of the lower electrode layer and the upper electrode is TiN. The thickness of the upper electrode is 10-60 nm.

[0051] In the following, reference Figures 2 to 8 , a method for manufacturing a hafnium oxide-based ferroelectric capacitor according to an embodiment of the present invention is described in detail by way of a specific example.

[0052] In the first embodiment of the present invention, it is generally believed that selecting an electrode material with a smaller thermal expansion coefficient can produce a stronger tensile stress effect during annealing, thereby enhancing the generation of the ferroelectric orthorhombic phase. 2 TiN ferroelectric material (thermal expansion coefficient is about 9.4×10 -6 / ℃), TiO 2 Has a smaller thermal expansion coefficient (about 5×10 -6 / ℃), therefore, before using atomic layer deposition (ALD) to prepare ferroelectric materials, the present application first uses an oxygen source (O3 ) to oxidize the TiN lower electrode to form a uniform and stable TiO 2 Interface layer. After an appropriate oxidation treatment period, the resulting interface layer will provide a sufficiently strong tensile stress to the ferroelectric layer during the subsequent rapid thermal annealing process, thereby significantly reducing the required annealing temperature.

[0053] HfO according to an embodiment of the present invention 2 The preparation method of the ferroelectric capacitor can effectively reduce the annealing temperature required for capacitor preparation. 3 The TiN bottom electrode of the ferroelectric capacitor is oxidized to form a uniform TiO 2 The interface layer, taking advantage of its much smaller thermal expansion coefficient than TiN, can generate sufficiently large tensile stress on the ferroelectric film during rapid thermal annealing, thereby promoting the generation of ferroelectric orthorhombic phase. Based on the stress effect enhanced by oxidation treatment, the device can induce a sufficient number of ferroelectric orthorhombic phases at a lower annealing temperature, and its annealing temperature can be reduced to about 300°C without causing ferroelectric degradation. Lowering the annealing temperature is first beneficial to improving the reliability of the device: high-temperature annealing will significantly increase the leakage current of the device, causing the device to fail after fewer read-write cycles, that is, the durability of the device is degraded; secondly, the thermal budget limit of the CMOS back-end process is usually around 400°C, which is lower than the existing types of HfO 2 The optimal annealing temperature of the HfO-based ferroelectric capacitor is, therefore, the process scheme proposed in the present invention for reducing the annealing temperature can effectively improve the HfO 2 Process compatibility of ferroelectric capacitors in large-scale device integration.

[0054] refer to Figure 2 , HfO 2 The ferroelectric capacitor comprises, from bottom to top, a substrate layer (1), a lower electrode (2), an interface layer (3), a dielectric layer (4) and an upper electrode (5); the comparative example does not contain the interface layer (3); and from bottom to top, the ferroelectric capacitor comprises, from bottom to top, a substrate layer (1), a lower electrode (2), a dielectric layer (4) and an upper electrode (5).

[0055] Through the oxidation treatment process proposed in the present invention, the annealing temperature of the capacitor can be reduced to about 300° C. without causing almost no ferroelectric degradation. Specifically, the above preparation method comprises the following steps:

[0056] Step 1: providing a Si substrate, on which a SiO 2 The substrate layer is cleaned and the substrate layer 1 is cleaned. The substrate is sequentially soaked, cleaned and blown dry with acetone and anhydrous ethanol; then soaked, rinsed and blown dry with deionized water.

[0057] Step 2, sputtering the cleaned substrate layer to prepare the lower electrode. On the substrate layer 1, the lower electrode 2 is sputtered using an ion beam sputtering process. Sputtering processes include but are not limited to ion beam sputtering, DC sputtering, reactive sputtering, etc. Exemplarily, an ion beam sputtering process is used: TiN target, beam voltage 700-900V, beam current 40-60mA, acceleration voltage 150-170V, gas is Ar / N2 mixed gas, and the flow rates are (7-9sccm) / (4-6sccm) respectively. Within this process range, a better film contrast can be obtained, which is conducive to the generation of ferroelectricity.

[0058] In addition to the sputtering process, other thin film deposition processes are also applicable to this step, including but not limited to atomic layer deposition (ALD), electron beam evaporation, etc. The applicable premise is the appropriate Ti / N ratio to ensure the conductivity of the electrode and the integrity of the electrode / dielectric interface, as well as the flatness of the electrode film (especially the lower electrode).

[0059] Step 3: Oxidize the lower electrode to produce TiO 2 The HZO dielectric layer was prepared by ALD process, and an oxygen source (O 3 ) The lower electrode 2 is subjected to oxidation treatment.

[0060] For example, the chamber temperature during oxidation is usually in the range of 250-300°C, and the oxidation time is 15-30 minutes. To ensure the best oxidation effect, that is, to produce a uniform and stable interface layer 3 to provide sufficient tensile stress, the oxidation treatment time is at least 20 minutes; while oxidation for too long will produce an overly thick interface layer 3, which will reduce the voltage applied to the HZO dielectric layer to a certain extent and reduce the polarization strength of the device due to its voltage divider effect during the electrical operation of the device.

[0061] Step 4: Deposit a HZO dielectric layer on the interface layer. The HZO dielectric layer 4 is prepared by ALD process. During deposition, a layer of ZrO is first grown. 2 , and then grow a layer of HfO 2 , cycle in sequence, the last layer of ZrO 2 For example, the precursor of Zr is tetrakis(ethylmethylamido)zirconium(IV) (TEMAZ), with the chemical formula Zr(NCH 3 CH 5 ) 4 The precursor of Hf is tetrakis(ethylmethylamido)hafnium(IV) (TEMAH), with the chemical formula Hf(NCH 3 C2 H 5 ) 4 . Using O 3 As an oxygen source. For example, the deposition temperature of HZO is 250-300°C, the precursors of Zr and Hf are heated to 100-140°C, and O 3 Keep room temperature and select N as carrier gas 2 , gas flow rate 40 ~ 80sccm. Hf and Zr precursors have other different options.

[0062] Step 5: Apply photoresist, expose and develop. Specifically, apply negative photoresist on the HZO dielectric layer 4, pre-bake at 150°C for 2 minutes, post-bake at 120°C for 2 minutes after exposure, soak in developer for 40-50 seconds for development, rinse with deionized water and blow dry. In addition, positive photoresist can also be used, and the hardening and exposure operations need to be adjusted accordingly.

[0063] Step 6: Prepare an upper electrode layer, and the specific operation is the same as step 2. Sputtering is performed on the dielectric layer after the above treatment to prepare an upper electrode layer.

[0064] Step 7: stripping, removing the photoresist and excess metal to form the upper electrode layer into the upper electrode 5. Apply photoresist on the dielectric layer, expose and develop, remove the photoresist and excess metal, and then anneal.

[0065] Step 8: Annealing. For example, annealing temperature of 300-600°C can induce ferroelectricity, but the thermal budget of the back-end process is usually limited to below 400°C, so the annealing temperature is set to 300-400°C, the annealing time is 30-60s, and the annealing atmosphere is N 2 .

[0066] Figure 3 The PE hysteresis curves of the capacitor at different annealing temperatures (300°C, 400°C and 500°C) after the lower electrode was oxidized for 20 minutes according to an embodiment of the present invention are compared. The results show that the annealing temperature of the capacitor after oxygen treatment can be reduced to 300°C without causing a decrease in the residual polarization intensity.

[0067] Figure 4 For existing capacitors that have not undergone oxidation treatment (i.e., capacitors without forming an interface layer), when the thickness of the ferroelectric dielectric layer is miniaturized from 10nm to 8nm, the capacitor changes from standard ferroelectric properties to obvious antiferroelectric properties in the initial state, resulting in a sharp decrease in the residual polarization intensity and a corresponding decrease in the storage window of the device.

[0068] Figure 5This is a PE hysteresis curve diagram after different lower electrode oxidation treatment times (5min, 10min, 20min and 30min) according to an embodiment of the present invention. The results show that an oxidation time of about 20min is required to achieve the best optimization effect. Too long oxidation time will also lead to degradation of the residual polarization strength of the device.

[0069] Figure 6 PE hysteresis curves at different operating voltages after 20 minutes of oxygen treatment according to an embodiment of the present invention. Specifically, the PE hysteresis curves at different operating voltages (1.6V, 2V, 2.4V, 2.8V and 3.2V) after the lower electrode was oxidized for 20 minutes, and the results showed that the polarization intensity had tended to saturation at an operating voltage of 2V, indicating that after the lower electrode oxidation treatment, a capacitor with an initial large residual polarization intensity without a wake-up effect can be obtained under the condition of shrinking the film thickness of the dielectric layer and reducing the annealing temperature, that is, the purpose of low-temperature annealing and reducing the operating voltage of the capacitor can be achieved without affecting the performance of the device.

[0070] Figure 8 : is the chip yield of the ferroelectric capacitor on the wafer according to the embodiment of the present invention annealed at 500°C and 350°C respectively. Figure 8 It can be seen that when the annealing temperature is 500° C., there are a number of ferroelectric capacitors that fail annealing. However, when the annealing temperature is 350° C., all the ferroelectric capacitors after annealing pass, and there is no ferroelectric capacitor that fails annealing.

[0071] In the second example, by adopting this oxidation process, a sufficient number of ferroelectric orthorhombic phases can be produced at a thinner ferroelectric layer thickness, and the antiferroelectric tetragonal phase that should be produced in the ferroelectric film when the film thickness is reduced can be suppressed, so that the capacitor has a larger residual polarization strength in the initial state, avoiding the strong wake-up effect caused by the presence of more antiferroelectric tetragonal phases in the original device. Under the premise that the coercive electric field strength required for the polarization reversal of the ferroelectric body is a fixed value, the reduced ferroelectric layer thickness can reduce the operating voltage of the device and effectively reduce the write power consumption of the memory; the device's wake-up-free feature enables it to have a larger storage window at the initial stage, increasing the signal recognition margin of the storage chip when the capacitor is integrated on a large scale.

[0072] Through the oxidation treatment process proposed in the present invention, the thickness of the ferroelectric layer can be reduced to less than 8nm, and the polarization intensity of the capacitor tends to saturation at an operating voltage of 2V, and its initial residual polarization intensity 2P r >27μC / cm 2 , and there is almost no awakening effect.

[0073] The preparation method of the comparative example not including the interface layer (3) comprises the following steps:

[0074] Step 1, providing a substrate and cleaning the substrate 1: soaking, cleaning and drying the substrate in acetone and anhydrous ethanol in sequence; then soaking, rinsing and drying the substrate in deionized water.

[0075] Step 2, prepare the lower electrode by sputtering on the cleaned substrate. On the substrate 1, prepare the lower electrode 2 by sputtering using an ion beam sputtering process. Sputtering processes include but are not limited to ion beam sputtering, DC sputtering, reactive sputtering, etc. Exemplarily, an ion beam sputtering process is used: TiN target, beam voltage 700-900V, beam current 40-60mA, acceleration voltage 150-170V, gas is Ar / N2 mixed gas, and the flow rates are (7-9sccm) / (4-6sccm) respectively. Within this process range, a better film contrast can be obtained, which is conducive to the generation of ferroelectricity.

[0076] In addition to the sputtering process, other thin film deposition processes are also applicable to this step, including but not limited to atomic layer deposition (ALD), electron beam evaporation, etc. The applicable premise is the appropriate Ti / N ratio to ensure the conductivity of the electrode and the integrity of the electrode / dielectric interface, as well as the flatness of the electrode film (especially the lower electrode).

[0077] Step 3: Deposit a HZO dielectric layer on the interface layer. For the embodiment (comparative example), the HZO dielectric layer 4 (3) is prepared by ALD process. During the deposition, a layer of ZrO is first grown. 2 , and then grow a layer of HfO 2 , cycle in sequence, the last layer of ZrO 2 For example, the precursor of Zr is tetrakis(ethylmethylamino)zirconium(IV) with the chemical formula Zr(NCH 3 CH 5 ) 4 (Tetrakis(ethylmethylamido)zirconium(IV),TEMAZ); the precursor of Hf is tetrakis(ethylmethylamido)hafnium(IV) with the chemical formula of Hf(NCH 3 C 2 H 5 ) 4 (Tetrakis(ethylmethylamido)hafnium(IV),TEMAH). Adopt O 3 As an oxygen source. For example, the deposition temperature of HZO is 250-300°C, the precursors of Zr and Hf are heated to 100-140°C, and O 3 Keep room temperature and select N as carrier gas 2 , gas flow rate 40 ~ 80sccm. Hf and Zr precursors have other different options.

[0078] For the embodiment, the thickness of the dielectric layer 4 is 8 nm; for the comparative example 1, the thickness of the dielectric layer 3 is 10 nm; for the comparative example 2, the thickness of the dielectric layer 3 is 8 nm.

[0079] Step 4, apply photoresist, expose and develop. Specifically, apply photoresist on the dielectric layer, expose and develop. Specifically: apply negative resist on the HZO dielectric layer 4 (implementation) / dielectric layer 3 (comparative example), pre-bake at 150°C for 2 minutes, post-bake at 120°C for 2 minutes after exposure, soak in developer for 45 seconds for development, rinse with deionized water and blow dry. In addition, positive resist can also be used as photoresist, and the hardening and exposure operations need to be adjusted accordingly.

[0080] Step six, preparing an upper electrode layer by sputtering on the dielectric layer after the above treatment.

[0081] Step 7: stripping, removing the photoresist and excess metal to obtain the upper electrode 5. After removing the photoresist and excess metal, annealing is performed.

[0082] Step 8: Annealing. For example, the annealing temperature is 300-400°C, the annealing time is 30-60s, and the annealing atmosphere is N 2 .

[0083] The HfO prepared by the comparative example 2 Compared with the ferroelectric capacitor, the HfO 2 The base ferroelectric capacitor and its preparation method provide a sufficiently strong tensile stress to the ferroelectric layer in the subsequent rapid thermal annealing process, which can significantly reduce the required annealing temperature. The interface layer 3 will reduce the voltage applied to the HZO dielectric layer to a certain extent and reduce the polarization strength of the device due to its voltage-dividing effect during the electrical operation of the device.

[0084] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0085] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for manufacturing a hafnium oxide-based ferroelectric capacitor, It is characterized in that include: forming a lower electrode layer on the substrate layer by a first sputtering process, wherein the substrate layer is located above the substrate; performing an oxidation treatment on a top portion of the lower electrode layer using an oxygen source to form the top portion of the lower electrode layer as an interface layer; forming a HZO dielectric layer on the interface layer by a deposition process; and An upper electrode layer is formed on the HZO dielectric layer by a second sputtering process, and then the upper electrode layer is formed into a plurality of upper electrodes by removing excess metal.

2. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 1, It is characterized in that The material of the lower electrode layer is TiN, wherein the top portion of the lower electrode layer is oxidized using an oxygen source to form the top portion of the lower electrode layer as an interface layer further comprises: placing the substrate on which the lower electrode layer is formed in an atomic layer deposition (ALD) chamber; and The temperature of the atomic layer deposition (ALD) chamber was set to 250-300°C and O was supplied from above the substrate. 3 As an oxygen source, the top portion of the lower electrode layer is oxidized to form TiO within an oxidation time of 15-30 min. 2 Interface layer.

3. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 2, It is characterized in that When the oxidation time is greater than or equal to 20 min, the TiO 2 The thickness of the interfacial layer increases, where the thickness of TiO 2 The interface layer performs voltage division to reduce the operating voltage applied to the HZO dielectric layer so as to reduce the polarization strength of the capacitor.

4. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 1, It is characterized in that The first sputtering process and the second sputtering process are the same ion beam sputtering process, DC sputtering process or reactive sputtering process, wherein the sputtering process ranges of the first sputtering process and the second sputtering process are: TiN target, beam voltage of 700-900V, beam current of 40-60mA, acceleration voltage of 150-170V, gas of Ar / N 2 The mixed gas has a flow rate of 7~9sccm / 4~6sccm respectively.

5. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 1, It is characterized in that Before forming a lower electrode layer on the substrate layer by a first sputtering process, the method further includes: Sequentially soaking and cleaning the substrate with acetone and anhydrous ethanol, and then drying the substrate; The substrate is again immersed and rinsed with deionized water, and then blown dry.

6. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 2, It is characterized in that Forming a HZO dielectric layer above the interface layer using a deposition process further includes: Under the condition of a deposition temperature of 250-300° C., ZrO is periodically grown on the interface layer by an atomic layer deposition (ALD) process in the atomic layer deposition (ALD) chamber. 2 Layer and HfO 2 layer and the last layer is HfO 2 layer, wherein the precursor of Zr and the precursor of Hf are heated to 100-140°C to form O 3 Keep room temperature and select carrier gas N 2 and setting the gas flow rate to 40-80 sccm to generate the ZrO 2 layer and the HfO 2 The precursor of Zr is tetrakis(ethylmethylamino)zirconium(IV) and the precursor of Hf is tetrakis(ethylmethylamino)hafnium(IV).

7. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 2, It is characterized in that After forming the HZO dielectric layer and before forming the upper electrode layer, the method further includes: Coating a negative resist on the HZO dielectric layer, and then pre-baking at 150° C. for 2 minutes; The negative photoresist is exposed to light and then post-baked at 120° C. for 2 minutes; Soaking the negative photoresist in a developer for 40-50 seconds to develop the negative photoresist; and The HZO dielectric layer is rinsed with deionized water and blown dry.

8. The method for manufacturing a hafnium oxide-based ferroelectric capacitor according to claim 1, It is characterized in that Forming the upper electrode layer into a plurality of upper electrodes by removing excess metal further comprises: Coating a photoresist on the upper electrode layer and exposing and developing the photoresist; etching the upper electrode layer using the developed photoresist to form the upper electrode layer into a plurality of upper electrodes, wherein a capacitor array is formed above the substrate; and After removing the remaining photoresist, the annealing temperature is 300-400℃ and the annealing atmosphere is N 2 The capacitor array is annealed for 30-60 seconds under the conditions of.

9. A hafnium oxide-based ferroelectric capacitor, It is characterized in that include: a substrate layer, located above the substrate; A lower electrode layer, located above the substrate layer; An interface layer is located above a portion of the lower electrode layer, wherein the material of the interface layer is TiO formed by oxidizing the top portion of the lower electrode layer. 2 ; A HZO dielectric layer located above the interface layer; and Multiple upper electrodes are located above the HZO dielectric layer and formed as an upper electrode array. Among them, the materials of the lower electrode layer and the upper electrodes are TiN.

10. The hafnium oxide-based ferroelectric capacitor according to claim 9, characterized in that the thickness of the interface layer is 1 - 2 nm; the thickness of the HZO dielectric layer is 6 - 8 nm; The thickness of the lower electrode layer and the upper electrode is 10-60 nm, wherein the TiO 2 The thermal expansion coefficient of TiN is smaller than that of TiN.

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