Magnetoresistive random access memory
By designing a magnetoresistive random access memory including two transistors and two magnetic tunneling junction structures, the problem of excessive size and excessive thickness of the device in the prior art is solved, and a higher data storage amount and thinner device are achieved.
Patent Information
- Application Number
- CN202311666825.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-27
- Filing Date
- 2023-12-06
- Publication Date
- 2025-05-27
AI Technical Summary
The existing magnetoresistive random access memory devices have large transistor sizes, which lead to excessive size and thickness, which cannot meet the miniaturization needs.
A magnetoresistive random access memory including two transistors and two magnetic tunneling junction structures is designed, and a magnetic tunneling junction structure with a shared source layer and a stacked magnetic tunneling junction structure is achieved, thereby achieving a higher data storage amount and a smaller thickness.
Without increasing the layout area, the data storage amount is increased, and by sharing the source layer and optimizing the transistor structure, the thinning of the memory device and the data retention capability are improved.
Smart Images
Figure CN120050942A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a magnetoresistive random access memory (MRAM), and more particularly to a magnetoresistive random access memory including a structure of two transistors and two magnetic tunnel junctions (MTJs). Background Art
[0002] Many modern electronic components include non-volatile memory. Non-volatile memory is an electronic memory capable of storing data when power is off. Magnetoresistive random access memory is a non-volatile memory that stores information according to the direction of magnetic moments in a magnetic film layer.
[0003] For a magnetoresistive random access memory including a structure of one transistor and one magnetic tunnel junction, the magnetic tunnel junction structure is usually disposed above the transistor and electrically connected to the transistor. However, in order for the magnetoresistive random access memory to have sufficient data retention ability, thermal stability, and switching current, a transistor with a relatively large size needs to be provided. In this way, a magnetoresistive random access memory device including multiple magnetoresistive random access memories will inevitably have a relatively large size and cannot meet the requirement of device miniaturization.
[0004] In addition, even though three-dimensional (3D) magnetoresistive random access memory devices have been developed in the current technology, although multiple magnetoresistive random access memories can be stacked on a substrate, since the transistor still requires a certain size, the problems of overly large size and overly thick thickness of the magnetoresistive random access memory device still cannot be effectively solved. Summary of the Invention
[0005] The present invention provides a magnetoresistive random access memory, which includes two transistors and two magnetic tunnel junction structures.
[0006] The magnetoresistive random access memory of the present invention includes a first magnetic tunneling junction structure, a first drain layer, a first channel layer, a source layer, a second channel layer, a second drain layer, a second magnetic tunneling junction structure, a word line structure, a first bit line structure, a second bit line structure, and a source line structure. The first magnetic tunneling junction structure is disposed on a substrate and includes a first pinned layer, a first tunneling barrier layer, and a first free layer sequentially disposed on the substrate. The first drain layer is disposed on the first magnetic tunneling junction structure. The first channel layer is disposed on the first drain layer. The source layer is disposed on the first channel layer. The second channel layer is disposed on the source layer. The second drain layer is disposed on the second channel layer. The second magnetic tunneling junction structure is disposed on the second drain layer and includes a second free layer, a second tunneling barrier layer, and a second pinned layer sequentially disposed on the second drain layer. The word line structure is disposed on the substrate and penetrates at least the second magnetic tunneling junction structure, the second drain layer, the second channel layer, the source layer, and the first channel layer. The first bit line structure is electrically connected to the second magnetic tunneling junction structure. The second bit line structure penetrates the second magnetic tunneling junction structure, the second drain layer, the second channel layer, the source layer, the first channel layer, and the first drain layer and is electrically connected to the first magnetic tunneling junction structure. The source line structure penetrates the second magnetic tunneling junction structure, the second drain layer, and the second channel layer and is connected to the source layer.
[0007] In an embodiment of the magnetoresistive random access memory of the present invention, the word line structure includes a word line and an insulating layer surrounding the sidewalls and bottom of the word line.
[0008] In an embodiment of the magnetoresistive random access memory of the present invention, the first bit line structure includes a first bit line and an insulating layer surrounding the sidewalls of the first bit line.
[0009] In an embodiment of the magnetoresistive random access memory of the present invention, the first bit line is connected to the second pinned layer.
[0010] In an embodiment of the magnetoresistive random access memory of the present invention, the second bit line structure includes a second bit line and an insulating layer surrounding the sidewalls of the second bit line.
[0011] In an embodiment of the magnetoresistive random access memory of the present invention, the second bit line is connected to the first pinned layer.
[0012] In an embodiment of the magnetoresistive random access memory of the present invention, the source line structure includes a source line and an insulating layer surrounding the sidewalls of the source line.
[0013] In an embodiment of the magnetoresistive random access memory of the present invention, a first contact window and an insulating layer are further included. The first contact window penetrates through the second magnetic tunneling junction structure, the second drain layer, the second channel layer, and the source layer and is connected to the first channel layer. The insulating layer surrounds the sidewall of the first contact window.
[0014] In an embodiment of the magnetoresistive random access memory of the present invention, a second contact window and an insulating layer are further included. The second contact window penetrates through the second magnetic tunneling junction structure and the second drain layer and is connected to the second channel layer. The insulation surrounds the sidewall of the second contact window.
[0015] In an embodiment of the magnetoresistive random access memory of the present invention, the materials of the first channel layer and the second channel layer each include polysilicon or epitaxial silicon.
[0016] Based on the above, the magnetoresistive random access memory of the present invention includes two transistors and two magnetic tunneling junction structures, that is, two magnetoresistive random access memory cells are stacked, so a higher data storage capacity can be achieved without increasing the layout area.
[0017] In addition, in the magnetoresistive random access memory of the present invention, the two transistors share the source layer, so that the magnetoresistive random access memory of the present invention can have a smaller thickness, which is beneficial to the thinning of the memory device.
[0018] In addition, in the magnetoresistive random access memory of the present invention, the channel layer in the transistor surrounds the word line serving as the gate. In this way, the transistor can have a larger effective channel length, thereby improving the data retention ability of the magnetoresistive random access memory. Brief Description of the Drawings
[0019] Figure 1 It is a cross-sectional schematic diagram of the magnetoresistive random access memory according to an embodiment of the present invention;
[0020] Figure 2 It is a three-dimensional schematic diagram of the magnetoresistive random access memory according to an embodiment of the present invention;
[0021] Figure 3 It is a circuit schematic diagram of the magnetoresistive random access memory according to an embodiment of the present invention.
[0022] Symbol Description
[0023] 10: Magnetoresistive random access memory
[0024] 10a: First magnetoresistive random access memory cell
[0025] 10b: Second magnetoresistive random access memory cell
[0026] 100: Substrate
[0027] 102: First magnetic tunneling junction structure
[0028] 102a: First pinned layer
[0029] 102b: First tunneling barrier layer
[0030] 102c: First free layer
[0031] 104: First drain layer
[0032] 106: First channel layer
[0033] 108: Source layer
[0034] 110: Second channel layer
[0035] 112: Second drain layer
[0036] 114: Second magnetic tunneling junction structure
[0037] 114a: Second free layer
[0038] 114b: Second tunneling barrier layer
[0039] 114c: Second pinned layer
[0040] 116: Word line structure
[0041] 116a: Word line
[0042] 116b, 118b, 120b, 122b, 126b, 128b: Insulating layer
[0043] 118: First bit line structure
[0044] 118a: First bit line
[0045] 120: Second bit line structure
[0046] 120a: Second bit line
[0047] 122: Source line structure
[0048] 122a: Source line
[0049] 124: Dielectric layer
[0050] 126a: First contact window
[0051] 128a: Second contact window Detailed implementation manners
[0052] Examples are listed below and described in detail with reference to the accompanying drawings. However, the provided examples are not intended to limit the scope covered by the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original scale. For ease of understanding, the same elements will be denoted by the same reference numerals in the following description.
[0053] Regarding the terms "comprising", "including", "having", etc. used herein, they are all open-ended terms, that is, they mean "including but not limited to".
[0054] When elements are described using terms such as "first", "second", etc., they are only used to distinguish these elements from each other and do not limit the order or importance of these elements. Therefore, in some cases, the first element may also be referred to as the second element, and the second element may also be referred to as the first element, and this does not deviate from the scope of the present invention.
[0055] In addition, the directional terms mentioned in the text, such as "upper", "lower", etc., are only used to refer to the direction of the drawings and do not limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when an element such as a layer or a film is placed "on" another element, the element can be directly placed on the other element, or there may be an intermediate element. On the other hand, when it is said that an element is placed "directly" on another element, there is no intermediate element between the two.
[0056] Figure 1 It is a cross-sectional schematic diagram of a magnetoresistive random access memory according to an embodiment of the present invention. Figure 2 A three-dimensional schematic diagram of a magnetoresistive random access memory according to an embodiment of the present invention. In Figure 2 order to make the drawings clear, the dielectric layer covering the magnetoresistive random access memory is omitted. In addition, in Figure 1 and Figure 2 the relative positions between the word line structure, the bit line structure, the source line structure, and the contact window are only exemplary, and the present invention is not limited thereto.
[0057] The magnetoresistive random access memory of this embodiment includes two transistors and two magnetic tunneling junction structures, wherein the two transistors are connected in series between the two magnetic tunneling junction structures, and the two transistors share a source layer. In this way, the magnetoresistive random access memory of this embodiment can include two magnetoresistive random access memory cells and can simultaneously have a smaller thickness. The following will describe this in detail.
[0058] Please refer to Figure 1 and Figure 2, the magnetoresistive random access memory 10 of this embodiment includes a first magnetic tunneling junction structure 102, a first drain layer 104, a first channel layer 106, a source layer 108, a second channel layer 110, a second drain layer 112, a second magnetic tunneling junction structure 114, a word line structure 116, a first bit line structure 118, a second bit line structure 120, and a source line structure 122 disposed on a substrate 100. In this embodiment, the magnetoresistive random access memory 10 is disposed on the substrate 100 in a cylindrical form, but the present invention is not limited thereto. In other embodiments, the magnetoresistive random access memory 10 may be disposed on the substrate 100 in a polygonal columnar form.
[0059] The first magnetic tunneling junction structure 102, the first drain layer 104, the first channel layer 106, the source layer 108, the second channel layer 110, the second drain layer 112, and the second magnetic tunneling junction structure 114 are sequentially stacked on the substrate 100. In this embodiment, the substrate 100 is a dielectric substrate, which is, for example, a dielectric layer formed on a silicon substrate, but the present invention is not limited thereto.
[0060] In this embodiment, the first magnetic tunneling junction structure 102 includes a first pinned layer 102a, a first tunneling barrier layer 102b, and a first free layer 102c sequentially stacked on the substrate 100, but the present invention is not limited thereto. Depending on actual requirements, the first magnetic tunneling junction structure 102 may further include other film layers and may have other architectures, which are well known to those skilled in the art and will not be described herein. The material of the first pinned layer 102a may be cobalt (Co), iron (Fe), boron (B), or a combination thereof. The first pinned layer 102a has a fixed or pinned magnetic direction. The material of the first tunneling barrier layer 102b may be magnesium oxide, aluminum oxide, or a combination thereof. The material of the first free layer 102c may be cobalt, iron, boron, or a combination thereof. The first free layer 102c has a variable or free magnetic direction, and thus can be switched between two or more different magnetic polarities, and different magnetic polarities can each represent different data storage states.
[0061] The first drain layer 104, the first channel layer 106, the source layer 108, the second channel layer 110, and the second drain layer 112 are sequentially stacked on the first magnetic tunneling junction structure 102. In this embodiment, the first drain layer 104, the source layer 108, and the second drain layer 112 may be polysilicon layers or epitaxial silicon layers having a first conductivity type, and the first channel layer 106 and the second channel layer 110 may be polysilicon layers or epitaxial silicon layers having a second conductivity type. The first conductivity type may be one of N-type and P-type, and the second conductivity type is the other of N-type and P-type.
[0062] The second magnetic tunneling junction structure 114 is disposed on the second drain layer 112. In this embodiment, the second magnetic tunneling junction structure 114 includes a second free layer 114a, a second tunneling barrier layer 114b, and a second pinned layer 114c that are sequentially stacked on the second drain layer 112, but the present invention is not limited thereto. Depending on actual requirements, the second magnetic tunneling junction structure 114 may further include other film layers and may have other architectures, which are well known to those skilled in the art and will not be described herein. The material of the second free layer 114a may be cobalt, iron, boron, or a combination thereof. The second free layer 114a has a variable or free magnetic direction, and thus can be switched between two or more different magnetic polarities, and different magnetic polarities can each represent different data storage states. The material of the second tunneling barrier layer 114b may be magnesium oxide, aluminum oxide, or a combination thereof. The material of the second pinned layer 114c may be cobalt, iron, boron, or a combination thereof. The second pinned layer 114c has a fixed or pinned magnetic direction.
[0063] In addition, in this embodiment, a dielectric layer 124 is disposed on the second magnetic tunneling junction structure 114 to serve as an inter-layer dielectric layer (ILD).
[0064] The word line structure 116 includes a word line 116a and an insulating layer 116b surrounding the sidewalls and bottom of the word line 116a. The material of the word line 116a is, for example, tungsten, tungsten silicide, or doped polysilicon. The material of the insulating layer 116b is, for example, silicon oxide. In this embodiment, the word line structure 116 penetrates through the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, the second channel layer 110, the source layer 108, and the first channel layer 106, and extends into the first drain layer 104, but the present invention is not limited thereto. In other embodiments, the word line structure 116 may extend into the first magnetic tunneling junction structure 102 or the substrate 100. The present invention does not limit the depth of the word line structure 116, as long as the bottom surface of the word line 116a is not higher than the bottom surface of the first channel layer 106.
[0065] The word line structure 116 can serve as the gate structure of the transistor in the magnetoresistive random access memory 10 of this embodiment, where the word line 116a can serve as the gate, and the insulating layer 116b can serve as the gate insulating layer. Therefore, the word line structure 116, the first drain layer 104, the first channel layer 106, and the source layer 108 can form a first transistor, and the word line structure 116, the source layer 108, the second channel layer 110, and the second drain layer 112 can form a second transistor. The first transistor and the second transistor can be connected in series with each other via the shared source layer 108.
[0066] In this way, by connecting the first drain layer 104 to the first free layer 102c of the first magnetic tunneling junction structure 102, the first transistor and the first magnetic tunneling junction structure 102 can form the first magnetoresistive random access memory cell 10a. In addition, by connecting the second drain layer 112 to the second free layer 114a of the second magnetic tunneling junction structure 114, the second transistor and the second magnetic tunneling junction structure 114 can form the second magnetoresistive random access memory cell 10b. That is to say, the magnetoresistive random access memory 10 of this embodiment can be regarded as being composed of the first magnetoresistive random access memory cell 10a and the second magnetoresistive random access memory cell 10b. Therefore, the magnetoresistive random access memory 10 of this embodiment can effectively increase the data storage capacity without increasing the layout area.
[0067] In addition, in the magnetoresistive random access memory 10 of this embodiment, since the first transistor and the second transistor share the source layer 108, the magnetoresistive random access memory 10 can have a smaller thickness, which is beneficial to the thinning of the memory device.
[0068] Furthermore, since the magnetoresistive random access memory 10 is disposed on the substrate 100 in a columnar form, the channel layer in the transistor can surround the word line 116a serving as the gate. In this way, the first transistor and the second transistor in the magnetoresistive random access memory 10 can each have a larger effective channel length, thereby improving the data retention ability of the magnetoresistive random access memory 10.
[0069] In this embodiment, an operating voltage can be applied to the first magnetic tunneling junction structure 102 through the second bit line structure 120, an operating voltage can be applied to the second magnetic tunneling junction structure 114 through the first bit line structure 118, and an operating voltage can be applied to the source layer 108 through the source line structure 122.
[0070] Specifically, the first bit line structure 118 penetrates through the dielectric layer 124 and is electrically connected to the second magnetic tunneling junction structure 114, and the second bit line structure 120 penetrates through the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, the second channel layer 110, the source layer 108, the first channel layer 106, and the first drain layer 104 and is electrically connected to the first magnetic tunneling junction structure 102. In addition, the source line structure 122 penetrates through the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, and the second channel layer 110 and is connected to the source layer 108.
[0071] The first bit line structure 118 includes a first bit line 118a and an insulating layer 118b surrounding the sidewall of the first bit line 118a. The material of the first bit line 118a is, for example, tungsten or a tantalum nitride / tantalum / copper composite material. The material of the insulating layer 118b is, for example, silicon oxide. In this embodiment, the first bit line structure 118 penetrates the dielectric layer 124 and contacts the top surface of the second pinned layer 114c of the second magnetic tunneling junction structure 114, but the present invention is not limited thereto. In other embodiments, the first bit line structure 118 may extend into the second pinned layer 114c. The present invention does not limit the depth of the first bit line structure 118, as long as the first bit line 118a does not penetrate the second pinned layer 114c.
[0072] The second bit line structure 120 includes a second bit line 120a and an insulating layer 120b surrounding the sidewall of the second bit line 120a. The material of the second bit line 120a is, for example, tungsten or a tantalum nitride / tantalum / copper composite material. The material of the insulating layer 120b is, for example, silicon oxide. In this embodiment, the second bit line structure 120 penetrates the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, the second channel layer 110, the source layer 108, the first channel layer 106, the first drain layer 104, the first free layer 102c, and the first tunneling barrier layer 102b, and contacts the top surface of the first pinned layer 102a of the first magnetic tunneling junction structure 102, but the present invention is not limited thereto. In other embodiments, the second bit line structure 120 may extend into the first pinned layer 102a. The present invention does not limit the depth of the second bit line structure 120, as long as the second bit line 120a does not penetrate the first pinned layer 102a.
[0073] The source line structure 122 includes a source line 122a and an insulating layer 122b surrounding the sidewall of the source line 122a. The material of the source line 122a is, for example, tungsten or a tantalum nitride / tantalum / copper composite material. The material of the insulating layer 122b is, for example, silicon oxide. In this embodiment, the source line structure 122 penetrates the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, and the second channel layer 110, and contacts the top surface of the source layer 108, but the present invention is not limited thereto. In other embodiments, the source line structure 122 may extend into the source layer 108. The present invention does not limit the depth of the source line structure 122, as long as the source line 122a does not penetrate the source layer 108.
[0074] In addition, depending on the actual situation, a contact window connected to the first channel layer 106 may be provided, and a contact window connected to the second channel layer 110 may be provided. In the case where the first channel layer 106 and the second channel layer 110 are floating, the above contact windows may be omitted.
[0075] In this embodiment, the first contact window 126a can penetrate through the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, the second channel layer 110, and the source layer 108 to connect with the first channel layer 106, and the insulating layer 126b surrounds the sidewall of the first contact window 126a. The material of the first contact window 126a is, for example, tungsten or a thallium / nitride / thallium / copper composite material. The material of the insulating layer 126b is, for example, silicon oxide. In this embodiment, the first contact window 126a penetrates through the dielectric layer 124, the second magnetic tunneling junction structure 114, the second drain layer 112, the second channel layer 110, and the source layer 108, and contacts the top surface of the first channel layer 106, but the present invention is not limited thereto. In other embodiments, the first contact window 126a can extend into the first channel layer 106. The present invention does not limit the depth of the first contact window 126a, as long as the first contact window 126a does not penetrate the first channel layer 106.
[0076] In this embodiment, the second contact window 128a can penetrate through the dielectric layer 124, the second magnetic tunneling junction structure 114, and the second drain layer 112 to connect with the second channel layer 110, and the insulating layer 128b surrounds the sidewall of the second contact window 128a. The material of the second contact window 128a is, for example, tungsten or a thallium / nitride / thallium / copper composite material. The material of the insulating layer 128b is, for example, silicon oxide. In this embodiment, the second contact window 128a penetrates through the dielectric layer 124, the second magnetic tunneling junction structure 114, and the second drain layer 112, and contacts the top surface of the second channel layer 110, but the present invention is not limited thereto. In other embodiments, the second contact window 128a can extend into the second channel layer 110. The present invention does not limit the depth of the second contact window 128a, as long as the second contact window 128a does not penetrate the second channel layer 110.
[0077] Figure 3 Schematic circuit diagram of a magnetoresistive random access memory according to an embodiment of the invention. As Figure 3 shown, in the magnetoresistive random access memory 10, two transistors are connected in series between the first magnetic tunneling junction structure 102 and the second magnetic tunneling junction structure 114. The first magnetic tunneling junction structure 102 is electrically connected to the source of one transistor, the second magnetic tunneling junction structure 114 is electrically connected to the source of the other transistor, and the two transistors share a common source (source layer 108). In addition, the word line 116a can serve as the gate of each of the two transistors. Therefore, the magnetoresistive random access memory 10 can be operated by applying voltages to the word line 116a, the first bit line 118a, the second bit line 120a, the source line 122a, the first contact window 126a, and the second contact window 128a, respectively.
[0078] In this embodiment, the magnetoresistive random access memory 10 is composed of a first magnetoresistive random access memory cell 10a and a second magnetoresistive random access memory cell 10b. Therefore, the data storage capacity can be effectively increased without increasing the layout area. In other embodiments, depending on actual requirements, a plurality of magnetoresistive random access memories 10 can be stacked and connected in series to form a memory device, and these magnetoresistive random access memories 10 share the word line structure 116 to further increase the data storage capacity of the memory device without increasing the layout area.
[0079] Although the present invention is disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.
Claims
1. A magnetoresistive random access memory, comprising: A first magnetic tunneling junction structure disposed on a substrate and including a first pinned layer, a first tunneling barrier layer, and a first free layer sequentially disposed on the substrate; A first drain layer disposed on the first magnetic tunneling junction structure; A first channel layer disposed on the first drain layer; A source layer disposed on the first channel layer; A second channel layer disposed on the source layer; A second drain layer disposed on the second channel layer; A second magnetic tunneling junction structure disposed on the second drain layer and including a second free layer, a second tunneling barrier layer, and a second pinned layer sequentially disposed on the second drain layer; A word line structure disposed on the substrate and at least penetrating the second magnetic tunneling junction structure, the second drain layer, the second channel layer, the source layer, and the first channel layer; A first bit line structure electrically connected to the second magnetic tunneling junction structure; A second bit line structure penetrating the second magnetic tunneling junction structure, the second drain layer, the second channel layer, the source layer, the first channel layer, and the first drain layer and electrically connected to the first magnetic tunneling junction structure; and A source line structure penetrating the second magnetic tunneling junction structure, the second drain layer, and the second channel layer and connected to the source layer.
2. The magnetoresistive random access memory according to claim 1, wherein the word line structure comprises: A word line; and An insulating layer surrounding the sidewalls and bottom of the word line.
3. The magnetoresistive random access memory according to claim 1, wherein the first bit line structure comprises: A first bit line; and An insulating layer surrounding the sidewall of the first bit line.
4. The magnetoresistive random access memory according to claim 3, wherein the first bit line is connected to the second pinned layer.
5. The magnetoresistive random access memory according to claim 1, wherein the second bit line structure comprises: A second bit line; and An insulating layer surrounding the sidewall of the second bit line.
6. The magnetoresistive random access memory according to claim 5, wherein the second bit line is connected to the first pinned layer.
7. The magnetoresistive random access memory according to claim 1, wherein the source line structure comprises: A source line; and An insulating layer surrounding the sidewall of the source line.
8. The magnetoresistive random access memory according to claim 1, further comprising: A first contact window penetrating the second magnetic tunneling junction structure, the second drain layer, the second channel layer, and the source layer and connected to the first channel layer; and An insulating layer surrounding the sidewall of the first contact window.
9. The magnetoresistive random access memory according to claim 1, further comprising: A second contact window penetrating the second magnetic tunneling junction structure and the second drain layer and connected to the second channel layer; and An insulating layer surrounding the sidewall of the second contact window.
10. The magnetoresistive random access memory according to claim 1, wherein the materials of the first channel layer and the second channel layer each include polysilicon or epitaxial silicon.