Implementation method and system for pcie physical layer built-in self-test code

Abstract

The application aims to provide an implementation method and system for PCIE physical layer built-in self-test code, which comprises the following steps: a controller layer integrates a PCIE BIST GEN module to pack data and send the data to a physical coding sublayer; the physical coding sublayer encodes the packed data and sends the data to a physical medium adaptation layer; and the physical medium adaptation layer converts the encoded data into serial data and returns the data to the controller layer. The application embeds a BIST test component conforming to the PIPE protocol requirement in the PCS layer. Through the simulation in the early stage and the data result analysis of the post-silicon test, compared with the traditional BIST test scheme, the application can not only meet the electrical performance test demand of the original analog circuit, but also increase the test coverage of the PCS layer. The application realizes the full-stack coverage test from the physical signal to the protocol logic.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically to a method and system for implementing self-test code built into the PCIe physical layer. Background Technology

[0002] With the iteration of the PCIe (Peripheral Component Interconnect Express) protocol to high-speed versions such as Gen5, its physical layer signal rate has reached the 32 GT / s level, posing unprecedented challenges to the signal integrity, timing accuracy, and anti-interference capabilities of circuit designs. The PCIe protocol is a high-speed serial computer expansion bus standard used to connect various internal computer components, such as graphics cards, network cards, and sound cards, to achieve efficient data transmission. The PCIe protocol uses a high-speed serial point-to-point dual-channel high-bandwidth transmission method, with each device having an independent channel and not sharing the bus, thus significantly improving data transmission speed and system performance. The PCIe protocol is widely used in connecting various peripherals in computer systems, such as graphics cards, network cards, and solid-state drives. With continuous technological advancements, the PCIe protocol is also constantly evolving and upgrading to meet the ever-increasing data transmission demands.

[0003] In the development of physical layer SerDes IPs, the attenuation, crosstalk, and jitter of high-speed serial signals are significantly aggravated, making it difficult for traditional testing methods to accurately evaluate chip performance. Meanwhile, the PCIe protocol mandates the use of efficient coding schemes such as 128b / 130b and 8b / 10b. How to simultaneously plan and build an in-house test architecture early in the circuit design process, so that it can meet the simulation needs of real-world scenarios in the early simulation stages (such as dynamic signal degradation reproduction) and support quantitative diagnostics in later post-silicon testing (such as bit error rate detection and eye diagram analysis), has become a core challenge for shortening the development cycle and ensuring chip functional reliability. Currently, the industry commonly adopts a solution that integrates a PRBS pattern generator and checker at the PMA (Physical Media Adaptor) layer. While this can achieve basic quality testing of high-speed serial signals, its testing scope is limited to analog circuit characteristics (such as signal integrity and jitter tolerance), and cannot cover protocol-related functional verification at the PCS (Physical Coding Sub) layer. This deficiency makes it difficult to comprehensively test key protocol behaviors such as link state machine control, training sequence interaction, and power management during IP development, creating a testing blind spot. Summary of the Invention

[0004] The purpose of this invention is to provide a method and system for implementing built-in self-test code in the PCIe physical layer. This method embeds a BIST test component compliant with the PIPE protocol requirements within the PCS layer. Through analysis of data results from preliminary simulation and post-silicon testing, compared to traditional BIST test schemes, it not only meets the electrical performance testing requirements of the original analog circuits but also increases the test coverage of the PCS layer. It achieves full-stack coverage testing from physical signals to protocol logic.

[0005] The method for implementing built-in self-test code in the PCIe physical layer is characterized by including: Integrate the PCIE BIST GEN module at the controller layer to package data and send it to the physical encoding sublayer; The physical coding sublayer encodes the packaged data and sends it to the physical media adaptation layer; The physical media adaptation layer converts the encoded data into serial data and transmits it back to the controller layer.

[0006] Preferably, the physical media adapter layer converts the encoded data into serial data and transmits it back to the controller layer, including: The physical media adaptation layer converts the encoded data into serial data and sends it to the physical encoding sublayer. The physical coding sublayer aligns and decodes the serial data; The decoded data is sent to the controller layer for unpacking. The PCIE BIST CHK module is integrated into the controller layer to complete the full-link closed-loop verification.

[0007] Preferably, the step of integrating the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer includes: The self-built PRBS generator in the PCIE BIST GEN module supports three standard polynomial sequences: PRBS-7, PRBS-23, and PRBS-31, as well as user-defined UDP code patterns. It also supports the dynamic insertion of error codes to simulate protocol violation scenarios.

[0008] Preferably, the integration of the PCIE BIST CHK module at the controller layer for completing end-to-end closed-loop verification includes: The integrated PCIE BIST CHK module supports the reception of programmable data streams with various data bit widths of 8 / 16 / 32-bit. After receiving the data stream conforming to the PIPE protocol from the elastic buffer, filter and remove K code and OS code control characters as well as invalid data; The received PRBS data is XORed with the reference data generated by the local PRBS generator in real time, and for UDP data, it is compared bit by bit with the user-preset template data. Verification anomalies trigger an error count accumulation mechanism, and the link quality is ultimately determined based on the bit error rate over a continuous statistical period.

[0009] Preferably, the physical encoding sublayer encodes the packaged data and sends it to the physical media adapter layer, including: When the transmitting end starts transmission, the txelecidle signal is set low. In Gen1 / Gen2 mode, the physical coding sublayer adopts an 8b / 10b coding mechanism. The data type is identified by the txdata_k signal, with 1 for regular data and 0 for K-code. When in Gen3 / Gen4 / Gen5 mode, the encoding mechanism is switched to 128b / 130b. Fine control is achieved by a combination of signals: high level to mark the start of a new data block (txstartblock), high level effective window for synchronization control signal and data (txdatavalid), 2'b01 to identify the OS code, and 2'b10 to identify regular data. Based on the bus data bit width requirements, periodically lower txdatavalid to balance the encoding and decoding throughput; Set the txelecidle signal high after the data transmission is complete.

[0010] Preferably, the physical coding sublayer aligns and decodes the serial data, including: The data stream undergoes physical layer alignment and decoding operations. The decoding module performs synchronization control based on the OS code and completes the decoding output according to the protocol timing. The receive clock and protocol layer clock are processed across clock domains through an elastic buffer. By monitoring the difference between the read and write pointers in real time, SKP code deletion / insertion operations are dynamically implemented to maintain the balance of the buffer.

[0011] Preferably, the step of integrating the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer further includes: A configurable-length COMMA code or EIEOS code is inserted into the sequence preamble to assist the receiver in aligning and locking the initial data. For frequency difference compensation between the CDR recovery clock and the PLL generated clock on the RX side, a dynamic SKP code insertion strategy under programmable configuration is supported.

[0012] An implementation system for built-in self-test code in the PCIe physical layer, comprising: The data transmission module is used to integrate the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer. The data encoding module is used by the physical encoding sublayer to encode the packaged data and send it to the physical media adapter layer; The data conversion module is used by the physical media adaptation layer to convert the encoded data into serial data and transmit it back to the controller layer.

[0013] An electronic device includes a chip, a processor, and a memory, the memory storing computer program code including computer instructions, wherein, when the chip executes the computer instructions, the electronic device executes a method for implementing built-in self-test code for the PCIe physical layer.

[0014] A computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor of an electronic device, cause the processor to perform a method for implementing built-in self-test code for the PCIe physical layer.

[0015] The beneficial effects of this invention are as follows: Compared to the traditional PRBS pattern generator and checker integrated into the PMA layer, this invention, by adding a BIST generation and check module compatible with the PIPE interface protocol to the PCS, can not only achieve basic quality testing of high-speed serial signals, but also cover protocol-related function verification of the PCS (Physical Code Sub) layer. This invention greatly reduces the testing blind spots in IP development and improves the testing coverage of IP. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the implementation method of the self-test code built into the PCIE physical layer according to the present invention. Figure 2 This is a system architecture diagram for implementing built-in self-test code in the PCIE physical layer according to the present invention; Figure 3 This is a schematic diagram of the hardware structure of an electronic device according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0021] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0022] In the development of physical layer SerDes IPs, the attenuation, crosstalk, and jitter of high-speed serial signals are significantly aggravated, making it difficult for traditional testing methods to accurately evaluate chip performance. Meanwhile, the PCIe protocol mandates the use of efficient coding schemes such as 128b / 130b and 8b / 10b. How to simultaneously plan and build an in-house test architecture early in the circuit design process, so that it can meet the simulation needs of real-world scenarios in the early simulation stages (such as dynamic signal degradation reproduction) and support quantitative diagnostics in later post-silicon testing (such as bit error rate detection and eye diagram analysis), has become a core challenge for shortening the development cycle and ensuring chip functional reliability. Currently, the industry commonly adopts a solution that integrates a PRBS pattern generator and checker at the PMA (Physical Media Adaptor) layer. While this can achieve basic quality testing of high-speed serial signals, its testing scope is limited to analog circuit characteristics (such as signal integrity and jitter tolerance), and cannot cover protocol-related functional verification at the PCS (Physical Coding Sub) layer. This deficiency makes it difficult to comprehensively test key protocol behaviors such as link state machine control, training sequence interaction, and power management during IP development, creating a testing blind spot.

[0023] Compared to traditional solutions integrating PRBS pattern generators and checkers into the PMA layer, this invention adds a BIST generation and checking module compatible with the PIPE interface protocol to the PCS. This not only enables basic quality testing of high-speed serial signals but also covers protocol-related function verification within the PCS (Physical Code Sub) layer. This invention significantly reduces the testing blind spots in IP development and improves IP testing coverage.

[0024] Example 1 The method for implementing built-in self-test code in the PCIe physical layer is characterized by referring to Figure 1 ,include: S100 integrates a PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer; The PCIE BIST GEN module is a Built-in Self-Test (BIST) signal generation module for PCI Express (PCIE) interfaces. It is primarily used to verify and test the functionality and performance of the PCIE interface, ensuring its compliance with design specifications and standards. The PCIE BIST GEN module includes: a Pattern Generator: generates test data patterns such as PRBS, fixed patterns, or custom patterns; Control Logic: controls the start, stop, and mode selection of tests; Configures test parameters such as data rate and packet size; Error Detection and Statistics: detects data errors at the receiving end (e.g., bit error rate, BER); Statistics on test results, such as the amount of data transmitted and the number of errors; and an Interface Adapter: adapts the generated test signals to the physical and protocol layers of the PCIe interface.

[0025] S200, the physical coding sublayer encodes the packaged data and sends it to the physical media adaptation layer; S300, the physical media adapter layer converts the encoded data into serial data and sends it back to the controller layer.

[0026] The PCIe subsystem primarily consists of two parts: the PCIe Controller and the PCIe Physical Layer (PCIe PHY). The Physical Layer is further divided into the Physical Coding Sublayer (PCS) and the Physical Media Adapter Layer (PMA). The controller layer and the physical layer communicate via the PIPE (PHY Interface for PCI Express) interface. During data transmission, data is first packaged at the controller layer and sent to the PCS via the PIPE interface. The PCS selects 8b / 10b or 128b / 130b encoding based on the transmission rate and then passes the data to the PMA. The PMA is responsible for converting parallel data into serial data and sending it out via a high-speed serial port. At the receiving end, the PMA converts the received serial data back into parallel data and sends it back to the PCS. The PCS aligns and decodes the data, handles cross-clock domain issues using a flexible buffer, and finally sends the data back to the controller layer for unpacking and processing via the PIPE interface. This structure ensures efficient data transmission and processing within the PCIe subsystem. Although this invention is used in the PCIE protocol, this patent can also be directly applied to the USB protocol, which also conforms to the PIPE requirement.

[0027] This invention innovatively embeds a protocol-aware BIST (Built-in Self-Test) architecture within the PCS layer: by integrating a programmable timing controller, it accurately generates training sequences (such as EIEOS, SKP, and SDS) conforming to the PIPE interface specification, and supports dynamic insertion of error codes to simulate protocol violation scenarios. This solution not only verifies the functional integrity of 8b / 10b or 128b / 130b codec modules, but also achieves full-stack coverage testing from physical signals to protocol logic by combining the generation and detection functions of the Electrically Idle Exit Sequence (EIEOS) specified by the protocol. Compared with traditional solutions, this increases the verification of protocol consistency while significantly reducing the dependence of post-silicon testing on high-end oscilloscopes and protocol analyzers.

[0028] Preferably, in step S300, the physical media adapter layer converts the encoded data into serial data and transmits it back to the controller layer, including: S310, the physical media adapter layer converts the encoded data into serial data and sends it to the physical coding sublayer; S320, the physical coding sublayer aligns and decodes serial data; S330 sends the decoded data to the controller layer for unpacking. The S340 integrates a PCIE BIST CHK module at the controller layer to complete end-to-end closed-loop verification.

[0029] The PCIE BIST CHK module is a built-in self-test checker in the PCI Express (PCIe) interface. Its main function is to receive and verify test data from the PCIE BIST GEN module (test signal generation module) to ensure the PCIe interface's receiver (RX) is functioning correctly and to detect errors in data transmission. The PCIE BIST CHK module receives test data from the PCIE BIST GEN module and verifies its correctness. For example, it checks whether the data matches the expected pattern (such as a PRBS pseudo-random sequence). It detects errors in data transmission, such as bit errors, packet loss, or protocol errors. For example, it checks data integrity using CRC (Cyclic Redundancy Check) or LCRC (Link CRC). It statistically analyzes test results, such as bit error rate (BER), transmission delay, and throughput. It generates test reports for analyzing the PCIe interface's performance. Troubleshooting: It helps locate problems at the receiver, such as poor signal integrity, clock jitter, or logic errors.

[0030] The PCIE BIST CHK module consists of the following components: Data Receiver: Receives test data from the PCIe interface. Pattern Checker: Compares the received data with expected patterns to detect errors. For example, it checks if the data matches a PRBS sequence. Error Detection Logic: Implements error detection mechanisms such as CRC checksum, LCRC checksum, or protocol check. Statistics and Reporting Module: Compiles test results (e.g., bit error rate, throughput) and generates reports. Control Logic: Controls the start, stop, and mode selection of the checking process. It also configures checking parameters such as data mode and error detection method.

[0031] The PCIE BIST GEN module is responsible for generating test signals and sending them to the PCIe interface. The PCIE BIST CHK module is responsible for receiving and verifying these test signals. When used together, they can comprehensively test the transmit (TX) and receive (RX) functions of the PCIe interface.

[0032] Preferably, in step S100, integrating the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer includes: The PCIE BIST GEN module supports a self-built PRBS generator that supports three standard polynomial sequences: PRBS-7, PRBS-23, and PRBS-31, as well as user-defined UDP code types. It also supports dynamically inserting error codes to simulate protocol violation scenarios.

[0033] This invention only supports PRBS-7, PRBS-23, and PRBS-31. For other PRBS code types, this invention can also be directly applied.

[0034] The present invention integrates a PCIE BIST GEN module at the sending end. The module has a built-in PRBS generator that supports three standard polynomial sequences: PRBS-7, PRBS-23, and PRBS-31, as well as user-defined UDP code patterns. It also supports the dynamic insertion of error codes to simulate protocol violation scenarios.

[0035] BIST testing uses a built-in pseudo-random binary sequence (PRBS) generator to generate test data to evaluate link signal quality. Its core code patterns include three standard modes: PRBS-7 (polynomial X^7 + X^6 + 1, sequence length 2^7 - 1 bits), PRBS-23 (X^23 + X^18 + 1, 2^23 - 1 bits), and PRBS-31 (X^31 + X^28 + 1, 2^31 - 1 bits), as well as a user-defined code pattern (UDP). The standard PRBS sequence is based on the principle of linear feedback shift register to achieve periodic looping, while the UDP mode supports configuring custom test templates through registers and implementing cyclic transmission, providing flexible programmable testing capabilities for high-speed links.

[0036] Preferably, in step S340, integrating a PCIE BIST CHK module at the controller layer to complete end-to-end closed-loop verification includes: The S341 integrates a PCIE BIST CHK module to support the reception of programmable data streams with various data bit widths of 8 / 16 / 32-bit. The data bit width in this invention supports 8-bit, 16-bit and 32-bit. If the data bit width is extended to 64-bit, this invention can also be directly applied.

[0037] S342, after receiving the data stream conforming to the PIPE protocol output from the elastic buffer, filter and remove K code and OS code control characters as well as invalid data; K-code stands for Control Character, used to represent non-data information (such as control commands, start / end of frame markers, etc.). In 8b / 10b encoding, K-code is distinguished from data characters (D-code) so that the receiving end can recognize and process control information. OS code stands for Ordered Set, used to transmit specific control or status information in high-speed serial communication. Ordered sets typically consist of multiple K-codes or D-codes and are used to implement functions such as link training, state switching, and error recovery.

[0038] S343 performs real-time XOR verification between the received PRBS data and the reference data generated by the local PRBS generator, and compares the UDP data bit by bit with the user-preset template data. The received data is represented as follows: ; M is a set of m-bit binary numbers of type n. The result is obtained by performing an XOR operation on all the data. ; The error rate of XOR check is expressed as: ; S344, the error count accumulation mechanism is triggered by the verification anomaly, and the link quality is finally determined based on the bit error rate within the continuous statistical period.

[0039] This invention deploys a PCIE BIST CHK module at the receiving end to complete end-to-end closed-loop verification. This module supports receiving data streams with programmable data bit widths (8 / 16 / 32-bit). Upon receiving a PIPE-compliant data stream from the elastic buffer, it first filters and removes control characters such as K-code and OS-code, as well as some invalid data. Then, it performs a real-time XOR check on the received PRBS data and the reference data generated by the local PRBS generator. For UDP data, it compares it bit-by-bit with user-preset template data. An error count is triggered if the check fails, and the link quality is ultimately determined based on the bit error rate (BER) over a continuous statistical period. This dual-end collaborative architecture can fully cover the functionality and fault tolerance verification of the entire SerDes path.

[0040] Preferably, in step S200, the physical encoding sublayer encodes the packaged data and sends it to the physical media adapter layer, including: S210, when the transmitting end starts transmission, the txelecidle signal is set low. In Gen1 / Gen2 mode, the physical coding sublayer adopts the 8b / 10b coding mechanism. S220 uses the txdata_k signal to identify the data type, with 1 for regular data and 0 for K-code; S230, when in Gen3 / Gen4 / Gen5 mode, the encoding mechanism is switched to 128b / 130b, and fine control is achieved by a combination of signals: high level to mark the start of a new data block txstartblock, high level effective window for synchronization control signal and data txdatavalid, 2'b01 to identify OS code, and 2'b10 to identify regular data. S240, according to the bus data bit width requirements, periodically sets txdatavalid low to balance the encoding and decoding throughput; S250 sets the txelecidle signal high after data transmission is complete.

[0041] The PIPE protocol imposes strict constraints on the timing control of data transmission and reception: When the transmitter initiates transmission, it must first set the txelecidle signal low. In Gen1 / Gen2 mode, the PCS layer uses an 8b / 10b encoding mechanism, and the data type is identified by the txdata_k signal (1 for regular data, 0 for K code). When upgrading to Gen3 / Gen4 / Gen5 mode, the encoding scheme switches to 128b / 130b, requiring fine-grained control through a combination of signals: txstartblock (high level to mark the start of a new data block), txdatavalid (high level for synchronization control signals and data within the active window), and txheader (2'b01 for OS code, 2'b10 for regular data). Simultaneously, based on the bus's data bit width requirements, txdatavalid needs to be periodically set low to balance encoding and decoding throughput. After data transmission is complete, the txelecidle signal must be set high. All signal timing must strictly adhere to the protocol specifications to ensure stable operation of the physical layer encoder.

[0042] Preferably, in step S320, the physical coding sublayer aligns and decodes the serial data, including: S321, the data stream undergoes physical layer alignment and decoding operations, wherein the decoding module performs synchronization control according to the OS code and completes the decoding output according to the protocol timing; The S322 uses an elastic buffer to handle cross-clock domain processing of the receive clock and protocol layer clock. By monitoring the difference between the read and write pointers in real time, it dynamically implements SKP code deletion / insertion operations to maintain the balance of the buffer.

[0043] The receiver's data processing flow follows strict protocol timing specifications: the data stream first undergoes physical layer alignment and decoding operations. The decoding module heavily relies on OS codes for synchronization control—data boundaries are detected by checking the OS codes, and decoding output is completed according to the protocol timing. Since the receive clock rxclk originates from the Clock Data Recovery (CDR) circuit, while the protocol layer's pclk is generated by a PLL, cross-clock domain processing is required via an Elastic Buffer Unit (EBUF). Given the inherent frequency difference between the two clock domains, long-term operation could lead to EBUF overflow risks, resulting in abnormal data reception. Therefore, the system dynamically implements SKP code deletion / insertion operations (Delete / Add SKP Ordered Sets) by real-time monitoring of the read / write pointer difference to maintain buffer balance and ensure data stream continuity.

[0044] Preferably, in step S340, integrating the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer further includes: S341, Insert a configurable length COMMA code or EIEOS code into the sequence preamble to assist the receiver in aligning and locking the initial data; S342 supports dynamic insertion of SKP code strategy under programmable configuration for frequency difference compensation between the CDR recovery clock and the PLL generated clock on the RX side.

[0045] In this embodiment of the invention, a configurable length COMMA code or EIEOS code can be inserted into the sequence preamble to assist the receiver in aligning and locking the initial data. For frequency difference compensation between the RX end rxclk (CDR recovery clock) and pclk (PLL generation clock), this invention supports a dynamically inserted SKP code strategy under programmable configuration. Furthermore, this invention supports outputting test data streams conforming to the PIPE protocol timing requirements at programmable data bit widths (8 / 16 / 32-bit). This test data stream can then cover the functional and electrical performance testing of the PCS, PMA, and the link.

[0046] Example 2 An implementation system for built-in self-test code in the PCIe physical layer, referenced. Figure 2 ,include: The data transmission module is used to integrate the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer. The data encoding module is used by the physical encoding sublayer to encode the packaged data and send it to the physical media adaptation layer; The data conversion module is used by the physical media adapter layer to convert the encoded data into serial data and transmit it back to the controller layer.

[0047] Example 3 An electronic device includes: a chip, a processor, and a memory, the memory for storing computer program code, the computer program code including computer instructions, wherein when the chip executes the computer instructions, the electronic device executes an implementation method for the PCIe physical layer built-in self-test code.

[0048] refer to Figure 3 The electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, memory 22, input device 23, and output device 24 are coupled together via connectors, which may include various interfaces, transmission lines, or buses, etc., and are not limited in this embodiment of the invention. It should be understood that in the various embodiments of the invention, coupling refers to mutual connection through a specific method, including direct connection or indirect connection through other devices, such as through various interfaces, transmission lines, buses, etc.

[0049] The processor 21 can be one or more graphics processing units (GPUs). If the processor 21 is a GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, with the multiple processors coupled to each other via one or more buses. Optionally, the processor can also be other types of processors, etc., and this embodiment of the invention is not limited thereto.

[0050] The memory 22 can be used to store computer program instructions, as well as various types of computer program code, including program code for executing the present invention. Optionally, the memory includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), which is used for related instructions and data.

[0051] Input device 23 is used to input data and / or signals, and output device 24 is used to output data and / or signals. Output device 24 and input device 23 can be independent devices or an integrated device.

[0052] Example 4 A computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor of an electronic device, cause the processor to perform an implementation method for the built-in self-test code of the PCIe physical layer.

[0053] Compared to traditional solutions integrating PRBS pattern generators and checkers into the PMA layer, this invention adds a BIST generation and checking module compatible with the PIPE interface protocol to the PCS. This not only enables basic quality testing of high-speed serial signals but also covers protocol-related function verification within the PCS (Physical Code Sub) layer. This invention significantly reduces the testing blind spots in IP development and improves IP testing coverage.

[0054] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for implementing built-in self-test code in the PCIe physical layer, characterized in that... ,include: Integrate the PCIE BIST GEN module at the controller layer to package data and send it to the physical encoding sublayer; The PCIE BIST GEN module is used to verify and test the functionality and performance of the PCIE interface. The PCIE BIST GEN module includes: a pattern generator, a control logic module, an error detection and statistics module, and an interface adapter. The physical coding sublayer encodes the packaged data and sends it to the physical media adaptation layer; The physical media adaptation layer converts the encoded data into serial data and transmits it back to the controller layer; The controller layer integrates a PCIE BIST CHK module to complete end-to-end closed-loop verification and transmit the data to the physical media adapter layer. The PCIE BIST CHK module is used to receive and verify test data from the PCIE BIST GEN module. The PCIE BIST CHK module includes: a data receiver, an error detection logic module, a statistics and reporting module, and a control logic module; The integration of a PCIE BIST CHK module at the controller layer for end-to-end closed-loop verification includes: the integrated PCIE BIST CHK module supports the reception of data streams with programmable data bit widths of 8 / 16 / 32-bit; Upon receiving the PIPE protocol-compliant data stream from the elastic buffer, filter and remove K-code and OS-code control characters, as well as invalid data; The received PRBS data is XORed with the reference data generated by the local PRBS generator in real time, and for UDP data, it is compared bit by bit with the user-preset template data. An error count is triggered during verification, and the link quality is ultimately determined based on the bit error rate within the continuous statistical period. The physical media adaptation layer converts the encoded data into serial data and sends it back to the controller layer, including: the physical media adaptation layer converts the encoded data into serial data and sends it to the physical encoding sublayer; The physical coding sublayer aligns and decodes the serial data; The decoded data is sent to the controller layer for unpacking. The step of integrating the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer includes: building a PRBS generator within the PCIE BIST GEN module to support three standard polynomial sequences, PRBS-7, PRBS-23, and PRBS-31, as well as user-defined UDP code types, and supporting dynamic insertion of error code types to simulate protocol violation scenarios. The physical coding sublayer encodes the packaged data and sends it to the physical media adapter layer, including: setting the txelecidle signal low when the transmitting end starts transmission; and using an 8b / 10b encoding mechanism in Gen1 / Gen2 mode. The data type is identified by the txdata_k signal, with 1 for regular data and 0 for K-code. When in Gen3 / Gen4 / Gen5 mode, the encoding mechanism switches to 128b / 130b, and fine control is achieved through a combination of signals: high level to mark the start of a new data block (txstartblock), high level effective window for synchronization control signal and data (txdatavalid), 2'b01 to identify the OS code, and 2'b10 to identify regular data. Based on the bus data width requirements, periodically set txdatavalid low to balance the encoding and decoding throughput; set txelecidle high after data transmission is complete. The physical coding sublayer aligns and decodes serial data, including: performing physical layer alignment and decoding operations on the data stream, wherein the decoding module performs synchronization control according to the OS code and completes the decoding output according to the protocol timing; Cross-clock domain processing of the receive clock and protocol layer clock is performed through an elastic buffer. By monitoring the difference between the read and write pointers in real time, SKP code deletion / insertion operations are dynamically implemented to maintain the balance of the buffer. The step of integrating the PCIE BIST GEN module at the controller layer to package data and send it to the physical coding sublayer also includes: inserting a configurable-length COMMA code or EIEOS code into the sequence preamble to assist the receiving end in aligning and locking the initial data; For frequency difference compensation between the CDR recovery clock and the PLL generated clock on the RX side, a dynamic SKP code insertion strategy under programmable configuration is supported.

2. A system for implementing built-in self-test code in the PCIe physical layer, applied to the method for implementing built-in self-test code in the PCIe physical layer as described in claim 1, characterized in that... ,include: The data transmission module is used to integrate the PCIE BIST GEN module at the controller layer to package data and send it to the physical encoding sublayer. The data encoding module is used by the physical encoding sublayer to encode the packaged data and send it to the physical media adapter layer; The data conversion module is used by the physical media adaptation layer to convert the encoded data into serial data and transmit it back to the controller layer.

3. An electronic device, characterized in that... The device includes a chip, a processor, and a memory, wherein the memory is used to store computer program code, the computer program code including computer instructions, and when the chip executes the computer instructions, the electronic device executes the implementation method for PCIe physical layer built-in self-test code as described in claim 1.

4. A computer-readable storage medium, characterized in that... The computer-readable storage medium stores a computer program, which includes program instructions that, when executed by a processor of an electronic device, cause the processor to perform the implementation method for the PCIe physical layer built-in self-test code as described in claim 1.

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