Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate, a first conductive layer located on one side of the substrate, the first conductive layer comprising a first power line, and a second conductive layer located on the side of the first conductive layer away from the substrate, the second conductive layer comprising a first signal line, a second signal line and a second power line located between the first signal line and the second signal line and arranged at intervals along a first direction, wherein the first power line, the first signal line, the second signal line and the second power line are formed in extension along a second direction, and the first power line and the second power line are connected through a via. In the application, the first power line and the second power line are connected through a via, which can increase the distribution area of the power line, thereby reducing the resistance of the power line, improving the influence of insufficient driving voltage on the display panel, and thereby improving the display effect of the display panel.

Description

[0001] This application is a divisional application based on the invention with application number 202211371395.7, application date November 3, 2022, applicants Hefei Visionox Technology Co., Ltd. and Kunshan Guoxian Optoelectronics Co., Ltd., entitled "Array Substrate and Display Panel". Technical Field

[0002] This application relates to the field of display, specifically to an array substrate and a display panel. Background Technology

[0003] Organic light-emitting diodes (OLEDs) are self-emissive display devices. Compared to traditional liquid crystal displays (LCDs), OLED technology does not require a backlight and is self-emissive. OLEDs use a thin layer of organic material and a glass substrate; when current flows through, the organic material emits light. Therefore, OLED display panels can significantly save energy, be made lighter and thinner, withstand a wider range of temperature variations than LCD panels, and have a wider viewing angle. OLED display panels are expected to become the next-generation flat panel display technology after LCDs and are currently one of the most watched technologies in the flat panel display field.

[0004] An OLED display panel consists of an array substrate and a display substrate. The array substrate includes power lines and pixel circuits. Drive signals are sent to the pixel circuits via the power lines, causing the pixel circuits to drive the display substrate to emit light. Excessive resistance in the power lines can lead to insufficient drive voltage, thus affecting the display panel's performance. Summary of the Invention

[0005] This application provides an array substrate and a display panel, which aim to improve the display effect of the display panel.

[0006] An embodiment of the first aspect of this application provides an array substrate, the array substrate comprising: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer including a first power line; and a second conductive layer located on the side of the first conductive layer opposite to the substrate, the second conductive layer including a first signal line, a second signal line and a second power line located between the first signal line and the second signal line, wherein the first power line, the first signal line, the second signal line and the second power line are all formed extending along a second direction, and the first power line and the second power line are connected by vias.

[0007] According to an embodiment of the first aspect of this application, the second power line includes a plurality of power blocks spaced apart along a second direction and a connecting line connecting two adjacent power blocks, wherein the width of the connecting line in the first direction is smaller than the width of the power blocks in the first direction.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the second conductive layer further includes:

[0009] The first connecting part is connected to the first signal line and located between the first signal line and the second signal line;

[0010] The second connector is connected to the second signal line and located between the first signal line and the second signal line;

[0011] Two connecting lines located on both sides of the same power supply block in the second direction and connected thereto, one of which is the first connecting line and the other is the second connecting line. The first connecting line extends between the first connecting part and the second signal line, and the second connecting line extends between the second connecting part and the first signal line.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the first connecting line is connected to the side of the power block facing the second signal line, and the second connecting line is connected to the side of the power block facing the first signal line.

[0013] According to any of the foregoing embodiments of the first aspect of this application, a plurality of second power lines are distributed at intervals along a first direction, and the power block of at least one second power line includes a functional block and an auxiliary block. The connecting line of the second power line also includes a third connecting line. The auxiliary block and the functional block are spaced apart in the second direction and connected to each other by the third connecting line. A first via is provided between the auxiliary block and the functional block.

[0014] The array substrate also includes a third conductive layer and a fourth conductive layer, which are disposed on opposite sides of the second conductive layer. The third conductive layer includes a third signal line, and the fourth conductive layer includes a pixel electrode. The pixel electrode is connected to the third signal line through a first via.

[0015] According to any of the foregoing embodiments of the first aspect of this application, among two adjacent second power lines along the first direction, one is a first sub-power line and the other is a second sub-power line. The first sub-power line includes a functional block but does not include an auxiliary block, and the second sub-power line includes a functional block and an auxiliary block. A second via is provided between the power block of the first sub-power line and the first connection portion and / or the second connection portion, and the pixel electrode is interconnected with the third signal line through the second via.

[0016] According to any of the foregoing embodiments of the first aspect of this application, it further includes:

[0017] The fourth conductive layer is located on the side of the second conductive layer away from the substrate. The fourth conductive layer includes a pixel electrode. The orthographic projection of the pixel electrode along the thickness direction of the array substrate and the orthographic projection of the second power line along the thickness direction are at least partially overlapped.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of each power block along the thickness direction at least partially overlaps with the orthographic projection of each pixel electrode along the thickness direction.

[0019] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the power block along the thickness direction is centrally symmetrical about the center of the orthographic projection of the pixel electrode along the thickness direction.

[0020] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the power block along the thickness direction is located within the orthographic projection of the pixel electrode along the thickness direction.

[0021] According to any of the foregoing embodiments of the first aspect of this application, at least two pixel electrodes have different areas, at least two power blocks have different areas, and the area of ​​the power block is positively correlated with the area of ​​its corresponding pixel electrode.

[0022] According to any of the foregoing embodiments of the first aspect of this application, the orthographic projection of the first power line on the substrate and the orthographic projection of the second power line on the substrate at least partially overlap.

[0023] According to any of the foregoing embodiments of the first aspect of this application, the array substrate further includes a plurality of pixel circuits disposed on one side of the substrate, and the plurality of pixel circuits are arranged in columns along the second direction;

[0024] The first signal line is a first data line, and the second signal line is a second data line. The first data line and the second data line are used to provide data signals to multiple pixel circuits arranged in the same column along the second direction.

[0025] According to any of the foregoing embodiments of the first aspect of this application, in two adjacent pixel circuits in the second direction, the data signal of one pixel circuit is provided by a first data line, and the data signal of the other pixel circuit is provided by a second data line.

[0026] An embodiment of the second aspect of this application provides a display panel including an array substrate of any of the embodiments of the first aspect described above.

[0027] In the array substrate provided in this application embodiment, the array substrate includes a substrate and a first conductive layer and a second conductive layer disposed on the substrate. A first power line is disposed in the first conductive layer, and a first signal line, a second signal line, and a second power line located between the first signal line and the second signal line are disposed in the second conductive layer. The first power line and the second power line are connected by vias, which can increase the distribution area of ​​the power lines, thereby reducing the resistance of the power lines and mitigating the impact of insufficient driving voltage on the display panel, thus improving the display effect of the display panel. In addition, the second conductive layer is also provided with a first signal line and a second signal line disposed parallel to the second power line along a first direction, which can enrich the function of the second conductive layer. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0029] Figure 1 This is a top view of an array substrate provided in one embodiment of this application;

[0030] Figure 2 yes Figure 1 A partial sectional view;

[0031] Figure 3 This is a top view of an array substrate provided in another embodiment of this application;

[0032] Figure 4 This is a schematic diagram of the pixel circuit structure of an array substrate provided in one embodiment of this application;

[0033] Figure 5 yes Figure 1 A partially enlarged structural diagram.

[0034] Explanation of reference numerals in the attached figures:

[0035] 01. Substrate;

[0036] 02, First conductive layer; 210, First power line;

[0037] 03. Second conductive layer; 310. First signal line; 320. Second signal line; 330. Second power line; 330a. First sub-power line; 330b. Second sub-power line; 331. Power block; 331a. Functional block; 331b. Auxiliary block; 332. Connecting line; 332a. First connecting line; 332b. Second connecting line; 332c. Third connecting line; 340. First connecting part; 350. Second connecting part; 360. First via part; 370. Second via part;

[0038] 04. Third conductive layer; 410. Third signal line;

[0039] 05. Fourth conductive layer; 510. Pixel electrode;

[0040] X, first direction; Y, second direction; Z, thickness direction. Detailed Implementation

[0041] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0042] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0043] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0044] This application provides an array substrate and a method for fabricating the same. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the array substrate and its fabrication method.

[0045] This application provides an array substrate that can be used for a display panel, which may be an organic light-emitting diode (OLED) display panel.

[0046] Please see Figure 1 and Figure 2 , Figure 1 This is a top view of a partial layer structure of an array substrate provided in one embodiment of this application. Figure 2 yes Figure 1 A partial sectional view.

[0047] like Figure 1 and Figure 2 As shown, an embodiment of the first aspect of this application provides an array substrate, which includes a substrate 01, a first conductive layer 02, and a second conductive layer 03. The first conductive layer 02 is located on one side of the substrate 01 and includes a first power line 210. The second conductive layer 03 is located on the side of the first conductive layer 02 away from the substrate 01 and includes a first signal line 310, a second signal line 320, and a second power line 330 located between the first signal line 310 and the second signal line 320, wherein the first power line 210, the first signal line 310, the second signal line 320, and the second power line 330 are all extended along the second direction Y and are connected by vias.

[0048] In the array substrate provided in this application embodiment, the array substrate includes a substrate 01 and a first conductive layer 02 and a second conductive layer 03 disposed on the substrate 01. A first power line 210 is disposed in the first conductive layer 02, and a first signal line 310, a second signal line 320, and a second power line 330 located between the first signal line 310 and the second signal line 320 are disposed in the second conductive layer 03. The first power line 210 and the second power line 330 are connected by vias, which can increase the distribution area of ​​the power lines, thereby reducing the resistance of the power lines, improving the impact of insufficient driving voltage on the display panel, and thus improving the display effect of the display panel. In addition, the second conductive layer 03 is also provided with the first signal line 310 and the second signal line 320 arranged side by side with the second power line 330 along the first direction X, which can enrich the function of the second conductive layer 03.

[0049] Please refer to the following: Figures 1 to 3 , Figure 3 This is an enlarged structural schematic diagram of an array substrate provided in another embodiment of this application. Figure 3 and Figure 1 The difference lies in the addition of a conductive layer, including pixel electrodes 510, to the array substrate.

[0050] Optionally, the display panel includes an array substrate and a light-emitting layer located on the array substrate. The light-emitting layer includes a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked sequentially. The pixel electrode 510 can be an anode or a cathode.

[0051] The second power line 330 is located between the first signal line 310 and the second signal line 320. The orthographic projection of the second power line 330 along the thickness direction Z of the array substrate overlaps with the orthographic projection of the pixel electrode 510 located on it along the thickness direction Z of the array substrate. By adjusting the shape of the second power line 330, the flatness of the pixel electrode 510 can be improved, thereby mitigating the color shift problem caused by the pixel electrode 510 reflecting the light emitted by the light-emitting layer in various directions, and thus improving the display effect of the display panel.

[0052] Optionally, an insulating layer is provided between the first conductive layer 02 and the second conductive layer 03 to prevent short-circuit connections between the traces of the first conductive layer 02 and the second conductive layer 03. In the embodiments of this application, an insulating layer is provided between adjacent conductive layers to prevent short-circuit connections, which will not be elaborated further here.

[0053] The substrate 01 can be a flexible substrate or a rigid substrate. For example, the material of the substrate 01 can include flexible materials such as polyimide, or rigid materials such as glass. Other films can also be disposed between the first conductive layer 02 and the substrate 01, as long as the first conductive layer 02 is located on one side of the substrate 01. The material of the first conductive layer 02 can include a metallic material, giving the first power line 210 good conductivity. The material of the second conductive layer 03 can also include a metallic material, giving the first signal line 310, the second signal line 320, and the second power line 330 good conductivity.

[0054] There are various ways to configure the first signal line 310 and the second signal line 320. In some optional embodiments, the first signal line 310 is a first data line and the second signal line 320 is a second data line. The array substrate also includes a plurality of pixel circuits disposed on one side of the substrate 01. The plurality of pixel circuits are arranged in a column along the second direction Y. The first data line and the second data line are used to provide data signals to the plurality of pixel circuits arranged in the same column along the second direction Y.

[0055] like Figure 4 As shown, the data line is used to send data signals to the pixel circuits. In an optional embodiment, in two adjacent pixel circuits in the same column, the data signal of one pixel circuit is provided by the first data line, and the data signal of the other pixel circuit is provided by the second data line. This reduces the number of pixel circuits that need to be driven by the same data line, thereby reducing the data signal transmission time on the data signal line, reducing latency, and increasing the power supply time of individual sub-pixels.

[0056] In these alternative embodiments, multiple pixel circuits in the same column can transmit data signals via two data lines, a first data line and a second data line, which can extend the charging time of a single pixel circuit and improve the display effect of the display panel.

[0057] In some optional embodiments, the array substrate further includes a fourth conductive layer 05, which is located on the side of the second conductive layer 03 away from the substrate 01, and includes a pixel electrode 510.

[0058] The first data line and the second data line correspond to the same column of pixel circuits. Therefore, the first data line and the second data line can correspond to the same column of pixel electrodes 510. The orthographic projection of the second power line 330 located between the first data line and the second data line along the thickness direction Z at least partially overlaps with the orthographic projection of the pixel electrode 510 along the thickness direction Z. The distribution of the second power line 330 affects the surface shape of the insulating layer on it, and thus affects the flatness of the pixel electrode 510. Therefore, by reasonably setting the distribution of the second power line 330, the flatness of the pixel electrode 510 can be improved, which is beneficial to improving the display effect. For example, improving the flatness of the pixel electrode 510 can improve the display effect of the display panel caused by the unevenness of the pixel electrode 510 reflecting the light emitted by the light-emitting layer.

[0059] In these optional embodiments, the second conductive layer 03 and the fourth conductive layer 05 are closer together. For example, when the pixel electrode 510 is fabricated after an insulating layer is fabricated on the second conductive layer 03, the flatness of the second conductive layer 03 facing the surface of the insulating layer will affect the flatness of the pixel electrode 510 surface on the insulating layer. The distribution of the first signal line 310, the second signal line 320, and the second power line 330 will also affect the flatness of the insulating layer surface, thus indirectly affecting the flatness of the pixel electrode 510. The orthographic projections of the pixel electrode 510 and the second power line 330 at least partially overlap, enabling the second power line 330 to improve the flatness of the pixel electrode 510.

[0060] Furthermore, by placing the first signal line 310 and the second signal line 320 within a conductive layer that is close to the pixel electrode 510, the distance between the first signal line 310 and the second signal line 320 and other signal lines in the array substrate along the thickness direction Z can be increased, thereby reducing parasitic circuits caused by the overlap of the first signal line 310 and the second signal line 320 with other signal lines and ensuring the stability of signal transmission.

[0061] There are several ways to set the second power line 330. Optionally, the second power line 330 can extend along the second direction Y and be set with equal width.

[0062] In some other alternative embodiments, such as Figure 3As shown, the second power line 330 includes a plurality of power blocks 331 spaced apart along the second direction Y and a connecting line 332 connecting two adjacent power blocks 331, wherein the extension width of the connecting line 332 in the first direction X is smaller than the width of the power block 331 in the first direction X.

[0063] In these optional embodiments, the second power line 330 includes a power block 331 and a connecting line 332. The power block 331 has a larger width, which can increase the distribution area of ​​the second power line 330, reduce the resistance of the second power line 330, and thus increase the driving voltage, thereby improving the display effect of the display panel.

[0064] Furthermore, by appropriately positioning the power block 331 and the connecting line 332, the orthographic projection of the power block 331 along the thickness direction Z of the array substrate can overlap with the orthographic projection of the pixel electrode 510 along the thickness direction Z of the array substrate. Since the orthographic projection area of ​​the power block 331 along the thickness direction Z of the array substrate is relatively large, the overlap area between the orthographic projection of the power block 331 and the orthographic projection of the pixel electrode 510 along the thickness direction Z can be increased. By appropriately positioning the shape of the power block 331, the flatness of the pixel electrode 510 can be indirectly affected, thereby better improving the problem of unevenness in the pixel electrode 510. Similarly, by appropriately positioning the connecting line 332, the problem of short-circuit connections between the second power line 330 and the first signal line 310 and the second signal line 320 can also be improved.

[0065] The power block 331 can be configured in various ways. Its orthographic projection onto the substrate 01 can be circular, semi-circular, polygonal, or irregular. Optionally, the orthographic projection of the power block 331 onto the substrate 01 can be a rectangle, square, rhombus, or other quadrilateral. The shape of the orthographic projection of the power block 331 onto the substrate 01 is not limited here; it can be set according to actual requirements.

[0066] When the second power line 330 includes a connecting line 332 and a power block 331, the orthographic projection of the connecting line 332 and / or the power block 331 along the thickness direction Z overlaps at least partially with the orthographic projection of the pixel electrode 510 along the thickness direction Z.

[0067] Optionally, the orthographic projection of each power block 331 along the thickness direction Z at least partially overlaps with the orthographic projection of each pixel electrode 510 along the thickness direction Z. The power block 331 has a larger distribution area, and the overlap between the power block 331 and the pixel electrode 510 can better improve the problem of unevenness of the pixel electrode 510.

[0068] Optionally, the orthographic projection of the power supply block 331 along the thickness direction Z is centrally symmetrical about the center of the orthographic projection of the pixel electrode 510 along the thickness direction Z. The center of the orthographic projection of the pixel electrode 510 along the thickness direction Z can be the geometric center of the orthographic projection of the pixel electrode 510 along the thickness direction Z. The centrally symmetrical arrangement of the orthographic projection of the power supply block 331 along the thickness direction Z about this geometric center makes the flatness of different positions on the periphery of the pixel electrode 510 more similar, thus better mitigating the impact of unevenness of the pixel electrode 510 on the display effect.

[0069] Optionally, at least a portion of the power block 331 satisfies the following condition: the orthographic projection of the power block 331 along the thickness direction Z is located within the orthographic projection of the pixel electrode 510 along the thickness direction Z, so that the power block 331 can better improve the impact of the unevenness of the pixel electrode 510 on the display effect.

[0070] For example, the center of the orthographic projection of the power block 331 along the thickness direction Z overlaps with the center of the orthographic projection of the pixel electrode 510 along the thickness direction Z, so that the power block 331 can better improve the impact of the unevenness of the pixel electrode 510 on the display effect.

[0071] The array substrate includes multiple pixel electrodes 510, and the area dimensions of each pixel electrode 510 may be the same or different. For example, when the array substrate is used for a display panel, and the display panel includes multiple sub-pixels, the distribution areas of the multiple sub-pixels may be the same or different. For example, in some embodiments, the sub-pixels of the display panel include red sub-pixels, blue sub-pixels, and green sub-pixels. The distribution area of ​​the blue sub-pixels may be larger, while the distribution area of ​​the green sub-pixels may be smaller. Correspondingly, the orthogonal projection area of ​​the pixel electrode 510 of the blue sub-pixel along the thickness direction Z is larger than the orthogonal projection area of ​​the pixel electrode 510 of the green sub-pixel along the thickness direction Z.

[0072] When the projected areas of the two pixel electrodes 510 along the thickness direction Z are not the same, the projected areas of the power blocks 331 corresponding to the two pixel electrodes 510 along the thickness direction Z can be the same or different.

[0073] In some optional embodiments, at least two pixel electrodes 510 have different areas, at least two power blocks 331 have different areas, and the area of ​​the power block 331 is positively correlated with the area of ​​its corresponding pixel electrode 510. For example, the pixel electrode 510 includes a first pixel electrode and a second pixel electrode, and the power block 331 includes a first power block and a second power block. The orthographic projection of the first power block along the thickness direction Z at least partially overlaps with the orthographic projection of the first pixel electrode along the thickness direction Z, and the orthographic projection of the second power block along the thickness direction Z at least partially overlaps with the orthographic projection of the second pixel electrode along the thickness direction Z. That is, the first power block corresponds to the first pixel electrode, and the second power block corresponds to the second pixel electrode. When the orthographic projection area of ​​the first pixel electrode along the thickness direction Z is greater than the orthographic projection area of ​​the second pixel electrode along the thickness direction Z, the orthographic projection area of ​​the first power block along the thickness direction Z is greater than the orthographic projection area of ​​the second power block along the thickness direction Z.

[0074] In these optional embodiments, pixel electrodes 510 of different areas correspond to power blocks 331 of different areas, and the area of ​​power block 331 and its corresponding pixel electrode 510 are positively correlated, which can better and more specifically improve the flatness of the pixel electrode 510 corresponding to the power block 331, and better improve the display effect of the display panel.

[0075] Please refer to the following: Figures 1 to 4 , Figure 5 yes Figure 1 A partially enlarged structural diagram.

[0076] In some alternative embodiments, such as Figures 1 to 5 As shown, the second conductive layer 03 further includes a first connecting portion 340 and a second connecting portion 350. The first connecting portion 340 is connected to the first signal line 310 and located between the first signal line 310 and the second signal line 320; the second connecting portion 350 is connected to the second signal line 320 and located between the first signal line 310 and the second signal line 320. Of the two connecting lines 332 located on both sides of the same power block 331 in the second direction Y and connected thereto, one is the first connecting line 332a and the other is the second connecting line 332b. The first connecting line 332a extends between the first connecting portion 340 and the second signal line 320, and the second connecting line 332b extends between the second connecting portion 350 and the first signal line 310. When the first signal line 310 is a first data line and is used to transmit data signals to the pixel circuit, the first connecting portion 340 is used, for example, to connect the first signal line 310 and the pixel circuit driven by the first signal line 310. Similarly, when the second signal line 320 is a second data line and the second data line is used to transmit data signals to the pixel circuit, the second connection part 350 can be used to connect the second signal line 320 and the pixel circuit driven by the second signal line 320.

[0077] In these optional embodiments, the second conductive layer 03 includes a first connecting portion 340 and a second connecting portion 350. The first connecting portion 340 is connected to the first signal line 310 and located between the first signal line 310 and the second signal line 320, i.e., there is a first gap between the first connecting portion 340 and the second signal line 320. The second connecting portion 350 is connected to the second signal line 320 and located between the first signal line 310 and the second signal line 320, i.e., there is a second gap between the first connecting portion 340 and the first signal line 310. Since the first connecting portion 340 is connected to the first signal line 310, the first gap is disposed closer to the second signal line 320, and similarly, the second gap is disposed closer to the first signal line 310. A first connecting line 332a and a second connecting line 332b are provided on both sides of the same power block 331. The first connecting line 332a extends between the first connecting part 340 and the second signal line 320, that is, the first connecting line 332a extends through the first gap. The second connecting line 332b is provided between the second connecting part 350 and the second signal line 320, and extends through the second gap, which can better ensure the insulation between the second power line 330 and the first signal line 310 and the second signal line 320.

[0078] There are multiple ways to set the connection positions of the first connecting line 332a and the second connecting line 332b with the power block 331. For example, the first connecting line 332a and the second connecting line 332b can be connected to the same side of the power block 331 in the first direction X.

[0079] In some alternative embodiments, the first connection line 332a is connected to the side of the power block 331 facing the second signal line 320, and the second connection line 332b is connected to the side of the power block 331 facing the first signal line 310.

[0080] In these alternative embodiments, on the one hand, when the first connecting line 332a is located on the side of the power block 331 facing the second signal line 320, the first connecting line 332a can pass between the second signal line 320 and the first connecting portion 340 along a relatively straight extension path, which simplifies the shape of the first connecting line 332a. Similarly, the second connecting line 332b is connected to the side of the power block 331 facing the first signal line 310, which also simplifies the shape of the second connecting line 332b and facilitates the fabrication of the first connecting line 332a and the second connecting line 332b. On the other hand, the first connecting line 332a and the second connecting line 332b are connected on opposite sides of the power block 331, and the first connecting line 332a and the second connecting line 332b are arranged relatively symmetrically with respect to the power block 331, which can better improve the unevenness problem of the pixel electrode 510.

[0081] In some alternative embodiments, such as Figures 1 to 5 As shown, multiple second power lines 330 are spaced apart along the first direction X. At least one second power line 330's power block 331 includes a functional block 331a and an auxiliary block 331b. Optionally, the orthographic projection of the functional block 331a along the thickness direction Z and the orthographic projection of the pixel electrode 510 along the thickness direction Z at least partially overlap. The distribution area and position of the functional block 331a indirectly affect the flatness of the pixel electrode 510; that is, the functional block 331a has the function of adjusting the flatness of the pixel electrode 510. The auxiliary block 331b is used to assist in increasing the distribution area of ​​the power block 331, thereby increasing the distribution area of ​​the second power lines 330 and reducing the resistance of the second power lines 330. The connecting line 332 of the second power lines 330 also includes a third connecting line 332c. The auxiliary block 331b and the functional block 331a are spaced apart along the second direction Y and interconnected through the third connecting line 332c. The third connecting line 332c may be located closer to the second signal line 320 of the first signal line 310 and the second signal line 320, or the third connecting line 332c may also be located closer to the first signal line 310 of the first signal line 310 and the second signal line 320.

[0082] A power block 331 may include one or more functional blocks 331a, and / or, a power block 331 may include one or more auxiliary blocks 331b. If the auxiliary blocks 331b and functional blocks 331a of a power block 331 need to be connected via multiple third connection lines 332c, then the multiple third connection lines 332c may be located on the same side. Specifically, compared to the second signal line 320, the multiple third connection lines 332c are all located closer to the first signal line 310; or, compared to the first signal line 310, the multiple third connection lines 332c are all located closer to the second signal line 320. Furthermore, the multiple third connection lines 332c may also be located on different sides; for example, some third connection lines 332c are located closer to the first signal line 310, and other third connection lines 332c are located closer to the second signal line 320.

[0083] The second conductive layer 03 may further include a first via 360 disposed between the auxiliary block 331b and the functional block 331a; the array substrate further includes a third conductive layer 04 and a fourth conductive layer 05 as described above, the third conductive layer 04 and the fourth conductive layer 05 being disposed on opposite sides of the second conductive layer 03, that is, the third conductive layer 04 is located on the side of the second conductive layer 03 facing the substrate 01, and the fourth conductive layer 05 is located on the side of the second conductive layer 03 away from the substrate 01. The third conductive layer 04 includes a third signal line 410, and at least one pixel electrode 510 of the fourth conductive layer 05 is connected to the third signal line 410 through the first via 360.

[0084] The third signal line 410 can be configured in various ways. For example, in the pixel circuit of the array substrate, the transistor TFT includes a semiconductor part, a gate, a source, and a drain, and the third signal line 410 can be either the source or the drain. Alternatively, the third signal line 410 can be a bridge line used to connect the pixel electrode 510 to the source or drain.

[0085] There are several ways to arrange the relative positions of the third conductive layer 04 and the first conductive layer 02. The third conductive layer 04 can be located on the side of the first conductive layer 02 facing the substrate 01, or the third conductive layer 04 can be located between the first conductive layer 02 and the second conductive layer 03, or the third conductive layer 04 and the first conductive layer 02 can be reused.

[0086] In these optional embodiments, the power supply block 331 is divided into an auxiliary block 331b and a functional block 331a. The auxiliary block 331b and the functional block 331a are interconnected via a third connecting line 332c. A first via 360 is provided between the auxiliary block 331b and the functional block 331a. That is, the power supply block 331 is located between the functional block 331a and the auxiliary block 331b to provide space for the first via 360. This allows the pixel electrode 510 to connect to the third signal line 410 through the first via 360.

[0087] There are several ways to set up the second power line 330. For example, the shape and setting method of the second power lines 330 arranged side by side at intervals along the first direction X can be the same.

[0088] In some other alternative embodiments, such as Figure 5 As shown, the shapes of two adjacent second power lines 330 along the first direction X are different. For example, among the two adjacent second power lines 330 along the first direction X, one is a first sub-power line 330a and the other is a second sub-power line 330b. The first sub-power line 330a includes the aforementioned functional block 331a but does not include the auxiliary block 331b, while the second sub-power line 330b includes both the aforementioned functional block 331a and the auxiliary block 331b. That is, among the two adjacent second power lines 330, the power block 331 of one is integrally formed, while the power block 331 of the other is divided into a functional block 331a and an auxiliary block 331b. In the first sub-power line 330a that does not include the auxiliary block 331b, a second via portion 370 is provided between the power block 331 and the first connecting portion 340 and / or the second connecting portion 350. The pixel electrode 510 is interconnected with the third signal line 410 through the second via portion 370, and the second via portion 370 is located in the second conductive layer 03.

[0089] As can be seen from the above, both the first via 360 and the second via 370 are used to connect the pixel electrode 510 to the third signal line 410. The difference between them is that the first via 360 and the second via 370 are positioned differently. The first via 360 is located in the column where the second sub-power line 330b is located, while the second via 370 is located in the column where the first sub-power line 330a is located. Therefore, the first via 360 is used to connect the pixel electrode 510 in the column where the second sub-power line 330b is located to the third signal line 410, and the second via 370 is used to connect the pixel electrode 510 in the column where the first sub-power line 330a is located to the third signal line 410. In these optional embodiments, the shapes of two adjacent second power lines 330 along the first direction X are different, and the corresponding connection positions of the pixel electrode 510 and the third signal line 410 are different. (Continue to refer to...) Figure 3 and Figure 5 In the example shown, the pixel electrode 510 includes a first pixel electrode 510a and a second pixel electrode 510b adjacent to each other along the first direction X. The orthographic projection of the first pixel electrode 510a along the thickness direction Z at least partially overlaps with the orthographic projection of the power block 331 of the first sub-power line 330a along the thickness direction Z. The orthographic projection of the second pixel electrode 510b and the functional block 331a of the second sub-power line 330b along the thickness direction Z at least partially overlap. The first pixel electrode 510a and the second pixel electrode 510b are connected to different third signal lines 410. The first pixel electrode 510a is connected to the third signal line 410 through the second via portion 370, and the second pixel electrode 510b is connected to the third signal line 410 through the first via portion 360. The reasonable arrangement of the positions of the first connecting portion 340, the second connecting portion 350, the first via portion 360, the second via portion 370, the first sub-power line 330a, and the second sub-power line 330b facilitates the realization of each function.

[0090] In the above embodiments, the second power line 330 may include alternately arranged first sub-power lines 330a and second sub-power lines 330b. In other embodiments, the second power line 330 may include only the first sub-power line 330a. In still other embodiments, the second power line 330 may include only the second sub-power line 330b.

[0091] Optionally, the projected area of ​​a power block 331 of the first sub-power line 330a along the thickness direction Z is larger than the projected area of ​​a functional block 331a of the second sub-power line 330b along the thickness direction Z, and the projected area of ​​a first pixel electrode 510 along the thickness direction Z is larger than the projected area of ​​a second pixel electrode 510 along the thickness direction Z. That is, for pixel electrodes 510 of different sizes, the power blocks 331 of the first sub-power line 330a and the second sub-power line 330b are designed with different dimensions, which can better improve the unevenness problem of the first pixel electrode 510 and the second pixel electrode 510.

[0092] In some optional embodiments, the orthographic projection of the first power line 210 on the substrate 01 at least partially overlaps with the orthographic projection of the second power line 330 on the substrate 01. This ensures that the distance between each first power line 210 and each second power line 330 is relatively short, facilitating the interconnection of the first power lines 210 and the second power lines 330. In any of the above embodiments, the first connecting line 332a and the second connecting line 332b can be arranged in various shapes, as long as both the first connecting line 332a and the second connecting line 332b can connect to adjacent power blocks 331.

[0093] For example, in the first sub-power line 330a, the first connecting line 332a and the second connecting line 332b can be arranged along a straight path. The first connecting line 332a is located on the side of the power block 331 of the first sub-power line 330a near the second signal line 320, and the second connecting line 332b is located on the side of the power block 331 of the first sub-power line 330a near the first signal line 310. Arranging the first connecting line 332a and the second connecting line 332b along a straight path simplifies their shapes and facilitates their fabrication.

[0094] Optionally, there may be multiple second vias 370, which may be located between the power block 331 of the first sub-power line 330a and the first connecting portion 340 and / or the second connecting portion 350. Optionally, the number of second vias 370 is the same as the number of power blocks 331 in the first sub-power line 330a, and each power block 331 is provided with a second via 370 on one side in the second direction Y, so as to increase the connection area between the first power line 210 and the first sub-power line 330a.

[0095] Optionally, in the second sub-power line 330b, the shape of the third connecting line 332c can be set in various ways. For example, the third connecting line 332c can be set to extend along a straight path to simplify the shape of the third connecting line 332c.

[0096] Optionally, the areas of functional block 331a and auxiliary block 331b can be the same or different. For example, the orthographic projection area of ​​functional block 331a along the thickness direction Z is greater than the orthographic projection area of ​​auxiliary block 331b along the thickness direction Z. Functional block 331a is overlapped with pixel electrode 510. A larger area of ​​functional block 331a can better improve the unevenness of pixel electrode 510.

[0097] Optionally, the first connecting line 332a and / or the second connecting line 332b are used to connect the functional block 331a of one of two adjacent power blocks 331 with the auxiliary block 331b of the other. The shapes of the first connecting line 332a and the second connecting line 332b can be arranged in various ways. For example, if the auxiliary block 331b and the power block 331 are aligned along the second direction Y towards the edge of the second signal line 320, the first connecting line 332a can extend along a straight line to connect the functional block 331a of one of the two adjacent power blocks 331 with the auxiliary block 331b of the other, thus simplifying the shape of the first connecting line 332a. Alternatively, if the auxiliary block 331b and the power block 331 are misaligned along the second direction Y towards the edge of the first signal line 310, the second connecting line 332b extends along a bent path to connect the functional block 331a of one of the two adjacent power blocks 331 with the auxiliary block 331b of the other.

[0098] Optionally, in the second sub-power line 330b, the first connecting line 332a and the third connecting line 332c are aligned along the second direction Y to simplify the shape of the connecting line 332.

[0099] The second aspect of this application also provides a display panel including the array substrate of any of the first aspects of the above-described embodiments. Since the display panel provided by the second aspect of this application includes the array substrate described above, the display panel provided by the second aspect of this application has the beneficial effects of the array substrate described above, which will not be repeated here.

[0100] The display panel provided in this application embodiment can be at least one of an organic light-emitting diode display panel, a liquid crystal display panel, and a micro light-emitting diode display panel.

[0101] An embodiment of the third aspect of this application also provides a display device, including the display panel of any of the first aspect embodiments described above. Since the display device provided by the third aspect embodiment includes the display panel of any of the first aspect embodiments described above, the display device provided by the third aspect embodiment has the beneficial effects of the display panel of any of the second aspect embodiments described above, which will not be elaborated further here.

[0102] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0103] The embodiments described above are not exhaustive, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, include: Substrate; A first conductive layer is located on one side of the substrate, and the first conductive layer includes a first power line; A second conductive layer is located on the side of the first conductive layer facing away from the substrate. The second conductive layer includes a first signal line, a second signal line, and a second power line located between the first signal line and the second signal line, all spaced apart along a first direction. The first power line, the first signal line, the second signal line, and the second power line all extend along a second direction, and the first power line and the second power line are connected by vias. The second power line includes a plurality of power blocks spaced apart along the second direction and a connecting line connecting two adjacent power blocks, wherein the width of the connecting line in the first direction is smaller than the width of the power block in the first direction. The second conductive layer further includes: A first connecting portion is connected to the first signal line and located between the first signal line and the second signal line; The second connector is connected to the second signal line and located between the first signal line and the second signal line. The power block is located between the first connection portion and the second connection portion, which are adjacent to each other in the second direction. In this configuration, multiple second power lines are spaced apart along the first direction, and the power block of at least one second power line includes a functional block and an auxiliary block, wherein the orthographic projection area of ​​the functional block along the thickness direction is greater than the orthographic projection area of ​​the auxiliary block along the thickness direction.

2. The array substrate according to claim 1, characterized in that, Of the two connecting lines located on both sides of the same power block in the second direction and connected thereto, one is a first connecting line and the other is a second connecting line. The first connecting line extends between the first connecting portion and the second signal line, and the second connecting line extends between the second connecting portion and the first signal line.

3. The array substrate according to claim 2, characterized in that, The first connecting line is connected to the side of the power supply block facing the second signal line, and the second connecting line is connected to the side of the power supply block facing the first signal line.

4. The array substrate according to claim 2, characterized in that, The connecting line of the second power line also includes a third connecting line. The auxiliary block and the functional block are spaced apart in the second direction and connected to each other through the third connecting line. A first through hole is provided between the auxiliary block and the functional block. The array substrate further includes a third conductive layer and a fourth conductive layer, which are disposed on opposite sides of the second conductive layer. The third conductive layer includes a third signal line, and the fourth conductive layer includes a pixel electrode. The pixel electrode is connected to the third signal line through the first via.

5. The array substrate according to claim 4, characterized in that, Of the two adjacent second power lines along the first direction, one is a first sub-power line and the other is a second sub-power line. The first sub-power line includes the functional block but does not include the auxiliary block. The second sub-power line includes the functional block and the auxiliary block. A second via is provided between the power block of the first sub-power line and the first connection portion and / or the second connection portion. The pixel electrode is connected to the third signal line through the second via.

6. The array substrate according to claim 5, characterized in that, It also includes pixel electrodes, wherein the pixel electrodes include a first pixel electrode and a second pixel electrode that are adjacent to each other along a first direction, wherein the orthographic projection of the first pixel electrode along the thickness direction overlaps at least partially with the orthographic projection of the power block of the first sub-power line along the thickness direction, and the second pixel electrode overlaps at least partially with the orthographic projection of the functional block of the second sub-power line along the thickness direction. The projected area of ​​a power block of the first sub-power line along the thickness direction is greater than the projected area of ​​a functional block of the second sub-power line along the thickness direction, and the projected area of ​​a first pixel electrode along the thickness direction is greater than the projected area of ​​a second pixel electrode along the thickness direction.

7. The array substrate according to any one of claims 2 to 5, characterized in that, Also includes: A fourth conductive layer is located on the side of the second conductive layer away from the substrate. The fourth conductive layer includes a pixel electrode. The orthographic projection of the pixel electrode along the thickness direction of the array substrate at least partially overlaps with the orthographic projection of the second power line along the thickness direction.

8. The array substrate according to claim 7, characterized in that, The orthographic projection of each power block along the thickness direction at least partially overlaps with the orthographic projection of each pixel electrode along the thickness direction.

9. The array substrate according to claim 7, characterized in that, The orthographic projection of the power block along the thickness direction is centrally symmetrical about the center of the orthographic projection of the pixel electrode along the thickness direction.

10. The array substrate according to claim 7, characterized in that, The orthographic projection of the power block along the thickness direction lies within the orthographic projection of the pixel electrode along the thickness direction.

11. The array substrate according to claim 7, characterized in that, At least two of the pixel electrodes have different areas, at least two of the power blocks have different areas, and the area of ​​the power block is positively correlated with the area of ​​its corresponding pixel electrode.

12. The array substrate according to any one of claims 1 to 5, characterized in that, The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second power line on the substrate.

13. The array substrate according to any one of claims 1 to 5, characterized in that, The array substrate further includes a plurality of pixel circuits disposed on one side of the substrate, and the plurality of pixel circuits are arranged in columns along the second direction; The first signal line is a first data line, and the second signal line is a second data line. The first data line and the second data line are used to provide data signals to the plurality of pixel circuits arranged in the same column along the second direction.

14. The array substrate according to claim 13, characterized in that, In two adjacent pixel circuits in the second direction, the data signal of one pixel circuit is provided by the first data line, and the data signal of the other pixel circuit is provided by the second data line.

15. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-14.

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