Media scrubber in a memory system

Abstract

This application relates to media scrubbers in memory systems. A controller can count a number of forwarded codewords in a memory medium, e.g., during a scrub cycle. The controller can add the number to a total number of forwarded codewords in the memory medium. The controller can refrain from forwarding additional codewords based on the number. When a spare bit is allocated to an erroneous bit in a codeword, the controller can write a valid logic state to the spare bit. Individual memory cells can indicate a change in spare bit allocation and whether a spare bit contains a valid logic state. The controller can retrieve a codeword from a memory medium and invert one or more bits of the codeword before writing the codeword to the memory medium.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application. Its parent application is the invention patent application filed on July 23, 2019, with application number 201980057563.5 and invention title "Media Scrubber in a Memory System".

[0003] Cross-referencing

[0004] This patent application claims priority to PCT application No. PCT / US2019 / 043052, filed July 23, 2019, entitled “Media Scrubber in Memory System,” filed by Pawlowski. This PCT application claims priority to U.S. Patent Application No. 16 / 516,936, filed July 19, 2019, entitled “Media Scrubber in Memory System,” and U.S. Provisional Patent Application No. 62 / 702,765, filed July 24, 2018, entitled “Media Scrubber in Memory System.” Each of these U.S. patent applications is assigned to the assignee of this application, and each of these U.S. patent applications is expressly incorporated herein by reference in its entirety. Technical Field

[0005] This technical field relates to media flushers in memory systems. Background Technology

[0006] The following content generally relates to operating the memory subsystem or system, and more specifically to media flushing operations within the memory system.

[0007] A computing system may include a memory subsystem or system comprising various types of memory devices and controllers coupled to one or more buses to manage information in multiple electronic devices such as computers, wireless communication devices, the Internet of Things, cameras, and digital displays. Memory devices are widely used to store information in such electronic devices. Information is stored by programming different states of the memory device. For example, a binary device has two states, typically represented by logic "1" or logic "0". In other systems, memory devices can store more than two states. To access the stored information, components of the electronic device can read or retrieve the stored states from the memory device. To store information, components of the electronic device can write or program states into the memory device.

[0008] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, NAND flash memory, phase-change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory can maintain its logic state for extended periods even without external power. Volatile memory cells (e.g., DRAM cells) may lose their stored state over time when disconnected from external power.

[0009] Improving computing systems can include enhancing the performance of memory systems, such as reducing power consumption, increasing memory capacity and reliability, improving read / write speeds, providing non-volatility through the use of persistent memory media, or reducing manufacturing costs at a certain performance point, as well as other metrics. Summary of the Invention

[0010] A method is described. The method may include: identifying the value of a first counter associated with a memory medium, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords; setting the value of a second counter associated with the memory medium, at least in part based on the value identifying the first counter, the second counter indicating a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords; and receiving a first codeword from the memory medium, at least in part based on the value of the second counter.

[0011] Another method is described. The method may include: receiving a codeword reserved at a portion of a memory medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword; accessing a memory array of a port manager at least in part based on receiving the codeword; performing an error control operation on the codeword to restore the logical state of the plurality of bits at least in part based on accessing the memory array of the port manager; and writing the logical state of the bits of the plurality of bits at the spare bits in the number of spare bits at least in part based on performing the error control operation.

[0012] Another method is described. The method may include: receiving a codeword from an address of a memory medium, the codeword comprising a set of bits; inverting a portion of the set of bits based at least partially on receiving the codeword; setting values ​​of bits in the set of bits to indicate a codeword condition including an inverted state of the codeword based at least partially on inverting the portion of the set of bits; and writing the codeword back to the address of the memory medium based at least partially on setting the values ​​of the bits indicating the inverted state. Attached Figure Description

[0013] Figure 1 An example of a computing system that supports media flushing operations in a memory system according to the aspects disclosed herein is shown.

[0014] Figure 2 An example of a computing system that supports media flushing operations in a memory system according to the aspects disclosed herein is shown.

[0015] Figure 3 Examples of codeword formats supporting media scrubbing operations in a memory system, based on the aspects disclosed herein, are shown.

[0016] Figure 4 Examples of memory die configurations and memory media configurations supporting media flushing operations in a memory system, according to the aspects disclosed herein, are shown.

[0017] Figure 5 A block diagram of a device supporting media flushing operation in a memory system according to aspects disclosed herein is shown.

[0018] Figures 6 to 8 One or more methods for supporting media flushing operations in a memory system according to the aspects disclosed herein are demonstrated. Detailed Implementation

[0019] The performance of a computing system (e.g., a server containing a memory system or subsystem) can depend on various factors, such as providing reliable information to the computing system with low latency (e.g., load-to-use latency). In the context of a computing system or subsystem, the data carrying information can be referred to as a codeword. In some cases, a codeword may contain a certain amount of user data and additional bits (e.g., bits supporting error control operations) that carry various information to provide reliable user data with low latency. Codewords can be associated with components of the computing system, such as the memory media of the memory system or subsystem, and can be transmitted and received during one or more access operations or background operations, or both. Background operations in a computing system can refer to processes that run without external or user intervention (e.g., access commands from a host device).

[0020] In some cases, memory cells in one or more memory dies within a memory medium can support a limited number of access operations (e.g., read cycles, write cycles, or both) before becoming unreliable or problematic. In other cases, a memory cell can experience changes in its electrical characteristics (e.g., the memory cell's threshold voltage) after a period of no access operations. Such changes (e.g., an increase in the memory cell's threshold voltage) can adversely affect the memory cell's operating window, potentially increasing the memory medium's error rate, such as the raw bit error rate (RBER). When a memory cell becomes unreliable (e.g., due to the limited number of access operations it can support, or inherent changes in the electrical characteristics of a memory cell without access operations, or both), the information generated by the memory cell may become erroneous, less reliable, or invalid, and such memory cells (or the information generated by memory cells) can be referred to as erroneous bits. When a certain number of memory cells associated with a codeword generate erroneous bits, the codeword (e.g., user data within the codeword) may become erroneous, less reliable, or invalid beyond the error recovery capabilities of the memory system or subsystem.

[0021] In some cases, one or more spare bits in a codeword can be allocated to retrieve error bits from the codeword. In some cases, the overall instability of the codeword may necessitate configuring the codeword as a forwarding codeword pointing to a different address to retrieve reliable user data. In some cases, performing access operations (e.g., read operations, write operations) can mitigate undesirable changes in the electrical characteristics of the memory cell holding the codeword. Therefore, operations that can efficiently perform the various functions described herein (e.g., allocating one or more spare bits to retrieve error bits from the codeword, writing one or more spare bits with valid information to replace error bits supporting low latency operations, counting and monitoring the number of forwarding codewords held at the memory media, and periodically performing access operations on the set of codewords held at the memory media) can improve system reliability. In some cases, the various functions described herein may be referred to as media scrubbing operations and may be performed as part of one or more background operations to improve the overall performance of the computing system.

[0022] A controller (e.g., a port manager associated with the memory media) may, in some cases, count or monitor the number of forwarding codewords retained in the memory media as part of a media scrubbing operation. The controller may identify the value of a first counter associated with the memory media. This first counter may indicate the number of codewords configured as forwarding codewords during a scrubbing cycle (e.g., the duration for which a media scrubbing operation may be performed on the memory media). The controller may set (e.g., initially set, update) the value of a second counter associated with the memory media based on the value of the first counter, wherein the second counter may indicate the total number of forwarding codewords that can accumulate in the memory media during its lifetime. The lifetime of the memory media may refer to the estimated duration for which the memory media meets a set of operational criteria.

[0023] The controller can also reset the value of the first counter based on the value of the second counter before initiating the next flush cycle, to count an additional number of codewords configured as forwarding codewords in the next flush cycle. In this way, the controller can count the number of codewords configured as forwarding codewords during a given flush cycle and can accumulate the total number of forwarding codewords retained on the memory media throughout its lifetime. In some cases, the controller can avoid configuring additional codewords as forwarding codewords based on the number of forwarding codewords during a flush cycle or during the lifetime of the memory media.

[0024] The memory array of a memory die can be configured to contain a set of Minimum Replacement Regions (MSRs). An MSR can be configured as a reasonable fault-tolerant region for efficient management (e.g., replacement, substitution) of faulty bits in the memory array. In some cases, an MSR can contain a group of memory cells configured to be associated with error control operations. Further, each bit of a codeword (e.g., each of 1,408 bits in a codeword) can be associated with a corresponding MSR in the set (e.g., 1,408 MSRs). A group of MSRs spanning a set of channels across the memory medium (e.g., a group of MSRs operating in parallel) can hold a number of codewords. A group of MSRs configured to generate a number of codewords can be referred to as an MSR stripe or an MSR region. In some cases, an MSR stripe can be associated with bits (e.g., flags) in a separate memory array, wherein these bits can be configured to indicate changes in the replacement relationships (e.g., one or more indicators for the allocation of spare bits to replace one or more faulty bits) for a number of codewords held at the MSR stripe.

[0025] The controller may, in some cases as part of media flushing operations (e.g., during the first media flushing cycle for an MSR strip), allocate one or more spare bits (e.g., one or more MSRs corresponding to the spare bits) in a codeword to retrieve an error bit (e.g., the MSR corresponding to the error bit) in a codeword (e.g., one of a number of codewords held at the MSR strip). The controller may set bits (e.g., flags) in a separate memory array to indicate such changes in the replacement relationship associated with the codeword held at the MSR strip. Setting bits (e.g., flags) may also indicate that, although the replacement relationship of the spare bits may have been determined, the spare bits may not contain a valid logical state of the codeword.

[0026] The controller can, in some cases as part of media scrubbing operations (e.g., during a second media scrubbing cycle for an MSR stripe), access codewords, replace erroneous bits with one or more spare bits according to a replacement relationship stored in a separate memory array, and perform error control operations to restore the logical state of the codeword (e.g., a codeword containing the one or more spare bits that replaced the erroneous bit). The controller can write the restored logical state (e.g., a valid logical state) at the one or more spare bits and can reset bits (e.g., flags) in the separate memory array. In this way, the one or more spare bits can contain the valid logical state of the codeword, and the bits (e.g., flags) can indicate that the one or more spare bits contain the valid logical state to be implemented (multiplexed into the bit stream of the codeword with a series of data bursts) when the host requests the codeword.

[0027] In some cases, the controller can retrieve a codeword from the memory medium as part of a media flushing operation and invert at least some (if not all) of the bits in the codeword before writing it back to the memory medium. Writing the codeword back to the memory medium can mitigate undesirable changes in the electrical characteristics of the memory cell that holds the codeword—for example, drift in the threshold voltage of the memory cell that may occur during extended periods without access operations. Inverting the logic state of the memory cell (e.g., writing a logic "1" to a memory cell that holds logic "0" or vice versa) can further mitigate undesirable changes in the electrical characteristics of the memory cell.

[0028] The following will be Figure 1 The features of this disclosure introduced herein are further described in the context of an exemplary system. Then... Figures 2 to 4 The specific instances of the configuration of the system and its memory media are described within the context of this disclosure. These and other features of this disclosure are further illustrated by... Figure 5 The device diagram and Figures 6 to 8 The flowchart is shown and described with reference to it. The device diagram describes the various components related to the controller. The flowchart relates to the operation in the media flushing operation in the memory system.

[0029] Figure 1 An example of a computing system 100 supporting media flushing operations in a memory system according to aspects disclosed herein is illustrated. The computing system 100 may include a host device 105 coupled to device 140 via a host interface 115 (which may also be referred to as a host link). Among other instances, the host device 105 may be or include a server, a system-on-a-chip (SoC), a central processing unit (CPU), or a graphics processing unit (GPU). In some instances, the host device 105 may access (e.g., read from, write to) one or more memory media 130 located in device 140 via the host interface 115.

[0030] Host interface 115 (e.g., host link) may be compatible with or employ protocols (e.g., Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX) protocol) to facilitate access operations between host device 105 and the one or more memory media 130. Host interface 115 may be configured to transfer data in at least one direction (e.g., sending or receiving) at a first data transfer rate (e.g., 25 gigabytes per second (GBps)). In some instances, a 25 GBps data transfer rate can support approximately 586 million transactions per second when the transaction size is 64 bytes. In other instances, a 25 GBps data transfer rate can support approximately 312.5 million transactions per second when the transaction size is 128 bytes.

[0031] Device 140 may be referred to in some cases as a memory system or subsystem or a memory device. In some cases, device 140 may include a power management component. The power management component can monitor power levels that can indicate power changes or losses in relation to device 140 or computing system 100. In some cases, fluctuations in power levels may exceed normal ranges to indicate such power change or loss events. Device 140 may include a controller 120 that can be coupled to one or more memory media 130 via channel 125. In some cases, channel 125 may be referred to as aggregation channel 125, which includes, as referenced... Figure 2 Multiple other channels are described (e.g., channels with bandwidth less than aggregated channel 125). Device 140 may include non-volatile memory 131 coupled to controller 120 via channel 126. In some instances, controller 120, the one or more memory media 130 or non-volatile memory 131, or any combination thereof, may be integrated with, contact with, or placed on a board (e.g., a Fast Peripheral Component Interconnect (PCIe) board). In some cases, non-volatile memory 131 may be integrated as part of controller 120.

[0032] Controller 120 may include various functional blocks that facilitate the operation of device 140 in conjunction with one or more memory media 130. In some cases, power management components may be integrated as part of controller 120. In some cases, controller 120 may include aspects of an interface controller to accommodate different specifications, limitations, or characteristics associated with host interface 115, channel 125, channel 126, or any combination thereof. In some instances, controller 120 may be an ASIC, a general-purpose processor, other programmable logic devices, discrete hardware components (e.g., chiplets), or the controller may be a combination of components.

[0033] In some cases, the controller 120 can be combined to perform various operations (e.g., writing data to a memory cell, reading data from a memory cell, and according to a reference). Figure 3 The local controller (e.g., local to memory media 130-a) of the described codeword format (arranged codewords) reads data from or writes data to memory media 130 (e.g., memory media 130-a). In some instances, the local controller can send requested data to controller 120 via one of the channels 125, which may be an instance of aggregated channels.

[0034] Each memory medium (e.g., memory medium 130-a) may contain multiple memory dies (e.g., forty-four (44) memory dies) to achieve a specified or desired memory capacity for the memory medium. In some instances, the memory die may contain a three-dimensional cross-point array of memory cells containing chalcogenides (e.g., a 3DXP memory die containing 3D XPoint™ memory cells). In other instances, the memory die may contain other types of memory devices (e.g., FeRAM dies, MRAM dies, PCM dies). In some instances, a codeword (e.g., a codeword containing 128 bytes of user data) may be partitioned across the multiple memory dies within the memory medium (e.g., memory medium 130-a).

[0035] In some cases, each of the plurality of memory dies (e.g., each 3DXP memory die) may generate a certain amount of data (e.g., 128 bits of data) as a whole in association with an access operation (e.g., a read operation). This amount of data (e.g., 128 bits of data) may comprise a series of bursts (e.g., sixteen (16) bursts), each burst containing a certain amount of data (e.g., eight (8) bits of data) transferred from the memory die on a bus (e.g., an 8-bit wide bus). As an example, when the memory medium contains eleven (11) memory dies operating in parallel, and when each of the eleven (11) memory dies generates eight (8) bits of data at a given burst, the memory medium may generate 88 bits of data for a given burst. Since eleven (11) memory dies can generate data on a total of sixteen (16) bursts, each burst containing 88 bits of data from the eleven (11) memory dies, a data unit associated with the memory medium during an access operation—for example, a data unit transferred on a channel (e.g., a converged channel)—can contain 1,408 bits.

[0036] Therefore, in this example, the codeword associated with the memory medium (e.g., a data unit during a transaction of an access operation) can contain 1,408 bits. In some cases, the burst can be referred to as a channel burst or a data burst. In some cases, the channel between the controller 120 and the memory medium (e.g., memory medium 130-a) can contain multiple channels, each of which is as described in the reference... Figure 3 and 4 The description may be associated with one or more memory dies of a memory medium (e.g., memory medium 130-a).

[0037] Memory media (e.g., memory media 130-a) may contain a collection of memory dies, each containing a memory array. Each memory die in the collection (e.g., each memory array) may be configured to contain a set of MSRs, as referenced. Figure 4 As described, an MSR can be configured to efficiently manage (e.g., replace, substitute) a reasonable fault-tolerant region for fault bits in a memory array. Additionally, at least some (if not every) of the MSRs in the set can be associated with a counter configured to count the number of fault bits in the MSRs of the set.

[0038] Channel 125 can be configured to transmit data (e.g., codewords) between controller 120 and one or more memory media 130. Each channel in channel 125 (e.g., channel 125-a, which may be an instance of an aggregated channel) may contain multiple other channels (e.g., channels with bandwidth less than channel 125-a) for parallel transmission of data (e.g., codewords). In some cases, a codeword may contain user data (e.g., 128 bytes of user data in the codeword) and other datasets (e.g., remaining data in the codeword for generating reliable data with low latency). Each channel in channel 125 (e.g., channel 125-a, which may be an instance of an aggregated channel) may contain additional channels to carry information related to various auxiliary functions, such as metadata. In some cases, a codeword format (which may also be referred to as a codeword layout) or a forwarded codeword format (e.g., a forwarded codeword layout) may define how each channel in channel 125 (e.g., channel 125-a) can transmit data (e.g., codewords) between controller 120 and one or more memory media 130.

[0039] Non-volatile memory 131 may comprise an array of non-volatile memory cells that can maintain their logical state for extended periods of time, even without external power. For example, among other instances, the non-volatile memory cells may be or may comprise 3D XPoint™ memory cells, PCM cells, FeRAM cells, or NAND memory cells. Additionally, non-volatile memory 131 may be configured to transmit information to controller 120 via channel 126. For example, non-volatile memory 131 may receive information from controller 120 via channel 126 and retain information when a power change or loss related to computing system 100 is detected.

[0040] In some cases, the memory subsystem or system that may include device 140 may include a power management component for managing power change or loss events. The power management component may be operable to detect indications of power change or loss (e.g., an indication of a potential power change or loss level) and transmit the indication of power change or loss to controller 120. Upon receiving the indication, controller 120 may transfer information stored in a memory array (e.g., an SRAM memory array) within controller 120 (e.g., an indication of an error state associated with a codeword, one or more indications of spare bit allocation to an error bit) to non-volatile memory 131. Non-volatile memory 131 may store information such that it can be retained even without a power supply to the memory subsystem or system, which may include device 140. When power to computing system 100 is restored or otherwise adjusted, controller 120 may retrieve information from non-volatile memory 131 based on the information stored therein to continue operation interrupted by the power change or loss event.

[0041] A controller (e.g., controller 120) may, in some cases, count the number of forwarding codewords retained in a memory medium (e.g., memory medium 130-a) as part of a media scrubber operation. A forwarding codeword may contain a number of copies of the codeword's forwarding address, as referenced. Figure 3 As described, controller 120 can identify the value of a first counter associated with the memory media. The first counter can indicate the number of codewords configured to be forwarded during a flushing cycle (e.g., the duration for which a media flushing operation can be performed on the memory media). The controller can set (e.g., initially set, update) the value of a second counter associated with the memory media based on the value of the first counter, wherein the second counter can indicate the total number of forwarded codewords that can accumulate in the memory media during its lifetime. The lifetime of the memory media can refer to the estimated duration for which the memory media meets a set of operational criteria—e.g., among other instances, a pre-configured ratio between the raw bit error rate (RBER) associated with the memory die contained in the memory media, the number of forwarded codewords and the total number of codewords retained in the memory media, or the load-to-use latency.

[0042] Controller 120 may also receive the first codeword from the memory media based on the value of a second counter. In some cases, controller 120 may initiate the next scrubbing cycle by receiving the first codeword from the memory media. In some cases, controller 120 may also reset the value of the first counter based on the value of the second counter before initiating the next scrubbing cycle to count another number of codewords configured to be forwarded during the next scrubbing cycle. The cycle may be the duration of a pre-configured cycle for scrubbing a set of codewords retrieved from the memory media. For example, a pre-configured cycle for performing one or more media scrubbing operations may correspond to several hours. In some cases, controller 120 may receive the first codeword as part of a periodic background operation (e.g., a media scrubbing operation) independent of access commands from the host.

[0043] In this way, controller 120 can count the number of codewords configured as forwarding codewords during a given flush cycle and can accumulate the total number of forwarding codewords retained on the memory medium (e.g., memory medium 130-a) over its lifetime. In some cases, the controller can avoid configuring additional codewords as forwarding codewords based on the number of forwarding codewords during a flush cycle or over the lifetime of the memory medium.

[0044] Figure 2 An example of a computing system 200 supporting media flushing operation in a memory system according to the aspects disclosed herein is shown. The computing system 200 may be a reference. Figure 1 An example of the described computing system 100. The computing system 200 may include a host device 205, which is coupled to a memory subsystem or system 220 using at least one host interface (e.g., host interface 215-a). In some cases, host interface 215 may be referred to as one or more host links. Host device 205 may be a reference... Figure 1 An example of the described host device 105. The host interface 215 may be a reference. Figure 1 An example of the described host interface 115. In some instances, host interface 215 may be configured to transmit data at a first data transfer rate (e.g., 50 GBps, of which 25 GBps are in each direction).

[0045] The computing system 200 may include a memory subsystem or system 220. The memory subsystem or system 220 may be a reference... Figure 1An example of the described device 140. The memory subsystem or system 220 may be referred to as one or more memory devices. The memory subsystem or system 220 may include a controller 230. In some cases, the memory subsystem or system 220 may include a power management component. The power management component can monitor power levels that can indicate power changes or losses related to the memory subsystem or system 220 or the computing system 200. In some cases, fluctuations in power levels may exceed normal ranges to indicate such power change or loss events. The controller 230 may be a reference... Figure 1 An example of the controller 120 described. Controller 230 may include interface component 210 and multiple port managers 260. In some cases, power management components may be integrated as part of controller 230.

[0046] Interface component 210 can be configured to facilitate data exchange between host device 205 and memory subsystem or system 220 via host interface 215. Interface component 210 can be configured to exchange data with the plurality of port managers 260 (e.g., using signal path 250). Each signal path in signal path 250 can be configured to exchange data at a rate different from a first data transfer rate of host interface 215 (e.g., 12.8 GBps). In some cases, interface component 210 can be configured to provide routing network functionality to allow more than one host interface (e.g., host interface 215-a and host interface 215-b) to be associated with the plurality of port managers 260.

[0047] The memory subsystem or system 220 may include non-volatile memory 296. Non-volatile memory 296 may be configured to transmit information to controller 230 via channel 292. Non-volatile memory 296 may be a reference. Figure 1 An example of the described non-volatile memory 131. Furthermore, channel 292 may be a reference. Figure 1 The described channel 126 may include instances or aspects of the channel. Furthermore, the non-volatile memory 296 may be configured to transmit information with the port manager 260 in the controller 230. For example, the port manager 260 may pass various information (e.g., indications of error states associated with codewords, one or more indications of spare bit allocation to error bits) to the non-volatile memory 296 via channel 292 and store information in the non-volatile memory 296 when the port manager 260 receives indications of power changes or losses related to the computing system 200 or the memory subsystem or system 220. In some cases, the non-volatile memory 296 may be integrated as part of the controller 230.

[0048] Each of the plurality of port managers 260 (e.g., port manager 260-b) can be coupled to a memory medium (e.g., memory medium 295-b) via an aggregation channel (e.g., aggregation channel 290-b). In some cases, each of the plurality of port managers can be coupled to one or more different memory media 295s. In some instances, individual port managers (e.g., port manager 260-a) of the plurality of port managers 260 can operate independently of each other (e.g., port managers 260-b, 260-c, and 260-c) and can support access operations or background operations associated with one or more memory media 295s. The one or more memory media 295s can be referenced. Figure 1 Examples of the one or more memory media 130 described herein. In some cases, each of the one or more memory media 295 may be referred to as a media port.

[0049] Each aggregation channel in aggregation channel 290 may contain one or more channels 291. In some cases, channel 291 may be referred to as logical channel 291. In some instances, each channel 291 may be associated with one or more memory dies in memory media (e.g., memory media 295-a) and may have a smaller bandwidth than that of the aggregation channel (e.g., aggregation channel 290-b). In some instances, an aggregation channel (e.g., aggregation channel 290-a) may contain eleven (11) channels 291 (e.g., channels 291-a to 291-k). As those skilled in the art will understand, the plurality of channels 291 (e.g., channels 291-a to 291-k) are depicted for port manager 260-a, thereby representing one of the aggregated channels 290 (e.g., aggregated channel 290-a), while the other aggregated channels 290 (e.g., aggregated channels 290-b, 290-c, and 290-d) are depicted for port managers 260-b, 260-c, and 260-d, and the plurality of channels 291 associated with each aggregated channel are not shown. This depiction is to increase the visibility and clarity of the features presented.

[0050] Individual memory media (e.g., memory media 295-a) among the one or more memory media 295 may contain one or more memory devices (e.g., 3DXP memory dies). In some cases, the memory devices in individual memory media may be configured to operate in parallel to obtain a desired (or specified) aggregate bandwidth through one of the aggregate channels 290. As an example, a 3DXP memory die may be configured to have an 8-bit wide data bus and may be associated with each of the channels 291 (e.g., channel 291-a), thereby making each channel 291 8 bits wide. Additionally, a 3DXP memory die may be configured to generate 128 bits of data during a series of sixteen (16) bursts, where each burst may generate 8 bits of data on channel 291. Thus, the 128 bits of data can be viewed as a single data unit generated by each 3DXP memory die based on an access command to read a memory cell within the 3DXP memory die (or during background operation).

[0051] In some cases, a codeword (or forwarding codeword) can be configured to contain a set of bit fields indicating multiple data bursts (e.g., a series of sixteen (16) bursts) spanning multiple channels (e.g., eleven (11) channels 291-a to 291-k, each generating 88 bits of data). Thus, a codeword can contain 1,408 bits of information in some cases. The description herein can be understood from a logical view of the memory medium. A number of physical 3DXP memory dies greater than the number of logical 3DXP memory dies can exist in the memory medium, thus illustrating the overhead associated with various access operations (e.g., read operations, write operations) or background operations related to the memory medium. Within the memory medium, as referenced... Figure 3 As described, codewords can be divided into parts and written to or read from more than one die (e.g., 128 bytes of user data held across ten (10) 3DXP memory dies).

[0052] The various examples described herein, using 3DXP memory dies (e.g., containing 3D XPoint™ memory cells) to demonstrate how memory media 295 can be configured and operated in conjunction with port manager 260, are based on the methods, devices, and systems disclosed herein that support media flushing operations in memory systems. In some cases, memory media 295 may contain other types of memory devices employing memory technologies different from 3DXP memory technology, such as FeRAM, PCM, and MRAM technologies. Therefore, the concepts disclosed herein are not limited to a specific memory technology (e.g., 3D XPoint™ memory technology).

[0053] Memory media (e.g., memory media 295-a) may contain a collection of memory dies, each containing a memory array. Each memory die in the collection (e.g., each memory array) may be configured to contain a set of MSRs, as referenced. Figure 4 As described, an MSR can be configured to efficiently manage (e.g., replace, substitute) a reasonable fault-tolerant region for faulty bits in a memory array. In some cases, each bit of a codeword (e.g., each of 1,408 bits in a codeword) can be associated with a corresponding MSR in a set (e.g., 1,408 MSRs). A group of MSRs across a set of channels of a memory medium (e.g., channels 291-a to 291-k of memory medium 295-a) can be configured to operate in parallel to retain or generate a number of codewords. In some cases, a group of MSRs configured to generate a number of codewords can be referred to as an MSR stripe or an MSR region. Additionally, at least some (if not every) of the MSRs in the set can be associated with a counter configured to count the number of faulty bits in the MSRs of the set.

[0054] A port manager (e.g., port manager 260-a) may, in some cases, count the number of forwarding codewords held in the memory media (e.g., memory media 295-a) as part of media scrubbing operations. A forwarding codeword may contain a number of copies of the codeword's forwarding address, as referenced. Figure 3 As described, port manager 260-a can identify the value of a first counter associated with the memory media. The first counter can indicate a first number of codewords configured to be forwarded during a first duration. In some cases, the first duration can be based on a pre-configured period for retrieving a set of codewords from the memory media. Port manager 260-a can set (e.g., initially set, update) the value of a second counter associated with the memory media based on the value of the first counter, wherein the second counter can indicate a second number of forwarded codewords that can be accumulated in the memory media during a second duration. In some cases, the second duration can be based on the lifespan of the memory media (e.g., an estimated duration for which the memory media meets a set of operational criteria). Port manager 260-a can also receive a first codeword from the memory media based on setting the value of the second counter.

[0055] In some cases, the Port Manager 260-a can determine that the first codeword meets the conditions used to configure it as a forwarding codeword. These conditions can be based on, as referenced... Figure 3The number of error bits in the first codeword described. Port manager 260-a can also configure the first codeword as a forwarding codeword based on determining that the first codeword meets certain conditions. In some cases, port manager 260-a can write the first codeword back to the memory medium (e.g., memory medium 295-a) based on configuring the first codeword as a forwarding codeword.

[0056] In some cases, port manager 260-a may update the value of the first counter based on configuring the first codeword as a forwarding codeword. Port manager 260-a may also determine an updated value of the first counter relative to a first threshold associated with the number of forwarding codewords retained at the memory media. In some cases, the first threshold may be related to the number of codeword forwarding events allowed during a first duration. In some cases, the number of codeword forwarding events may be pre-configured based on the ratio between the total number of forwarding codewords budgeted in the memory media and the total number of codewords retained in the memory media. In other cases, the first threshold may be related to one or more defective mechanisms that could make the memory cell cluster unreliable or problematic. As a result of updating the value of the first counter (e.g., configuring a codeword as a forwarding codeword during a flushing cycle), port manager 260-a may determine that the value of the first counter (e.g., the number of updated codeword forwarding events) may be equal to the number of codeword forwarding events allowed during the first duration or within a determined range of the number of codeword forwarding events allowed during the first duration.

[0057] Furthermore, port manager 260-a can receive a second codeword from the memory medium based on updating the value of the first counter. Port manager 260-a can also determine, based on receiving the second codeword, that the second codeword meets the conditions for configuring the second codeword as a forwarding codeword. In some cases, port manager 260-a can avoid configuring the second codeword as a forwarding codeword based on the updated value of the first counter relative to a first threshold. For example, port manager 260-a can initiate an alternative error control scheme (e.g., a replacement codeword channel) instead of configuring the second codeword as a forwarding codeword. A replacement codeword channel may be a more efficient scheme for managing error bits in codewords when the error bit may be due to one or more defect mechanisms associated with the memory die of the memory medium.

[0058] In some cases, port manager 260-a can determine that the first codeword corresponds to the last codeword retained at the storage media (e.g., a media scrubber operation completing the current scrubbering cycle). Port manager 260-a can also update the value of a second counter based on updating the value of a first counter and determining that the first codeword corresponds to the last codeword retained at the storage media. In some cases, port manager 260-a can determine an updated value of the second counter relative to a second threshold associated with the number of forwarded codewords retained at the storage media. Port manager 260-a can also avoid configuring a codeword as a forwarded codeword based on the updated value of the second counter. In some cases, the second threshold may be related to the number of codeword forwarding events allowed during the lifetime of the storage media. In some cases, the number of codeword forwarding events allowed during the lifetime of the storage media may be pre-configured based on the ratio between the total number of forwarded codewords for the storage media budget and the total number of codewords retained in the storage media.

[0059] Figure 3 An example of a codeword format (also referred to as codeword layout 300) supporting media flushing operation in a memory system according to the aspects disclosed herein is shown. Codeword format 300 may be an example of a codeword format used for the entire codeword. The codeword may contain indications across multiple channels (e.g., reference...). Figure 2 The set of bit fields for multiple data bursts in channels 291-a to 291-k as described. Figure 3 It also includes displays for individual channels (e.g., reference). Figure 2 The various configurations of the described channel 291-a) are formatted in formats 301 to 305 (also known as layouts). Figure 3 Format 306 is also shown, which may correspond to a portion of a codeword (e.g., a subset of bit fields during one or more first data bursts across the plurality of channels).

[0060] As an example of a codeword format and structure, codeword format 300 may contain a number of fields (e.g., bit fields) of data (e.g., 1,408 bits of data), said data may be stored on a memory medium (e.g., a reference medium). Figure 1 and 2 The described memory medium 130-a or memory medium 295-a is generated in response to an access command or during background operation, or both. The codeword may contain 128 bytes (e.g., 1,024 bits) of user data. The remaining bit field within the codeword (e.g., 384 bits of data) may carry various information that can facilitate the transfer of accurate user data during access operation, during background operation, or both. Furthermore, the remaining bits carrying various information may be configured to facilitate low-latency operations (e.g., spare replacement) associated with the codeword during access operation.

[0061] Codeword format 300 can span multiple channels (e.g., channels 310-a to 310-k). One of these channels (e.g., 310-a to 310-k) can be a reference. Figure 2 The described channel 291 (e.g., channel 291-a) is an instance or includes aspects of the channel. In some cases, each of the plurality of channels 310 (e.g., channel 310-a) may be associated with one or more 3DXP dies, which may contain an 8-bit wide data bus. For example, each channel may generate a total of 128 bits of data as a single object of a transaction (e.g., communication, operation) associated with an access command (e.g., a read command) or a background operation or both. Further, the 128 bits of data may be generated as a series of sixteen (16) data bursts, each configured to generate eight (8) bits of data on an 8-bit wide data bus. Therefore, each channel within the codeword format (e.g., each of channels 310-a to 310-k) can correspond to 128 bits of data comprising sixteen (16) groups of 8-bit data, such as G7..G0 of channel 310-g, where G7..G0 can represent a series of eight (8) 0s and 1s, where G7 can be the most significant bit (e.g., the eighth bit in the series of eight (8) 0s and 1s) and G0 can be the least significant bit (e.g., the first bit in the series of eight (8) 0s and 1s), where each of the sixteen (16) groups of 8-bit data can be associated with one of the sixteen (16) data bursts.

[0062] In one instance, codeword format 300 may span eleven (11) channels, and each of the eleven (11) channels may generate 8 bits of data at each data burst, and a total of 88 bits of data may be generated across the eleven (11) channels at each data burst (e.g., a first data burst 320-1 of 88 bits of data). Therefore, codeword format 300 may contain 1,408 bits of data (e.g., first data burst 320-1 to 16th data burst 320-16, where each data burst generates 88 bits of data) as a single object of a transaction for a memory medium (e.g., memory medium 130-a or memory medium 295-a). Codeword format 300 may support reliable transactions (e.g., conveying the accurate content of user data) with low latency (e.g., a small number of clock edges for generating user data).

[0063] Each field (e.g., each bit field) or set of fields (e.g., a set of bit fields) within a codeword may contain information that facilitates reliable user data transactions with low latency. In some cases, one or more fields (e.g., bit fields) within the codeword format may be configured to indicate codeword conditions (e.g., using one or more CwCon bits). The codeword may be configured to be in one of several possible states (e.g., four states) indicated by the CwCon bits.

[0064] As an example, one or more CwCon bits may indicate that a codeword is either a normal codeword or a forwarding codeword. As an example, a normal codeword may contain codeword format 300. A forwarding codeword may contain a codeword layout that facilitates the identification of a valid replacement address (e.g., a forwarding address) for the codeword. In some cases, a forwarding codeword may contain at least one copy of the valid address associated with the codeword. Further, one or more CwCon bits may additionally or alternatively indicate that a codeword is either a non-inverted codeword or an inverted codeword. In some cases, the logical state of bits within an inverted codeword (e.g., 1 and 0) may need to be inverted (e.g., flipped, reversed) before the information of the inverted codeword can be interpreted (e.g., parsed), while a non-inverted codeword may not need to be inverted before the information of the non-inverted codeword can be interpreted (e.g., parsed), whereas a non-inverted codeword may not need to be inverted before the information of the non-inverted codeword is interpreted (e.g., parsed).

[0065] Controller (e.g., reference) Figure 1 and 2 The described controller 120 or port manager 260-a) can, in some cases, be used as part of media flushing operation to remove media from memory (e.g., reference 120). Figure 1 and 2 The described memory medium 130-a or memory medium 295-a) retrieves a codeword and reverses at least some (if not all) of the bits of the codeword before writing the codeword back to the memory medium. Writing the codeword back to the memory medium can mitigate undesirable changes in the electrical characteristics of the memory cell holding the codeword—for example, drift in the threshold voltage of the memory cell that may occur during extended periods without access operations. Reversing the logical state of the memory cell (e.g., writing a logic "1" to a memory cell holding logic "0" or vice versa) can further mitigate undesirable changes in the electrical characteristics of the memory cell.

[0066] In some cases, the controller may receive a codeword from an address on the memory medium, the codeword comprising a set of bits (e.g., a set of bit fields). The controller may also invert a portion of the bits based on the received codeword. In some cases, the controller may set the value of a bit in the set (e.g., a CwCon bit) based on inverting said portion of the bits to indicate a codeword condition containing the inverted state of the codeword. The controller may also write the codeword back to an address on the memory medium based on setting the value of the bit indicating the inverted state. In some cases, said portion of the bits may comprise each bit in the set. In some cases, the controller may retrieve each of a plurality of codewords held at the memory medium as part of a periodic background operation (e.g., a media flushing operation) independent of access commands from the host, wherein said portion of the bits may be inverted based on retrieving each of said plurality of codewords.

[0067] In some cases, one or more fields within the codeword format can be configured to indicate the number of access operations (e.g., read operations, write operations) associated with the codeword (e.g., the WrCnt bit). In some cases, one or more fields within the codeword format can be configured to indicate that a portion of the codeword may be invalid (e.g., using a poisoned or indicator bit). In some cases, one or more fields within the codeword format can be configured as Cyclic Redundancy Check (CRC) bits that can identify error bits associated with error control operations.

[0068] In some cases, one or more fields within the codeword format can be configured as codeword error control bits (e.g., CwECC bits) to support error control operations. In other cases, one or more fields within the codeword format can be configured as XOR bits. Each XOR bit can contain the numeric or Boolean XOR product of the corresponding bit from the other channels of the corresponding data burst. Therefore, XOR bits can support the repair of corresponding bits from other channels and can be referred to as repair bits. In some cases, each XOR bit (e.g., XOR / Sub bit or XORSub bit) can replace a field within the codeword instead of repairing a field.

[0069] In some cases, one or more fields within the codeword format can be configured as spare bits (e.g., CRC / spare bit, XORSub / spare bit). Among other alternatives, bits configured as spare bits can be configured as CRC bits or XOR bits (or XORSub bits). As an example, Figure 3The codeword format 300 described herein may contain up to twenty-two (22) spare bits—for example, twenty (20) CRC / spare bits and two (2) XORSub / spare bits. That is, some fields of the CRC bits may be configured as spare bits. Similarly, some fields of the repair bits (e.g., XORSub bits) may be configured as spare bits. Thus, a certain number of spare bits within the codeword may be configurable, as said number of spare bits may be interchangeable with a certain number of CRC bits or XORSub bits. In some cases, the number of spare bits in the codeword may be determined based on the maturity of the memory technology (e.g., 3D XPoint™, FeRAM, MRAM technology) used to construct the memory media (e.g., memory media 130, memory media 295).

[0070] In some cases, a spare bit can be configured to operate as a spare bit to retrieve a designated invalid bit (e.g., an error bit) of the codeword. In some cases, a designated invalid bit may be associated with a memory die's MSR (e.g., an MSR containing a number of memory cells that may have become invalid or unreliable). A spare bit (e.g., the MSR corresponding to the spare bit) can be routed (e.g., multiplexed using a multiplexing component) to replace (e.g., substitute) the designated invalid bit (e.g., the MSR corresponding to the error bit) to support reliable transactions of user data within the codeword.

[0071] Still refer to Figure 3 Individual fields within the codeword format (e.g., bit fields) can be configured (e.g., arranged) to support low latency operations during access operations associated with the memory media. Figure 3 Formats 301 to 305 contain various configurations demonstrating 8-bit groups for individual channels (e.g., each of channels 310-a to 310-k). For example, each of formats 301 to 305 contains an eight (8)-bit group that a memory device (e.g., a 3DXP die) within a memory medium (e.g., memory medium 295-a) can produce at a given data burst. Example formats are described below, but the disclosure herein is not limited to these examples.

[0072] Format 301 may include one or more (e.g., three) fields for CwCon bits, one or more (e.g., two) fields for CRC / spare bits (which may be configured as CRC bits or spare bits), and one or more (e.g., three) fields for CRC bits. Format 302 may include one or more (e.g., three) fields for CwCon bits, one or more (e.g., two) fields for CRC / spare bits (which may be configured as CRC bits or spare bits), one or more (e.g., two) fields for CRC bits, and one or more (e.g., three) fields for WrCnt bits (e.g., counter bits).

[0073] Format 303 may include one or more (e.g., three) fields for CwCon bits, one or more (e.g., two) fields for CRC / spare bits (which may be configured as CRC bits or spare bits), and one or more (e.g., three) fields for WrCnt bits (e.g., counter bits). Format 304 may include one or more (e.g., three) fields for CwCon bits, one or more (e.g., two) fields for CRC / spare bits (which may be configured as CRC bits or spare bits), one or more fields for WrCnt bits (e.g., counter bits), and one or more (e.g., two) fields for corruption bits (e.g., bits indicating invalidity of a portion of the codeword). Format 305 may include one or more (e.g., three) fields for CwCon bits, one or more (e.g., two) fields for XORSub / spare bits (which may be configured as XORSub bits or spare bits), and one or more (e.g., three) fields for XORSub bits.

[0074] Codeword format 300 can also display 1,024-bit user data fields (e.g., channels 310-a to 310-h on the second data burst 320-2 to the 16th data burst 320-16 and channels 310-i and 310-j on the second data burst 320-2 to the fifth data burst 320-5), CwECC fields (e.g., channels 310-i and 310-j on the 6th data burst 320-6 to the 16th data burst 320-16) and XOR / Sub fields (e.g., channel 310-k on the second data burst 320-2 to the 16th data burst 320-16).

[0075] As an example of a codeword format supporting low latency operation, a subset of bit fields corresponding to the first data burst (e.g., data burst 320-1) can be configured as shown in format 306. In format 306, each 8-bit group of channels 310-a (e.g., A7..A0) and 310-b (e.g., B7..B0) can be configured with format 301. Similarly, the 8-bit groups of channels 310-c (e.g., C7..C0) can be configured with format 302. At least some (if not every) of the 8-bit groups of channels 310-d (e.g., D7..D0) to 310-i (e.g., I7..I0) can be configured with format 303. The 8-bit groups of channels 310-j (e.g., J7..J0) can be configured with format 304. Additionally, the 8-bit groups of channels 310-k (e.g., K7..K0) can be configured with format 305.

[0076] As a result of configuring a subset of bit fields (e.g., a total of 88 bits comprising eight (8) bits from each of the eleven (11) channels) of a first data burst corresponding to codeword format 300 (e.g., first data burst 320-1), the 88-bit (e.g., 88 bits of format 306) first data burst may contain information to facilitate low-latency, reliable transactions for access operations associated with the codeword (e.g., reading 1,024 bits of user data). In some cases, a port manager (e.g., port manager 260-a) may receive a first portion of the codeword associated with the memory medium (e.g., bits of format 306 corresponding to first data burst 320-1). During subsequent data bursts, the port manager may simultaneously parse (e.g., interpret) the first portion of the codeword (e.g., identify spare bits) with the received additional portions of the codeword (e.g., bits of codeword format 300 corresponding to second data burst 320-2, etc.). Thus, the port manager can parallelize various operations associated with the codeword to provide reliable, low-latency communication or information exchange with the host.

[0077] When codewords become unreliable or nearly unreliable, the controller (e.g., reference) Figure 1 and 2The described controller 120 or port manager 260-a) can configure a codeword as a forwarding codeword. Compared to a codeword format containing user data (e.g., codeword format 300), a forwarding codeword format (which may also be referred to as a forwarding codeword layout) can contain a number of copies of a forwarding address (e.g., a replacement address) to facilitate access to user data. Additionally, in some cases, the forwarding codeword format can contain a number of bit fields (e.g., one or more CwCon bits) indicating codeword conditions. The forwarding codeword format can also support low latency operations, which may further include determining that the codeword is a forwarding codeword and identifying the forwarding address from the forwarding codeword.

[0078] In some cases, the controller may decide to configure a codeword for forwarding without waiting for the codeword (e.g., user data within it) to become unrecoverable beyond the error recovery capabilities of the memory system or subsystem. Because the codeword may contain information related to error control operations (e.g., one or more CRC bits, one or more CwECC bits), the controller may, in some cases, determine the number of erroneous bits (e.g., faulty bits) in the codeword based on the error control operations performed on the codeword during an access operation (e.g., a read operation). The controller may determine the number of faulty bits relative to (e.g., exceeding, equaling, or approaching) an error threshold (e.g., an error threshold at which the codeword might become unreliable or invalid). In some cases, the error threshold may be related to an acceptable limit on the number of faulty bits in the codeword (e.g., the number of faulty bits pre-configured for recovery).

[0079] The controller can configure a codeword as a forwarding codeword based on the number of error bits in the codeword and according to the forwarding codeword format. In some cases, the error threshold can be configurable based on a number of factors (e.g., the memory technology used to manufacture the memory medium, the maturity of such memory technology, and the memory medium usage pattern). The controller can also set one or more CwCon bits to indicate that the codeword is a forwarding codeword.

[0080] Figure 4 Examples of configuration 401 and configuration 402 of a memory array supporting media flushing operation in a memory system according to the aspects disclosed herein are shown. The memory array depicted in configuration 401 may be a reference. Figure 1 and 2 An example of a memory die in the described memory medium (e.g., memory medium 130 or memory medium 295). The memory medium depicted in configuration 402 may be a reference. Figure 1 and 2Examples of the described memory media (e.g., memory media 130 or memory media 295). The memory media depicted in configuration 402 may contain a number of memory arrays (e.g., forty-four (44) memory arrays) that can be configured according to configuration 401.

[0081] Configuration 401 may include memory array 410. In some cases, memory array 410 may include a set of memory cells (e.g., 512 gigabits of memory cells, 2...). 39 (A memory cell). The memory array 410 can be organized to have an array width 415 and an array depth 425. In some cases, the array width 415 can be referred to as the die width 415, and the array depth 425 can be referred to as the die depth 425. Further, the array width 415 and the array depth 425 can each be divided into a certain number of partitions. In some cases, the array width 415 can be divided into 128 segments. Therefore, the segment 420 depicted in configuration 401 can represent one of the 128 segments in the array width 415. Further, each segment (e.g., segment 420) can be divided into 128 blocks, such that the array depth 425 can be divided into 128 bars. A bar can be referred to as a segment, sub-segment, part, element, etc. Therefore, the bar 430 depicted in configuration 401 can represent one of the 128 bars in the array depth 425.

[0082] Therefore, the memory array 410 (e.g., a 512 gigabits memory cell) can be divided into a number of segments 435 (e.g., segments 435-a, 435-b, or 435-c), each depicted as a box within the memory array 410 as an example. In this example, as a result of dividing the array width 415 into 128 segments, each further divided into 128 bars (e.g., sections, subsections, portions, elements) within the array depth 425, the memory array 410 can contain 16,384 segments. Each segment 435 of the memory array 410 can be referred to as an MSR 435. In some cases, the MSR 435 can contain a group of memory cells (e.g., 2) that can be configured as data units associated with error control operations. 25 (Each memory cell). The MSR can be configured to efficiently manage (e.g., replace, substitute) a reasonable fault-tolerant area for faulty bits in the memory array 410.

[0083] The number of segments in array width 415 (e.g., 128 segments) can be determined based on the manner in which the memory array (e.g., memory array 410) is constructed in the memory die. For example, memory array 410 may have a certain number of tiles (e.g., 128 tiles), and the number of segments in array width 415 can be based on the number of tiles in memory array 410. Similarly, the number of bars in array depth 425 (e.g., 128 bars) can be determined based on common characteristics associated with various functional components such as row decoders, column decoders, etc. As a result of partitioning memory array 410 as depicted in configuration 401, each segment 435 (e.g., containing 16,384 MSRs in a 512 gigabits memory array 410 containing 2 25 The MSR of a memory cell can provide groups of memory cells (e.g., data units) to efficiently manage (e.g., replace, substitute) fault bits in memory array 410 without incurring huge overhead. In some cases, the size of the memory cell (e.g., 2 of the MSR) can be used to manage (e.g., replace, substitute) fault bits in memory array 410. 25 A memory cell can be referred to as the data granularity used to support efficient error control operations associated with the memory media.

[0084] Referring again to configuration 401, a bar 430 spanning a certain number of segments (e.g., 128 segments) can represent a first number of bits (e.g., 128 bits) generated by memory array 410 as part of a codeword (e.g., part of a codeword containing 1,408 bits). The first number of bits (e.g., 128 bits) of bar 430 can be further down-multiplexed to a second number of bit sets (e.g., eight (8) bits), each set of which can be generated at a given data burst (e.g., one of sixteen (16) data bursts that produce a total of 128 bits). Thus, bar 430 can generate a portion of a codeword, where each segment 435 (e.g., MSR 435) contributes one bit of the first number of bits (e.g., 128 bits) of the codeword. Further, bar 430 (e.g., 128 bits generated over 16 data bursts) can correspond to a channel (e.g., refer to Figure 2 The described channel 291-a). When a number of memory arrays 410 (e.g., eleven (11) memory arrays 410) operate in parallel such that each memory array 410 can generate a portion of the bits that constitute a complete codeword, a complete codeword (e.g., a 1,408-bit codeword) can be generated – for example, each memory array 410 generates 128 bits across eleven (11) channels on sixteen (16) data bursts, resulting in a total of 1,408 bits for the codeword.

[0085] Configuration 402 may include a collection of memory arrays 410 (e.g., forty-four (44) memory arrays 410) to implement memory media (e.g., reference). Figure 1 and 2 The desired or specified capacity of the described memory medium 130 or memory medium 295. The memory array set in the memory medium can be arranged to form multiple channels for the memory medium. In some cases, the memory medium may contain eleven (11) channels (e.g., channels 440-a to 440-k) as shown in configuration 402. Each channel 440 may be a reference Figure 2 The described channels 291 (e.g., channels 291-a to 291-k) are instances or aspects of said channels. Further, each channel 440 may be configured to contain a subset of memory arrays. In some cases, a channel (e.g., channel 440-a) may contain four (4) memory arrays 410-a to 410-d. Thus, each of the plurality of channels may, in some cases, contain a total number of bars 430 (e.g., 512 bars) corresponding to a multiple of the number of bars in the memory array 410 within the channel (e.g., 128 bars) multiplied by the number of memory arrays 410 (e.g., four (4) memory arrays).

[0086] In some cases, a group of MSRs spanning multiple channels that generate codewords (e.g., eleven (11) channels, i.e., channels 440-a to 440-k) may be referred to as an MSR stripe (e.g., MSR stripe 445 depicted in configuration 402). An MSR stripe may also be referred to as an MSR region. For example, the memory medium of configuration 402 contains 512 MSR stripes (e.g., 512 MSR regions). Similarly, an MSR stripe (e.g., MSR stripe 445) may correspond to a collective array depth (e.g., collective die depth) of the memory medium—for example, MSR stripe 445 depicted in configuration 402 may correspond to the 130th array depth of the memory medium (e.g., the 130th MSR stripe in the total array depth of 512 MSR stripes), where each memory array 410 contains 128 MSR stripes. In some cases, a flag may be associated with an MSR stripe (or MSR region) to indicate a change in the allocation of spare bits associated with a codeword reserved at the MSR stripe (e.g., MSR stripe 345 or MSR region 345). The flag may be part of a separate memory array (e.g., an SRAM memory cell), which in some cases may be integrated into the controller (e.g., a reference module). Figure 1 and 2 The controller 120 or port manager 260-a) described herein.

[0087] At least some (if not every) of the MSRs (e.g., MSR435-a, MSR435-b, MSR435-c) of the memory array (e.g., memory array 410) may be associated with a counter configured to count the number of error bits therein. For example, a port manager (e.g., reference...) Figure 2 The described port manager 260-a) can read codewords from an MSR stripe (e.g., MSR stripe 445) and perform error control operations on the codewords as part of a background operation (e.g., media flushing operation). The port manager can identify a number of error bits and correct the number of error bits in the codeword using a set of bits in the codeword (e.g., bits that support error correction). Each error bit (e.g., an erroneous or unreliable memory cell) in the number of error bits can correspond to a corresponding MSR of the MSR stripe. The port manager can update a first counter associated with a first MSR of the MSR stripe to count the number of error bits (e.g., error bit count) in the first MSR of the MSR stripe.

[0088] The port manager can sort the values ​​(e.g., error bit counts) in the counters stored in the codeword (e.g., 1,408 counters each corresponding to 1,408 MSRs) to identify subsets of values ​​greater than the remaining values. For example, the port manager can sort the values ​​(e.g., error bit counts) in descending order to identify subsets of values ​​(e.g., the 160 highest error bit counts out of the 1,408 error bit counts associated with the codeword). In this way, the port manager can identify subsets of MSRs that each contain a higher number of error bits compared to other MSRs. The port manager can identify subsets of MSRs (e.g., 160 out of 1,408 MSRs) as candidates for replacement (e.g., replacing such MSRs with reliable MSRs, such as spare MSRs). In some cases, the port manager can configure the number of values ​​in the subset based on the number of error bits identified in the codeword (e.g., 200 highest error bit counts instead of 160 highest error bit counts). In some cases, such quantities of values ​​in a subset (e.g., a subset of MSRs identified as candidates for replacement) can be based on a variety of factors (e.g., the memory technology used to manufacture the memory media, the maturity of such memory technology, and the usage patterns of the memory media).

[0089] Furthermore, the port manager can replace one or more MSRs with higher error bit counts (e.g., a subset of MSRs identified as candidates for replacement) with a set of spare MSRs until the set of spare MSRs is exhausted. The port manager can determine which MSR to replace based on the number of error bits in the MSR relative to a threshold (e.g., a bit-level replacement threshold). In some cases, the port manager can determine to replace an MSR with an error bit count equal to or greater than the threshold with a spare MSR. The threshold can be based on the raw bit error rate (RBER) associated with the memory media. In some cases, the threshold can be based on the size of the MSR (e.g., 2 in the MSR). 25 (Units). In some cases, the threshold can be configurable (e.g., programmable) to indicate the maturity of the technology used to manufacture memory cells of the memory medium, such as process variations that may affect the electrical characteristics of the memory cells of the memory medium.

[0090] The port manager can assign a spare MSR (e.g., a spare bit in a codeword) to replace any of the MSRs identified as candidates for replacement (e.g., an error bit in a codeword). In some cases, spare bits (e.g., spare MSRs) can be assigned on a first-come, first-served basis. The port manager can repeatedly assign spare bits to error bits in a codeword until all spare bits (e.g., reference bits) are used. Figure 3 The maximum number of spare bits described (up to twenty-two (22)) are allocated until all are allocated. In some cases, spare bits (e.g., spare MSRs) may be reassigned to different error bits (e.g., different MSRs containing an equal to or greater than the bit-level threshold of error bits). In other cases, once a spare bit has been allocated to the corresponding error bit, each spare bit may remain allocated to the corresponding error bit in the codeword.

[0091] The port manager may, in some cases as part of media flushing operations (e.g., during the first media flushing cycle for an MSR strip), allocate one or more spare bits (e.g., one or more MSRs corresponding to the spare bits) in a codeword to retrieve an error bit (e.g., the MSR corresponding to the error bit) in a codeword (e.g., one of the codewords reserved at the MSR strip). The port manager may set bits (e.g., flags) in a separate memory array to indicate such changes in the replacement relationships associated with the codewords reserved at the MSR strip. Setting bits (e.g., flags) may also indicate that, although the replacement relationships for the spare bits may have been determined, the spare bits may not contain a valid logical state of the codeword.

[0092] The port manager can store substitution relationships (e.g., spare bit allocations to corresponding error bits) for codewords reserved at memory media (e.g., MSR stripes) in a separate memory array. In some cases, the memory array can be integrated as part of the port manager. In some cases, the separate memory array can contain static random access memory (SRAM) cells.

[0093] The size of the memory array allocated to store replacement relationships (e.g., the number of SRAM cells) may be based on bits indicating changes in replacement relationships (e.g., flags indicating changes in spare allocation), identifiers of channels associated with a codeword (e.g., identifiers of the channel to be replaced), the number of spare bits in the codeword (e.g., up to twenty-two (22) spare bits), identifiers of MSRs in a first number of MSRs associated with the codeword (e.g., 1,408 MSRs), the number of bits associated with the forwarding codeword in the memory medium, error correction capability for replacement relationships, the number of memory dies corresponding to the channels associated with the codeword (e.g., four (4) memory dies per channel), or a second number of MSR groups in the memory dies of the said number of memory dies (e.g., 128 MSR bars), or any combination thereof.

[0094] The port manager can, in some cases as part of media scrubbing operations (e.g., during a second media scrubbing cycle for an MSR stripe), access codewords, replace erroneous bits with one or more spare bits according to a replacement relationship stored in a memory array (e.g., an SRAM cell), and perform error control operations to restore the logical state of the codeword (e.g., a codeword containing the one or more spare bits that replaced the erroneous bit). The port manager can write the restored logical state (e.g., a valid logical state) at the one or more spare bits and can reset bits (e.g., flags) in the memory array (e.g., an SRAM cell). In this way, the one or more spare bits can contain the valid logical state of the codeword, and the bits (e.g., flags) can indicate that the one or more spare bits in the codeword contain the valid logical state to be implemented (multiplexed into the bit stream of the codeword with a series of data bursts) when the host requests the codeword.

[0095] In some cases, the port manager may receive a codeword reserved at a portion of the memory medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword. The port manager may also access its memory array based on the received codeword. In some cases, the port manager may perform an error control operation on the codeword based on access to its memory array to restore the logical state of the plurality of bits. The port manager may also write the logical state of the bits among the plurality of bits at the spare bits among the number of spare bits based on the execution of the error control operation. In some cases, receiving the codeword may include retrieving each of the plurality of codewords reserved at the portion of the memory medium as part of a periodic background operation independent of access commands from the host.

[0096] In some cases, the port manager can replace bits in the plurality of bits with spare bits from the plurality of spare bits based on access to the memory array, wherein error control operations on the codeword can be performed based on replacing bits in the plurality of bits. The port manager can also identify the value of a flag in the memory array based on access to the memory array, the value of the flag indicating a change in the replacement relationship of codewords held at the portion of the memory medium, wherein error control operations on the codeword can be performed based on the value of the flag. In some cases, the port manager can reset the value of a flag in the memory array based on the logical state written to bits in the plurality of bits, the value of the flag indicating that the spare bits in the plurality of spare bits contain a logical state valid for replacing bits in the plurality of bits.

[0097] In some cases, the port manager can receive power level indications from a power management component coupled to the port manager and pass information stored in the memory array (e.g., SRAM cells) (e.g., indications of error states associated with codewords, one or more indications of spare bit allocation to error bits) to a reference. Figure 1 and 2 The described non-volatile memory (e.g., permanent memory).

[0098] Figure 5 A block diagram 500 is shown of a controller 515 supporting media flushing operation in a memory system according to aspects disclosed herein. The controller 515 may be a reference... Figures 1 to 2 Examples of various aspects of the described controller 120 or controller 230. Controller 515 may include bias component 520, timing component 525, access manager 530, codeword manager 535, and error control manager 540. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0099] Access manager 530 may receive a first codeword from the memory medium based on setting the value of a second counter. In some cases, access manager 530 may receive a second codeword from the memory medium based on updating the value of a first counter. In some cases, access manager 530 may write the first codeword back to the memory medium based on configuring the first codeword as a forwarding codeword. In some cases, receiving the first codeword may further include retrieving the first codeword as part of a periodic background operation independent of access commands from the host.

[0100] In some cases, the access manager 530 may receive a codeword reserved at a portion of the memory medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword. In some cases, the access manager 530 may write the logical state of the bits in the spare bits of the plurality of bits based on performing an error control operation. In some cases, receiving the codeword may further include retrieving each of the plurality of codewords reserved at the portion of the memory medium as part of a periodic background operation independent of access commands from the host, wherein access to the memory array may be based on retrieving each of the plurality of codewords.

[0101] In some cases, the access manager 530 can receive a codeword containing a set of bits from an address on the memory medium. In other cases, the access manager 530 can write the codeword back to an address on the memory medium based on the value of a bit indicating a reverse state.

[0102] The codeword manager 535 can identify the value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords. In some cases, the codeword manager 535 can set the value of a second counter associated with the memory medium based on the value of the first counter, the second counter indicating a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords. In some cases, the codeword manager 535 can configure a first codeword as a forwarding codeword based on a determination.

[0103] In some cases, codeword manager 535 may update the value of the first counter based on configuring the first codeword as a forwarding codeword. In some cases, codeword manager 535 may determine an updated value of the first counter relative to a first threshold associated with the number of forwarding codewords held at the memory medium. In some cases, codeword manager 535 may avoid configuring a second codeword as a forwarding codeword based on the updated value of the first counter relative to the first threshold. In some cases, codeword manager 535 may determine that the first codeword corresponds to the last codeword held at the memory medium. In some cases, codeword manager 535 may update the value of the second counter based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword held at the memory medium.

[0104] In some cases, codeword manager 535 can determine an updated value of the second counter relative to a second threshold associated with the number of forwarded codewords held at the memory medium. In some cases, codeword manager 535 can avoid configuring a codeword as a forwarded codeword based on the updated value of the second counter. In some cases, codeword manager 535 can reset the value of the first counter based on setting the value of the second counter, wherein receiving the first codeword can be based on resetting the value of the first counter. In some cases, the first duration can be based on a pre-configured period for retrieving a set of codewords from the memory medium. In some cases, the second duration can be based on the lifetime of the memory medium, and wherein the lifetime of the memory medium can be based on an estimated duration for which the memory medium meets a set of operational criteria. In some cases, the forwarded codeword can contain a certain number of copies of the forwarding address of the first codeword.

[0105] In some cases, codeword manager 535 may invert a portion of a bit set based on a received codeword, wherein the codeword may contain the bit set. In some cases, codeword manager 535 may set the values ​​of bits in the bit set based on inverting a portion of the bits to indicate a codeword condition containing the inverted state of the codeword. In some cases, a portion of the bits may contain each bit in the bit set.

[0106] Error control manager 540 can determine that a first codeword meets the conditions for configuring the first codeword as a forwarding codeword, said conditions being based on the number of error bits in the first codeword. In some cases, error control manager 540 can determine that a second codeword meets the conditions for configuring the second codeword as a forwarding codeword based on receiving a second codeword.

[0107] In some cases, the error control manager 540 may access the port manager's memory array based on received codewords. In some cases, the error control manager 540 may perform error control operations on codewords based on access to the port manager's memory array to restore the logical state of multiple bits of the codeword. In some cases, the error control manager 540 may replace bits among the multiple bits with spare bits from the specified number of spare bits based on access to the memory array, wherein performing error control operations on the codeword may be based on replacing bits among the multiple bits. In some cases, the error control manager 540 may identify the value of a flag in the memory array based on access to the memory array, the value of which indicates a change in the replacement relationship of codewords held at the specified portion of the memory medium, wherein performing error control operations on the codeword may be based on the value of the flag.

[0108] In some cases, the error control manager 540 may reset the value of a flag in the memory array based on the logical state of bits written among the plurality of bits, the value of which indicates that a spare bit among a certain number of spare bits contains a logical state valid for replacing a bit among the plurality of bits. In some cases, the size of the memory array used to store replacement relationships for codewords reserved at said portion of the memory medium may be based on bits indicating changes in replacement relationships, an identifier of a channel associated with a codeword, the number of spare bits in the codeword, an identifier of a minimum replacement region (MSR) in a first number of MSRs associated with the codeword, the number of bits associated with forwarded codewords in the memory medium, the error correction capability of the replacement relationship, the number of memory dies corresponding to a channel associated with the codeword, or a second number of MSR groups in the memory dies of said number of memory dies, or any combination thereof.

[0109] Figure 6 A flowchart illustrating method 600 for media flushing operation in a supporting memory system according to aspects disclosed herein is shown. The operation of method 600 can be performed by, as referenced... Figures 1 to 2 The described controller or its components are implemented. For example, the operation of method 600 can be implemented by a reference. Figures 1 to 2 The described controller 120 or controller 230 performs the functions described below. In some instances, controller 230 may execute a set of codes for functional elements of a control device to perform the functions described below. Alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0110] At 605, controller 230 can identify the value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords. The operation of 605 can be based on reference... Figure 1-5 The described method is used for execution. In some instances, aspects of the 605 operation can be handled as described in the reference. Figure 5 The described codeword manager is executed.

[0111] At 610, controller 230 can set the value of a second counter associated with the memory medium based on the value of an identifier first counter. This second counter indicates a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords. The operation of 610 can be referenced. Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 610 can be determined by reference, etc. Figure 5 The described codeword manager is executed.

[0112] At point 615, controller 230 can receive a first codeword from the memory medium based on setting the value of the second counter. The operation of 615 can be referenced. Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 615 can be performed as described in the reference. Figure 5 The described access manager is executed.

[0113] A means for performing one or more methods, such as method 600, is described. The means may include: means for identifying the value of a first counter associated with a memory medium, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords; means for setting the value of a second counter associated with the memory medium based on the value of the identified first counter, the second counter indicating a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords; and means for receiving a first codeword from the memory medium based on the value of the set second counter.

[0114] Another apparatus for performing one or more methods, such as method 600, is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller is operable to: identify the value of a first counter associated with the memory medium, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured to be forwarded; set the value of a second counter associated with the memory medium based on the identified value of the first counter, the second counter indicating a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured to be forwarded; and receive a first codeword from the memory medium based on the set value of the second counter.

[0115] Some examples of the method 600 and apparatus described herein may further include processes, features, components, or instructions for determining that a first codeword satisfies conditions for configuring the first codeword as a forwarding codeword, said conditions being based on the number of error bits in the first codeword. Some examples of the method 600 and apparatus described herein may further include processes, features, components, or instructions for configuring the first codeword as a forwarding codeword based on the determination. Some examples of the method 600 and apparatus described herein may further include processes, features, components, or instructions for updating the value of a first counter based on configuring the first codeword as a forwarding codeword. Some examples of the method 600 and apparatus described herein may further include processes, features, components, or instructions for determining an updated value of the first counter relative to a first threshold associated with the number of forwarding codewords held at the memory medium.

[0116] Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for receiving a second codeword from a memory medium based on updating the value of a first counter. Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for determining, based on receiving the second codeword, that the second codeword satisfies conditions for configuring the second codeword as a forwarding codeword. Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for avoiding configuring the second codeword as a forwarding codeword based on an update value of the first counter relative to a first threshold.

[0117] Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for determining that the first codeword corresponds to the last codeword reserved at the memory medium. Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for updating the value of a second counter based on updating the value of a first counter and determining that the first codeword corresponds to the last codeword reserved at the memory medium. Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for determining an updated value of the second counter relative to a second threshold associated with the number of forwarding codewords reserved at the memory medium. Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for avoiding configuring a codeword as a forwarding codeword based on the updated value of the second counter.

[0118] Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for writing a first codeword back to a memory medium based on configuring a first codeword as a forwarding codeword. Some examples of the method 600 and apparatus described herein may further include procedures, features, components, or instructions for resetting the value of a first counter based on setting the value of a second counter, wherein receiving the first codeword may be based on resetting the value of the first counter. In some examples of the method 600 and apparatus described herein, a first duration may be based on a pre-configured period for retrieving a set of codewords from the memory medium. In some examples of the method 600 and apparatus described herein, a second duration may be based on the lifetime of the memory medium, and wherein the lifetime of the memory medium may be based on an estimated duration for which the memory medium meets a set of operational criteria.

[0119] In some instances of the method 600 and apparatus described herein, receiving the first codeword may further include retrieving the first codeword as part of a periodic background operation independent of access commands from the host. In some instances of the method 600 and apparatus described herein, the forwarding codeword may contain a number of copies of the forwarding address of the first codeword.

[0120] Figure 7 A flowchart illustrating a method 700 for operating a media flusher in a supporting memory system according to aspects disclosed herein is shown. The operation of method 700 can be performed by, as referenced... Figures 1 to 2 The described controller or its components are implemented. For example, the operation of method 700 can be implemented by a reference. Figures 1 to 2The described controller 120 or controller 230 performs the functions described below. In some instances, controller 230 may execute a set of codes for functional elements of a control device to perform the functions described below. Alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0121] At 705, controller 230 can receive a codeword reserved in a portion of the memory medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword. Operation of 705 can be based on reference... Figure 1-5 The described method is used for execution. In some instances, aspects of the 705 operation can be determined by reference, etc. Figure 5 The described access manager is executed.

[0122] At 710, controller 230 can access the port manager's memory array based on the received codeword. The operation of 710 can be referenced. Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 710 can be determined by reference, etc. Figure 5 The described error control manager is executed.

[0123] At 715, controller 230 can perform error control operations on the codeword based on access to the port manager's memory array to restore the logical state of the plurality of bits. The operation of 715 can be based on reference... Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 715 can be performed as described in the reference. Figure 5 The described error control manager is executed.

[0124] At 720, controller 230 can write the logical state of a bit among the plurality of bits at the spare bits among the plurality of spare bits based on performing an error control operation. The operation of 720 can be based on a reference. Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 720 can be performed as described in the reference. Figure 5 The described access manager is executed.

[0125] A means for performing one or more methods, such as method 700, is described. The means may include: means for receiving a codeword reserved at a portion of a memory medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword; means for accessing a memory array of a port manager based on the received codeword; means for performing an error control operation on the codeword based on the access to the memory array of the port manager to restore the logical state of the plurality of bits; and means for writing the logical state of the bits among the plurality of bits at the spare bits among the number of spare bits based on the performed error control operation.

[0126] Another apparatus for performing one or more methods, such as method 700, is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller is operable to: receive a codeword held at a portion of the memory medium, the codeword comprising a plurality of bits including a number of spare bits for the codeword; access a memory array of a port manager based on the received codeword; perform an error control operation on the codeword based on the access to the memory array of the port manager to restore the logical state of the plurality of bits; and write the logical state of the bits of the plurality of bits at the spare bits of the number of spare bits based on the execution of the error control operation.

[0127] Some examples of the method 700 and apparatus described herein may further include processes, features, components, or instructions for replacing bits in the plurality of bits with spare bits in the plurality of spare bits based on access to a memory array, wherein performing error control operations on a codeword may be based on replacing bits in the plurality of bits.

[0128] Some examples of the method 700 and apparatus described herein may further include procedures, features, components, or instructions for identifying the value of a flag in the memory array based on access to the memory array, the value of the flag indicating a change in the substitution relationship of codewords reserved at the portion of the memory medium, wherein error control operations on the codewords may be performed based on the value of the flag. Some examples of the method 700 and apparatus described herein may further include procedures, features, components, or instructions for resetting the value of a flag in the memory array based on the logical state of bits written to the plurality of bits, the value of the flag indicating that a spare bit among a plurality of spare bits contains a logical state valid for replacing a bit among the plurality of bits.

[0129] In some instances of the method 700 and apparatus described herein, the size of the memory array for storing the substitution relationships of codewords reserved at said portion of the memory medium may be based on bits indicating changes in the substitution relationships, identifiers of channels associated with the codewords, the number of spare bits in the codewords, identifiers of minimum replacement regions (MSRs) in a first number of MSRs associated with the codewords, the number of bits associated with forwarded codewords in the memory medium, the error correction capability of the substitution relationships, the number of memory dies corresponding to channels associated with the codewords, or a second number of MSR groups in the memory dies of said number of memory dies, or any combination thereof.

[0130] In some instances of the method 700 and apparatus described herein, receiving a codeword may further include retrieving each of a plurality of codewords held at said portion of the memory medium as part of a periodic background operation independent of access commands from the host, wherein access to the memory array may be based on retrieving each of the plurality of codewords.

[0131] Figure 8 A flowchart illustrating method 800 for media flushing operation in a supporting memory system according to aspects disclosed herein is shown. The operation of method 800 can be performed by, as referenced... Figures 1 to 2 The described controller or its components are implemented. For example, the operation of method 800 can be implemented by a reference. Figures 1 to 2 The described controller 120 or controller 230 performs the functions described below. In some instances, controller 230 may execute a set of codes for functional elements of a control device to perform the functions described below. Alternatively, controller 230 may use dedicated hardware to perform aspects of the functions described below.

[0132] At 805, controller 230 can receive a codeword containing a set of bits from an address on the memory medium. The operation of 805 can be referenced. Figure 1-5 The described method is used for execution. In some instances, aspects of the 805 operation can be determined by reference, etc. Figure 5 The described access manager is executed.

[0133] At 810, controller 230 can invert a portion of the bits based on the received codeword. The operation of 810 can be referenced. Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 810 can be determined by reference, etc. Figure 5 The described codeword manager is executed.

[0134] At 815, controller 230 can set the value of bits in the set based on inverting said portion of the bits to indicate a codeword condition containing the inverted state of the codeword. The operation of 815 can be based on reference... Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 815 can be determined by reference, etc. Figure 5 The described codeword manager is executed.

[0135] At 820, controller 230 can write the codeword back to the address of the memory medium based on the value of the bit indicating the inversion state. The operation of 820 can be referenced. Figure 1-5 The described method is used for execution. In some instances, aspects of the operation of 820 can be determined by reference, etc. Figure 5 The described access manager is executed.

[0136] A means for performing one or more methods, such as method 800, is described. The means may include: means for receiving a codeword from an address of a memory medium, the codeword comprising a set of bits; means for inverting a portion of the bits based on the received codeword; means for setting values ​​of bits in the set based on the inversion of the portion of bits to indicate a codeword condition containing an inverted state of the codeword; and means for writing the codeword back to an address of the memory medium based on setting the values ​​of the bits indicating the inverted state.

[0137] Another apparatus for performing one or more methods, such as method 800, is described. The apparatus may include a memory medium and a controller in electronic communication with the memory medium, wherein the controller is operable to: receive a codeword from an address of the memory medium, the codeword comprising a set of bits; invert a portion of the bits based on the received codeword; set the values ​​of bits in the set based on the inverted portion of the bits to indicate a codeword condition containing the inverted state of the codeword; and write the codeword back to an address of the memory medium based on the set values ​​of the bits indicating the inverted state.

[0138] In some instances of the method 800 and apparatus described herein, the portion of the bit may comprise each bit in the set. In some instances of the method 800 and apparatus described herein, receiving a codeword may further comprise retrieving each of a plurality of codewords held at a memory medium as part of a periodic background operation independent of access commands from a host, wherein inverting the portion of the bit may be based on the sequential retrieval of each of the plurality of codewords.

[0139] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, instances of two or more methods in the methods can be combined.

[0140] The information and signals described herein can be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some figures may show signals as single signals; however, those skilled in the art will understand that signals can represent signal buses, where buses can have various bit widths.

[0141] The terms "electronic communication" and "coupling" refer to a relationship between components that enables the flow of electrons between them. This can include direct connections between components or it can include intermediate components. Components that are electronically communicating or coupled to each other may actively exchange electrons or signals (e.g., in a powered circuit) or may not actively exchange electrons or signals (e.g., in a de-energized circuit), but can be configured and operable to exchange electrons or signals when the circuit is powered on. For example, two components physically connected by a switch (e.g., a transistor) may be electronically communicating or coupled regardless of the state of the switch (i.e., open or closed).

[0142] Chalcogenide materials can be materials or alloys containing at least one of the elements S, Se, and Te. The phase change materials discussed herein can be chalcogenide materials. Chalcogenide materials can be alloys containing S, Se, Te, Ge, As, Al, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), and platinum (Pt). Example chalcogenide materials and alloys may include, but are not limited to: Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge- As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te- Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd or Ge-Te-Sn-Pt. As used herein, hyphenated chemical composition symbols indicate the elements contained in a particular compound or alloy and are intended to represent all stoichiometry containing the indicated element. For example, Ge-Te could contain Ge x Te y Where x and y can be any positive integers. Other examples of variable resistance materials may include binary metal oxide materials or mixed-valence oxides containing two or more metals, such as transition metals, alkaline earth metals, and / or rare earth metals. Examples are not limited to specific variable resistance materials or materials associated with memory elements of memory cells. For example, other examples of variable resistance materials may be used to form memory elements and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, etc.

[0143] The devices discussed herein, including memory media 130, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be an epitaxial layer of semiconductor material on a substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping means.

[0144] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be practiced within the scope of the claims or that fall within the scope of the claims. The term "exemplary" as used herein means "serving as an example or instance" or "illustration," and not "preferred" or "superior to other instances." Detailed descriptions, including specific details, are provided to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0145] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, components of the same type may be distinguished by adding a dash after the reference numeral and a second reference numeral to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any component among similar components having the same first reference numeral, regardless of the second reference numeral.

[0146] The information and signals described herein can be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0147] The various illustrative blocks and modules described herein can be implemented or executed using a general-purpose processor, DSP, ASIC, field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0148] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination of these. Features implementing the functions can also be physically located at various locations, including being distributed such that different parts of the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of, for example, at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, an exemplary step described as “based on condition A” can be based on both condition A and condition B without departing from the scope disclosed herein. In other words, as used herein, the phrase “based on” should be interpreted in the same way as the phrase “at least partially based on”.

[0149] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose computer or a special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and that can be accessed by a general-purpose computer or a special-purpose computer or a general-purpose processor or a special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, discs and platters include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein discs typically copy data magnetically, while platters copy data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0150] The description herein is provided to enable those skilled in the art to form or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: A controller, associated with the memory media and configured to perform the following operations: The value of a first counter associated with the memory medium is identified, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords; The value of a second counter associated with the memory medium is set based on the value of the first counter, the second counter indicating a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords; as well as The first codeword is received from the memory medium based on the value set by the second counter.

2. The memory device of claim 1, wherein the controller is further configured to perform the following operations: Determine that the first codeword satisfies the conditions for configuring the codeword as a forwarding codeword, the conditions being based on the number of error bits in the codeword; and The first codeword is configured as a forwarding codeword based on the determination that the first codeword satisfies the conditions.

3. The memory device of claim 2, wherein the controller is further configured to perform the following operations: The value of the first counter is updated based on configuring the first codeword as a forwarding codeword; and An update value for the first counter is determined relative to a first threshold associated with the number of forwarding codewords retained at the memory medium.

4. The memory device of claim 3, wherein the controller is further configured to perform the following operations: The second codeword is received from the memory medium based on the updated value of the first counter; Determine that the second codeword satisfies the conditions used to configure the codeword as a forwarding codeword; as well as The second codeword is avoided from being configured as a forwarding codeword, partly based on the updated value of the first counter relative to the first threshold.

5. The memory device of claim 3, wherein the controller is further configured to perform the following operations: Determine that the first codeword corresponds to the last codeword stored in the memory medium; The value of the second counter is updated based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword stored at the memory medium; Determine an updated value for the second counter relative to a second threshold associated with the number of forwarding codewords retained at the memory medium; as well as The updated value of the second counter is used to avoid configuring other codewords as forwarding codewords.

6. The memory device of claim 2, wherein the controller is further configured to perform the following operations: The first codeword is written back to the memory medium by configuring the first codeword as a forwarding codeword.

7. A memory device comprising: Memory media; A first counter is configured to indicate a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords; A second counter is configured to indicate a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords. as well as The controller is configured to perform the following operations: Identify the value of the first counter; The value of the second counter is set based on the value identifying the first counter; and The first codeword is received from the memory medium based on the value set by the second counter.

8. The memory device of claim 7, wherein the controller is further configured to perform the following operations: Determine that the first codeword satisfies the conditions for configuring the codeword as a forwarding codeword, the conditions being based on the number of error bits in the codeword; and Based on the determination that the first codeword satisfies the conditions, the first codeword is configured as the first forwarding codeword.

9. A method executed by a memory device, comprising: The value of a first counter associated with the memory medium is identified, the first counter indicating a first number of codewords retained on the memory medium during a first duration, the first number of codewords being configured as forwarding codewords; The value of a second counter associated with the memory medium is set based on the value of the first counter, the second counter indicating a second number of codewords retained on the memory medium during a second duration, the second number of codewords being configured as forwarding codewords; as well as The first codeword is received from the memory medium based on the value set by the second counter.

10. The method of claim 9, further comprising: The first codeword is determined to satisfy the conditions for configuring the codeword as a forwarding codeword, the conditions being based on the number of error bits in the codeword; as well as The first codeword is configured as a forwarding codeword based on the determination that the first codeword satisfies the conditions.

11. The method of claim 10, further comprising: The value of the first counter is updated based on configuring the first codeword as a forwarding codeword; as well as An update value for the first counter is determined relative to a first threshold associated with the number of forwarding codewords retained at the memory medium.

12. The method of claim 11, further comprising: The second codeword is received from the memory medium based on the updated value of the first counter; Determine that the second codeword satisfies the conditions used to configure the codeword as a forwarding codeword; as well as The second codeword is avoided from being configured as a forwarding codeword, partly based on the updated value of the first counter relative to the first threshold.

13. The method of claim 11, further comprising: Determine that the first codeword corresponds to the last codeword stored in the memory medium; The value of the second counter is updated based on updating the value of the first counter and determining that the first codeword corresponds to the last codeword stored at the memory medium; Determine an updated value for the second counter relative to a second threshold associated with the number of forwarding codewords retained at the memory medium; as well as The updated value of the second counter is used to avoid configuring other codewords as forwarding codewords.

14. The method of claim 10, further comprising: The first codeword is written back to the memory medium by configuring the first codeword as a forwarding codeword.

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