Backside illuminated global shutter image sensor with trench memory gate

Abstract

The invention relates to a backside illuminated global shutter image sensor with trench memory gates. The invention provides an image sensor. The image sensor may include an array of global shutter image pixels arranged in rows and columns. Each global shutter image pixel may include a storage gate implemented as a trench transistor. The memory gate may be at least partially covered by a corresponding backside deep trench isolation structure. The deep trench isolation structure may be filled with a light shielding material. Configured in this manner, the global shutter image pixels exhibit improved global shutter efficiency.

Description

Technical Field

[0001] This application generally relates to imaging devices, and more particularly to image sensors having charge transfer gates. Background Art

[0002] Image sensors are often used in electronic devices such as mobile phones, cameras, and computers to capture images. In a typical arrangement, an image sensor is provided with an array of image pixels arranged in pixel rows and pixel columns. An image sensor may sometimes include global shutter pixels. Designing global shutter pixels can be challenging. If not careful, global shutter pixels may suffer from poor global shutter efficiency, lower charge capacity due to the need for additional storage gate nodes, and higher pixel noise.

[0003] The embodiments described herein arise in this context. Brief Description of the Drawings

[0004] Figure 1 is a schematic diagram of an exemplary electronic device having an image sensor according to some embodiments.

[0005] Figure 2 is a schematic diagram of an exemplary pixel array and associated row and column control circuits for reading an image signal from an image sensor according to some embodiments.

[0006] Figure 3 is a circuit diagram of an exemplary global shutter pixel according to some embodiments.

[0007] Figure 4 is a cross-sectional side view of an exemplary back-illuminated image sensor having a trench storage gate structure aligned with a backside deep trench isolation structure according to some embodiments.

[0008] Figure 5A is a top plan view of various exemplary pixel regions according to some embodiments.

[0009] Figure 5B is a top plan view of an exemplary backside deep trench isolation structure having the same occupied area as the storage node region according to some embodiments.

[0010] Figure 5C is a top plan view of an exemplary backside deep trench isolation structure having a larger occupied area than the storage node region according to some embodiments.

[0011] Figure 6 is for manufacturing according to some embodiments Figure 4 is a flowchart of exemplary steps for manufacturing a back-illuminated image sensor of the type shown. Detailed Description

[0012] Embodiments of the present invention relate to image sensors. Those skilled in the art will appreciate that exemplary embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order to avoid unnecessarily obscuring embodiments of the present invention.

[0013] Electronic devices such as digital cameras, computers, cellular phones, and other electronic devices may include an image sensor that collects incoming light to capture an image. The image sensor may include a pixel array. The pixels in the image sensor may include photosensitive elements, such as photodiodes, that convert incoming light into an image signal. The image sensor may have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor may, for example, have hundreds or thousands or millions of pixels (e.g., megapixels). The image sensor may include control circuitry (such as circuitry for operating the pixels) and a readout circuit for reading out an image signal corresponding to the charge generated by the photosensitive elements.

[0014] Figure 1 is a diagram of an illustrative imaging and response system that includes an imaging system that uses an image sensor to capture an image. Figure 1 The system 100 may be an electronic device, such as a camera, a cellular phone, a video camera, or other electronic device that captures digital image data, may be a vehicle safety system (e.g., an active braking system or other vehicle safety system), or may be a surveillance system.

[0015] As Figure 1 shown, the system 100 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). The imaging system 10 may include a camera module 12. The camera module 12 may include one or more image sensors 14 and one or more lenses.

[0016] Each image sensor in the camera module 12 may be the same, or different types of image sensors may be present in a given image sensor array integrated circuit. During an image capture operation, each lens may focus light onto an associated image sensor 14. The image sensor 14 may include photosensitive elements (i.e., image sensor pixels) that convert light into digital data. The image sensor may have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., megapixels). For example, the image sensor 14 may also include bias circuitry (e.g., a source follower load circuit), a sample and hold circuit, a correlated double sampling (CDS) circuit, an amplifier circuit, an analog-to-digital converter circuit, a data output circuit, a memory (e.g., a buffer circuit), an addressing circuit, and the like.

[0017] Still image data and video image data from the camera sensor 14 may be provided to the image processing and data formatting circuitry 16 via path 28. The image processing and data formatting circuitry 16 may be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, and the like. The image processing and data formatting circuitry 16 may also be used to compress raw camera image files (e.g., into a Joint Photographic Experts Group format or JPEG format for short) as desired. In a typical arrangement (sometimes referred to as a system-on-chip (SoC) arrangement), the camera sensor 14 and the image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, the camera sensor 14 and the image processing circuitry 16 may be formed on separate semiconductor substrates. For example, the camera sensor 14 and the image processing circuitry 16 may be formed on separate substrates that have been stacked.

[0018] Imaging system 10 (e.g., image processing and data formatting circuitry 16) may communicate acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include processing software for detecting objects in an image, detecting motion of an object between image frames, determining distances to objects in an image, filtering, or otherwise processing images provided by imaging system 10.

[0019] If desired, the system 100 can provide the user with many advanced functions. For example, in a computer or advanced mobile phone, the user can be provided with the ability to run user applications. To achieve these functions, the host subsystem 20 of the system 100 may have input-output devices 22 (such as a keypad, input-output ports, a joystick, and a display) and storage and processing circuits 24. The storage and processing circuits 24 may include volatile memory and non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid state drive, etc.). The storage and processing circuits 24 may also include microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, etc.

[0020] Figure 2 It is shown in Figure 1 An example of the arrangement of the image sensor 14 is shown in FIG. Figure 2 As shown, image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44 (sometimes referred to as control and processing logic) may sometimes be considered to be Figure 1 2. Image sensor 14 may include an array of pixels, such as array 32 of pixels 34 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels). Control and processing circuitry 44 may be coupled to row control circuitry 40 via control path 27 and may be coupled to column control and readout circuitry 42 via data path 26.

[0021] The row control circuit 40 may receive row addresses from the control and processing circuit 44 and may supply corresponding row control signals (e.g., pixel reset control signals, charge transfer control signals, halo control signals, row select control signals, dual conversion gain control signals, or any other desired pixel control signals) to the image pixels 34 via the control path 36.

[0022] The column control and readout circuit 42 may be coupled to the columns of the pixel array 32 via one or more conductors (such as column lines 38). The column lines 38 may be coupled to each column of image pixels 34 in the image pixel array 32 (e.g., each column of pixels may be coupled to a corresponding column line 38). The column lines 38 may be used to read out image signals from the image pixels 34 and to provide bias signals (e.g., bias current or bias voltage) to the image pixels 34. During an image pixel readout operation, the row driver circuit 40 may be used to select a row of pixels in the image pixel array 32, and the image data associated with the image pixels 34 of that pixel row may be read out by the column readout circuit 42 on the column lines 38. The column readout circuit 42 may include column circuits such as column amplifiers for amplifying the signals read out from the array 32, sample and hold circuits for sampling and storing the signals read out from the array 32, analog-to-digital converter circuits for converting the read out analog signals to corresponding digital signals, and column memories for storing the read out signals and any other desired data. The column control and readout circuit 42 may output digital pixel readout values to the control and processing logic 44 via the line 26.

[0023] The array 32 may have any number of rows and columns. Generally, the size of the array 32 and the number of rows and columns in the array 32 will depend on the specific implementation of the image sensor 14. Although rows and columns are generally described herein as being horizontal and vertical, rows and columns may refer to any grid-like structure (e.g., features described herein as rows may be arranged vertically and features described herein as columns may be arranged horizontally).

[0024] Typically, backside-illuminated (BSI) pixel architectures exhibit improved performance relative to frontside-illuminated (FSI) pixel architectures. However, due to the difficulty of shielding the charge storage nodes within the pixels from stray light, BSI pixels using global shutter (GS) readout methods that rely on charge-domain storage nodes typically suffer from very low global shutter efficiency.

[0025] Figure 3 A suitable circuit implementation of a global shutter image sensor pixel (such as pixel 34) is shown. As Figure 3As shown, the global shutter pixel 34 may include a photosensitive element such as a pinned photodiode PD, which is coupled to an anti-halo transistor that is at least partially activated using a control signal AB to suck out overflow charge from the photodiode (e.g., by discharging any excess overflow charge to a positive power supply line on which a power supply voltage Vaa is provided). The anti-halo transistor may also be fully activated using the control signal AB to reset the photodiode.

[0026] The photodiode PD may be coupled to a storage gate controlled by a control signal SG. The storage gate may act as a temporary memory node of the pixel 34 and is thus sometimes referred to as a storage node, a storage gate node, a storage gate memory node, or a global shutter storage node. The storage gate may be coupled to a floating diffusion node FD via a charge transfer transistor controlled by a signal TX. The charge transfer transistor is sometimes referred to as a charge transfer gate.

[0027] Any charge transferred to the floating diffusion node FD causes a change in the electric potential on that node, and this change is sensed by a source follower transistor SF. The source terminal of the source follower transistor is connected via a row selection transistor to a sensor array column sense line 38, which delivers the pixel signal to the periphery of the array for further processing. The row selection control signal RS is made effective to activate the row selection transistor to transfer the pixel signal to the column sense line 38. After charge sensing has been completed, the floating diffusion node FD may be reset to the power supply voltage Vaa (e.g., a nominal positive power supply voltage provided on the power supply line) by making the reset control signal RST effective to turn on a reset transistor. If desired, the storage gate and the floating diffusion node may be reset simultaneously by making the signals RST and TX effective at the same time.

[0028] Figure 3 The illustrated global shutter image sensor pixel 34 is merely exemplary and is not intended to limit the scope of the present embodiment. This pixel scheme may be extended or applied to pixel architectures where two, three, four, or more charge storage nodes / regions share a common floating diffusion node for each pixel 34. Generally, the global shutter image sensor pixel 34 may include any number of storage gates, any number of capacitors, and any number of associated charge transfer transistors, charge reset transistors, readout transistors, conversion gain transistors, and selection transistors for supporting global shutter readout operations.

[0029] Figure 4 is a cross-sectional side view of an exemplary back-illuminated image sensor such as the image sensor 14 according to some embodiments. As Figure 4As shown, the image sensor 14 may include a substrate such as a p-type (p-doped) semiconductor substrate 100, a front-side dielectric stack 102 formed on the front (upper) surface of the substrate 100, and a back-side dielectric stack 104 formed on the back (lower) surface of the substrate 100.

[0030] Figure 4 At least two adjacent image sensor pixels 34-1 and 34-2 formed in the substrate 100 are shown. Each pixel may include at least a gate conductor 106 of a row selection transistor, a gate conductor 108 of a source follower transistor, and additional pixel circuitry (not shown in this particular cross-section) formed in the front surface of the substrate 100. As Figure 4 shown, the source follower transistor may be relatively wider than other pixel transistors, which can help reduce read noise and increase the frame rate (e.g., the SF transistor may be at least twice as wide, more than 50% wider, 1 to 5 times wider, or 1 to 10 times wider than the row selection transistor or other transistors in the pixel). The pixel structure of each pixel 34 may be at least partially surrounded by a shallow trench isolation (STI) structure such as an STI structure 110 formed in and at the front surface of the substrate 100.

[0031] Each pixel 34 may also include a storage gate structure 114 formed at the front surface of the substrate 100. The storage gate structure 114 may represent a storage gate controlled by a signal SG in Figure 3 . The storage gate 114 may include a gate conductor 120 formed in a trench of the substrate 100. The gate conductor 120 may be formed of polysilicon, metal, or other suitable conductive gate material. An n-type (n-doped) well region 116 may be formed in the region of the substrate 100 surrounded by the gate conductor 120. A gate insulating liner 118 may be formed in the trench at the interface separating the gate conductor 120 from the well 116. The N-doped well 116 may be used as a buried channel region of the storage gate 114. The buried channel region 116 may be at least partially surrounded by the trench in which the trench gate conductor 120 is formed. The storage gate structure 114 constructed in such a way that the gate conductor 118 extends vertically into the trench formed in the substrate 100 is sometimes referred to and defined herein as a trench transistor, trench gate, trench storage gate, or trench gate transistor. The trench transistor (as defined herein) is different from a conventional planar transistor in which the gate conductor is formed on the top of the front surface of the substrate 100.

[0032] Implementing the storage gate as a trench transistor significantly reduces the footprint of the storage gate, thereby allowing a large PD region and can contribute to improved global shutter efficiency. Since the area of the storage gate is not limited by the pixel size, the trench storage gate can have an increased charge capacity; simply increasing the depth of the trench storage gate increases the charge storage capacity. If desired, the charge transfer transistor controlled by signal TX (see Figure 3 ) can also be implemented as a trench transistor.

[0033] The storage gate conductor 114 can be coupled to one or more metal layers in the dielectric stack 102 using vertical vias 134. The dielectric stack 102 can include alternating metal wiring layers 130 and dielectric layers 132 through which conductive vias can be formed. The dielectric stack 102 is sometimes referred to as an interconnect stack. The dielectric stack 102 can include at least two metal wiring layers, at least three metal wiring layers, four or more metal wiring layers, five or more metal wiring layers, six or more metal wiring layers, or other numbers of conductive wiring layers.

[0034] Deep trench isolation (DTI) structures, such as DTI structure 140, can be formed in and at the backside of the substrate 100. The trench depth of the deep trench isolation structure 140 can be greater than the trench depth of the shallow trench isolation structure 110. For example, the DTI structure 140 can be at least 2 times, 4 times, 6 times, 8 times, 2 to 10 times, or more than 10 times deeper than the STI structure 110. Each pixel 34 can include a photodiode region PD that is at least partially surrounded by the DTI structure 140. Each PD region can have a portion 144 that extends laterally beneath the channel region 116 of the associated storage gate structure 114. The region between the buried channel 116 and the PD portion 114 is the transfer region through which charge can be transferred from the photodiode to the global shutter storage node. A p-type (p-doped) well, such as p-well 112, can be formed in the substrate 100 to provide charge isolation between the photodiode region below the well 112 and the planar transistor structure above the well 112.

[0035] Specifically, the storage gate 114 can be laterally aligned with the DTI structure 140 (i.e., each storage gate 114 can be hidden beneath the corresponding backside deep trench isolation structure). In other words, when viewing the image sensor 14 from above, the DTI structure 140 overlaps with the storage gate structure 114 (see the plan view in Figures 5A to 5C ). Directly covering the storage gate node from the backside using the DTI structure can contribute to improved global shutter efficiency. The DTI structure 140 can optionally be filled with metal 142, which can provide light-blocking capabilities and reflect any stray light away from the storage gate structure. A DTI structure with metal filling is sometimes referred to as a light-blocking or light-shielding deep trench isolation structure.

[0036] The back dielectric stack 104 may include at least one metal wiring layer sandwiched between two dielectric layers. In other suitable arrangements, the dielectric stack 104 may include at least two metal wiring layers, at least three metal wiring layers, four or more metal wiring layers, five or more metal wiring layers, six or more metal wiring layers, or other numbers of conductive wiring layers.

[0037] An array of color filter structures may be formed on the dielectric stack 104. In Figure 4 an example, a first color filter element CF-1 is formed on pixel 34-1, while a second color filter element CF-2 is formed on pixel 34-2. The color filter elements may be part of a color filter array having red color filter elements, green color filter elements, blue color filter elements, cyan color filter elements, magenta color filter elements, yellow color filter elements, black color filter elements, transparent color filter elements, some combination of these color filter elements, and / or other color filter elements.

[0038] An array of microlens structures 150 may be formed above the color filter array. Each microlens 150 may be configured to direct incoming light 152 away from the storage gate region. For example, some of the microlenses 150 may be configured to focus red light away from the storage gate node. As another example, some of the microlenses 150 may be configured to focus blue light away from the storage gate node. As yet another example, some of the microlenses 150 may be configured to focus green light away from the storage gate node. The image sensor 14 implemented in this way is referred to as a back-illuminated image sensor because the light 152 enters the image sensor from the back (bottom) surface of the substrate 100.

[0039] Figure 5A is a top plan (layout) view of various exemplary pixel regions according to some embodiments. As Figure 5A shown, a charge transfer gate 190 may be formed between the floating diffusion region FD and the storage gate 192. The occupied area of the storage gate 192 may be significantly smaller than the occupied area of the underlying photodiode (e.g., see Figure 4 ).

[0040] Figure 5B is Figure 5A a top plan view of an exemplary backside deep trench isolation structure 140 having the same occupied area as the storage gate 192 shown. As described above, the backside DTI 140 may be formed directly below the storage gate 192 to help provide shielding for the storage gate node. The example of Figure 5B where the occupied area of the DTI structure 140 is the same as the occupied area of the storage gate 192 is only exemplary. Figure 5CAnother example is shown in which the backside deep trench isolation structure 140’ is configured to have a larger footprint than the storage gate 192. The relatively large DTI footprint may help provide better light blocking capabilities, but may affect the size of the surrounding photodiode regions.

[0041] Figure 6 is a flowchart of exemplary steps for manufacturing Figure 4 a back-illuminated global shutter image sensor 14 of the type shown. At step 200, a photodiode PD is implanted from the front surface of a semiconductor substrate 100. For example, the photodiode PD may be formed by first performing a deep n-type dopant implant and then performing a shallow n-type dopant implant.

[0042] At step 202, a shallow p-well 112 is implanted from the front surface of the substrate 100.

[0043] At step 204, a shallow trench isolation structure 110 may be formed at the front surface of the substrate 100. The STI structure 110 may form the active regions for planar pixel transistors.

[0044] At step 206, trenches are etched for the storage gate (and / or optionally for the charge transfer gate). At step 208, a potential well 116 is implanted from the front surface of the substrate 100 into the regions of the substrate 100 located between the trenches. At step 210, a threshold adjustment dopant (e.g., a p-type dopant) may be implanted for the storage gate. At step 212, a trench gate oxide liner 118 may be grown and a conductive gate material (such as polysilicon) may be deposited into the trenches to form a trench gate conductor 118.

[0045] At step 214, planar transistors (e.g., row select transistors, source follower transistors, charge transfer transistors, reset transistors, and / or other pixel switching transistors) may be formed within the active regions surrounded by the STI structure 110.

[0046] At step 216, a dielectric stack 102 and associated interconnect wiring may be formed on the front side of the substrate 100. At step 218, the image sensor may be flipped (turned over), bonded to a carrier wafer, and thinned to a desired thickness. The relatively thick substrate 100 generally improves global shutter efficiency. For example, the thickness of the substrate 100 may be greater than 5 microns, greater than 10 microns, greater than 1 micron, may be from 1 micron to 10 microns, 5 microns to 10 microns, 10 microns to 20 microns, or other suitable thicknesses.

[0047] At step 220, an anti-reflection coating layer may be formed on the back surface of the substrate 100. A deep trench isolation structure may be formed in the back surface. The deep trench isolation structure may optionally be filled with metal or other light-blocking materials.

[0048] At step 222, a color filter array may be formed on the back surface of the substrate 100, and a microlens array may be formed above the color filter array.

[0049] These steps are merely illustrative. At least some of the described steps may be modified or omitted; some of the described steps may be performed in parallel; additional steps may be added or inserted between the described steps; the order of certain steps may be reversed or changed; or the timing of the described steps may be adjusted such that they occur at slightly different times.

[0050] Various embodiments are disclosed. According to some embodiments, an image sensor is provided that includes: a substrate having a front surface and a back surface; a photodiode formed in the substrate; a charge transfer transistor coupled to the photodiode and formed in the front surface of the substrate; a storage gate coupled between the photodiode and the charge transfer transistor, wherein the storage gate includes a trench transistor formed in the front surface of the substrate; and a deep trench isolation structure formed in the back surface of the substrate, wherein the deep trench isolation structure is laterally aligned with the storage gate. The deep trench isolation structure may be filled with a light-blocking material such as metal. The storage gate may include a gate conductor formed in the trench, a buried channel region at least partially surrounded by the trench, and a gate insulating layer located between the gate conductor and the buried channel region. The storage gate may have a first footprint area, while the deep trench isolation structure may have a second footprint area that is the same as or larger than the first footprint area.

[0051] According to some embodiments, a method of manufacturing an image sensor is provided that includes: obtaining a substrate having a front surface and a back surface; etching a trench in the front surface of the substrate; implanting a potential well in an area of the substrate at least partially surrounded by the trench; growing a gate oxide layer in the trench; depositing a conductive gate material into the trench; and forming a deep trench isolation structure in the back surface of the substrate, wherein the deep trench isolation structure is aligned with the trench. The deep trench isolation structure may be filled with a light-blocking material. The method may further include: forming a planar transistor at the front surface of the substrate, forming a photodiode region in the substrate, and forming an isolation well between the photodiode region and the planar transistor.

[0052] According to some embodiments, an image sensor pixel is provided, comprising: a substrate having an upper surface and a lower surface; a trench transistor formed in the upper surface; and a deep trench isolation structure formed in the lower surface, wherein the deep trench isolation structure at least partially covers the trench transistor from the lower surface. The trench transistor can be used as a global shutter storage gate or can be used as a charge transfer transistor. The pixel may further include a photodiode region laterally surrounded by the deep trench isolation structure, wherein the photodiode region has a portion extending into the region of the substrate located between the trench transistor and the deep trench isolation structure.

[0053] The foregoing is merely an illustrative description of the principles of the present invention, and those skilled in the art can make various modifications without departing from the scope and essence of the present invention. The above embodiments can be implemented individually or in any combination.

Claims

1. An image sensor, comprising: a substrate having a front surface and a back surface; a photodiode formed in the substrate; a charge transfer transistor coupled to the photodiode and formed in the front surface of the substrate; a storage gate coupled between the photodiode and the charge transfer transistor, wherein the storage gate comprises a trench transistor formed in the front surface of the substrate; and A deep trench isolation structure is formed in the rear surface of the substrate, wherein the deep trench isolation structure is laterally aligned with the storage gate. 2 . The image sensor according to claim 1 , wherein the deep trench isolation structure is filled with a light shielding material. The image sensor according to claim 2 , wherein the light shielding material comprises metal.

4. The image sensor according to claim 1, wherein the storage gate comprises: a gate conductor formed in the trench; a buried channel region at least partially surrounded by the trench; and A gate insulating layer is located between the gate conductor and the buried channel region.

5. The image sensor according to claim 4, further comprising: a source follower transistor coupled to the charge transfer transistor and formed at the front surface of the substrate; and A charge isolation well is located between the photodiode and the source follower transistor.

6. The image sensor according to claim 5, further comprising: A row select transistor is coupled in series with the source follower transistor, wherein the source follower transistor is wider than the row select transistor. 7 . The image sensor of claim 1 , wherein the photodiode has a portion extending into a region between the storage gate and the deep trench isolation structure. 8 . The image sensor of claim 1 , wherein the charge transfer transistor comprises a planar transistor formed at the front surface of the substrate.

9. The image sensor of claim 1, wherein the charge transfer transistor includes an additional trench transistor having a similar structure as the storage gate. 10 . The image sensor of claim 1 , wherein the storage gate has a first footprint, and wherein the deep trench isolation structure has a second footprint that is the same as the first footprint. 11 . The image sensor of claim 1 , wherein the storage gate has a first footprint, and wherein the deep trench isolation structure has a second footprint greater than the first footprint.

12. The image sensor according to claim 1, further comprising: a color filter element formed on the rear surface of the substrate; and A microlens is formed on the color filter element and is configured to focus incoming light away from the storage gate.

13. A method for manufacturing an image sensor, comprising: obtaining a substrate having a front surface and a back surface; etching a trench in the front surface of the substrate; implanting a potential well in a region of the substrate at least partially surrounded by the trench; growing a gate oxide layer in the trench; depositing a conductive gate material into the trench; as well as A deep trench isolation structure is formed in the rear surface of the substrate, wherein the deep trench isolation structure is aligned with the trench.

14. The method according to claim 13, further comprising: The deep trench isolation structure is filled with a light blocking material.

15. The method according to claim 13, further comprising: forming a planar transistor at the front surface of the substrate; forming a photodiode region in the substrate; as well as An isolation well is formed between the photodiode region and the planar transistor.

16. The method according to claim 13, further comprising: forming a row select transistor at the front surface of the substrate; as well as A source follower transistor is formed at the front surface of the substrate, the source follower transistor being at least 50% wider than the row select transistor.

17. An image sensor pixel, comprising: a substrate having an upper surface and a lower surface; a trench transistor formed in the upper surface; and A deep trench isolation structure is formed in the lower surface, wherein the deep trench isolation structure at least partially covers the trench transistor from the lower surface.

18. The image sensor pixel of claim 17, wherein the trench transistor comprises a global shutter storage gate.

19. The image sensor pixel of claim 17, further comprising: a photodiode formed in the substrate; and A floating diffusion region is formed in the substrate, wherein the trench transistor includes a charge transfer transistor coupled between the photodiode and the floating diffusion region.

20. The image sensor pixel of claim 17, further comprising: A photodiode region is laterally surrounded by the deep trench isolation structure, wherein the photodiode region has a portion extending into a region of the substrate between the trench transistor and the deep trench isolation structure.

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