Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes: a substrate; the patterned stacked structure is located on the substrate and comprises first dielectric layers and first conductive layers which are alternately stacked, each first conductive layer comprises a wire connecting part and a first conductive wire, and the first conductive wire is connected to the wire connecting part in the first direction; the step structure is located on the substrate and comprises a plurality of step layer groups arranged in a stacked mode, the step layer groups form multiple steps distributed in the second direction, each step layer group comprises a second dielectric layer, a second conductive layer and a third dielectric layer, the second conductive layer is connected with the wire connecting part in the first direction, and in the same step layer group, the third conductive layer is connected with the wire connecting part in the second direction. The third dielectric layer and the second conductive layer are arranged along the second direction, and the orthographic projections of the third dielectric layer and the second conductive layer on the substrate are overlapped with the orthographic projection of the second dielectric layer on the substrate; and the orthographic projection areas of the plurality of second conductive layers of the plurality of step layer groups on the substrate are the same. According to the embodiment of the invention, the RC delay between each layer of conductive wires is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technologies, three-dimensional storage devices have emerged. In three-dimensional storage devices, signals of conductive lines (such as bit lines and word lines) of each layer of storage devices are usually led out through a stepped structure.

[0003] However, when using a traditional stepped structure to lead out signals, with the increase in the number of stacked layers, there is a significant RC delay problem between the conductive lines (such as bit lines and word lines) of each layer of storage devices. Summary of the Invention

[0004] Based on this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to effectively improve the RC delay problem between the conductive lines (such as bit lines and word lines) of each layer.

[0005] A semiconductor structure includes:

[0006] A substrate;

[0007] A patterned stacked structure located on the substrate, including a first dielectric layer and a first conductive layer that are alternately stacked and whose orthographic projections on the substrate overlap. The first conductive layer includes a wire connection portion and a first conductive wire, and the first conductive wire is connected to the wire connection portion in a first direction;

[0008] A stepped structure located on the substrate and on a side of the wire connection portion away from the first conductive wire in the first direction, including a plurality of stepped layer groups stacked, the plurality of stepped layer groups constituting a multi-step step distributed in a second direction, and the stepped layer group including a second dielectric layer, a second conductive layer, and a third dielectric layer. The second conductive layer is connected to the wire connection portion in the first direction, and within the same stepped layer group, the third dielectric layer and the second conductive layer are arranged in the second direction and their orthographic projections on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate. The orthographic projection areas of the plurality of second conductive layers of the plurality of stepped layer groups on the substrate are the same, and the second direction intersects with the first direction.

[0009] In one embodiment, within the same stepped layer group, the second dielectric layer is away from the substrate relative to the second conductive layer and the third dielectric layer.

[0010] In one embodiment, the stepped structure has a first stepped region, a non-stepped region, and a second stepped region. The first stepped region and the second stepped region are located on both sides of the non-stepped region in the second direction. The plurality of stepped layer groups form the multi-step structure in both the first stepped region and the second stepped region. In the same stepped layer group, a second conductive layer is provided in the first stepped region and / or the second stepped region.

[0011] In one embodiment, within the same stepped layer group, the second conductive layer is located on both sides of the third dielectric layer in the second direction.

[0012] In one embodiment, within the same stepped layer group, the second conductive layer is only located on one side of the third dielectric layer in the second direction. Along the direction perpendicular to the substrate, the second conductive layers in adjacent stepped layer groups are located on opposite sides in the second direction.

[0013] In one embodiment, the semiconductor structure further includes a plurality of conductive plugs. The plurality of conductive plugs respectively penetrate the multi-step structure to connect to the corresponding second conductive layers, and the conductive plugs penetrating the odd-numbered steps are located in the first stepped region, and the conductive plugs penetrating the even-numbered steps are located in the second stepped region.

[0014] In one embodiment, the plurality of second conductive layers of the plurality of stepped layer groups are completely staggered in sequence along the second direction.

[0015] In one embodiment, the plurality of second conductive layers of the plurality of stepped layer groups are partially staggered in sequence along the second direction.

[0016] In one embodiment, the wire connection portions are provided on both sides of the first wire in the first direction, and the stepped structures are provided on both sides of the patterned stacked structure in the first direction.

[0017] A method for manufacturing a semiconductor structure, comprising:

[0018] Providing a substrate;

[0019] Forming a patterned stacked structure on the substrate. The patterned stacked structure includes a first dielectric layer and a first conductive layer that are alternately stacked and whose orthographic projections on the substrate overlap. The first conductive layer includes a wire connection portion and a first wire, and the first wire is connected to the wire connection portion in the first direction;

[0020] A stepped structure is formed on the substrate on the side of the wire connection portion away from the first wire in the first direction. The stepped structure includes a plurality of stacked stepped layer groups, and the plurality of stepped layer groups constitute a multi-step stepped structure distributed in the second direction. The stepped layer group includes a second dielectric layer, a second conductive layer, and a third dielectric layer. The second conductive layer is connected to the wire connection portion in the first direction. In the same stepped layer group, the third dielectric layer and the second conductive layer are arranged in the second direction, and the orthographic projections of the two on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate. The orthographic projection areas of the second conductive layers of the plurality of stepped layer groups on the substrate are the same, and the second direction intersects the first direction.

[0021] In one embodiment, forming the patterned stacked structure on the substrate includes:

[0022] Alternately stack a first dielectric material layer and a sacrificial material layer on the substrate;

[0023] Perform patterning on the first dielectric material layer and the sacrificial material layer. The remaining first dielectric material layer forms the first dielectric layer, and the remaining sacrificial material layer forms a sacrificial layer;

[0024] Remove the sacrificial layer, and form the first conductive layer in the removal area of the sacrificial layer.

[0025] In one embodiment, the material of the first dielectric material layer includes silicon oxide, and the material of the sacrificial material layer includes silicon nitride.

[0026] In one embodiment, forming the stepped structure on the substrate on the side of the wire connection portion away from the first wire in the first direction includes:

[0027] Form a stepped initial structure on the substrate on the side of the wire connection portion away from the first wire in the first direction. The stepped initial structure includes a plurality of stacked stepped initial layer groups. The widths of the plurality of stepped initial layer groups in the second direction decrease sequentially with the stacking height and constitute a multi-step stepped structure distributed in the second direction. The stepped initial layer group includes a third dielectric initial layer and a second dielectric layer formed in sequence. In the same stepped initial layer group, the orthographic projection of the third dielectric initial layer on the substrate overlaps with the orthographic projection of the second dielectric layer on the substrate;

[0028] Laterally etch the third dielectric initial layer to form a hollowed-out area, and the remaining third dielectric initial layer forms the third dielectric layer;

[0029] Form the second conductive layer in the hollowed-out area.

[0030] In one embodiment, a step initial structure is formed on a substrate on a side of the wire connection portion away from the first wire in the first direction, including:

[0031] The second dielectric material layer and the third dielectric material layer are alternately stacked on the substrate;

[0032] The second dielectric material layer and the third dielectric material layer are etched to form the step initial structure. The remaining third dielectric material layer after etching forms the third dielectric initial layer, and the remaining second dielectric material layer after etching forms the second dielectric layer.

[0033] In one embodiment, the material of the second dielectric material layer includes silicon oxide, and the material of the third dielectric material layer includes silicon nitride.

[0034] In one embodiment, after the step structure is formed on the substrate on the side of the wire connection portion away from the first wire in the first direction, it further includes:

[0035] A plurality of contact holes are formed respectively penetrating through the multi-step;

[0036] A conductive plug is formed in the contact hole, and the conductive plug on each step is connected to the second conductive layer corresponding to the step.

[0037] In the above semiconductor structure and its manufacturing method, the first wire of each layer of the memory device is connected to the second conductive layer with the same area through the corresponding wire connection portion, so that the signal is led out through the second conductive layer with the same area. Therefore, the RC delay between the first wires of each layer can be effectively reduced. Moreover, the multi-step is distributed in the second direction, so that the area of the step structure can be effectively saved, which is beneficial to improving the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0039] Figure 1 FIG. 1 is a schematic three-dimensional structure diagram of a semiconductor structure provided in an embodiment;

[0040] FIG. 2(a) is a related top view structure diagram of a first conductive layer and a second conductive layer provided in an embodiment;

[0041] FIG. 2(b) is a top - view structural schematic diagram of the first dielectric layer provided in an embodiment;

[0042] Figure 3 is a three - dimensional structural schematic diagram of a semiconductor structure provided in another embodiment;

[0043] Figure 4 is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment;

[0044] Figure 5 is a three - dimensional structural schematic diagram of the structure obtained by alternately stacking to form a first dielectric material layer and a sacrificial material layer in a method for manufacturing a semiconductor structure provided in an embodiment;

[0045] FIG. 6(a) is a top - view structural schematic diagram of the first dielectric layer obtained after patterning the first dielectric material layer and the sacrificial material layer in a method for manufacturing a semiconductor structure provided in an embodiment;

[0046] FIG. 6(b) is a top - view structural schematic diagram of the sacrificial layer obtained after patterning the first dielectric material layer and the sacrificial material layer in a method for manufacturing a semiconductor structure provided in an embodiment;

[0047] Figure 7 is a three - dimensional structural schematic diagram of region B in FIG. 6(a) and FIG. 6(b);

[0048] Figure 8 is Figure 7 a three - dimensional structural schematic diagram of the structure obtained after removing the sacrificial layer in;

[0049] Figure 9 is Figure 8 a three - dimensional structural schematic diagram of the structure obtained after forming a first conductive layer in;

[0050] Figure 10 is a partial three - dimensional structural schematic diagram after forming a step initial structure in a method for manufacturing a semiconductor structure provided in an embodiment;

[0051] Figure 11 is a partial three - dimensional structural schematic diagram after forming a hollowed - out region in a method for manufacturing a semiconductor structure provided in an embodiment;

[0052] Figure 12 is a partial three - dimensional structural schematic diagram after forming a second conductive layer in a method for manufacturing a semiconductor structure provided in an embodiment;

[0053] Figure 13 is a related top - view structural schematic diagram of the first conductive layer and the second conductive layer after forming contact holes in a method for manufacturing a semiconductor structure provided in an embodiment;

[0054] Figure 14 In the preparation method of a semiconductor structure provided in an embodiment, it is a schematic diagram of a local three-dimensional structure after forming a conductive plug;

[0055] Figure 15 It is a schematic diagram of a three-dimensional structure of a semiconductor structure provided in another embodiment.

[0056] Explanation of reference numerals:

[0057] 100 - Substrate; 200 - Patterned stack structure; 210 - First dielectric layer; 2101 - First dielectric material layer; 220 - First conductive layer; 221 - Wire connection part; 222 - First conductive wire; 230 - Sacrificial layer; 2301 - Sacrificial material layer; 300 - Step structure; 3001 - Initial step structure; 310 - Step layer group; 3101 - Initial step layer group; 311 - Second dielectric layer; 312 - Second conductive layer; 313 - Third dielectric layer; 3131 - Initial third dielectric layer; 400 - Conductive plug; 500 - Memory array; 10 - Contact hole; 20 - Conductive wire hole. Detailed implementation manners

[0058] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0060] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0061] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0062] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0063] As described in the background art, when using a traditional step structure to lead out signals, with the increase in the number of stacked layers, there is a significant RC delay problem between the conductive lines (such as bit lines and word lines) of each layer of memory devices.

[0064] Based on this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the semiconductor structure. Among them, the semiconductor structure can, but is not limited to, be formed by the method for manufacturing the semiconductor structure in the following embodiments. At the same time, the semiconductor structure and the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure can, but are not limited to, be applied to the manufacture of three-dimensional dynamic random access memory (DRAM) devices.

[0065] In one embodiment, please refer to Figure 1 , a semiconductor structure is provided. The semiconductor structure includes a substrate 100, a patterned stacked structure 200, and a step structure 300. The patterned stacked structure 200 and the step structure 300 are located in different regions on the substrate 100.

[0066] It should be noted that Figure 1 in, for the sake of clarity of the drawings, the substrate 100 under the step structure 300 is not shown, but in fact the step structure 300 is also formed on the substrate 100.

[0067] The substrate 100 may include a substrate. The substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate may also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the substrate should not limit the protection scope of the present disclosure.

[0068] As an example, the substrate 100 may further include a peripheral circuit structure (not shown), and the peripheral circuit structure may be formed based on a semiconductor substrate. Of course, the peripheral circuit structure is located on the side of the step structure 300 away from the substrate 100, and this is not limited here.

[0069] The patterned stacked structure 200 includes a first dielectric layer 210 and a first conductive layer 220 that are alternately stacked. The bottom layer of the patterned stacked structure may be the first dielectric layer 210 or the first conductive layer 220. And the top layer of the patterned stacked structure may be the first dielectric layer 210 or the first conductive layer 220.

[0070] Referring to FIG. 2(a), the first conductive layer 220 includes a wire connection portion 221 and a first conductive wire 222. The first conductive wire 222 is connected to the wire connection portion 221 in the first direction.

[0071] The material of the first conductive layer 220 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), etc.

[0072] As an example, the first conductive wire 222 may be a bit line or a word line of a memory cell. The first conductive layer 220 may include a plurality of first conductive wires 222. The plurality of first conductive wires 222 may be arranged along a second direction. The second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction. At the same time, on the same side in the first direction, the plurality of first conductive wires 222 may be connected to the same wire connection portion 221.

[0073] Referring to FIG. 2(b), the first dielectric layer 210 and the first conductive layer 220 are alternately stacked. They have the same shape, and their orthographic projections on the substrate 100 overlap.

[0074] It can be understood that the "orthographic projection overlap" referred to herein means that the outlines of the orthographic projections are consistent and overlap with each other. At the same time, the "orthographic projection overlap" is an overlap in a broad sense, and in actual processes, a certain process error is allowed.

[0075] The material of the first dielectric layer 210 includes, but is not limited to, a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (Al 2 O 3 ), or a silicon oxynitride layer (SiON).

[0076] In addition, the opening area of the patterned stack structure 200 may be filled with a fourth dielectric layer (not shown), and memory cells (such as including transistors, capacitors, etc.) may be provided in the fourth dielectric layer in the opening area. The memory cells may be connected to the first conductive wire 222. And a plurality of memory cells may be arranged in an array to form a memory array 500. Referring to FIG. 2(a). For the sake of clarity of the drawings, in FIG. 2(a), the memory array 500 is schematically shown in a block diagram form.

[0077] Referring to Figure 1 and FIG. 2(a), the step structure 300 is located on the side of the wire connection portion 221 away from the first conductive wire 222 in the first direction. That is, the step structure 300 and the first conductive wire 222 are respectively provided on the opposite sides of the wire connection portion 221 in the first direction.

[0078] Please refer to Figure 1 The stepped structure 300 includes a plurality of stepped layer groups 310 arranged in a stacked manner. At the same time, the plurality of stepped layer groups 310 arranged in a stacked manner form a multi-step stepped structure distributed in the second direction.

[0079] Each stepped layer group 310 includes a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313.

[0080] Within the same stepped layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged in the second direction, so they are located at the same film layer position.

[0081] As an example, within the same stepped layer group 310, relative to the second conductive layer 312 and the third dielectric layer 313, the second dielectric layer 311 can be away from the substrate 100. At this time, both the third dielectric layer 313 and the second conductive layer 312 can be located in the lower layer of the stepped layer group 310, and the second dielectric layer 311 can be located in the upper layer of the stepped layer group 310.

[0082] Or, within the same stepped layer group 310, relative to the second conductive layer 312 and the third dielectric layer 313, the second dielectric layer 311 can be close to the substrate 100. At this time, both the third dielectric layer 313 and the second conductive layer 312 can be located in the upper layer of the stepped layer group 310, and the second dielectric layer 311 can be located in the lower layer of the stepped layer group 310.

[0083] At the same time, within the same stepped layer group 310, the orthographic projections of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlap with the orthographic projection of the second dielectric layer 311 on the substrate 100.

[0084] Please refer to Figure 1 And Fig. 2(a), the second conductive layer 312 is connected to the wire connection part 221 in the first direction, and then is electrically connected to the first wire 222 through the wire connection part 221. The projections of the second conductive layers 312 of the plurality of stepped layer groups 310 on the substrate 100 can be at least partially staggered in the second direction, so as to facilitate leading out the signal of the first wire 222 through the second conductive layers 312 of each layer, and the parasitic capacitance between the second conductive layers 312 of each layer can be effectively reduced.

[0085] As an example, the projections of the second conductive layers 312 of the plurality of stepped layer groups 310 on the substrate 100 can be completely staggered in sequence in the second direction. Or, the projections of the second conductive layers 312 of the plurality of stepped layer groups 310 on the substrate 100 can also be partially staggered in sequence in the second direction.

[0086] The material of the second conductive layer 312 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), etc. The material of the second conductive layer 312 may be the same as or different from the material of the first conductive layer 220, and no limitation is imposed herein.

[0087] Meanwhile, in the first direction, the third dielectric layer 313 may also be connected to the wire connection portion 221, and the second dielectric layer 311 may be connected to the first dielectric layer 210. Moreover, the thicknesses of the third dielectric layer 313 and the second conductive layer 312 may be the same as the thickness of the first conductive layer 220, and the thickness of the second dielectric layer 311 may be the same as the thickness of the first dielectric layer 210.

[0088] The material of the third dielectric layer 313 and / or the second dielectric layer 311 may include, but is not limited to, a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), or a silicon oxynitride layer (SiON). As an example, the material of the second dielectric layer 311 may be set to be the same as the material of the first dielectric layer 210 and different from the material of the third dielectric layer 313. For example, the material of the second dielectric layer 311 and the first dielectric layer 210 may be set to be silicon oxide, and the material of the third dielectric layer 313 may be silicon nitride.

[0089] Meanwhile, the orthographic projection areas of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 are the same. That is, the area of each second conductive layer 312 is the same.

[0090] In this embodiment, multiple stepped layer groups 310 are provided to form multi-step steps distributed in the second direction. The distribution direction of the steps is set in another direction intersecting the first direction, rather than in the first direction (the connection direction of the second conductive layer 312 and the first conductive layer 220). Therefore, the length of the second conductive layer 312 in the first direction does not need to increase with the increase in the stacking layers. Meanwhile, in each stepped layer group 310, a third dielectric layer 313 located at the same film layer position as the second conductive layer 312 is provided, and the third dielectric layer 313 and the second conductive layer 312 are arranged in the second direction. Therefore, the length of the second conductive layer 312 in the second direction also does not need to increase with the increase in the stacking layers, so that the area of each second conductive layer 312 can be set to be the same. Meanwhile, the second conductive layer 312 is provided to be connected to the wire connection portion 221 in the first direction. At this time, the first wire 222 and the second conductive layer 312 can be effectively electrically connected through the wire connection portion 221.

[0091] At this time, the first conductive wires 222 of each layer of the storage device are all connected to the second conductive layer 312 of the same area through the corresponding wire connection parts 221, so that signals are led out through the second conductive layer 312 of the same area. Therefore, the RC delay between the first conductive wires 222 of each layer can be effectively reduced.

[0092] Moreover, in this embodiment, the multi-step is distributed along the second direction, so that the area of the step structure 300 can be effectively saved, which is conducive to improving the storage density.

[0093] In one embodiment, please refer to Figure 1 , the step structure 300 has a first step area A1, a non-step area A2, and a second step area A3. The first step area A1, the non-step area A2, and the second step area A3 can be arranged in sequence along the second direction. That is, the first step area A1 and the second step area A3 are located on both sides of the non-step area A2 in the second direction.

[0094] Multiple step layer groups 310 form a multi-step in both the first step area A1 and the second step area A3. In the same step layer group 310, the second conductive layer 312 can be arranged in the first step area A1 and / or the second step area A3.

[0095] At this time, the first conductive wires 222 (bit lines or word lines) of different layers can lead out signals through the second conductive layers 312 located in the first step area A1 and the second step area A3 respectively, so as to reduce the signal interference between the first conductive wires 222 of different layers.

[0096] In one embodiment, please refer to Figure 1 , when multiple step layer groups 310 form a multi-step in both the first step area A1 and the second step area A3, within the same step layer group 310, the second conductive layer 312 is located on both sides of the third dielectric layer 313 in the second direction.

[0097] For each step layer group 310, the second conductive layer 312 can be symmetrically arranged on both sides of the third dielectric layer 313 in the second direction. In each step layer group 310, the second conductive layers 312 located on both sides of the third dielectric layer 313 in the second direction can be respectively located at the step positions of the first step area A1 and the second step area A3. At this time, it is convenient for the processing and preparation of the step layer group 310.

[0098] Of course, in other embodiments, the arrangement form of the second conductive layer 312 and the third dielectric layer 313 in the step layer group 310 is not limited to this. For example, please refer to Figure 15, within the same stepped layer group 310, the second conductive layer 312 is only located on one side of the third dielectric layer 313 in the second direction. Along the direction perpendicular to the substrate 100, the second conductive layers 312 in adjacent stepped layer groups 310 are located on opposite sides in the second direction. At this time, within adjacent stepped layer groups 310 in the direction perpendicular to the substrate 100, the second conductive layer 312 can be respectively arranged in the first stepped area A1 and the second stepped area A3.

[0099] In one embodiment, please refer to Figure 3 , the semiconductor structure further includes a plurality of conductive plugs 400, and the plurality of conductive plugs 400 respectively penetrate through multiple steps to connect to the corresponding second conductive layer 312. At the same time, the conductive plugs 400 can extend into the peripheral circuit structure located within the substrate 100, so that the conductive plugs 400 are electrically connected to the peripheral circuit structure. It should be noted that Figure 3 in order to make the figure clear, the substrate 100 below the stepped structure 300 is moved downward. However, in the actual structure, the substrate 100 below the stepped structure 300 and the substrate 100 below the patterned stacked structure 200 are the same substrate.

[0100] Of course, the peripheral circuit structure can also be arranged on the top of the conductive plug 400, so that the conductive plug 400 is electrically connected to the peripheral circuit structure.

[0101] When the plurality of conductive plugs 400 respectively penetrate through multiple steps to connect to the corresponding second conductive layer 312, at each step, the conductive plug 400 can penetrate through the second conductive layer 312 to be connected thereto. Of course, the connection formation between the conductive plug 400 and the second conductive layer 312 is not limited thereto. For example, in some embodiments, third dielectric layers 313 (not shown) can be provided on both sides of the second conductive layer 312 along the second direction. At this time, the conductive plug 400 can also penetrate through the third dielectric layer 313 to connect to the second conductive layer 312 in the second direction. Or, the conductive plug 400 can penetrate through the third dielectric layer 313 and the second conductive layer 312 simultaneously.

[0102] At the same time, a plurality of stepped layer groups 310 are provided to form multiple steps in both the first stepped area A1 and the second stepped area A3. And the conductive plugs 400 penetrating through the odd-numbered steps are located in the first stepped area A1, and the conductive plugs 400 penetrating through the even-numbered steps are located in the second stepped area A3.

[0103] At this time, the conductive plugs 400 for leading out the signals of the first conductive lines 222 (bit lines or word lines) of different layers can be respectively arranged in the first stepped area A1 and the second stepped area A3, so as to reduce the arrangement density of the conductive plugs 400, and further effectively prevent the short-circuit risk between the conductive plugs 400.

[0104] In one embodiment, please refer toFigure 1 As shown in FIG. 2(a), wire connection portions 221 are provided on both sides of the first conductive wire 222 in the first direction, and step structures 300 are provided on both sides of the patterned stacked structure 200 in the first direction.

[0105] At this time, as an example, referring to FIG. 2(a), the semiconductor structure may include two wire connection portions 221 extending in the second direction. And the two wire connection portions 221 are oppositely arranged in the first direction.

[0106] A plurality of first conductive wires 222 (such as bit lines or word lines) arranged in the second direction are provided between the two wire connection portions 221. Each first conductive wire 222 is arranged to be connected to the two wire connection portions 221 on both sides of it in the first direction.

[0107] At this time, the first conductive wires 222 (bit lines or word lines) of different layers can be respectively connected to the second conductive layer 312 in different step structures 300 through different wire connection portions 221 to lead out signals, thereby reducing signal interference between the first conductive wires 222 of different layers. At the same time, the conductive plugs 400 provided on the second conductive layer 312 can be distributed on the step structures 300 on both sides of the patterned stacked structure 200 in the first direction, thereby reducing the arrangement density of the conductive plugs 400, and further effectively preventing the short - circuit risk between the conductive plugs 400.

[0108] In one embodiment, referring to Figure 4 , a method for manufacturing a semiconductor structure is further provided, including the following steps:

[0109] Step S10: Provide a substrate 100;

[0110] Step S20: Form a patterned stacked structure 200 on the substrate 100. The patterned stacked structure 200 includes a first dielectric layer 210 and a first conductive layer 220 that are alternately stacked and whose orthographic projections on the substrate 100 overlap. The first conductive layer 220 includes a wire connection portion 221 and a first conductive wire 222. The first conductive wire 222 is connected to the wire connection portion 221 in the first direction;

[0111] In step S30, a step structure 300 is formed on the substrate 100 on the side of the wire connection portion 221 away from the first wire 222 in the first direction. The step structure 300 includes a plurality of step layer groups 310 stacked on top of each other. The plurality of step layer groups 310 form a multi-step structure distributed in the second direction. And the step layer group 310 includes a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313. The second conductive layer 312 is connected to the wire connection portion 221 in the first direction. And within the same step layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction, and their orthographic projections on the substrate 100 overlap with the orthographic projection of the second dielectric layer 311 on the substrate 100. The orthographic projection areas of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 are the same. The second direction intersects with the first direction.

[0112] In step S10, the substrate 100 may include a substrate. The substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate may also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the substrate should not limit the protection scope of the present disclosure.

[0113] As an example, the substrate 100 may further include a peripheral circuit structure, and the peripheral circuit structure may be formed based on a semiconductor substrate. Of course, the peripheral circuit structure may also be formed after the step structure 300 is formed, and this is not limited here.

[0114] In step S20, please refer to Figure 5 and Figure 9 , the patterned stacked structure 200 may be formed in the first region A4 on the substrate 100, and it may be formed through a patterning process. The patterned stacked structure 200 includes a first dielectric layer 210 and a first conductive layer 220. The bottom layer of the patterned stacked structure may be the first dielectric layer 210 or the first conductive layer 220. And the top layer of the patterned stacked structure may be the first dielectric layer 210 or the first conductive layer 220.

[0115] The first dielectric layer 210 and the first conductive layer 220 are alternately stacked, and they have the same shape, and their orthographic projections on the substrate 100 overlap.

[0116] It can be understood that the "orthographic projection overlap" referred to herein means that the outlines of the orthographic projections are consistent and overlap with each other. At the same time, the "orthographic projection overlap" is an overlap in a broad sense, and in actual processes, a certain process error is allowed.

[0117] The material of the first conductive layer 220 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), etc.

[0118] The first conductive layer 220 includes a wire connection portion 221 and a first conductive wire 222. The first conductive wire 222 is connected to the wire connection portion 221 in the first direction.

[0119] As an example, the first conductive wire 222 may be a bit line or a word line of a memory cell. The first conductive layer 220 may include a plurality of first conductive wires 222. The plurality of first conductive wires 222 may be arranged in the second direction. The second direction intersects the first direction. For example, the second direction may be perpendicular to the first direction. At the same time, on the same side in the first direction, the plurality of first conductive wires 222 may be connected to the same wire connection portion 221.

[0120] The material of the first dielectric layer 210 includes, but is not limited to, a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (A l2 O 3 ), or a silicon oxynitride layer (SiON).

[0121] In step S30, referring to Figure 5 and Figure 12 , a stepped structure 300 may be formed in the second region A5 on the substrate 100. The second region A5 is connected to the first region A4 in the first direction. As an example, the second region A5 is located at the edge of the substrate 100 in the first direction.

[0122] Before forming the stepped structure 300, a fourth dielectric layer may be first filled in the opening region of the patterned stack structure 200 in the first region A4 to level the first region A4. The material of the fourth dielectric layer may include, but is not limited to, a silicon oxide layer (SiO 2 ), a silicon nitride layer (Si 3 N 4 ), an aluminum oxide (Al 2 O 3 ), or a silicon oxynitride layer (SiON).

[0123] The fourth dielectric layer may be a single-layer structure or a multi-layer structure.

[0124] As an example, before forming the stepped structure 300, in addition to filling the opening region of the patterned stacked structure 200 with the fourth dielectric layer, storage units (such as transistors, capacitors, etc.) located within the fourth dielectric layer may also be formed in the opening region. The storage units may be arranged in an array to form a storage array.

[0125] After filling the fourth dielectric layer, the stepped structure 300 is then formed, so that the formation of the stepped structure 300 will not affect the structure within the first region A4.

[0126] After forming the stepped structure 300, a plurality of stepped layer groups 310 arranged in a stack are formed. At the same time, the plurality of stepped layer groups 310 arranged in a stack constitute a multi-step stepped structure distributed in the second direction.

[0127] Each stepped layer group 310 includes a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313.

[0128] Within the same stepped layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged in the second direction, so they are located at the same film layer position.

[0129] As an example, within the same stepped layer group 310, relative to the second conductive layer 312 and the third dielectric layer 313, the second dielectric layer 311 may be away from the substrate 100. At this time, the third dielectric layer 313 and the second conductive layer 312 may both be located in the lower layer of the stepped layer group 310, and the second dielectric layer 311 may be located in the upper layer of the stepped layer group 310.

[0130] Or, within the same stepped layer group 310, relative to the second conductive layer 312 and the third dielectric layer 313, the second dielectric layer 311 may be close to the substrate 100. At this time, the third dielectric layer 313 and the second conductive layer 312 may both be located in the upper layer of the stepped layer group 310, and the second dielectric layer 311 may be located in the lower layer of the stepped layer group 310.

[0131] At the same time, within the same stepped layer group 310, the orthographic projections of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlap with the orthographic projection of the second dielectric layer 311 on the substrate 100.

[0132] The second conductive layer 312 is electrically connected to the wire connection portion 221 in the first direction, and then is electrically connected to the first wire 222 through the wire connection portion 221. The projections of the second conductive layers 312 of the plurality of stepped layer groups 310 on the substrate 100 may be at least partially staggered in the second direction, so as to facilitate leading out the signals of the first wire 222 through the second conductive layers 312 of each layer, and the parasitic capacitance between the second conductive layers 312 of each layer can be effectively reduced.

[0133] As an example, the projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 may be staggered in sequence along the second direction and completely staggered. Alternatively, the projections of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 may also be staggered in sequence along the second direction and partially staggered.

[0134] The material of the second conductive layer 312 may include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), etc. The material of the second conductive layer 312 may be the same as or different from the material of the first conductive layer 220, and no limitation is imposed here.

[0135] Meanwhile, in the first direction, the third dielectric layer 313 may also be connected to the wire connection portion 221, and the second dielectric layer 311 may be connected to the first dielectric layer 210. Moreover, the thicknesses of the third dielectric layer 313 and the second conductive layer 312 may be the same as the thickness of the first conductive layer 220, and the thickness of the second dielectric layer 311 may be the same as the thickness of the first dielectric layer 210.

[0136] The material of the third dielectric layer 313 and / or the second dielectric layer 311 may include, but is not limited to, silicon oxide layer (SiO 2 ), silicon nitride layer (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), or silicon oxynitride layer (SiON). As an example, the material of the second dielectric layer 311 may be set to be the same as the material of the first dielectric layer 210 and different from the material of the third dielectric layer 313. For example, the material of the second dielectric layer 311 and the first dielectric layer 210 may be set to be silicon oxide, and the material of the third dielectric layer 313 may be silicon nitride.

[0137] Meanwhile, the positive projection areas of the multiple second conductive layers 312 of the multiple stepped layer groups 310 on the substrate 100 are the same. That is, the area of each second conductive layer 312 is the same.

[0138] In this embodiment, the first conductive wire 222 of each layer of the memory device is connected to the second conductive layer 312 with the same area through the corresponding wire connection portion 221, so that signals are led out through the second conductive layer 312 with the same area. Therefore, the RC delay between the first conductive wires 222 of each layer can be effectively reduced. Moreover, the multi-step steps are distributed along the second direction, so that the area of the stepped structure 300 can be effectively saved, which is beneficial to improving the storage density.

[0139] In one embodiment, step S20 includes:

[0140] Step S21, alternately stack a first dielectric material layer 2101 and a sacrificial material layer 2301 on the substrate 100. Please refer to Figure 5 ;

[0141] Step S22, perform patterning on the first dielectric material layer 2101 and the sacrificial material layer 2301. The remaining first dielectric material layer 2101 forms a first dielectric layer 210. Please refer to Fig. 6(a). The remaining sacrificial material layer 2301 forms a sacrificial layer 230. Please refer to Fig. 6(b);

[0142] Step S23, remove the sacrificial layer 230, and form a first conductive layer 220 in the removal area of the sacrificial layer 230. Please refer to Figures 7 to 9 。

[0143] In step S21, please refer to Figure 5 , the first dielectric material layer 2101 and the sacrificial material layer 2301 can be alternately formed on the substrate 100 in sequence through a deposition process. As an example, it can be set that the material of the first dielectric material layer 2101 includes silicon oxide, and the material of the sacrificial material layer 2301 includes silicon nitride.

[0144] The deposition process can include but is not limited to one or more of processes such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High-Density Plasma (HDP) process, Plasma-Enhanced Deposition process, and Spin-on Dielectric (SOD).

[0145] As an example, the first dielectric material layer 2101 can be first formed on the surface of the substrate 100, then the sacrificial material layer 2301 is formed, and then the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately formed repeatedly. At this time, after the first conductive layer 220 is formed in subsequent step S23, the first conductive layer 220 can be effectively isolated from the substrate 100 through the first dielectric layer 210. Of course, in other examples, the sacrificial material layer 2301 can also be first formed on the surface of the substrate 100. There is no limitation here.

[0146] As an example, after the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately stacked on the substrate 100, the top layer of the stacked layers can be the first dielectric material layer 2101. At this time, after the sacrificial layer 230 is removed in subsequent step S23, the top first dielectric layer 210 can be effectively retained. Of course, in other examples, after the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately stacked on the substrate 100, the top layer of the stacked layers can also be the sacrificial material layer 2301. There is no limitation here.

[0147] In step S22, a patterned photoresist can be formed on the alternately stacked first dielectric material layer 2101 and sacrificial material layer 2301. Then, the alternately stacked first dielectric material layer 2101 and sacrificial material layer 2301 are dry-etched based on the patterned photoresist, so as to form the first dielectric layer 210 and the sacrificial layer 230. Please refer to FIGS. 6(a) and 6(b). Then, the patterned photoresist can be removed.

[0148] In step S23, the sacrificial layer 230 can be dry-etched first from the regions where the first dielectric material layer 2101 and the sacrificial material layer 2301 are etched and removed, so as to remove the sacrificial layer 230. Please refer to Figure 7 and Figure 8 .

[0149] Then, the first conductive layer 220 can be formed in the removal region of the sacrificial layer 230 by means of electroplating or chemical vapor deposition, etc. Please refer to Figure 9 .

[0150] In this embodiment, by first alternately stacking the first dielectric material layer 2101 and the sacrificial material layer 2301, it is convenient to perform good etching during the formation process of the patterned stacked structure 200, and then perform good patterning. Of course, in other embodiments, during the formation process of the patterned stacked structure 200, the first dielectric material layer 2101 and the first conductive material layer can also be directly alternately stacked, and then the two are patterned to form the first dielectric layer 210 and the first conductive layer 220.

[0151] In one embodiment, step S30 includes:

[0152] Step S31. Please refer to Figure 10, a step initial structure 3001 is formed on the substrate 100 on the side of the wire connection portion 221 away from the first wire 222 along the first direction. The step initial structure 3001 includes a plurality of stacked step initial layer groups 3101. The widths of the plurality of step initial layer groups 3101 in the second direction decrease successively with the stacking height to form a multi-step structure distributed along the second direction. And the step initial layer group 3101 includes a third dielectric initial layer 3131 and a second dielectric layer 311 formed in sequence. Within the same step initial layer group 3101, the orthographic projection of the third dielectric initial layer 3131 on the substrate 100 overlaps with the orthographic projection of the second dielectric layer 311 on the substrate 100;

[0153] Step S32, please refer to Figure 11 , laterally etch the third dielectric initial layer 3131 to form a hollowed-out area, and the remaining third dielectric initial layer 3131 forms the third dielectric layer 313;

[0154] Step S33, please refer to Figure 12 , form a second conductive layer 312 within the hollowed-out area.

[0155] In step S31, please refer to Figure 10 , the third dielectric initial layer 3131 can be disposed opposite to the first conductive layer 220, and their thicknesses can be the same. The second dielectric layer 311 can be disposed opposite to the first dielectric layer 210, and their thicknesses can be the same.

[0156] As an example, step S31 may include:

[0157] Step S311, alternately stack a second dielectric material layer and a third dielectric material layer on the substrate 100;

[0158] Step S312, etch the second dielectric material layer and the third dielectric material layer to form the step initial structure 3001. The remaining third dielectric material layer after etching forms the third dielectric initial layer 3131, and the remaining second dielectric material layer after etching forms the second dielectric layer 311.

[0159] In step S311, the second dielectric material layer and the third dielectric material layer can be alternately stacked on the substrate 100 in sequence by a deposition process.

[0160] As an example, the material of the second dielectric material layer includes silicon oxide, and the material of the third dielectric material layer includes silicon nitride.

[0161] In step S312, the second dielectric material layer and the third dielectric material layer can be etched by means such as cyclic shrinkage photoresist to form the step initial structure 3001.

[0162] As an example, the initial step structure 3001 may include two sets of multi-step structures symmetrically arranged in the second direction.

[0163] In step S32, refer to Figure 10 and Figure 11 , the initial third dielectric layer 3131 can be laterally etched by wet etching the third dielectric layer 3131 to form a hollowed-out area.

[0164] When the initial step structure 3001 includes two sets of multi-step structures symmetrically arranged in the second direction, both sides of the initial third dielectric layer 3131 in the second direction can be laterally etched to form symmetric hollowed-out areas.

[0165] In step S33, refer to Figure 12 , the second conductive layer 312 can be formed in the hollowed-out area by processes such as electroplating or chemical vapor deposition.

[0166] When symmetric hollowed-out areas are formed, symmetric second conductive layers 312 can be formed on both sides of the third dielectric layer 313 along the second direction.

[0167] In this embodiment, by using lateral etching to form a hollowed-out area and then forming the second conductive layer 312 in the hollowed-out area. Currently, lateral etching technology is mature and controllable, and it can effectively control the same projected area of different second conductive layers 312 of different step layer groups 310 on the substrate 100, thereby effectively reducing the RC delay. At the same time, the steps of the semiconductor structure can be fabricated monolithically, thereby reducing the wafer process cost.

[0168] In one embodiment, after step S30, it further includes:

[0169] Step S40, forming a plurality of contact holes 10 respectively penetrating the multi-step structures, refer to Figure 13 ;

[0170] Step S50, forming conductive plugs 400 in the contact holes 10, and the conductive plugs 400 on each step are connected to the corresponding second conductive layer 312 of the step, refer to Figure 14 .

[0171] In step S40, the plurality of contact holes 10 can penetrate the corresponding second conductive layers 312 of each step. The second conductive layers 312 can be completely staggered to facilitate the formation of mutually spaced contact holes 10. Of course, the second conductive layers 312 can also be partially staggered.

[0172] In step S50, a plug material layer can be deposited first, and then it is subjected to chemical mechanical polishing (CMP) treatment to form the conductive plugs 400.

[0173] The conductive plug 400 can extend into the peripheral circuit structure located within the substrate 100, such that the conductive plug 400 is electrically connected to the peripheral circuit structure. Alternatively, after forming the conductive plug 400, a peripheral circuit structure can be formed on top of the conductive plug 400, such that the conductive plug 400 is electrically connected to the peripheral circuit structure.

[0174] The material of the conductive plug 400 can include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), aluminum (Al), etc. The material of the conductive plug 400 can be the same as or different from the material of the second conductive layer 312.

[0175] As an example, when symmetric second conductive layers 312 are formed on both sides of the third dielectric layer 313 along the second direction, the stepped structure 300 can include two sets of multi-step steps symmetrically arranged in the second direction. Let one set of multi-step steps be located in the first step region A1, and the other set of multi-step steps be located in the second step region A3, and the region between them is the non-step region A2.

[0176] At this time, the contact holes 10 passing through the odd-numbered steps can be set to be located in the first step region A1, and the contact holes 10 passing through the even-numbered steps can be set to be located in the second step region A3. At this time, the density of the contact holes 10 can be effectively reduced, and then the density of the subsequently formed conductive plugs 400 can be reduced, thereby preventing short circuits between the conductive plugs 400.

[0177] As an example, the second region A5 where the stepped structure 300 is formed can be located on both sides of the first region A4 where the patterned stacked structure 200 is formed, such that the stepped structure 300 is located on both sides of the patterned stacked structure 200 along the first direction.

[0178] At this time, the first conductive wire 222 formed in the first region A4 can be led out from the second conductive layers 312 on both sides in its first direction, and thus the flexibility of setting the contact holes 10 and the conductive plugs 400 on the second conductive layer 312 can be improved, and then their setting density can be reduced.

[0179] Meanwhile, as an example, while step S40 forms a plurality of contact holes 10 respectively passing through the multi-step steps, a conductive wire hole 20 passing through the patterned stacked structure 200 can also be formed. While step S50 forms the conductive plugs 400 in the contact holes 10, a second conductive wire (not shown) is also formed in the conductive wire hole 20. One of the second conductive wire and the first conductive wire 222 is a bit line, and the other is a word line.

[0180] It should be understood that although Figure 4The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 4 At least some of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in rotation with at least some of the steps or stages in other steps or other steps.

[0181] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0182] The above-described embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can be made, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure patent shall be subject to the appended claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate; a patterned stack structure located on the substrate, including a first dielectric layer and a first conductive layer that are alternately stacked and overlap in the orthographic projection on the substrate, the first conductive layer including a wire connection portion and a first wire, and the first wire being connected to the wire connection portion in a first direction; a stepped structure located on the substrate and on a side of the wire connection portion away from the first wire in the first direction, including a plurality of stepped layer groups stacked, the plurality of stepped layer groups constituting a multi-step stepped structure distributed in a second direction, and the stepped layer group including a second dielectric layer, a second conductive layer, and a third dielectric layer, the second conductive layer being connected to the wire connection portion in the first direction, and within the same stepped layer group, the third dielectric layer and the second conductive layer are arranged in the second direction and their orthographic projections on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers of the plurality of stepped layer groups on the substrate are the same, and the second direction intersects the first direction.

2. The semiconductor structure according to claim 1, characterized in that, within the same stepped layer group, relative to the second conductive layer and the third dielectric layer, the second dielectric layer is away from the substrate.

3. The semiconductor structure according to claim 1, characterized in that, the stepped structure has a first stepped region, a non-stepped region, and a second stepped region, the first stepped region and the second stepped region are located on two sides of the non-stepped region in the second direction, the plurality of stepped layer groups form the multi-step stepped structure in both the first stepped region and the second stepped region, and within the same stepped layer group, a second conductive layer is provided in the first stepped region and / or the second stepped region.

4. The semiconductor structure according to claim 3, characterized in that, within the same stepped layer group, the second conductive layer is located on two sides of the third dielectric layer in the second direction.

5. The semiconductor structure according to claim 3, characterized in that, within the same stepped layer group, the second conductive layer is only located on one side of the third dielectric layer in the second direction, and in a direction perpendicular to the substrate, the second conductive layers in adjacent stepped layer groups are located on opposite sides in the second direction.

6. The semiconductor structure according to claim 3, characterized in that, the semiconductor structure further includes a plurality of conductive plugs, the plurality of conductive plugs respectively penetrate the multi-step stepped structure and connect to the corresponding second conductive layers, and the conductive plugs penetrating the odd-numbered steps are located in the first stepped region, and the conductive plugs penetrating the even-numbered steps are located in the second stepped region.

7. The semiconductor structure according to claim 1, characterized in that, the plurality of second conductive layers of the plurality of stepped layer groups are completely staggered in sequence in the second direction.

8. The semiconductor structure according to claim 1, characterized in that, the plurality of second conductive layers of the plurality of stepped layer groups are partially staggered in sequence in the second direction.

9. The semiconductor structure according to claim 1, characterized in that, the wire connection portions are provided on both sides of the first conductive wire in the first direction, and the stepped structures are provided on both sides of the patterned stacked structure in the first direction.

10. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a substrate; forming a patterned stacked structure on the substrate, the patterned stacked structure including a first dielectric layer and a first conductive layer that are alternately stacked and whose orthographic projections on the substrate overlap, the first conductive layer including a wire connection portion and a first conductive wire, the first conductive wire being connected to the wire connection portion in the first direction; forming a stepped structure on the substrate on a side of the wire connection portion away from the first conductive wire along the first direction, the stepped structure including a plurality of stacked stepped layer groups, the plurality of stepped layer groups constituting a multi-step stepped structure distributed in a second direction, and the stepped layer group including a second dielectric layer, a second conductive layer, and a third dielectric layer, the second conductive layer being connected to the wire connection portion in the first direction, and within the same stepped layer group, the third dielectric layer and the second conductive layer are arranged in the second direction and their orthographic projections on the substrate overlap with the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers of the plurality of stepped layer groups on the substrate are the same, and the second direction intersects the first direction.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, the forming of the patterned stacked structure on the substrate includes: alternately stacking a first dielectric material layer and a sacrificial material layer on the substrate; performing a patterning process on the first dielectric material layer and the sacrificial material layer, and the remaining first dielectric material layer forms the first dielectric layer, and the remaining sacrificial material layer forms a sacrificial layer; removing the sacrificial layer, and forming the first conductive layer in an area where the sacrificial layer is removed.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that, the material of the first dielectric material layer includes silicon oxide, and the material of the sacrificial material layer includes silicon nitride.

13. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, the forming of the stepped structure on the substrate on a side of the wire connection portion away from the first conductive wire along the first direction includes: forming a stepped initial structure on the substrate on a side of the wire connection portion away from the first conductive wire along the first direction, the stepped initial structure including a plurality of stacked stepped initial layer groups, the widths of the plurality of stepped initial layer groups in the second direction decrease successively with the stacking height and constitute a multi-step stepped structure distributed in the second direction, and the stepped initial layer group includes a third dielectric initial layer and a second dielectric layer formed in sequence, and within the same stepped initial layer group, the orthographic projection of the third dielectric initial layer on the substrate overlaps with the orthographic projection of the second dielectric layer on the substrate; Etch the third dielectric initial layer laterally to form a hollowed-out area, and the remaining third dielectric initial layer forms the third dielectric layer; Form the second conductive layer within the hollowed-out area.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein, forming a stepped initial structure on the substrate on the side of the wire connection portion away from the first conductive wire along the first direction includes: alternately stacking a second dielectric material layer and a third dielectric material layer on the substrate; etch the second dielectric material layer and the third dielectric material layer to form the stepped initial structure, the remaining third dielectric material layer after etching forms the third dielectric initial layer, and the remaining second dielectric material layer after etching forms the second dielectric layer.

15. The method for manufacturing a semiconductor structure according to claim 10, wherein, after forming the stepped structure on the substrate on the side of the wire connection portion away from the first conductive wire along the first direction, further includes: forming a plurality of contact holes respectively penetrating through the multi-step; forming conductive plugs within the contact holes, and the conductive plugs on each step are connected to the second conductive layer corresponding to the step.

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