Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises the components of a substrate which is internally provided with a plurality of active regions which are arranged at intervals along a first direction; a plurality of contact holes which are arranged at intervals in the first direction are also formed in the substrate, and the adjacent active regions are exposed out of the contact holes; the contact hole is filled with the contact structure, and the contact structure comprises a first contact structure located above the active region; the first side wall structure covers at least part of the side surface of the first contact structure; the second contact structure covers at least part of the side face of the first side wall structure, the second contact structure is located between the two adjacent active areas, the first contact structure is in electric contact with one of the adjacent active areas, and the second contact structure is in electric contact with the other one of the adjacent active areas. The semiconductor structure provided by the embodiment of the invention at least can improve the reliability of the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A DRAM (Dynamic Random Access Memory) memory is a common semiconductor memory. The memory includes word lines, bit line structures, and capacitors. The bit line structures and the capacitors are usually in signal transmission with transistors through different contact structures.

[0003] During the manufacturing process of semiconductor memories, two adjacent contact structures are formed in different contact holes respectively. The two contact structures electrically connect the bit line structure and the capacitor to different active regions respectively. However, as the size of semiconductor memories becomes smaller and smaller, the adjacent contact structures formed in different contact holes are prone to electrical contact problems and cause short circuits, thereby reducing the reliability of semiconductor memories. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the reliability of the semiconductor structure.

[0005] Embodiments of the present disclosure provide a semiconductor structure, including: a substrate having a plurality of active regions arranged at intervals along a first direction; the substrate further having a plurality of contact holes arranged at intervals along the first direction, and the contact holes expose adjacent active regions; a contact structure filled in the contact holes, the contact structure including: a first contact structure located above the active region; a first sidewall structure covering at least a part of the side surface of the first contact structure; a second contact structure covering at least a part of the side surface of the first sidewall structure, and the second contact structure is located between two adjacent active regions, wherein the first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions.

[0006] In some embodiments, the contact structure includes: two spaced second contact structures, and the two second contact structures are respectively in electrical contact with different active regions.

[0007] In some embodiments, the active regions extend along a preset direction, and the active regions include a first source / drain region, a channel region, and a second source / drain region arranged at intervals along the preset direction. The channel region is located on both sides of the first source / drain region, and the second source / drain region is located on the side of the channel region away from the first source / drain region; the plurality of active regions include: first active regions and second active regions arranged alternately along the first direction; wherein, the first contact structure is in electrical contact with the first source / drain region of one of the adjacent first active regions or second active regions, and the second contact structure is in electrical contact with the second source / drain region of the other of the adjacent first active regions or second active regions.

[0008] In some embodiments, the semiconductor structure further includes: a plurality of bit line structures arranged at intervals along a third direction on the substrate, the bit line structures extending along a second direction, the first direction, the second direction, and the third direction intersecting pairwise, and the third direction being perpendicular to the second direction; and a plurality of capacitor structures, each capacitor structure being located on the substrate and coupled to the second contact structure.

[0009] In some embodiments, the orthographic projection shape of the contact hole in the second direction is an inverted trapezoid or an ellipse, the orthographic projection shape of the contact hole in the third direction is a rectangle, and the second contact structure is located on the sidewall of the contact hole in the third direction.

[0010] Correspondingly, an embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a substrate in which a plurality of active regions are arranged at intervals along a first direction; forming a contact hole in the substrate, the bottom of the contact hole exposing one of the adjacent active regions, and the sidewall of the contact hole exposing the other of the adjacent active regions; forming a second contact structure on a part of the sidewall of the contact hole, the second contact structure being in electrical contact with the active region exposed by the sidewall of the contact hole; forming a first sidewall structure in the contact hole, the first sidewall structure at least covering the second contact structure; and forming a first contact structure filling the remaining contact hole, where the first contact structure is located above the active region exposed by the bottom of the contact hole and is in electrical contact with the active region.

[0011] In some embodiments, the method for forming the contact hole includes: forming a first mask layer on the substrate; patterning the first mask layer to form a first opening in the first mask layer, the first opening being partially opposite to one of the adjacent active regions and also being partially opposite to the other of the adjacent active regions; and using a first etching process to etch the substrate along the first opening to expose the active region, thereby forming the contact hole.

[0012] In some embodiments, the method for forming the second contact structure includes: using a deposition process to form an initial second contact structure on the sidewall of the contact hole, where the initial second contact structure covering the sidewall of the contact hole in the third direction has a first thickness, and the initial second contact structure covering the sidewall of the contact hole in the second direction has a second thickness, the first thickness being greater than the second thickness, the first direction, the second direction, and the third direction intersecting pairwise, and the third direction being perpendicular to the second direction, and the sidewall of the contact hole in the third direction exposing the active region; using a second etching process to etch the initial second contact structure to remove all of the initial second contact structure covering the sidewall of the contact hole in the second direction and a part of the initial second contact structure covering the sidewall of the contact hole in the third direction, and the remaining initial second contact structure serves as the second contact structure.

[0013] In some embodiments, before forming the contact holes, the method further includes: forming an isolation structure located between adjacent active regions, where the bottom of the formed contact holes exposes the active regions and a part of the isolation structure on both sides of the active regions, and the second contact structure is located on the surface of the exposed isolation structure.

[0014] In some embodiments, the first sidewall structure includes a first silicon oxide layer and a first silicon nitride layer stacked in sequence in a direction away from the first contact structure.

[0015] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0016] In the semiconductor structure provided by the embodiments of the present disclosure, the contact structure filled in the contact holes includes a first contact structure and a second contact structure. The first contact structure is located above the active region, and the second contact structure is located between adjacent active regions. The first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions. That is, the first contact structure and the second contact structure are respectively in electrical contact with different active regions among adjacent active regions, so as to be able to lead out the signals of different active regions or transmit external signals to different active regions.

[0017] For example, the first contact structure can form signal transmission between the active region and the bit line structure, and the second contact structure can form signal transmission between the active region and the capacitor.

[0018] Since both the first contact structure and the second contact structure are located in the same contact hole, in the actual process of fabricating the semiconductor structure, there is no need to etch different contact holes in the substrate to form the first contact structure and the second contact structure respectively, avoiding the process damage caused by etching different contact holes, which may lead to electrical connection between the formed first contact structure and the second contact structure, thereby improving the reliability of the semiconductor structure.

[0019] The first contact structure and the second contact structure are insulated from each other by the first sidewall structure, avoiding electrical contact between the first contact structure and the second contact structure, which may cause a short circuit, and further improving the reliability of the semiconductor structure.

[0020] The gate structure is located on the substrate in the peripheral region, which can ensure that the process of actually fabricating the gate structure has a large process window, so that the topography of the gate structure meets the expectations and maintains good performance of the gate structure. While ensuring better performance of the gate structure, the parasitic capacitance of the array region is reduced, thereby improving the overall performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figures 1 to 4 It is a schematic cross-sectional structure diagram corresponding to different steps in a method for preparing a semiconductor structure;

[0023] Figure 5 It is a top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 6 It is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figure 7 It is a top view of a partial structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 8 It is a top view of a partial structure of another semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 9 It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0028] Figure 10 It is a top view of another semiconductor structure provided by an embodiment of the present disclosure;

[0029] Figure 11 It is a schematic cross-sectional structure diagram of yet another semiconductor structure provided by an embodiment of the present disclosure;

[0030] Figure 12 It is a schematic cross-sectional structure diagram of yet another semiconductor structure along the aa' direction provided by an embodiment of the present disclosure;

[0031] Figure 13 It is a schematic cross-sectional structure diagram of yet another semiconductor structure along the bb' direction provided by an embodiment of the present disclosure;

[0032] Figures 14 to 35 It is a schematic cross-sectional structure diagram corresponding to different steps in a method for preparing a semiconductor structure provided by another embodiment of the present disclosure. Detailed implementation manners

[0033] As can be seen from the background art, the reliability of the current semiconductor structure needs to be further improved. Analysis reveals that one of the reasons for the need to further improve the reliability of the semiconductor structure is that currently, different contact structures need to be prepared in different contact holes to electrically connect the bit line structure to the capacitor and different active regions respectively.

[0034] As Figure 1 shown, first, a first contact hole 1 is formed in the substrate 10. An active region is exposed at the bottom of the first contact hole 1, and an initial first contact structure 12 is formed. The initial first contact structure 12 fills multiple first contact holes 1 and is in electrical contact with the active region 11 in the substrate 10.

[0035] After the initial first contact structure 12 is formed, different film layers required for forming the bit line structure are deposited on the top surface of the initial first contact structure 12.

[0036] After that, as Figure 2 shown, in the same process step, a patterning etching process is performed on the above different film layers and the initial first contact structure 12 to form discrete bit line structures 14 and first contact structures 13. The first contact structure 13 is located in the first contact hole 1, and the bit line structure 14 is located on the top surface of the first contact structure 13.

[0037] It should be noted that due to the continuously decreasing size of the semiconductor structure, the size of the first contact hole 1 is also getting smaller, and the aspect ratio of the first contact hole 1 is getting larger. As a result, when etching the initial first contact structure 12, it is difficult to completely etch the initial first contact structure 12 at the bottom of the first contact hole 1. As shown by the dashed box in Figure 2 , the remaining part is caused by incomplete etching. The bottom of the formed first contact structure 13 is likely to occupy the entire bottom or nearly the entire bottom of the first contact hole 1. Or, due to incomplete alignment of the alignment marks during the patterning process, an etching deviation occurs, resulting in a very narrow space between the first contact structure 13 and one side of the first contact hole 1, making it even more difficult to completely etch the bottom of the first contact structure 13 on the narrow side.

[0038] As Figure 3 shown, a sidewall structure 15 is formed on the sidewalls of the bit line structure 14 and the first contact structure 13. Since the bottom of the first contact structure 13 occupies the entire bottom or nearly the entire bottom of the first contact hole 1, the sidewall structure 15 cannot contact the bottom of the first contact hole 1. That is, the sidewall structure 15 is formed on the top surface of the remaining part in the dashed box and cannot be formed on the side surface of the remaining part. Furthermore, it cannot provide protection for the side surface of the remaining part.

[0039] After that, as Figure 4As shown, etch a part of the substrate 10 and a part of the sidewall structure 15 in the first contact hole 1 to form a second contact hole 2, and the second contact hole 2 is adjacent to the first contact hole 1. Since the sidewall structure is formed on the top surface of the remaining part in the dashed box, it cannot provide protection for the side surface of the remaining part. Therefore, during the process of etching the sidewall structure 15 in the first contact hole 1, it is easy to etch through the sidewall structure 15 on the top surface of the remaining part in the dashed box, and then expose the bottom of the first contact structure 13 in the dashed box. After forming the second contact structure 16 in the second contact hole 2, the second contact structure 16 will form an electrical connection with the exposed bottom of the first contact structure 15, thereby causing a short - circuit problem, as Figure 4 shown by the dashed box in, reducing the reliability of the semiconductor structure.

[0040] An embodiment of the present disclosure provides a semiconductor structure. Since both the first contact structure and the second contact structure are located in the same contact hole, during the actual process of fabricating the semiconductor structure, there is no need to etch different contact holes in the substrate to form the first contact structure and the second contact structure respectively, avoiding the process damage caused by etching different contact holes, which may lead to an electrical connection between the formed first contact structure and the second contact structure, and thus improving the reliability of the semiconductor structure. The first contact structure and the second contact structure are insulated from each other by the first sidewall structure, avoiding electrical contact between the first contact structure and the second contact structure and resulting in a short - circuit, further enhancing the reliability of the semiconductor structure.

[0041] The following will elaborate on each embodiment of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0042] Figure 5 is a top - view diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 5 and the dashed box in represents the contact hole; Figure 6 is a schematic cross - sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 6 is a cross - sectional structure diagram in the aa' direction, and the direction of aa' can be referred to Figure 5 as shown in.

[0043] Refer to Figure 5 and Figure 6, the semiconductor structure includes: a substrate 100 having a plurality of active regions 101 arranged at intervals along a first direction X; the substrate 100 further has a plurality of contact holes 103 arranged at intervals along the first direction X, and the contact holes 103 expose adjacent active regions 101. The semiconductor structure further includes: a contact structure filled in the contact holes 103, the contact structure includes: a first contact structure 104 located above the active region 101; a first sidewall structure 105 covering at least part of the side surface of the first contact structure 104; a second contact structure 106 covering at least part of the side surface of the first sidewall structure 105, and the second contact structure 106 is located between two adjacent active regions 101, wherein the first contact structure 104 is in electrical contact with one of the adjacent active regions 101, and the second contact structure 106 is in electrical contact with the other of the adjacent active regions 101.

[0044] The first contact structure 104 is located above the active region 101 and is in electrical contact with the top of the active region 101. The second contact structure 106 is located between the active regions 101 adjacent along the first direction X, and the first contact structure 104 is in electrical contact with one of the adjacent active regions 101, and the second contact structure 106 is in electrical contact with the other of the adjacent active regions 101. That is, the first contact structure 104 and the second contact structure 106 are respectively in electrical contact with different active regions 101 among the adjacent active regions 101, so that signals of different active regions 101 can be led out, or external signals can be transmitted into different active regions 101.

[0045] In some embodiments, the first contact structure 104 can form signal transmission between the active region 101 and the bit line structure, and the second contact structure 106 can form signal transmission between the active region 101 and the capacitor.

[0046] Both the first contact structure 104 and the second contact structure 106 are located in the same contact hole 103. Therefore, in the actual process of fabricating the semiconductor structure, there is no need to etch different contact holes 103 in the substrate 100 to respectively form the first contact structure 104 and the second contact structure 106, avoiding the problem that the first contact structure 104 and the second contact structure 106 formed due to the process damage caused by etching different contact holes 103 are electrically connected, thereby improving the reliability of the semiconductor structure.

[0047] In addition, since the first sidewall structure 105 covers at least part of the side surface of the first contact structure 104, and the second contact structure 106 covers at least part of the side surface of the first sidewall structure 105, the first contact structure 104 and the second contact structure 106 are insulated from each other through the first sidewall structure 105, avoiding the problem of short circuit caused by electrical contact between the first contact structure 104 and the second contact structure 106, and further improving the reliability of the semiconductor structure.

[0048] In some embodiments, the material of the substrate 100 may be a semiconductor material. In some embodiments, the material of the substrate 100 may be silicon. In some embodiments, the substrate 100 may also be germanium, silicon germanium, or silicon on insulator.

[0049] Reference Figure 5 、 Figure 7 and Figure 8 , in some embodiments, the active region 101 extends along a preset direction W. The active region 101 includes a first source-drain region 111, a channel region 113, and a second source-drain region 112 that are arranged at intervals along the preset direction W. The channel region 113 is located on both sides of the first source-drain region 111, and the second source-drain region 112 is located on a side of the channel region 113 away from the first source-drain region 111; the plurality of active regions 101 include: a first active region 1011 and a second active region 1012 that are alternately arranged along a first direction X; wherein, the first contact structure 104 is in electrical contact with the first source-drain region 111 of one of the adjacent first active region 1011 or second active region 1012, and the second contact structure 106 is in electrical contact with the second source-drain region 112 of the other of the adjacent first active region 1011 or second active region 1012.

[0050] That is to say, for one active region 101, the number of the first source-drain regions 111 is 1, the number of the channel regions 113 is 2, which are respectively located on both sides of the first active region 1011, and the number of the second source-drain regions 112 is 2, which are respectively located on both sides of the channel region 113 away from the first source-drain region 111.

[0051] One first source-drain region 111, one channel region 113, and one second source-drain region 112 can form one transistor. Since in one active region 101, the number of the channel regions 113 and the number of the second source-drain regions 112 are both 2, therefore, one active region 101 can form 2 transistors. The two transistors share the same first source-drain region 111.

[0052] In some embodiments, the first source-drain region 111 can be used as the source electrode of the transistor, and the second source-drain region 112 can be used as the drain electrode of the transistor.

[0053] In some embodiments, the doping ion types of the first source-drain region 111 and the second source-drain region 112 may be the same, and the doping ion type of the channel region 113 may be different from that of the first source-drain region 111 and the second source-drain region 112. For example, the doping ions in the first source-drain region 111 and the second source-drain region 112 are both N-type doping ions, the doping ion type of the channel region 113 is P-type doping ions, and the type of the transistor formed in the active region 101 is an NMOS transistor. For another example, the doping ion types of the first source-drain region 111 and the second source-drain region 112 may also be both P-type doping ions, the doping ion type of the channel region 113 may be N-type doping ions, and the type of the transistor formed in the active region 101 is a PMOS transistor.

[0054] In some embodiments, the N-type doping ion may be any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0055] In some embodiments, the P-type doping ion may be any one of boron ions, aluminum ions, gallium ions, or indium ions.

[0056] The first active region 1011 and the second active region 1012 are the same active region 101. In order to distinguish between two adjacent active regions 101 in the embodiments of the present disclosure, the adjacent active regions 101 are respectively named as the alternately arranged first active region 1011 and the second active region 1012. That is, the active regions 101 arranged at intervals along the first direction X include: the first active region 1011, the second active region 1012, the first active region 1011, the second active region 1012,... the first active region 1011, the second active region 1012 that are alternately arranged along the first direction X.

[0057] The first contact structure 104 may be in electrical contact with the first source-drain region 111 of the first active region 1011 among two adjacent active regions 101, and the second contact structure 106 may be in electrical contact with the second source-drain region 112 of the second active region 1012 among two adjacent active regions 101. If the first source-drain region 111 serves as the source electrode of the transistor and the second source-drain region 112 serves as the drain electrode of the transistor, the first contact structure 104 is used to transmit the source signal of the first active region 1011, and the second contact structure 106 is used to transmit the drain signal of the second active region 1012. That is, the first contact structure 104 and the second contact structure 106 respectively transmit different signals in two adjacent active regions 101.

[0058] In some embodiments, the contact structure includes: two spaced second contact structures 106, and the two second contact structures 106 are respectively in electrical contact with different active regions 101.

[0059] In some embodiments, the two second contact structures 106 may be respectively located on both sides of the first contact structure 104.

[0060] In some embodiments, the active regions 101 arranged at intervals along the first direction X include: first active regions 1011, second active regions 1012, first active regions 1011, second active regions 1012, ..., first active regions 1011, second active regions 1012, which are alternately arranged along the first direction X. The first contact structure 104 is located above the first active region 1011 and is in electrical contact with the first active region 1011. Then, one of the two second contact structures 106 can be in electrical contact with one of the second active regions 1012 adjacent to the first active region 1011, and the other of the two contact structures can be in electrical contact with the other second active region 1012 adjacent to the first active region 1011.

[0061] In a specific example, the first contact structure 104 is in electrical contact with the first source / drain region 111 of the first active region 1011, one second contact structure 106 is in electrical contact with the second source / drain region 112 of one second active region 1012 adjacent to the first active region 1011, and the other second contact structure 106 is in electrical contact with the second source / drain region 112 of the other second active region 1012 adjacent to the first active region 1011.

[0062] More specifically, the two second source / drain regions 112 in each active region 101 are respectively located at two opposite ends of the active region 101, which are respectively denoted as: the head second source / drain region and the tail second source / drain region, so as to distinguish the different end positions where the two second source / drain regions 112 are located. The first contact structure 104 is in electrical contact with the first source / drain region 111 of the first active region 1011, one second contact structure 106 is in electrical contact with the head second source / drain region of one second active region 1012 adjacent to the first active region 1011, and the other second contact structure 106 is in electrical contact with the tail second source / drain region of the other second active region 1012 adjacent to the first active region 1011.

[0063] In some embodiments, the contact structure may also only include one second contact structure 106. For the same contact structure, if the first contact structure 104 is in electrical contact with the first active region 1011, then the second contact structure 106 is only in electrical contact with one of the second active regions 1012 adjacent to the first active region 1011, and is not in electrical contact with the other second active region 1012 adjacent to the first active region 1011.

[0064] It can be understood that whether the number of the second contact structures 106 is one or two, each second contact structure 106 is isolated from the first contact structure 104 by the first sidewall structure 105.

[0065] Reference Figure 7, in some embodiments, the first sidewall structure 105 can surround the entire side surface of the first contact structure 104, and the second contact structure 106 only covers a partial side surface of the first sidewall structure 105.

[0066] Reference Figure 8 , in some embodiments, the first sidewall structure 105 can also only cover a partial side surface of the first contact structure 104, and the second contact structure 106 is only located on the surface of the first sidewall structure 105, so that the first sidewall structure 105 can isolate the first contact structure 104 from the second contact structure 106, avoiding the problem of short circuit caused by electrical connection between the first contact structure 104 and the second contact structure 106.

[0067] In some embodiments, the contact hole 103 extends in a direction pointing from the surface of the substrate 100 into the substrate 100. In the extending direction of the contact hole 103, the heights of the first sidewall structure 105, the first contact structure 104, and the second contact structure 106 are the same. The top surfaces of the first sidewall structure 105, the first contact structure 104, and the second contact structure 106 are all flush with the opening of the contact hole 103, and the bottom surfaces of the first sidewall structure 105, the first contact structure 104, and the second contact structure 106 are all flush with the bottom of the contact hole 103.

[0068] In some embodiments, the material of the first contact structure 104 can include any one of polysilicon, amorphous silicon, or microcrystalline silicon. The material of the second contact structure 106 can include any one of polysilicon, amorphous silicon, or microcrystalline silicon.

[0069] Figure 9 It is a schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present disclosure. Figure 9 It is a schematic cross-sectional structure diagram in the aa' direction, and the aa' direction can be referred to Figure 5 to the direction shown in.

[0070] Reference Figure 9 , in some embodiments, the first sidewall structure 105 can be a double-layer structure, including a first silicon oxide layer 1051 and a first silicon nitride layer 1052 stacked in sequence along the direction away from the first contact structure 104. The material of the first silicon oxide layer 1051 includes silicon oxide, and the material of the first silicon nitride layer 1052 includes silicon nitride.

[0071] In some embodiments, the first sidewall structure 105 can also be a triple-layer structure, including a first silicon oxide layer and first silicon nitride layers on both sides of the first silicon oxide layer. Specifically, the triple-layer structure is: a first silicon nitride layer, a first silicon oxide layer, and a first silicon nitride layer stacked in sequence along the direction away from the first contact structure 104. The material of the first silicon nitride layer includes silicon nitride, and the material of the first silicon oxide layer includes silicon oxide.

[0072] It should be noted that whether the first sidewall structure 105 is a double-layer structure or a triple-layer structure, the total thickness is the same or close, so that the overall size of the contact hole 103 can be ensured to be small.

[0073] In some embodiments, the semiconductor structure may further include: an isolation structure 102 located between adjacent active regions 101 for isolating the adjacent active regions 101. The first contact structure 104 is located on the top surface of the active region 101, and the second contact structure 106 may be located on the top surface of the isolation structure 102 between adjacent active regions 101. In some embodiments, the material of the isolation structure 102 may be silicon oxide.

[0074] Reference Figures 10 to 11 , in some embodiments, the semiconductor structure further includes: a plurality of bit line structures 107 arranged at intervals along the third direction Z on the substrate 100, the bit line structures 107 extending along the second direction Y, the first direction X, the second direction Y, and the third direction Z intersecting pairwise, and the third direction Z being perpendicular to the second direction Y; a plurality of capacitor structures, each capacitor structure being located on the substrate 100 and coupled to the second contact structure 106.

[0075] The substrate 100 includes active regions 101 arranged in an array, the active regions 101 being arranged at intervals along the first direction X and the second direction Y, wherein each row of active regions 101 is arranged at intervals along the first direction X, each column of active regions 101 is arranged at intervals along the second direction Y, and multiple columns of active regions 101 are arranged at intervals along the third direction Z. A plurality of bit line structures 107 arranged at intervals along the third direction Z correspond to multiple columns of active regions 101 arranged at intervals along the third direction Z one by one, and each bit line structure 107 is coupled to the first source / drain region 111 of each active region 101 in each column of active regions 101 through the first contact structure 104.

[0076] In some embodiments, the bit line structure 107 may include: a bit line barrier layer 121, a bit line conductive layer 122, and a bit line capping layer 123 stacked in sequence along a direction away from the surface of the substrate 100.

[0077] The bit line barrier layer 121 covers the top surface of the first contact structure 104 and is located between the first contact structure 104 and the bit line conductive layer 122, serving to prevent the problem of mutual diffusion of ions between the first contact structure 104 and the bit line conductive layer 122. The material of the bit line barrier layer 121 may include any one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride.

[0078] The bit line conductive layer 122 mainly functions to conduct electricity and is used to transmit electrical signals. The material of the bit line conductive layer 122 may include a metal material, for example, at least one of metal materials such as tungsten, titanium, or nickel.

[0079] The bit line capping layer 123 is used to protect the bit line conductive layer 122. In some embodiments, the material of the bit line capping layer 123 may include any one of silicon nitride or silicon oxynitride.

[0080] Reference Figure 11 , in some embodiments, the semiconductor structure further includes: a second sidewall structure 108, which is located on opposite sidewalls of the bit line structure 107 in the first direction X, that is, covering the sidewalls of the bit line barrier layer 121, the bit line conductive layer 122, and the bit line capping layer 123 in the first direction X.

[0081] In some embodiments, the second sidewall structure 108 may be a double-layer structure, including: a second silicon oxide layer 1081 and a second silicon nitride layer 1082 stacked in sequence along the direction away from the bit line structure 107.

[0082] In some embodiments, the second sidewall structure 108 may also be a triple-layer structure, including: one layer of second silicon oxide layer and two layers of second silicon nitride layers, specifically: a second silicon nitride layer, a second oxide layer, and a second silicon nitride layer stacked in sequence along the direction away from the bit line structure 107.

[0083] The material of the second sidewall structure 108 may be the same as that of the first sidewall structure 105. In other words, the first sidewall structure 105 and the second sidewall structure 108 may both be the above double-layer structure or both be the above triple-layer structure. The thickness of the first silicon oxide layer 1051 in the first sidewall structure 105 may be the same as or close to the thickness of the second silicon oxide layer in the second sidewall structure 108. The thickness of the first silicon nitride layer 1052 in the first sidewall structure 105 may be the same as or close to the thickness of the second silicon nitride layer in the second sidewall structure 108.

[0084] The number of capacitor structures may be multiple, and each capacitor structure is coupled to the second source / drain region 112 of each active region 101.

[0085] Reference Figure 11 , in some embodiments, the semiconductor structure may further include: a capacitor contact plug 110, which is located between two adjacent bit line structures 107 along the first direction X on the substrate 100. The bottom surface of the capacitor contact plug 110 contacts the top surface of the second contact structure 106, and the capacitor structure is located on the top surface of the capacitor contact plug 110 and is coupled to the active region 101 through the capacitor contact plug 110 and the second contact structure 106.

[0086] In some embodiments, the material of the capacitor contact plug 110 may be the same as that of the second contact structure 106, for example, it may be polysilicon.

[0087] It can be understood that since the first contact structure 104 and the second contact structure 106 are located in the same contact hole 103, in the actual manufacturing process, the first contact structure 104 and the second contact structure 106 can be fabricated in the contact hole 103 first, and then, the bit line structure 107 and the capacitor contact plug 110 are formed in sequence, so that the bit line structure 107 contacts the first contact structure 104, and the capacitor contact plug 110 contacts the second contact structure 106. In this way, the first contact structure 104 and the bit line structure 107 are formed in different steps, which can avoid the problem that the first contact structure 104 is incompletely etched due to the simultaneous etching of the bit line structure 107 and the first contact structure 104, and further avoid the short-circuit problem in the related art.

[0088] Figure 12 FIG. aa'-direction cross-sectional structure schematic diagram of still another semiconductor structure provided by an embodiment of the present disclosure, specifically Figure 10 the aa'-direction cross-sectional structure schematic diagram in Figure 13 FIG. bb'-direction cross-sectional structure schematic diagram of still another semiconductor structure provided by an embodiment of the present disclosure, specifically Figure 10 the bb'-direction cross-sectional structure schematic diagram in. In the embodiment of the present disclosure, the aa' direction shown is consistent with the extension direction of the third direction, and the bb' direction shown is consistent with the extension direction of the second direction.

[0089] Referring to Figure 10 and Figure 13 , in some embodiments, the semiconductor structure further includes: a plurality of word lines 109, the word lines 109 are located in the substrate 100 to form buried word lines. The plurality of word lines 109 are arranged at intervals along the second direction Y, and each word line 109 extends along the third direction Z, and the word line 109 is electrically connected to the channel region 113 of the active region 101. Among them, the two channel regions 113 of each active region 101 are respectively electrically connected to two word lines 109.

[0090] The word line 109 may include a word line conductive layer 131, a word line barrier layer 132, and a word line capping layer 133 stacked in sequence. The word line barrier layer 132 is located on the top surface of the word line conductive layer 131, and the word line capping layer 133 is located on the top surface of the word line conductive layer 131. The material of the word line barrier layer 132 may include any one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride. The material of the word line conductive layer 131 may include a metal material, for example, at least one of metal materials such as tungsten, titanium, or nickel. The material of the word line capping layer 133 may include any one of silicon nitride or silicon oxynitride.

[0091] Referring to Figure 6 , Figure 9 and Figure 12 , wherein, Figure 6 , Figure 9and Figure 12 Both are schematic cross-sectional structures in the aa' direction. In some embodiments, the shape of the orthographic projection of the contact hole 103 in the second direction Y is a trapezoid or an ellipse.

[0092] Reference Figure 13 , Figure 13 is a schematic cross-sectional structure in the bb' direction. In some embodiments, the shape of the orthographic projection of the contact hole 103 in the third direction Z is a rectangle, and the second contact structure 106 is located on the sidewall of the contact hole 103 in the third direction Z.

[0093] The contact holes 103 are arranged in an array in the substrate 100. The contact holes 103 are spaced along the first direction X and the second direction Y. Each row of contact holes 103 is spaced along the first direction X, and each column of contact holes 103 is spaced along the second direction Y. Each contact hole 103 corresponds to an active region 101, that is, the contact structure in each contact hole 103 corresponds to an active region 101.

[0094] That is to say, the shape of the orthographic projection of the contact hole 103 in the extending direction of the bit line structure 107 is a trapezoid or an ellipse, and the shape of the orthographic projection of the contact hole 103 in the arranging direction of the bit line structure 107 is a rectangle. That is, the sidewall of the contact hole 103 in the extending direction of the bit line structure 107 is perpendicular to the surface of the substrate 100, and the sidewall of the contact hole 103 in the arranging direction of the bit line structure 107 is inclined with respect to the surface of the substrate 100, and the sidewall of the contact hole 103 in the arranging direction of the bit line structure 107 exposes the active region 101. Since the second contact structure 106 is formed on the sidewall of the contact hole 103, in the actual step of forming the second contact structure 106, the material layer of the second contact structure 106 is initially deposited on the entire sidewall of the contact hole 103. The thickness of the material layer of the second contact structure 106 deposited on the vertical sidewall of the contact hole 103 is smaller than the thickness of the material layer of the second contact structure 106 deposited on the inclined sidewall. In the subsequent step of further etching the material layer of the second contact structure 106 on the sidewall of the contact hole 103, after the material layer on the vertical sidewall of the contact hole 103 is completely etched, there is still a residue of the material layer on the inclined sidewall of the contact hole 103. That is, the unetched material layer on the sidewall of the contact hole 103 in the arranging direction of the bit line structure 107 can be used as the final second contact structure 106. In this way, the second contact structures 106 on the opposite two sidewalls of the contact hole 103 in the arranging direction of the bit line structure 107 are separated from each other and are respectively in electrical contact with two active regions 101.

[0095] It should be noted that the orthographic projection shape of the contact hole 103 in the extending direction of the bit line structure 107 is an inverted trapezoid or an ellipse, and the orthographic projection shape of the contact hole 103 in the arranging direction of the bit line structure 107 is a rectangle, which both refer to the orthographic projection shape of the contact hole 103 located in the substrate 100.

[0096] In the semiconductor structure provided by the above embodiment, both the first contact structure 104 and the second contact structure 106 are located in the same contact hole 103. During the actual preparation process of the semiconductor structure, there is no need to etch different contact holes 103 in the substrate 100 to form the first contact structure 104 and the second contact structure 106 respectively, so as to avoid the process damage caused by etching different contact holes 103, which may lead to the electrical connection between the formed first contact structure 104 and the second contact structure 106, thereby improving the reliability of the semiconductor structure. The first contact structure 104 and the second contact structure 106 are insulated from each other through the first sidewall structure 105, avoiding electrical contact between the first contact structure 104 and the second contact structure 106 and resulting in a short circuit, and further improving the reliability of the semiconductor structure.

[0097] Correspondingly, the embodiment of the present disclosure further provides a method for preparing a semiconductor structure. The method for preparing the semiconductor structure can be used to prepare the semiconductor structure provided by the above embodiment. Hereinafter, a semiconductor structure provided by an embodiment of the present disclosure will be described in detail with reference to the drawings. It should be noted that the aa' direction and the bb' direction mentioned below can be referred to Figure 5 or Figure 10 to the aa' direction and the bb' direction shown in

[0098] Referring to Figures 14 to 35 , the method for preparing a semiconductor structure includes:

[0099] Referring to Figure 14 , provide a substrate 100, and a plurality of active regions 101 arranged at intervals along the first direction X are formed in the substrate 100.

[0100] In some embodiments, the material of the substrate 100 may be a semiconductor material. In some embodiments, the material of the substrate 100 may be silicon. In some embodiments, the substrate 100 may also be germanium, germanium silicon, or silicon on insulator.

[0101] In some embodiments, the method for forming the active region 101 includes:

[0102] An initial substrate is provided, and the initial substrate is a substrate that has not been doped or etched. A patterning process is performed on the surface of the initial substrate for the position of the active region 101. In some embodiments, any one of the SADP (Self-aligned Double Patterning) process or the SAQP (Self-Aligned Quadruple Patterning) process can be used to pattern the surface of the initial substrate. Thereafter, an etching process is performed on the patterned surface of the initial substrate to etch a part of the thickness of the initial substrate to form a plurality of spaced trenches in the substrate 100 and the active region 101 separated by the trenches. In some embodiments, the etching process can be any one of a dry etching process or a wet etching process.

[0103] In some embodiments, the active region 101 extends along a preset direction W (refer to Figure 7 ), and the active region 101 includes a first source / drain region 111 (refer to Figure 7 ) spaced along the preset direction W, a channel region 113 (refer to Figure 7 ), and a second source / drain region 112 (refer to Figure 7 ). The channel region 113 is located on both sides of the first source / drain region 111, and the second source / drain region 112 is located on the side of the channel region 113 away from the first source / drain region 111.

[0104] For one active region 101, the number of the first source / drain regions 111 is 1, the number of the channel regions 113 is 2, which are respectively located on both sides of the first active region 1011, and the number of the second source / drain regions 112 is 2, which are respectively located on both sides of the channel region 113 away from the first source / drain region 111.

[0105] One first source / drain region 111, one channel region 113, and one second source / drain region 112 can form one transistor. Since in one active region 101, the number of the channel regions 113 and the number of the second source / drain regions 112 are both 2, therefore, one active region 101 can form 2 transistors. The two transistors share the same first source / drain region 111.

[0106] Refer to Figure 14 , Figure 14 which is a schematic cross-sectional structure diagram in the aa' direction. In some embodiments, the method for manufacturing a semiconductor structure further includes: forming an isolation structure 102, and the isolation structure 102 is located between adjacent active regions 101.

[0107] In some embodiments, isolation material may be deposited in the trenches to form an isolation structure 102 that fills the trenches. In some embodiments, either an atomic layer deposition process or a chemical vapor deposition process may be used to form the isolation structure 102. In some embodiments, the material of the isolation structure 102 may be silicon oxide.

[0108] In some embodiments, after the active region 101 is formed, a doping process is performed on the active region 101 to form a first source / drain region 111, a channel region 113, and a second source / drain region 112.

[0109] In some embodiments, the doping ion types of the first source / drain region 111 and the second source / drain region 112 may be the same, and the doping ion type of the channel region 113 may be different from the doping ion types of the first source / drain region 111 and the second source / drain region 112. For example, the doping ions of the first source / drain region 111 and the second source / drain region 112 are both N-type doping ions, and the N-type doping ions may be any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions. The doping ion type of the channel region 113 may be P-type doping ions, and the P-type doping ions may be any one of boron ions, aluminum ions, gallium ions, or indium ions.

[0110] In some embodiments, the doping process may be an ion implantation process.

[0111] Reference Figure 15 , Figure 15 is a schematic cross-sectional structure diagram in the bb' direction. After the active region 101 is formed, a plurality of buried word lines 109 may be formed in the substrate 100. The plurality of word lines 109 are arranged at intervals along the second direction Y, and each word line 109 extends along the third direction Z. The word line 109 is electrically connected to the channel region 113 of the active region 101. Among them, the two channel regions 113 of each active region 101 are respectively electrically connected to two word lines 109. The first direction X, the second direction Y, and the third direction Z intersect pairwise, and the third direction Z is perpendicular to the second direction Y.

[0112] The word line 109 may include a word line conductive layer 131, a word line barrier layer 132, and a word line capping layer 133 stacked in sequence. The word line barrier layer 132 is located on the top surface of the word line conductive layer 131, and the word line capping layer 133 is located on the top surface of the word line conductive layer 131. The material of the word line barrier layer 132 may include any one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride. The material of the word line conductive layer 131 may include a metal material, for example, at least one of metal materials such as tungsten, titanium, or nickel. The material of the word line capping layer 133 may include any one of silicon nitride or silicon oxynitride.

[0113] The embodiments of the present disclosure will not elaborate too much on the method of forming the word line 109. Any method capable of forming an embedded word line can be used to form the word line 109 in the embodiments of the present disclosure.

[0114] Reference Figures 16 to 18 , Figure 16 and Figure 17 are schematic cross-sectional structures in the aa' direction, Figure 18 are schematic cross-sectional structures in the bb' direction. After forming the word line 109, contact holes 103 are formed in the substrate 100. The bottom of the contact hole 103 exposes one of the adjacent active regions 101, and the sidewall of the contact hole 103 exposes the other of the adjacent active regions 101.

[0115] In some embodiments, the method of forming the contact holes 103 includes:

[0116] First, a first mask layer is formed on the substrate 100. Before forming the first mask layer, a first interlayer dielectric layer 141 and a second interlayer dielectric layer 142 may be formed on the substrate 100. The material of the first interlayer dielectric layer 141 may include silicon nitride, and the material of the second interlayer dielectric layer 142 may include silicon oxide.

[0117] The first mask layer is formed on the top surface of the second interlayer dielectric layer 142, and the material of the second mask layer may be photoresist.

[0118] Next, the first mask layer is patterned to form a first opening in the first mask layer. The first opening is partially aligned with one of the adjacent active regions 101 and is also partially aligned with the other of the adjacent active regions 101.

[0119] Specifically, the active regions 101 arranged at intervals along the first direction X include: first active regions 1011 (reference Figure 7 ) and second active regions 1012 (reference Figure 7 ) that are alternately arranged along the first direction X, first active regions 1011, second active regions 1012,..., first active regions 1011, second active regions 1012.

[0120] Taking three active regions 101 as an example to illustrate the alignment relationship between the first opening and the active regions 101, the three active regions 101 are: the first active region 1011 and two second active regions 1012 adjacent to the first active region 1011. Among them, the first opening is aligned with the first source / drain region 111 of the first active region 1011, and the first opening is respectively aligned with the second source / drain regions 112 of its two second active regions 1012. In this way, after etching the second interlayer dielectric layer 142, the first interlayer dielectric layer 141, and the substrate 100 along the first opening subsequently, the active regions 101 corresponding to the part aligned with the first opening can be exposed.

[0121] Reference Figures 16 to 18 ,Using a first etching process, the substrate 100 is etched along the first opening to expose the active region 101, and a contact hole 103 is formed.

[0122] Specifically, the active regions 101 arranged at intervals along the first direction X include: first active regions 1011, second active regions 1012, first active regions 1011, second active regions 1012,... first active regions 1011, second active regions 1012 that are alternately arranged along the first direction X.

[0123] Taking three active regions 101 as an example to illustrate the relationship between the first opening and the contact hole 103, the three active regions 101 are respectively: the first active region 1011 and two second active regions 1012 adjacent to the first active region 1011. The bottom of the contact hole 103 exposes the first source / drain region 111 of the first active region 1011, and the opposite two sidewalls of the contact hole 103 respectively expose the second source / drain regions 112 of the two second active regions 1012.

[0124] Reference Figure 18 ,In some embodiments, the sidewall of the contact hole 103 in the second direction Y may expose the word line capping layer 133 in the word lines 109 adjacent along the second direction Y, and the sidewall of the contact hole 103 in the third direction Z may expose the second active region 1012.

[0125] Reference Figure 16 and Figure 17 ,In some embodiments, the shape of the orthographic projection of the contact hole 103 in the second direction Y is an inverted trapezoid or an ellipse; reference Figure 18 ,The shape of the orthographic projection of the contact hole 103 in the third direction Z is a rectangle, and the sidewall of the contact hole 103 in the third direction Z exposes the active region 101.

[0126] It should be noted that the shape of the orthographic projection of the contact hole 103 in the extending direction of the bit line structure 107 is an inverted trapezoid or an ellipse, and the shape of the orthographic projection of the contact hole 103 in the arrangement direction of the bit line structure 107 is a rectangle, both referring to the shape of the orthographic projection of the contact hole 103 located in the substrate 100.

[0127] In some embodiments, the first etching process may include: a dry etching process. Specifically, the etching gas used in the first etching process may include chlorine gas, tetrafluoromethane, difluoromethane, and argon gas. Among them, the gas flow rate of chlorine gas may be 5 sccm to 30 sccm, the gas flow rate of tetrafluoromethane may be 20 sccm to 100 sccm, the gas flow rate of difluoromethane may be 1 sccm to 10 sccm, and the gas flow rate of argon gas may be 100 sccm to 300 sccm. The reaction pressure of the first etching process may be 5 Torr to 15 mTorr. The RF power of the first etching process may be 600 W to 1200 W. Under the above process conditions, the first etching process can etch the active region exposed by the first opening, and in the contact hole 103 obtained by etching, the active region exposed on the sidewall of the contact hole 103 has an area of a desired size, so that the second contact structure formed on the sidewall of the contact hole 103 subsequently has a larger contact area with the active region, thereby ensuring good electrical contact performance between the second contact structure and the active region.

[0128] Reference Figures 19 to 21 , Figure 19 is a schematic cross-sectional structure diagram in the aa' direction, Figure 20 is a schematic cross-sectional structure diagram in the bb' direction, Figure 21 is a schematic cross-sectional structure diagram in the aa' direction. After forming the contact hole 103, a second contact structure 106 is formed on a part of the sidewall of the contact hole 103, and the second contact structure 106 is in electrical contact with the active region 101 exposed on the sidewall of the contact hole 103.

[0129] In some embodiments, the method for forming the second contact structure 106 includes:

[0130] Reference Figures 19 to 20 , an initial second contact structure 30 is formed on the sidewall of the contact hole 103 by using a deposition process. Among them, the initial second contact structure 30 covering the sidewall of the contact hole 103 in the third direction Z has a first thickness, and the initial second contact structure 30 covering the sidewall of the contact hole 103 in the second direction Y has a second thickness. The first thickness is greater than the second thickness, and the sidewall of the contact hole 103 in the third direction Z exposes the active region 101.

[0131] Reference Figure 19 , in some embodiments, the shape of the positive projection of the contact hole 103 in the second direction Y is an inverted trapezoid or an ellipse. Reference Figure 20 , the shape of the positive projection of the contact hole 103 in the third direction Z is a rectangle. That is to say, the sidewall of the contact hole 103 in the second direction Y is perpendicular to the surface of the substrate 100 and is a vertical surface (reference Figure 20 ), and the sidewall of the contact hole 103 in the third direction Z is inclined with respect to the surface of the substrate 100 and is an inclined surface (reference Figure 19), and the sidewalls of the contact hole 103 in the third direction Z expose the active region 101. Compared with the vertical surface, the initial second contact structure 30 is more likely to be deposited on the inclined surface. Therefore, the deposition thickness of the initial second contact structure 30 on the sidewalls of the contact hole 103 in the third direction Z is greater than that on the sidewalls of the contact hole 103 in the second direction Y.

[0132] The initial second contact structure 30 is not only deposited on the sidewalls of the contact hole 103, but also part of the initial second contact structure 30 is higher than the opening of the contact hole 103. The initial second contact structure 30 higher than the opening of the contact hole 103 is deposited on the top surface of the second interlayer dielectric layer 142, and part of the initial second contact structure 30 is also deposited on the bottom surface of the contact hole 103.

[0133] In some embodiments, the initial second contact structure 30 can be formed by an atomic layer deposition process, and the material of the initial second contact structure 30 can be polysilicon.

[0134] In some embodiments, the bottom of the formed contact hole 103 exposes the active region 101 and part of the isolation structure 102 on both sides of the active region 101. The initial second contact structure 30 covers the active region 101 and the top surfaces of part of the isolation structure 102 on both sides of the active region 101.

[0135] Reference Figure 21 , the initial second contact structure 30 is etched by a second etching process to remove all of the initial second contact structure 30 covering the sidewalls of the contact hole 103 in the second direction Y, and part of the initial second contact structure 30 covering the sidewalls of the contact hole 103 in the third direction Z. The remaining initial second contact structure 30 serves as the second contact structure 106. Since the first thickness is greater than the second thickness, when the material layer of the initial second contact structure 30 on the sidewalls of the contact hole 103 in the second direction Y is completely etched, there is still remaining initial second contact structure 30 on the sidewalls of the contact hole 103 in the third direction Z. In this way, the second contact structure 106 is only located on part of the sidewalls of the contact hole 103, and the second contact structures 106 on the opposite two sidewalls of the contact hole 103 in the third direction Z are separated from each other. Since the two sidewalls of the contact hole 103 in the third direction Z expose the active region 101, the second contact structures 106 covering the two sidewalls of the contact hole 103 in the third direction Z are in electrical contact with the two active regions 101 respectively.

[0136] In some embodiments, the second etching process may include: a dry etching process. Specifically, the etching gas used in the second etching process may include: chlorine gas and hydrogen bromide. Among them, the gas flow rate of chlorine gas may be 5 sccm to 30 sccm, and the gas flow rate of hydrogen bromide may be 10 sccm to 100 sccm. The reaction pressure of the second etching process may be 10 Torr to 30 mTorr. The radio frequency power of the second etching process may be 400 W to 800 W.

[0137] In some embodiments, the active region 101 and a part of the isolation structure 102 on both sides of the active region 101 are exposed at the bottom of the formed contact hole 103, and the second contact structure 106 is located on the surface of the exposed isolation structure 102. In this way, it is possible to avoid the electrical contact between the bottom of the second contact structure 106 and the active region 101 exposed at the bottom of the contact hole 103, and ensure that the second contact structure 106 is only in electrical contact with the active region 101 exposed on the sidewall of the contact hole 103.

[0138] Reference Figures 22 to 25 , Figures 22 to 25 are all schematic cross-sectional structures in the aa' direction. A first sidewall structure 105 is formed in the contact hole 103, and the first sidewall structure 105 at least covers the second contact structure 106.

[0139] In some embodiments, the method for forming the first sidewall structure includes:

[0140] An initial second sidewall structure 105 is formed on the side surface of the second contact structure 106 in the contact hole 103 and on the sidewall of the remaining part of the contact hole 103 not covered by the second contact structure 106. The initial first sidewall structure is also higher than the opening of the contact hole 103, and the initial first sidewall structure higher than the opening of the contact hole 103 covers the top surface of the second interlayer dielectric layer 142. And the initial first sidewall structure also covers the bottom of the contact hole 103.

[0141] In some embodiments, the initial first sidewall structure may be formed by a deposition process, and the deposition process may include any one of atomic layer deposition, chemical vapor deposition, or other deposition methods.

[0142] An etch-back process is performed on the initial first sidewall structure to remove the initial first sidewall structure located on the top surface of the second interlayer dielectric layer 142 and the initial first sidewall structure covering the bottom of the contact hole 103.

[0143] In the above etch-back step, a part of the thickness of the initial first sidewall structure on the side surface of the second contact structure 106 and at least a part of the thickness of the initial first sidewall structure on the sidewall of the contact hole 103 are also etched away.

[0144] It should be noted that, since the side wall of the contact hole 103 in the second direction Y is perpendicular to the surface of the substrate 100 and is a vertical surface, and the side wall of the contact hole 103 in the third direction Z is inclined with respect to the surface of the substrate 100 and is an inclined surface, therefore, the thickness of the initial first sidewall structure deposited on the side surface of the second contact structure 106 is greater than the thickness of the initial first sidewall structure deposited on the side wall of the contact hole 103 in the second direction Y.

[0145] In a specific example, the process parameters of the above-mentioned etch-back process can be adjusted to completely remove the initial first sidewall structure located on the side wall of the contact hole 103 in the second direction Y, and only retain a part of the initial first sidewall structure located on the side surface of the second contact structure 106.

[0146] In another specific example, the process parameters of the above-mentioned etch-back process can be adjusted to remove a part of the thickness of the initial first sidewall structure located on the side wall of the contact hole 103 in the second direction Y, and remove a part of the thickness of the initial first sidewall structure located on the side surface of the second contact structure 106, so as to form a first sidewall structure.

[0147] The bottom surface of the first sidewall structure can be in contact with the isolation structure 102 exposed at the bottom of the contact hole 103. Alternatively, a part of the bottom surface of the first sidewall structure can be in contact with the isolation structure 102 exposed at the bottom of the contact hole 103, and the remaining part of the bottom surface can be in contact with the active region 101 exposed at the bottom of the contact hole 103.

[0148] In some embodiments, the first sidewall structure 105 includes a first silicon oxide layer 1051 and a first silicon nitride layer 1052 stacked in sequence in a direction away from the first contact structure 104.

[0149] The method of forming the first side-inclined structure may include:

[0150] Refer to Figure 22 , first, an initial first silicon nitride layer 31 is formed on the side surface of the second contact structure 106 in the contact hole 103 and on the side walls of the remaining part of the contact hole 103 not covered by the second contact structure 106. The initial first silicon nitride layer 31 also extends above the top surface of the contact hole 103, is located on the surface of the second interlayer dielectric layer 142, and is also located at the bottom of the contact hole 103.

[0151] Refer to Figure 23 , then, an etch-back process is performed on the initial first silicon nitride layer 31 to remove the initial first silicon nitride layer 31 above the top surface of the contact hole 103 and the initial first silicon nitride layer 31 located at the bottom of the contact hole 103, so as to form the first silicon nitride layer 1052.

[0152] Refer to Figure 24, an initial first silicon oxide layer 33 is formed. The initial first silicon oxide layer 33 covers the sidewalls of the first silicon nitride layer 1052. The initial first silicon oxide layer 33 is also higher than the top surface of the contact hole 103 and is located on the surface of the second interlayer dielectric layer 142. The initial first silicon oxide layer 33 is also located at the bottom of the contact hole 103.

[0153] Reference Figure 25 , an etch-back process is performed on the initial first silicon oxide layer 33 to remove the initial first silicon oxide layer 33 that is higher than the top surface of the contact hole 103 and the initial first silicon oxide layer 33 that is located at the bottom of the contact hole 103, forming a first silicon oxide layer 1051.

[0154] In some embodiments, the first sidewall structure can also be a three-layer structure, including a first silicon oxide layer and first silicon nitride layers on both sides of the first silicon oxide layer. Specifically, the three-layer structure is: a first silicon nitride layer, a first silicon oxide layer, and a first silicon nitride layer stacked in sequence along the direction away from the first contact structure.

[0155] Reference Figures 26 to 31 , Figures 26 to 31 are all schematic cross-sectional structures in the aa' direction. After forming the first sidewall structure 105, a first contact structure 104 that fills the remaining contact hole 103 is formed. Among them, the first contact structure 104 is located above the active region 101 exposed at the bottom of the contact hole 103 and is in electrical contact with the active region 101.

[0156] In the embodiments of the present disclosure, a first contact structure 104, a first sidewall structure 105, and a second contact structure 106 are pre-formed in the contact hole 103. Since the aspect ratio of the contact hole 103 is small, the morphologies of the deposited first contact structure 104, first sidewall structure 105, and second contact structure 106 are better and the uniformity is higher. At the same time, it is possible to avoid the problem in the related art that since the bit line structure 107 and the first contact structure 104 are etched simultaneously, the first contact structure 104 is not completely etched, and then in the step of forming the second contact structure 106 subsequently, process damage occurs, resulting in electrical connection between the second contact structure 106 and the first contact structure 104, causing the semiconductor structure to short-circuit.

[0157] In the embodiments of the present disclosure, the second contact structure 106, the first sidewall structure 105, and the first contact structure 104 are formed in sequence, and the first sidewall structure 105 covers the surface of the second contact structure 106, and the first contact structure 104 covers the surface of the first sidewall structure 105, which can ensure that the first contact structure 104 and the second contact structure 106 are completely isolated through the first sidewall structure, avoiding short circuits.

[0158] In some embodiments, the method of forming the first contact structure 104 may include:

[0159] Reference Figure 6 A filling layer 34 is formed to fill the remaining contact holes 103. The filling layer 34 is higher than the opening of the contact holes 103 and is located on the surface of the second interlayer dielectric layer 142. In some embodiments, the filling layer 34 can be formed by a deposition process. The material of the filling layer 34 can be a hard mask material, such as SOH.

[0160] Reference Figure 27 The filling layer 34 higher than the opening of the contact holes 103 is etched away.

[0161] Reference Figure 28 A third etching process is performed on the second interlayer dielectric layer 142, the filling layer 34, the first sidewall structure 105, and the second contact structure 106 to remove the filling layer 34, the first sidewall structure 105, and the second contact structure 106 that are opposite to the second interlayer dielectric layer 142 and the second interlayer dielectric layer 142, so that the top surfaces of the remaining filling layer 34, the first sidewall structure 105, and the second contact structure 106 are flush with the top surface of the first interlayer dielectric layer 141.

[0162] Since the filling layer 34 fills the contact holes 103 and contacts the first sidewall structure 105, the filling layer 34 can protect the first sidewall structure 105 from being damaged during the third etching process.

[0163] In some embodiments, during the third etching process, the etching selectivity for the second interlayer dielectric layer 142, the first sidewall structure 105, and the second contact structure 106 is the same. In this way, after only one third etching process, the first sidewall structure 105 and the second contact structure 106 are both flush with the first interlayer dielectric layer 141.

[0164] Reference Figure 29 The filling layer 34 in the contact holes 103 is removed. In some embodiments, the filling layer 34 can be removed by a wet etching process.

[0165] Reference Figure 30 An initial first contact structure 35 is formed to fill the remaining contact holes 103. The initial first contact structure 35 covers the side surface of the first contact structure 104. The initial first contact structure 35 is also higher than the opening of the contact holes 103, is located on the top surface of the first interlayer dielectric layer 141, and the initial first contact structure 35 also covers the bottom surface of the contact holes 103 and contacts the active region 101 exposed on the bottom surface of the contact holes 103.

[0166] In some embodiments, the initial first contact structure 35 can be formed by a deposition process, such as an atomic layer deposition process. The material of the initial first contact structure 35 can be polysilicon.

[0167] Reference Figure 31, a recess etching process is performed on the initial first contact structure 35 to remove the initial first contact structure 35 above the top surface of the contact hole 103, and the remaining initial first contact structure 35 serves as the first contact structure 104.

[0168] Reference Figures 32 to 33 , Figure 32 and Figure 33 are all schematic cross-sectional structures in the aa' direction. In some embodiments, the method for manufacturing a semiconductor structure further includes:

[0169] A bit line structure 107 is formed on the top surface of the first contact structure 104, and the bit line structure 107 is in electrical contact with the first contact structure 104.

[0170] In some embodiments, the number of the bit line structures 107 is multiple, and the multiple bit line structures 107 are arranged at intervals along the third direction Z, and each bit line structure 107 extends along the second direction Y. The multiple bit line structures 107 arranged at intervals along the third direction Z correspond one-to-one with multiple columns of active regions 101 arranged at intervals along the third direction Z, and each bit line structure 107 is coupled to the first source / drain region 111 of each active region 101 in each column of active regions 101 through the first contact structure 104.

[0171] In some embodiments, the bit line structure 107 includes: a bit line barrier layer 121, a bit line conductive layer 122, and a bit line capping layer 123 stacked in sequence in a direction away from the surface of the substrate 100.

[0172] In some embodiments, the method for forming the bit line structure 107 may include:

[0173] Reference Figure 32 , an initial bit line barrier layer 41, an initial bit line conductive layer 42, and an initial bit line capping layer 43 are sequentially formed on the substrate 100 by a deposition process. Then, a patterning process is performed on the initial bit line barrier layer 41, the initial bit line conductive layer 42, and the initial bit line capping layer 43 to form the bit line barrier layer 121, the bit line conductive layer 122, and the bit line capping layer 123. The patterning process may include any one of the SADP process or the SAQP process.

[0174] Specifically, an initial bit line barrier layer 41, an initial bit line conductive layer 42, and an initial bit line capping layer 43 may be sequentially formed on the substrate 100 by a deposition process. The material of the initial bit line barrier layer 41 may include any one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride. The material of the initial bit line conductive layer 42 may include a metal material, for example, at least one of metal materials such as tungsten, titanium, or nickel. The material of the initial bit line capping layer 43 may include any one of silicon nitride or silicon oxynitride.

[0175] After that, continue to refer to Figure 32, a hard mask layer is formed on the surface of the initial bit line capping layer 43. The hard mask layer may include a sub-first hard mask layer 51, an etch stop layer 52, and a sub-second hard mask layer 53 that are sequentially stacked in a direction away from the initial bit line capping layer 43. The pattern of the sub-second hard mask layer 53 is the same as the shape of the bit line structure 107 and is used to define the shape of the bit line structure 107.

[0176] In some embodiments, the material of the sub-first hard mask layer 51 may include APF, the material of the etch stop layer 52 may include silicon oxynitride, and the material of the sub-second hard mask layer may include a spin-on hard mask.

[0177] Next, referring to Figure 33 , the first hard mask layer and the etch stop layer 52 are etched based on the pattern of the sub-second hard mask layer 53 until the top surface of the initial bit line capping layer 43 is exposed. The etching of the initial bit line capping layer 43, the initial bit line conductive layer 42, and the initial bit line barrier layer 41 is continued until the top surface of the first interlayer dielectric layer 141 is exposed. The remaining initial bit line capping layer 43 forms the bit line capping layer 123, the remaining initial bit line conductive layer 42 forms the bit line conductive layer 122, and the remaining initial bit line barrier layer 41 forms the bit line barrier layer 121.

[0178] It is not difficult to find that in the embodiments of the present disclosure, in the step of etching to form the bit line structure 107, there is no need to etch and remove the first contact structure 104 in the contact hole 103, which avoids the problem of insufficient etching ability of the first contact structure 104 due to an excessive etching aspect ratio, and further avoids the problem of etching residue of the first contact structure 104. From the root cause, the problem of short circuit of the semiconductor structure caused by the electrical contact between the remaining first contact structure 104 and the second contact structure 106 is avoided.

[0179] Referring to Figure 34 , Figure 34 is a schematic cross-sectional structure diagram in the aa' direction. After the bit line structure 107 is formed, a second sidewall structure 108 is formed on the sidewall of the bit line structure 107, and the bottom surface of the second sidewall structure 108 contacts the top surface of the first sidewall structure 105. In some embodiments, the second sidewall structure 108 can be formed by a deposition process.

[0180] In some embodiments, the second sidewall structure 108 can be a double-layer structure, including: a second silicon oxide layer and a second silicon nitride layer that are sequentially stacked in a direction away from the bit line structure 107.

[0181] In some embodiments, the second sidewall structure 108 can also be a triple-layer structure, including: a layer of second silicon oxide layer and two layers of second silicon nitride layer, specifically: a second silicon nitride layer, a second oxide layer, and a second silicon nitride layer that are sequentially stacked in a direction away from the bit line structure 107.

[0182] Referring to Figure 11, a capacitive contact plug 110 is formed on the substrate 100. The capacitive contact plug 110 is located between adjacent bit line structures 107 and is in electrical contact with the top surface of the second contact structure 106.

[0183] Compared with the case where the capacitive contact plug 110 and the second contact structure 106 are formed in the same capacitive via, the capacitive contact plug 110 and the second contact structure 106 are formed separately, so that the aspect ratios of forming the capacitive contact plug 110 and forming the second contact structure 106 are both small, thereby improving the topography uniformity of forming the capacitive contact plug 110 and the second contact structure 106.

[0184] In some embodiments, the method of forming the capacitive contact plug 110 includes:

[0185] Reference Figure 35 , Figure 35 As a schematic cross-sectional structure diagram in the aa' direction, the second sidewall structure 108 on the substrate 100 can be removed by SADP process or SAQP process to form a capacitive via, and the top surface of the second contact structure 106 is exposed at the bottom of the capacitive via.

[0186] Reference Figure 11 , a capacitive contact plug 110 filled in the capacitive via is formed by a deposition process. In some embodiments, an atomic layer deposition process can be used to form the capacitive contact plug, and the material of the capacitive contact plug 110 can be polysilicon.

[0187] After the capacitive contact plug 110 is formed, a capacitive structure is formed. Each capacitive structure is located on the side of the capacitive contact plug 110 away from the substrate 100 and is in electrical contact with the capacitive contact plug 110.

[0188] In the method for preparing the semiconductor structure provided by the above embodiments, the first contact structure 104, the first sidewall structure 105 and the second contact structure 106 are pre-formed in the contact hole 103. Since the aspect ratio of the contact hole 103 is small, the topography of the deposited first contact structure 104, the first sidewall structure 105 and the second contact structure 106 is better and the uniformity is higher. At the same time, it is possible to avoid the problem in the related art that the first contact structure 104 is not etched completely due to the simultaneous etching of the bit line structure 107 and the first contact structure 104, and then in the subsequent step of forming the second contact structure 106, process damage occurs and the second contact structure 106 is electrically connected to the first contact structure 104, resulting in a short circuit of the semiconductor structure.

[0189] Those of ordinary skill in the art will understand that the above-described embodiments are specific examples for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate having a plurality of active regions arranged at intervals along a first direction; the substrate further having a plurality of contact holes arranged at intervals along the first direction, the contact holes exposing adjacent ones of the active regions; a contact structure filled in the contact holes, the contact structure comprising: a first contact structure located above the active region; a first sidewall structure covering at least part of the side surface of the first contact structure; a second contact structure covering at least part of the side surface of the first sidewall structure, and the second contact structure being located between two adjacent active regions, wherein the first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions.

2. The semiconductor structure according to claim 1, characterized in that, the contact structure comprises: two spaced second contact structures, and the two second contact structures are respectively in electrical contact with different active regions.

3. The semiconductor structure according to claim 1 or 2, characterized in that, the active region extends along a preset direction, the active region comprising a first source / drain region, a channel region, and a second source / drain region arranged at intervals along the preset direction, the channel region being located on both sides of the first source / drain region, and the second source / drain region being located on a side of the channel region away from the first source / drain region; the plurality of active regions comprise: a first active region and a second active region arranged alternately along the first direction; wherein the first contact structure is in electrical contact with a first source / drain region of one of the adjacent first active region or the second active region, and the second contact structure is in electrical contact with a second source / drain region of the other of the adjacent first active region or the second active region.

4. The semiconductor structure according to claim 3, characterized in that, the semiconductor structure further comprises: a plurality of bit line structures arranged at intervals along a third direction on the substrate, the bit line structures extending along a second direction, the first direction, the second direction, and the third direction intersecting pairwise, and the third direction being perpendicular to the second direction; a plurality of capacitor structures, each capacitor structure being located on the substrate and coupled to the second contact structure.

5. The semiconductor structure according to claim 4, characterized in that, the contact hole has a trapezoidal or elliptical shape in a front projection along the second direction, and has a rectangular shape in a front projection along the third direction, and the second contact structure is located on a sidewall of the contact hole in the third direction.

6. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a substrate, and forming a plurality of active regions arranged at intervals along a first direction in the substrate; forming contact holes in the substrate, a bottom of the contact holes exposing one of the adjacent active regions, and sidewalls of the contact holes exposing the other of the adjacent active regions; forming a second contact structure on a part of sidewalls of the contact holes, the second contact structure being in electrical contact with the active region exposed by the sidewalls of the contact holes. Form a first sidewall structure within the contact hole, where the first sidewall structure at least covers the second contact structure; Form a first contact structure that fills the remaining contact hole. Among them, the first contact structure is located above the active region exposed at the bottom of the contact hole and is in electrical contact with the active region.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The method for forming the contact hole includes: forming a first mask layer on the substrate; Pattern the first mask layer to form a first opening in the first mask layer. The first opening is partially opposite to one of the adjacent active regions, and the first opening is also partially opposite to the other of the adjacent active regions; Use a first etching process to etch the substrate along the first opening to expose the active region and form the contact hole.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, The method for forming the second contact structure includes: Use a deposition process to form an initial second contact structure on the sidewall of the contact hole. Among them, the initial second contact structure covering the sidewall of the contact hole in the third direction has a first thickness, and the initial second contact structure covering the sidewall of the contact hole in the second direction has a second thickness. The first thickness is greater than the second thickness. The first direction, the second direction, and the third direction intersect pairwise, and the third direction is perpendicular to the second direction. The sidewall of the contact hole in the third direction exposes the active region; Use a second etching process to etch the initial second contact structure to remove all the initial second contact structures covering the sidewall of the contact hole in the second direction and part of the initial second contact structures covering the sidewall of the contact hole in the third direction. The remaining initial second contact structure serves as the second contact structure.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, Before forming the contact hole, it further includes: forming an isolation structure between adjacent active regions. The formed contact hole exposes the active region and part of the isolation structure on both sides of the active region at the bottom. The second contact structure is located on the surface of the exposed isolation structure.

10. The method for manufacturing a semiconductor structure according to claim 6, wherein, The first sidewall structure includes a first silicon oxide layer and a first silicon nitride layer stacked in sequence along the direction away from the first contact structure.

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