Semiconductor structure and preparation method thereof, and memory

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and a memory, and the method comprises the steps: providing a substrate, and forming a laminated structure on the substrate; the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated along the direction vertical to the substrate; the laminated structure is etched to form an etching groove extending in the first direction and word line grooves, and the word line grooves are located on the two opposite sides of the etching groove and communicated with the etching groove; the first direction is parallel to the upper surface of the substrate; forming a virtual word line in the word line trench; word line release holes are formed in the two opposite sides of the word line groove; removing the virtual word line based on the word line release hole to release the word line trench; a word line structure and a preset channel layer are formed in the word line groove, the word line structure comprises a word line conducting layer and a gate dielectric layer wrapping the periphery of the word line conducting layer, and the preset channel layer wraps the periphery of the gate dielectric layer; and removing the preset channel layer exposed by the word line release hole. According to the method, the etching difficulty can be reduced, the technological process is simplified, and the influence of a parasitic channel is eliminated.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and manufacturing technologies, and particularly to a semiconductor structure, a preparation method thereof, and a memory. Background Art

[0002] In the field of integrated circuit design and manufacturing technologies, with the miniaturization of process dimensions, the aspect ratio of capacitors in memories increases exponentially, making it increasingly difficult to miniaturize the memory process. Researchers have built three-dimensional structures to effectively address the challenges brought about by process miniaturization, enabling the production of more chips per unit wafer area, obtaining memories with higher integration densities and larger storage capacities, thereby achieving the goal of reducing costs. Therefore, memories with three-dimensional structures have gradually become one of the important research directions for current memories.

[0003] However, the current traditional manufacturing processes for fabricating three-dimensional memories have large etching difficulties, complex process flows, and are prone to generating parasitic channels, which affect the further improvement of the three-dimensional memory structure and performance. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure, a preparation method thereof, and a memory, which can at least reduce the etching difficulty, simplify the process flow, and eliminate the influence of parasitic channels.

[0005] To solve the above technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a preparation method of a semiconductor structure. In some embodiments, it includes:

[0006] Providing a substrate, and forming a stacked structure on the substrate; the stacked structure includes sacrificial layers and dielectric layers alternately stacked in a direction perpendicular to the substrate;

[0007] Etching the stacked structure to form an etching groove and word line trenches extending in a first direction, the word line trenches being located on opposite sides of the etching groove and communicating with the etching groove; the first direction is parallel to the upper surface of the substrate;

[0008] Forming a dummy word line in the word line trenches;

[0009] Forming word line release holes on opposite sides of the word line trenches;

[0010] Removing the dummy word line based on the word line release holes to release the word line trenches;

[0011] Forming a word line structure and a preset channel layer in the word line trenches, the word line structure including a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer, and the preset channel layer covering the periphery of the gate dielectric layer;

[0012] Remove the preset channel layer exposed by the word line release holes to form a channel layer, and the channel layers are arranged at intervals along the first direction.

[0013] In some embodiments, the etching grooves divide the stacked structure into sub-stacked structures arranged at intervals along a second direction, the second direction is perpendicular to the first direction and parallel to the upper surface of the substrate; after forming virtual word lines in the word line grooves and before forming word line release holes on opposite sides of the word line grooves, it further includes:

[0014] Fill the etching grooves with a bit line material layer;

[0015] Etch the bit line material layer and the sub-stacked structure to form a plurality of bit line isolation grooves and a plurality of capacitor release holes; each bit line isolation groove extends along the second direction, and the plurality of bit line isolation grooves are arranged at intervals along the first direction to form a plurality of bit lines arranged at intervals along the first direction; the plurality of capacitor release holes are arranged at intervals along the first direction and are correspondingly arranged with the bit line isolation grooves;

[0016] Form a first filling dielectric layer, and the first filling dielectric layer fills the bit line isolation grooves and the capacitor release holes;

[0017] Forming word line release holes on opposite sides of the word line groove includes: forming word line release holes in the first filling dielectric layer on opposite sides of the word line groove.

[0018] In some embodiments, after forming the first filling dielectric layer and before forming word line release holes on opposite sides of the word line groove, it further includes:

[0019] Remove the remaining sacrificial layer to form capacitor holes;

[0020] Form a capacitor structure in the capacitor holes.

[0021] In some embodiments, after forming the first filling dielectric layer and before removing the remaining sacrificial layer to form capacitor holes, it further includes: removing a part of the sub-stacked structure to expose a part of the upper surface of the substrate on the side of the sub-stacked structure away from the etching grooves;

[0022] The capacitor structure includes a lower electrode layer, a capacitor dielectric layer on the surface of the lower electrode layer, and an upper electrode layer on the surface of the capacitor dielectric layer; the capacitor structure is also located on the exposed upper surface of the substrate, and a plurality of capacitor structures on the same side of the etching groove share the upper electrode layer.

[0023] In some embodiments, forming a word line structure and a preset channel layer in the word line groove includes:

[0024] Form a word line conductive material layer, a gate dielectric material layer, and a channel material layer in both the word line release holes and the word line grooves;

[0025] Remove the word line conductive material layer, the gate dielectric material layer, and the channel material layer located within the word line release hole to form a word line structure and a preset channel layer.

[0026] In some embodiments, forming a dummy word line within the word line trench includes: forming an amorphous carbon layer within the word line trench as the dummy word line.

[0027] In some embodiments, the sacrificial layer includes a silicon nitride layer, and the dielectric layer includes a silicon oxide layer.

[0028] In some embodiments, after removing the preset channel layer exposed by the word line release hole, a removal gap is formed; after removing the preset channel layer exposed by the word line release hole, it further includes:

[0029] Form a second filling dielectric layer, and the second filling dielectric layer fills the word line release hole and the removal gap.

[0030] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, including a substrate, a word line structure, and a channel layer; a dielectric layer is formed on the substrate and is stacked at intervals along a direction perpendicular to the substrate, and an etching groove and a word line trench extending along a first direction are formed, and the word line trench is located on opposite sides of the etching groove and is connected to the etching groove; the first direction is parallel to the upper surface of the substrate; the word line structure is located within the word line trench, and the word line structure includes a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer; the channel layers are arranged at intervals along the first direction and cover the periphery of a part of the gate dielectric layer.

[0031] In some embodiments, bit lines and bit line isolation structures arranged at intervals along a second direction are provided within the etching groove, the second direction is perpendicular to the first direction and is parallel to the upper surface of the substrate; the bit line isolation structure includes a first filling dielectric layer and a second filling dielectric layer, the first filling dielectric layer is located between adjacent bit lines, and the second filling dielectric layer is located on both sides of the first filling dielectric layer.

[0032] In some embodiments, the semiconductor structure further includes a plurality of capacitor structures; the capacitor structures are located on a side of the word line trench away from the etching groove and extend along the first direction; the capacitor structure includes a lower electrode layer, a capacitor dielectric layer on the surface of the lower electrode layer, and an upper electrode layer on the surface of the capacitor dielectric layer; the lower electrode layer is in contact with the channel layer; the capacitor structures are also located on the exposed upper surface of the substrate, and the plurality of capacitor structures on the same side of the etching groove share the upper electrode layer.

[0033] According to some embodiments, yet another aspect of the present disclosure provides a memory including the above semiconductor structure.

[0034] The embodiments of the present disclosure may / at least have the following advantages:

[0035] In the embodiments of the present disclosure, by etching the stacked structure, an etching groove and a word line groove extending in the first direction are formed, reducing the difficulty of the etching process. Moreover, by forming a dummy word line in the word line groove, word line release holes are formed on opposite sides of the word line groove, and then the dummy word line is removed based on the word line release holes to release the word line groove, avoiding the deposition of the channel layer at the narrow slit and reducing the process difficulty. In addition, a word line structure is formed in the word line groove, the word line structure includes a word line conductive layer and a gate dielectric layer coated around the word line conductive layer, the channel layers are arranged at intervals in the first direction and are coated around part of the gate dielectric layer, thereby forming a horizontal all-around channel (Channel-All-Around, abbreviated as CAA) structure, which is beneficial to saving the structure size and process stacking to improve the storage density of the device. Then, the channel layer exposed by the word line release hole is removed to eliminate the influence of the parasitic channel. In this way, the embodiments of the present disclosure can simplify the process flow and improve the performance of the memory. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0037] Figure 1 It is a schematic flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0038] Figure 2 It is a top view schematic diagram of the structure obtained in step 10 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0039] Figure 3 In FIG. (a) is Figure 2 a cross-sectional schematic diagram of the shown structure along the aa' direction, and in FIG. (b) is Figure 2 a cross-sectional schematic diagram of the shown structure along the bb' direction, in FIG. (c) is Figure 2 a cross-sectional schematic diagram of the shown structure along the cc' direction, and in FIG. (d) is Figure 2 a cross-sectional schematic diagram of the shown structure along the dd' direction;

[0040] Figure 4 It is a top view schematic diagram of the structure obtained in step 21 in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0041] Figure 5 In FIG. (a) is Figure 4 a cross-sectional schematic diagram of the shown structure along the aa' direction, and in FIG. (b) is Figure 2Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 2 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 2 Schematic cross-sectional view of the shown structure along the dd' direction;

[0042] Figure 6 Schematic three-dimensional structure view of the structure obtained in step 22 of a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0043] Figure 7 is Figure 6 Schematic top view of the shown structure;

[0044] Figure 8 In (a) of Figure 7 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 7 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 7 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 7 Schematic cross-sectional view of the shown structure along the dd' direction;

[0045] Figure 9 Schematic three-dimensional structure view of the structure obtained in step 23 of a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0046] Figure 10 is Figure 9 Schematic top view of the shown structure;

[0047] Figure 11 In (a) of Figure 10 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 10 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 10 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 10 Schematic cross-sectional view of the shown structure along the dd' direction;

[0048] Figure 12 Schematic three-dimensional structure view of the structure obtained in step 311 of a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0049] Figure 13 is Figure 12 Schematic top view of the shown structure;

[0050] Figure 14 In (a) of Figure 13 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 13Schematic cross-sectional view of the structure shown along the bb' direction. Diagram (c) is Figure 13 Schematic cross-sectional view of the structure shown along the cc' direction. Diagram (d) is Figure 13 Schematic cross-sectional view of the structure shown along the dd' direction;

[0051] Figure 15 Schematic three-dimensional view of the structure obtained in step 312 of a method for fabricating a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Figure 16 is Figure 15 Schematic top view of the structure shown;

[0053] Figure 17 In (a) of Figure 16 Schematic cross-sectional view of the structure shown along the aa' direction. Diagram (b) is Figure 16 Schematic cross-sectional view of the structure shown along the bb' direction. Diagram (c) is Figure 16 Schematic cross-sectional view of the structure shown along the cc' direction. Diagram (d) is Figure 16 Schematic cross-sectional view of the structure shown along the dd' direction;

[0054] Figure 18 Schematic three-dimensional view of the structure obtained in step 41 of a method for fabricating a semiconductor structure provided in an embodiment of the present disclosure;

[0055] Figure 19 is Figure 18 Schematic top view of the structure shown;

[0056] Figure 20 In (a) of Figure 19 Schematic cross-sectional view of the structure shown along the aa' direction. Diagram (b) is Figure 19 Schematic cross-sectional view of the structure shown along the bb' direction. Diagram (c) is Figure 19 Schematic cross-sectional view of the structure shown along the cc' direction. Diagram (d) is Figure 19 Schematic cross-sectional view of the structure shown along the dd' direction;

[0057] Figure 21 Schematic three-dimensional view of the structure obtained in step 42 of a method for fabricating a semiconductor structure provided in an embodiment of the present disclosure;

[0058] Figure 22 is Figure 21 Schematic top view of the structure shown;

[0059] Figure 23 In (a) of Figure 22 Schematic cross-sectional view of the structure shown along the aa' direction. Diagram (b) is Figure 22Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 22 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 22 Schematic cross-sectional view of the shown structure along the dd' direction;

[0060] Figure 24 Schematic three-dimensional structure view of the structure obtained in step 43 of a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0061] Figure 25 is Figure 24 Schematic top view of the shown structure;

[0062] Figure 26 In figure (a) of Figure 25 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 25 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 25 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 25 Schematic cross-sectional view of the shown structure along the dd' direction;

[0063] Figure 27 Schematic three-dimensional structure view of the structure obtained in step 44 of a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0064] Figure 28 is Figure 27 Schematic top view of the shown structure;

[0065] Figure 29 In figure (a) of Figure 28 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 28 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 28 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 28 Schematic cross-sectional view of the shown structure along the dd' direction;

[0066] Figure 30 Schematic three-dimensional structure view of the structure obtained in step 45 of a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0067] Figure 31 is Figure 30 Schematic top view of the shown structure;

[0068] Figure 32 In figure (a) of Figure 31 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 31Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is the schematic cross-sectional view of the structure shown in Figure 31 along the cc' direction, and Figure (d) is Figure 31 the schematic cross-sectional view of the shown structure along the dd' direction;

[0069] Figure 33 Schematic three-dimensional structure view of the structure obtained in step 46 in a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0070] Figure 34 is Figure 33 the schematic top view of the shown structure;

[0071] Figure 35 In (a) of Figure 34 the schematic cross-sectional view of the shown structure along the aa' direction, (b) is Figure 34 the schematic cross-sectional view of the shown structure along the bb' direction, (c) is Figure 34 the schematic cross-sectional view of the shown structure along the cc' direction, (d) is Figure 34 the schematic cross-sectional view of the shown structure along the dd' direction;

[0072] Figure 36 Schematic three-dimensional structure view of the structure obtained in step 51 in a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0073] Figure 37 is Figure 36 the schematic top view of the shown structure;

[0074] Figure 38 In (a) of Figure 37 the schematic cross-sectional view of the shown structure along the aa' direction, (b) is Figure 37 the schematic cross-sectional view of the shown structure along the bb' direction, (c) is Figure 37 the schematic cross-sectional view of the shown structure along the cc' direction, (d) is Figure 37 the schematic cross-sectional view of the shown structure along the dd' direction;

[0075] Figure 39 Schematic three-dimensional structure view of the structure obtained in step 70 in a semiconductor structure preparation method provided in an embodiment of the present disclosure;

[0076] Figure 40 is Figure 39 the schematic top view of the shown structure;

[0077] Figure 41 In (a) of Figure 40 the schematic cross-sectional view of the shown structure along the aa' direction, (b) is Figure 40 the schematic cross-sectional view of the shown structure along the bb' direction, (c) isFigure 40 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 40 Schematic cross-sectional view of the shown structure along the dd' direction;

[0078] Figure 42 Schematic three-dimensional view of the structure obtained in step 81 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0079] Figure 43 is Figure 42 Schematic top view of the shown structure;

[0080] Figure 44 In (a) of Figure 43 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 43 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 43 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 43 Schematic cross-sectional view of the shown structure along the dd' direction;

[0081] Figure 45 Schematic three-dimensional view of the structure obtained in step 82 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0082] Figure 46 is Figure 45 Schematic top view of the shown structure;

[0083] Figure 47 In (a) of Figure 46 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 46 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 46 Schematic cross-sectional view of the shown structure along the cc' direction. Figure (d) is Figure 46 Schematic cross-sectional view of the shown structure along the dd' direction;

[0084] Figure 48 Schematic three-dimensional view of the structure obtained in step 90 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0085] Figure 49 is Figure 48 Schematic top view of the shown structure;

[0086] Figure 50 In (a) of Figure 49 Schematic cross-sectional view of the shown structure along the aa' direction. Figure (b) is Figure 49 Schematic cross-sectional view of the shown structure along the bb' direction. Figure (c) is Figure 49Schematic cross-sectional view of the shown structure along the cc' direction. Diagram (d) is Figure 49 Schematic cross-sectional view of the shown structure along the dd' direction;

[0087] Figure 51 Schematic three-dimensional structure view of the structure obtained in step 100 in a semiconductor structure manufacturing method provided in an embodiment of the present disclosure;

[0088] Figure 52 is Figure 51 Schematic top view of the shown structure;

[0089] Figure 53 In (a) of Figure 52 Schematic cross-sectional view of the shown structure along the aa' direction. Diagram (b) is Figure 52 Schematic cross-sectional view of the shown structure along the bb' direction. Diagram (c) is Figure 52 Schematic cross-sectional view of the shown structure along the cc' direction. Diagram (d) is Figure 52 Schematic cross-sectional view of the shown structure along the dd' direction.

[0090] Explanation of reference numerals:

[0091] 1. Substrate; 2. Stacked structure; 201. Sub-stacked structure; 21. Sacrificial layer; 22. Dielectric layer;

[0092] E1. Etching groove; G1. Word line groove; G2. Bit line isolation groove; H1. Word line release hole; H2. Capacitor release hole; H3. Capacitor hole; S1. Removal gap;

[0093] 3. Word line structure; 301. Virtual word line; 3011. Virtual word line material layer; 31. Word line conductive layer; 311. Word line conductive material layer; 32. Gate dielectric layer; 321. Gate dielectric material layer; 4. Bit line; 401. Bit line material layer; 41. Bit line isolation structure; 411. First filling dielectric layer; 412. Second filling dielectric layer; 5. Channel layer; 501. Channel material layer; 51. Preset channel layer; 6. Capacitor structure; 61. Lower electrode layer; 62. Capacitor dielectric layer; 63. Upper electrode layer; 71. First mask layer; 72. Second mask layer; 73. Patterned photoresist layer. Detailed implementation manners

[0094] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0095] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0096] The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. When using "including", "having", and "comprising" as described herein, another component may be added unless an explicit limiting term such as "only", "consisting of", etc. is used. Unless stated to the contrary, terms in the singular form may include the plural form and should not be construed as having a quantity of one.

[0097] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0098] Here, embodiments of the invention are described with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure, and thus variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0099] Please refer to Figure 1 , according to some embodiments, the present disclosure provides a semiconductor structure and a method for manufacturing the same, the method comprising:

[0100] S10: Providing a substrate and forming a stacked structure on the substrate; the stacked structure includes a sacrificial layer and a dielectric layer alternately stacked in a direction perpendicular to the substrate;

[0101] S20: Etching the stacked structure to form an etching groove and a word line groove extending in a first direction, the word line groove being located on opposite sides of the etching groove and communicating with the etching groove; the first direction is parallel to the upper surface of the substrate;

[0102] S30: Forming a dummy word line in the word line groove;

[0103] S50: Forming word line release holes on opposite sides of the word line groove;

[0104] S70: Removing the dummy word line based on the word line release holes to release the word line groove;

[0105] S80: Form a word line structure and a preset channel layer in the word line trench. The word line structure includes a word line conductive layer and a gate dielectric layer coated around the word line conductive layer, and the preset channel layer is coated around the gate dielectric layer.

[0106] S90: Remove the preset channel layer exposed by the word line release hole to form a channel layer, and the channel layers are arranged at intervals along the first direction.

[0107] In the method for preparing the semiconductor structure of the above embodiment, by etching the stacked structure to form an etching groove and a word line trench extending along the first direction, the etching process difficulty is reduced. And, by forming a dummy word line in the word line trench, forming word line release holes on opposite sides of the word line trench, and then removing the dummy word line based on the word line release holes to release the word line trench, deposition of the channel layer at narrow slits is avoided, reducing the process difficulty. Also, a word line structure is formed in the word line trench, the word line structure includes a word line conductive layer and a gate dielectric layer coated around the word line conductive layer, and the channel layers are arranged at intervals along the first direction and are coated around part of the gate dielectric layer, thereby forming a horizontal all-around channel (Channel-All-Around, abbreviated as CAA) structure, which is beneficial to saving the structure size and process stacking to improve the storage density of the device. Then, the channel layer exposed by the word line release hole is removed to eliminate the influence of parasitic channels. In this way, the embodiments of the present disclosure can simplify the process flow and improve the performance of the memory.

[0108] In some embodiments, step S30, forming a dummy word line in the word line trench, includes:

[0109] S31: Form an amorphous carbon layer in the word line trench as the dummy word line.

[0110] In some embodiments, the etching groove divides the stacked structure into sub-stacked structures arranged at intervals along the second direction, the second direction is perpendicular to the first direction and parallel to the upper surface of the substrate; after step S30, forming a dummy word line in the word line trench and before step S50, forming word line release holes on opposite sides of the word line trench, further includes:

[0111] S41: Fill the etching groove with a bit line material layer;

[0112] S42: Etch the bit line material layer and the sub-stacked structure to form a plurality of bit line isolation grooves and a plurality of capacitor release holes; each bit line isolation groove extends along the second direction, and the plurality of bit line isolation grooves are arranged at intervals along the first direction to form a plurality of bit lines arranged at intervals along the first direction; the plurality of capacitor release holes are arranged at intervals along the first direction and are correspondingly arranged with the bit line isolation grooves;

[0113] S43: Form a first filling dielectric layer, and the first filling dielectric layer fills the bit line isolation grooves and the capacitor release holes;

[0114] Step S50, forming word line release holes on opposite sides of the word line trench includes:

[0115] S51: Forming word line release holes in the first filling dielectric layer on opposite sides of the word line trench.

[0116] In some embodiments, after step S43 of forming the first filling dielectric layer and before step S51 of forming word line release holes on opposite sides of the word line trench, it further includes:

[0117] S45: Removing the remaining sacrificial layer to form a capacitor hole;

[0118] S46: Forming a capacitor structure in the capacitor hole.

[0119] In some embodiments, after step S43 of forming the first filling dielectric layer and before step S45 of removing the remaining sacrificial layer to form a capacitor hole, it further includes:

[0120] S44: Removing a part of the sub-stack structure to expose a part of the upper surface of the substrate on the side of the sub-stack structure away from the etching groove;

[0121] The capacitor structure includes a lower electrode layer, a capacitor dielectric layer on the surface of the lower electrode layer, and an upper electrode layer on the surface of the capacitor dielectric layer; the capacitor structure is also located on the exposed upper surface of the substrate, and multiple capacitor structures on the same side of the etching groove share the upper electrode layer.

[0122] In some embodiments, step S80 of forming a word line structure and a preset channel layer in the word line trench includes:

[0123] S81: Forming a word line conductive material layer, a gate dielectric material layer, and a channel material layer in both the word line release holes and the word line trench;

[0124] S82: Removing the word line conductive material layer, the gate dielectric material layer, and the channel material layer in the word line release holes to form a word line structure and a preset channel layer.

[0125] In some embodiments, the sacrificial layer includes a silicon nitride layer, and the dielectric layer includes a silicon oxide layer.

[0126] In some embodiments, after step S90 of removing the preset channel layer exposed by the word line release hole and forming a removal gap; after step S90 of removing the preset channel layer exposed by the word line release hole, it further includes:

[0127] Step S100: Forming a second filling dielectric layer, and the second filling dielectric layer fills the word line release holes and the removal gap.

[0128] It should be understood that although Figure 1The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least a part of the steps of Figure 1 may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0129] To more clearly illustrate the method for preparing a storage unit provided in some of the above embodiments, please refer to the following in combination with Figures 2 to 53 to understand some embodiments of the present application.

[0130] The present application does not specifically limit the constituent material of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate 1, a silicon germanium carbon (SiGeC) substrate 1, a silicon carbide (SiC) substrate 1, a gallium arsenide (GaAs) substrate 1, an indium arsenide (InAs) substrate 1, an indium phosphide (InP) substrate 1, or other III / V semiconductor substrates 1 or II / VI semiconductor substrates 1. Or, for another example, the substrate 1 can be a layered substrate 1 including a stack of Si and SiGe, a stack of Si and SiC, silicon on insulator (SOI), or silicon germanium on insulator.

[0131] Please refer to Figures 2 to 3 , in step S10, a stacked structure 2 is formed on the substrate 1; the stacked structure 2 includes a sacrificial layer 21 and a dielectric layer 22 that are alternately stacked in a direction perpendicular to the substrate 1.

[0132] Exemplarily, the bottom layer and the top layer of the stacked structure 2 are both dielectric layers 22.

[0133] It can be understood that those skilled in the art can set the number of layers of the stacked stacked structure 2 according to requirements to obtain a three-dimensional memory with different stacking layers.

[0134] In some embodiments, the sacrificial layer 21 includes a silicon nitride layer, and the dielectric layer 22 includes a silicon oxide layer.

[0135] Please refer to Figures 4 to 11, in step S20, the stacked structure 2 is etched to form an etching groove E1 extending in a first direction and word line grooves G1. The word line grooves G1 are located on opposite sides of the etching groove E1 and communicate with the etching groove E1, thereby reducing the difficulty of the etching process; wherein, the first direction is parallel to the upper surface of the substrate 1; for example, the first direction can be the Figure 4 Y direction shown in

[0136] In some embodiments, step S20 may include:

[0137] S21: As shown in Figures 4 to 5 , a first mask layer 71, a second mask layer 72, and a photoresist (PR) layer are sequentially formed on the stacked structure 2, and the photoresist layer is exposed and developed to form a first pattern in the photoresist layer, thereby forming a patterned photoresist layer 73; wherein, the first pattern defines the position of the etching groove E1.

[0138] S22: As shown in Figures 6 to 8 , based on the first pattern, the first mask layer 71 and the second mask layer 72 are etched to transfer the first pattern into the first mask layer 71 and the second mask layer 72, and the patterned photoresist layer 73 is removed; then, based on the first pattern in the first mask layer 71 and the second mask layer 72, the stacked structure 2 is etched to form an etching groove E1 extending in the first direction, and the remaining first mask layer 71 and second mask layer 72 are removed;

[0139] wherein, the etching groove E1 divides the stacked structure 2 into sub-stacked structures 201 arranged at intervals in a second direction. The second direction is perpendicular to the first direction and parallel to the upper surface of the substrate 1;

[0140] Exemplarily, the first direction can be the Figure 6 X direction shown in

[0141] S23: As shown in Figures 9 to 11 , based on the etching groove E1, the sidewalls of the sacrificial layer 21 are etched to form word line grooves G1 extending in the first direction;

[0142] Exemplarily, in step S23, a side etching process can be used to etch the sidewalls of the sacrificial layer 21, so as to more precisely control the morphology of the obtained word line grooves G1.

[0143] Please refer to Figures 12 to 17 , step S30, a dummy word line 301 is formed in the word line groove G1;

[0144] In some embodiments, step S30 includes:

[0145] S31: An amorphous carbon layer is formed in the word line groove G1 as the dummy word line 301.

[0146] Exemplarily, step S31 may include:

[0147] S311: As Figures 12 to 14 shown, deposit a dummy word line material layer 3011, and the dummy word line material layer 3011 fills the etch groove E1 and the word line trench G1;

[0148] For example, the dummy word line material layer 3011 includes an amorphous carbon layer.

[0149] S312: As Figures 15 to 17 shown, remove the dummy word line material layer 3011 located in the etch groove E1 to form a dummy word line 301.

[0150] Please refer to Figures 18 to 23 , in some embodiments, after step S30, forming a dummy word line 301 in the word line trench G1, and before step S50, forming word line release holes H1 on two opposite sides of the word line trench G1, it further includes:

[0151] S41: As Figures 18 to 20 shown, fill the etch groove E1 with a bit line material layer 401;

[0152] Exemplarily, the material of the bit line material layer 401 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicon nitride or a combination thereof.

[0153] S42: As Figures 21 to 23 shown, etch the bit line material layer 401 and the sub-stack structure 201 to form a plurality of bit line isolation trenches G2 and a plurality of capacitor release holes H2;

[0154] Among them, etch the bit line material layer 401 to form a plurality of bit line isolation trenches G2 exposing the dummy word line 301, each bit line isolation trench G2 extends along the second direction, and a plurality of bit line isolation trenches G2 are arranged at intervals along the first direction, and the remaining bit line material layer 401 forms a plurality of bit lines 4 arranged at intervals along the first direction;

[0155] Etch the sub-stack structure 201 to form a plurality of capacitor release holes H2 exposing the dummy word line 301, and a plurality of capacitor release holes H2 are arranged at intervals along the first direction and are correspondingly arranged with the bit line isolation trenches G2.

[0156] Exemplarily, a one-time etching process may be used to simultaneously etch the bit line material layer 401 and the sub-stack structure 201 to form a plurality of bit line isolation trenches G2 and a plurality of capacitor release holes H2, or a step-by-step etching process may be used to separately etch the bit line material layer 401 to form a plurality of bit line isolation trenches G2 and etch the sub-stack structure 201 to form a plurality of capacitor release holes H2;

[0157] It should be added that the "first etching process" mentioned in some embodiments of the present disclosure can be understood as: etching based on the pattern of the same mask for forming the same pattern; and it is not limited to a specific etching method only. For example, it can be implemented by dry etching, can be implemented by wet etching, or can be implemented by a combination of dry etching and wet etching, etc.

[0158] Exemplarily, step S42 can etch the bit line material layer 401 and the sub-stack structure 201 by using an anisotropic etching process. Anisotropic etching can selectively etch the material in a preset crystal orientation or crystal plane direction, and only leave very little or almost no etching traces in other directions. Using the anisotropic etching process in this step can make the morphology of the obtained structure more precise and controllable.

[0159] S43: As Figures 24 to 26 shown, form the first filling dielectric layer 411, and the first filling dielectric fills the bit line isolation groove G2 and the capacitor release hole H2;

[0160] Exemplarily, the first filling dielectric layer 411 can select a material with a large etching selectivity ratio with respect to the sacrificial layer 21, so as to better remove the sacrificial layer 21 in subsequent processes. For example, the first filling dielectric layer 411 can be the same as or similar to the material of the dielectric layer 22, and the first filling dielectric layer 411 can also be a silicon oxide layer.

[0161] In some embodiments, after step S43 of forming the first filling dielectric layer 411, it further includes:

[0162] S44: As Figures 27 to 29 shown, remove a part of the sub-stack structure 201 to expose a part of the upper surface of the substrate 1 on the side of the sub-stack structure 201 away from the etching groove E1, so as to expand the subsequent process window.

[0163] S45: As Figures 30 to 32 shown, remove the remaining sacrificial layer 21 to form a capacitor hole H3; the capacitor hole H3 exposes a part of the side wall of the virtual word line 301;

[0164] Exemplarily, the remaining sacrificial layer 21 can be removed by using a wet etching process.

[0165] S46: As Figures 33 to 35As shown, a lower electrode layer 61, a capacitive dielectric layer 62, and an upper electrode layer 63 are sequentially formed in the capacitive via H3. The lower electrode layer 61 covers the sidewalls of the capacitive via H3 and the exposed partial sidewalls of the dummy word line 301. The capacitive dielectric layer 62 covers the lower electrode layer 61 and the side surfaces of the sub-stack structure 201. The upper electrode layer 63 is located on the surface of the capacitive dielectric layer 62 and fills the capacitive via H3. The capacitive structure 6 is also located on the exposed upper surface of the substrate 1, and multiple capacitive structures 6 on the same side of the etching groove E1 share the upper electrode layer 63.

[0166] Exemplarily, the material of the upper electrode is the same as or similar to that of the lower electrode. For example, the materials of the upper electrode and the lower electrode are selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicon nitride, titanium carbide, polysilicon, or a combination thereof.

[0167] Exemplarily, the material of the capacitive dielectric layer 62 can be selected as a high-K dielectric material to increase the capacitance value of the capacitor per unit area, which includes at least one of zirconium oxide (ZrOx), hafnium oxide (HfOx), zirconium titanium oxide (ZrTiOx), ruthenium oxide (RuOx), antimony oxide (SbOx), and aluminum oxide (AlOx).

[0168] Please refer to Figures 36 to 38 , step S50, forming word line release holes H1 on opposite sides of the word line trench G1 includes:

[0169] S51: As Figures 36 to 38 shown, forming word line release holes H1 in the first filling dielectric layer 411 on opposite sides of the word line trench G1;

[0170] Exemplarily, the word line release holes H1 expose the opposite sidewalls of the dummy word line 301 along the second direction and the opposite sidewalls of the capacitive structure 6 along the first direction, so as to expand the process window for removing the dummy word line 301 subsequently.

[0171] Please refer to Figures 39 to 41 , in step S70, removing the dummy word line 301 based on the word line release holes H1 to release the word line trench G1. Since the word line release holes H1 are located on opposite sides of the word line trench G1, both sidewalls of the dummy word line 301 are exposed by the word line release holes H1, so that the dummy word line 301 can be better removed, reducing the process difficulty.

[0172] Please refer to Figures 42 to 50 , in some embodiments, step S80, forming a word line structure 3 and a preset channel layer 51 in the word line trench G1, the word line structure 3 includes a word line conductive layer 31 and a gate dielectric layer 32 coated around the word line conductive layer 31, and the preset channel layer 51 is coated around the gate dielectric layer 32. Step S80 may include:

[0173] S81: AsFigures 42 to 44 As shown, a word line conductive material layer 311, a gate dielectric material layer 321, and a channel material layer 501 are formed both in the word line release hole H1 and in the word line groove G1; since the word line release hole H1 and the word line groove G1 provide sufficient space for depositing the channel material layer 501, it avoids depositing the channel material layer 501 at the narrow slit, reducing the process difficulty.

[0174] Exemplarily, the material of the channel material layer 501 can be a metal oxide. For example, the material of the metal oxide can be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the semiconductor structure is small (the leakage current is less than or equal to 10 -15 A), thus ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and other materials, as long as the leakage current of the semiconductor structure can meet the requirements, and those skilled in the art can adjust according to the actual situation.

[0175] S82: As Figures 45 to 47 shown, remove the word line conductive material layer 311, the gate dielectric material layer 321, and the channel material layer 501 in the word line release hole H1 to form a word line structure 3 and a preset channel layer 51.

[0176] In step S82, the word line structure 3 includes a word line conductive layer 31, a gate dielectric layer 32 coated around the word line conductive layer 31, and the preset channel layer 51 is coated around the gate dielectric layer 32, so as to form a horizontal channel-all-around (CAA) structure, which is beneficial to saving the structure size and process stack to improve the storage density of the device.

[0177] Exemplarily, the constituent material of the word line conductive layer 31 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi).

[0178] Exemplarily, the material of the gate dielectric layer 32 can include, but is not limited to, silicon oxide (such as silicon dioxide), silicon nitride (silicon oxynitride), nitride (such as silicon nitride), metal oxide (such as Al2O3), metal oxynitride (such as AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, antiferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3).

[0179] Please refer to Figures 48 to 50 , in some embodiments, in step S90, the preset channel layer exposed by the word line release hole H1 is removed to form the channel layer 5. The channel layers 5 are arranged at intervals along the first direction, and a removal gap S1 is formed to eliminate the influence of parasitic channels.

[0180] Please refer to Figures 51 to 53 , after step S90 of removing the preset channel layer exposed by the word line release hole H1 to form the channel layer 5, it further includes:

[0181] Step S100: Form a second filling dielectric layer 412, and the second filling dielectric layer 412 fills the word line release hole H1 and the removal gap S1;

[0182] Exemplarily, the second filling dielectric layer 412 can be the same as or similar to the material of the first filling dielectric layer 411. For example, the second filling dielectric layer 412 can also be a silicon oxide layer.

[0183] Among them, the second filling dielectric layer 412 located between adjacent bit lines 4 and in the word line release hole H1, and the reserved first filling dielectric layer 411 located between adjacent bit lines 4 can jointly form a bit line isolation structure 41, that is, the first filling dielectric layer 411 and the second filling dielectric layer 412 in the bit line isolation groove G2 can jointly form the bit line isolation structure 41.

[0184] Based on the same inventive concept, please refer to Figures 51 to 53 , some embodiments of the present disclosure also provide a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure in the above-mentioned some embodiments. The technical advantages of the preparation method of the above-mentioned semiconductor structure are also possessed by this semiconductor structure, which will not be elaborated here.

[0185] The semiconductor structure includes a substrate 1, a word line structure 3, and a channel layer 5; a dielectric layer 22 is formed on the substrate 1 and is stacked at intervals along the direction perpendicular to the substrate 1, and an etching groove E1 and a word line groove G1 extending along the first direction are formed, and the word line groove G1 is located on opposite sides of the etching groove E1 and is connected to the etching groove E1; the first direction is parallel to the upper surface of the substrate 1; the word line structure 3 is located in the word line groove G1, and the word line structure 3 includes a word line conductive layer 31 and a gate dielectric layer 32 coated around the word line conductive layer 31; the channel layer 5 is arranged at intervals along the first direction and is coated around a part of the gate dielectric layer 32.

[0186] In some embodiments, bit lines 4 and a bit line isolation structure 41 arranged at intervals along the second direction are provided in the etching groove, the second direction is perpendicular to the first direction and is parallel to the upper surface of the substrate 1; the bit line isolation structure 41 includes a first filling dielectric layer 411 and a second filling dielectric layer 412, the first filling dielectric layer 411 is located between adjacent bit lines 4, and the second filling dielectric layer 412 is located on both sides of the first filling dielectric layer 411.

[0187] In some embodiments, the semiconductor structure further includes a plurality of capacitor structures 6; the capacitor structures 6 are located on the side of the word line groove G1 away from the etching groove E1 and extend along the first direction; the capacitor structure 6 includes a lower electrode layer 61, a capacitor dielectric layer 62 on the surface of the lower electrode layer 61, and an upper electrode layer 63 on the surface of the capacitor dielectric layer 62; the lower electrode layer 61 is in contact with the channel layer 5; the capacitor structures 6 are also located on the exposed upper surface of the substrate 1, and the plurality of capacitor structures 6 on the same side of the etching groove E1 share the upper electrode layer 63.

[0188] In some embodiments, a memory is also provided, including the above-mentioned semiconductor structure.

[0189] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present disclosure.

[0190] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0191] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0192] The above embodiments only represent several implementation manners of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation to the scope of the disclosed patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present disclosure, several modifications and improvements can still be made, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, comprising: providing a substrate, and forming a stacked structure on the substrate; the stacked structure includes sacrificial layers and dielectric layers alternately stacked in a direction perpendicular to the substrate; etching the stacked structure to form an etching groove extending in a first direction and word line trenches, the word line trenches being located on opposite sides of the etching groove and communicating with the etching groove; the first direction is parallel to the upper surface of the substrate; forming a dummy word line in the word line trenches; forming word line release holes on opposite sides of the word line trenches; removing the dummy word line based on the word line release holes to release the word line trenches; forming a word line structure and a preset channel layer in the word line trenches, the word line structure includes a word line conductive layer and a gate dielectric layer coated around the word line conductive layer, and the preset channel layer is coated around the gate dielectric layer; removing the preset channel layer exposed by the word line release holes to form channel layers, and the channel layers are arranged at intervals in the first direction.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, the etching groove divides the stacked structure into sub-stacked structures arranged at intervals in a second direction, the second direction is perpendicular to the first direction and parallel to the upper surface of the substrate; after forming the dummy word line in the word line trenches and before forming the word line release holes on opposite sides of the word line trenches, further comprising: filling the etching groove with a bit line material layer; etching the bit line material layer and the sub-stacked structures to form a plurality of bit line isolation grooves and a plurality of capacitor release holes; each of the bit line isolation grooves extends in the second direction, and the plurality of bit line isolation grooves are arranged at intervals in the first direction to form a plurality of bit lines arranged at intervals in the one direction; the plurality of capacitor release holes are arranged at intervals in the first direction and are correspondingly arranged with the bit line isolation grooves; forming a first filling dielectric layer, and the first filling dielectric layer fills the bit line isolation grooves and the capacitor release holes; forming the word line release holes on opposite sides of the word line trenches includes: forming the word line release holes in the first filling dielectric layer on opposite sides of the word line trenches.

3. The method for fabricating a semiconductor structure according to claim 2, characterized in that, after forming the first filling dielectric layer and before forming the word line release holes on opposite sides of the word line trenches, further comprising: removing the remaining sacrificial layers to form capacitor holes; forming capacitor structures in the capacitor holes.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, after forming the first filling dielectric layer and before removing the remaining sacrificial layers to form capacitor holes, further comprising: removing a part of the sub-stacked structures to expose a part of the upper surface of the substrate on the side of the sub-stacked structures away from the etching groove; The capacitive structure includes a lower electrode layer, a capacitive dielectric layer on the surface of the lower electrode layer, and an upper electrode layer on the surface of the capacitive dielectric layer; the capacitive structure is also located on the exposed upper surface of the substrate, and multiple capacitive structures on the same side of the etching groove share the upper electrode layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein, forming a word line structure and a preset channel layer in the word line trench includes: forming a word line conductive material layer, a gate dielectric material layer, and a channel material layer in both the word line release hole and the word line trench; removing the word line conductive material layer, the gate dielectric material layer, and the channel material layer located in the word line release hole to form the word line structure and the preset channel layer.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein, forming a dummy word line in the word line trench includes: forming an amorphous carbon layer in the word line trench as the dummy word line.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein, the sacrificial layer includes a silicon nitride layer, and the dielectric layer includes a silicon oxide layer.

8. The method for manufacturing a semiconductor structure according to any one of claims 1 to 7, wherein, after removing the preset channel layer exposed by the word line release hole, a removal gap is formed; after removing the preset channel layer exposed by the word line release hole, it further includes: forming a second filling dielectric layer, and the second filling dielectric layer fills the word line release hole and the removal gap.

9. A semiconductor structure, wherein, including: a substrate, on which a dielectric layer is formed by being stacked at intervals along a direction perpendicular to the substrate, and an etching groove and a word line trench extending along a first direction, the word line trench being located on opposite sides of the etching groove and communicating with the etching groove; the first direction is parallel to the upper surface of the substrate; a word line structure, located in the word line trench, the word line structure including a word line conductive layer and a gate dielectric layer covering the periphery of the word line conductive layer; channel layers, arranged at intervals along the first direction, covering the periphery of part of the gate dielectric layer.

10. The semiconductor structure according to claim 9, wherein, bit lines and bit line isolation structures arranged at intervals along a second direction are provided in the etching groove, the second direction is perpendicular to the first direction and parallel to the upper surface of the substrate; the bit line isolation structure includes a first filling dielectric layer and a second filling dielectric layer, the first filling dielectric layer is located between adjacent bit lines, and the second filling dielectric layer is located on both sides of the first filling dielectric layer.

11. The semiconductor structure according to claim 9, wherein, it further includes a plurality of capacitive structures; the capacitive structures are located on the side of the word line trench away from the etching groove and extend along the first direction; The capacitive structure includes a lower electrode layer, a capacitive dielectric layer on the surface of the lower electrode layer, and an upper electrode layer on the surface of the capacitive dielectric layer; the lower electrode layer is in contact with the channel layer; the capacitive structure is also located on the exposed upper surface of the substrate, and a plurality of the capacitive structures on the same side of the etching groove share the upper electrode layer.

12. A memory device, characterized in that, it includes: The semiconductor structure according to any one of claims 9-11.

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