Memory device and manufacturing method thereof

Abstract

The embodiment of the invention discloses a memory device and a manufacturing method thereof, the memory device comprises a first semiconductor structure, the first semiconductor structure comprises a semiconductor column extending along a first direction, and the semiconductor column is provided with a first end and a second end which are oppositely arranged in the first direction; the bit line is positioned on one side, close to the first end, of the semiconductor column and is coupled with the first end; the bit lines extend along a second direction perpendicular to the first direction; the first side of the bit line along the third direction is aligned with the first side of the semiconductor column along the third direction in the first direction, and the size of the bit line in the third direction is smaller than the size of the semiconductor column in the third direction; wherein the third direction is perpendicular to the first direction and intersects with the second direction.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a memory device and a method for manufacturing the same. Background Art

[0002] Some memory devices, such as Dynamic Random Access Memory (DRAM), may include a memory array and peripheral circuits. The peripheral circuits can control the memory array and operate the memory array to perform read, write, or refresh operations. To improve the performance of memory devices, there is much room for improvement in memory devices and their manufacturing methods. Summary of the Invention

[0003] According to some aspects of embodiments of the present disclosure, a memory device is provided, including a first semiconductor structure. The first semiconductor structure includes: a semiconductor pillar extending along a first direction, the semiconductor pillar having a first end and a second end disposed opposite to each other in the first direction; a bit line located on a side of the semiconductor pillar close to the first end and coupled to the first end; the bit line extending along a second direction perpendicular to the first direction; a first side of the bit line along a third direction being aligned with a first side of the semiconductor pillar along the third direction in the first direction, and a dimension of the bit line in the third direction being smaller than a dimension of the semiconductor pillar in the third direction; wherein the third direction is perpendicular to the first direction and intersects with the second direction.

[0004] In some embodiments, a second side of the bit line along the third direction is located between a first side and a second side of the semiconductor pillar along the third direction.

[0005] In some embodiments, a projection of the bit line in a first plane and a projection of the semiconductor pillar in the first plane are offset along the third direction; wherein the first plane is perpendicular to the first direction.

[0006] In some embodiments, the memory device further includes: a dielectric layer located between two adjacent bit lines in the third direction.

[0007] In some embodiments, the dielectric layer includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer sequentially arranged along the third direction; wherein, the first dielectric layer is located at one end of the semiconductor pillar close to the first end, and the sum of the dimensions of the first dielectric layer and the bit line in the third direction is less than the dimension of the semiconductor pillar in the third direction; the projection of the first dielectric layer on the second plane overlaps with the projection of the bit line on the second plane; the second plane is perpendicular to the third direction; the second dielectric layer includes a first portion extending along the first direction and a second portion extending along the third direction, the second portion is located between the first dielectric layer and the first portion, and the projection of the second portion on the second plane overlaps with the projection of the bit line on the second plane; both the third dielectric layer and the fourth dielectric layer extend along the first direction.

[0008] In some embodiments, the constituent materials of the first dielectric layer and the fourth dielectric layer include: silicon oxide; the constituent materials of both the second dielectric layer and the third dielectric layer include: aluminum oxide or silicon nitride.

[0009] In some embodiments, the memory device further includes: a word line located on at least one side surface of the semiconductor pillar, and at least a part of the word line extends along the third direction; a gate dielectric layer located between the word line and the semiconductor pillar.

[0010] In some embodiments, the word line includes a first word line and a second word line; the first word line and the second word line are respectively located on two opposite side surfaces of the semiconductor pillar along the second direction.

[0011] In some embodiments, the first word line and / or the second word line includes a protrusion, and the protrusion is located at one end of the first word line and / or the second word line close to the bit line; the protrusion extends in a direction away from the semiconductor pillar.

[0012] In some embodiments, the word line covers one side surface of the semiconductor pillar perpendicular to the first direction; or, the word line covers two side surfaces of the semiconductor pillar perpendicular to the first direction; or, the word line covers three side surfaces of the semiconductor pillar perpendicular to the first direction.

[0013] In some embodiments, the memory device further includes: a capacitor structure located on a side of the semiconductor pillar away from the bit line; the capacitor structure is coupled to the second end.

[0014] In some embodiments, the size of the end of the capacitive structure away from the bit line in the second direction and / or the third direction is greater than the size of the end of the capacitive structure close to the bit line in the second direction and / or the third direction.

[0015] In some embodiments, the capacitive structure includes: a first electrode, and a fifth dielectric layer and a second electrode surrounding the first electrode; the fifth dielectric layer is located between the first electrode and the second electrode.

[0016] In some embodiments, the memory device further includes: a second semiconductor structure, which includes a peripheral circuit and is located on a side of the capacitive structure away from the semiconductor pillar; the second semiconductor structure is bonded to the first semiconductor structure.

[0017] In some embodiments, the second semiconductor structure further includes: a first interconnection layer and a pad located on a surface of the second semiconductor structure away from the first semiconductor structure, and the first interconnection layer and the pad are coupled to the second semiconductor structure.

[0018] According to some aspects of embodiments of the present disclosure, a memory device is provided, including: a semiconductor pillar extending along a first direction, the semiconductor pillar having a first end and a second end oppositely arranged in the first direction; a bit line, located on a side of the semiconductor pillar close to the first end and coupled to the first end; the bit line extends along a second direction perpendicular to the first direction; a first side of the bit line along a third direction is aligned with a first side of the semiconductor pillar along the third direction in the first direction, and the size of the bit line in the third direction is smaller than the size of the semiconductor pillar in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with the second direction; a capacitive structure, located on a side of the semiconductor pillar away from the bit line and coupled to the second end; a peripheral circuit, located on a side of the capacitive structure away from the semiconductor pillar; wherein, the peripheral circuit is coupled to at least the capacitive structure and the bit line.

[0019] In some embodiments, a second side of the bit line along the third direction is located between a first side and a second side of the semiconductor pillar along the third direction.

[0020] In some embodiments, a projection of the bit line in a first plane and a projection of the semiconductor pillar in the first plane have an offset along the third direction; wherein, the first plane is perpendicular to the first direction.

[0021] In some embodiments, the memory device further includes: a dielectric layer, located between two adjacent bit lines in the third direction.

[0022] In some embodiments, the dielectric layer includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer sequentially arranged along the third direction; wherein, the first dielectric layer is located at one end of the semiconductor pillar close to the first end, and the sum of the dimensions of the first dielectric layer and the bit line in the third direction is less than the dimension of the semiconductor pillar in the third direction; the projection of the first dielectric layer on the second plane overlaps with the projection of the bit line on the second plane; the second plane is perpendicular to the third direction; the second dielectric layer includes a first portion extending along the first direction and a second portion extending along the third direction, the second portion is located between the first dielectric layer and the first portion, and the projection of the second portion on the second plane overlaps with the projection of the bit line on the second plane; both the third dielectric layer and the fourth dielectric layer extend along the first direction.

[0023] In some embodiments, the constituent materials of the first dielectric layer and the fourth dielectric layer include: silicon oxide; the constituent material of the second dielectric layer includes: aluminum oxide or silicon nitride; the constituent materials of both the third dielectric layer and the third dielectric layer include: aluminum oxide or silicon nitride.

[0024] In some embodiments, the memory device further includes: a word line located on at least one side surface of the semiconductor pillar and extending along the third direction; a gate dielectric layer located between the word line and the semiconductor pillar.

[0025] In some embodiments, the word line includes a first word line and a second word line; the first word line and the second word line are respectively located on two opposite side surfaces of a semiconductor pillar along the second direction.

[0026] In some embodiments, the first word line and / or the second word line includes a protrusion, and the protrusion is located at one end of the first word line and / or the second word line close to the bit line; the protrusion extends in a direction away from the semiconductor pillar.

[0027] In some embodiments, the word line covers one side surface of the semiconductor pillar perpendicular to the first direction; or, the word line covers two side surfaces of the semiconductor pillar perpendicular to the first direction; or, the word line covers three side surfaces of the semiconductor pillar perpendicular to the first direction.

[0028] In some embodiments, the dimension of the end of the capacitor structure away from the bit line in the second direction and / or the third direction is greater than the dimension of the end of the capacitor structure close to the bit line in the second direction and / or the third direction.

[0029] In some embodiments, the capacitive structure includes: a first electrode, and a fifth dielectric layer and a second electrode surrounding the first electrode; the fifth dielectric layer is located between the first electrode and the second electrode.

[0030] In some embodiments, the semiconductor pillar, the bit line, and the capacitive structure are located in a first semiconductor structure; the peripheral circuit is located in a second semiconductor structure; the first semiconductor structure is bonded to the second semiconductor structure.

[0031] In some embodiments, the memory device further includes: a first interconnect layer and pads located on a surface of the second semiconductor structure away from the first semiconductor structure, and the first interconnect layer and the pads are coupled to the second semiconductor structure.

[0032] According to some aspects of embodiments of the present disclosure, a first semiconductor structure is formed, and a manufacturing method of the first semiconductor structure includes: forming a semiconductor pillar extending along a first direction, the semiconductor pillar having a first end and a second end oppositely arranged in the first direction; forming a bit line extending along a second direction perpendicular to the first direction on a side of the semiconductor pillar close to the first end; the bit line is coupled to the first end, a first side of the bit line in a third direction is aligned with a first side of the semiconductor pillar in the third direction in the first direction, and a dimension of the bit line in the third direction is smaller than a dimension of the semiconductor pillar in the third direction; wherein the third direction is perpendicular to the first direction and intersects with the second direction.

[0033] In some embodiments, the method of forming the bit line includes: providing a first substrate structure; wherein the first substrate structure includes a first dielectric layer and a semiconductor layer stacked; forming a first trench penetrating the semiconductor layer and the first dielectric layer along the first direction; the first trench extends along the second direction; the first trench divides the semiconductor layer into semiconductor strips; reducing a dimension of the first dielectric layer in a third direction, and forming a bit line extending along the second direction on a side of the semiconductor strip close to the first dielectric layer.

[0034] In some embodiments, the manufacturing method of the first substrate structure includes: providing a first substrate including a first insulating layer, providing a second substrate including a second insulating layer; bonding the first insulating layer and the second insulating layer to form the first dielectric layer, and thinning a surface of the first substrate away from the first dielectric layer to form the semiconductor layer.

[0035] In some embodiments, the method of forming the bit line further includes: removing a part of the first dielectric layer and reducing the size of the first dielectric layer in the third direction to form a first opening with an opening direction facing the third direction, the first opening extending along the second direction; filling the first opening to form a second dielectric layer, the second dielectric layer covering the sidewall of the first trench; the second dielectric layer and the first dielectric layer surround the side surface of the semiconductor strip and surround the surface of the semiconductor strip close to the first dielectric layer, exposing the surface of the semiconductor strip far from the first dielectric layer; filling the remaining cavity of the first trench to form a third dielectric layer; removing the second dielectric layer on one side of the first dielectric layer to form a second trench; wherein, the second trench exposes the first dielectric layer, exposes the side surface of the semiconductor strip, and exposes the surface of the semiconductor strip close to the first dielectric layer; forming the bit line in a part of the second trench extending towards the first dielectric layer.

[0036] In some embodiments, the method of forming the second trench further includes: removing a part of the thickness of the third dielectric layer and reducing the size of the third dielectric layer in the third direction.

[0037] In some embodiments, the method of forming the bit line includes: filling the second trench to form a first conductive layer, the first conductive layer including parts extending along the first direction and the third direction respectively; wherein, the part of the first conductive layer extending along the third direction extends towards the first dielectric layer; removing a part of the first conductive layer extending along the first direction to form a third trench; wherein, the third trench exposes the third dielectric layer and exposes one side surface of the semiconductor strip; the remaining first conductive layer forms the bit line.

[0038] In some embodiments, the method of manufacturing the first semiconductor structure further includes: filling the third trench to form a fourth dielectric layer.

[0039] In some embodiments, the method of forming the semiconductor pillar further includes: forming a fourth trench penetrating the semiconductor strip, the fourth trench dividing the semiconductor strip into semiconductor pillars; the fourth trench extends along the third direction; the method of manufacturing the first semiconductor structure further includes: sequentially forming a gate dielectric layer and a word line on at least one side surface of the semiconductor pillar.

[0040] In some embodiments, the method of forming the word line includes: forming a sixth dielectric layer at the bottom of the fourth trench, the size of the sixth dielectric layer in the first direction being smaller than the size of the semiconductor pillar in the first direction; sequentially forming a gate dielectric layer and a second conductive layer on the sidewalls of the fourth trench and the sixth dielectric layer; penetrating the second conductive layer along the first direction to form a first word line and a second word line on two opposite side surfaces of the semiconductor pillar along the second direction.

[0041] In some embodiments, when penetrating the second conductive layer, a remaining part of the second conductive layer on the sixth dielectric layer forms a protrusion at one end of the first word line and / or the second word line close to the bit line, and the protrusion extends in a direction away from the semiconductor pillar.

[0042] In some embodiments, the word line covers one side surface of the semiconductor pillar along a direction perpendicular to the first direction; alternatively, the word line covers two side surfaces of the semiconductor pillar along a direction perpendicular to the first direction; alternatively, the word line covers three side surfaces of the semiconductor pillar along a direction perpendicular to the first direction.

[0043] In some embodiments, the manufacturing method of the first semiconductor structure further includes: forming a capacitor structure on a side of the semiconductor pillar away from the bit line, and the capacitor structure is coupled to the second end of the semiconductor pillar.

[0044] In some embodiments, the size of one end of the capacitor structure away from the bit line in the second direction and / or the third direction is larger than the size of one end of the capacitor structure close to the bit line in the second direction and / or the third direction.

[0045] In some embodiments, the capacitor structure includes: a first electrode, and a fifth dielectric layer and a second electrode surrounding the first electrode; the fifth dielectric layer is located between the first electrode and the second electrode.

[0046] In some embodiments, the manufacturing method of the memory device includes: providing a second semiconductor structure; bonding the second semiconductor structure and the first semiconductor structure on a side of the capacitor structure away from the bit line.

[0047] In some embodiments, the manufacturing method further includes: forming a first interconnection layer and a pad on a surface of the second semiconductor structure away from the first semiconductor structure, and the first interconnection layer and the pad are coupled to the second semiconductor structure.

[0048] An embodiment of the present disclosure provides a memory device. A semiconductor pillar has two opposite ends in a first direction. A bit line is located on a side of the semiconductor pillar close to the first end and is coupled to the first end. The bit line extends in a second direction. A first side of the bit line in a third direction is aligned with a first side of the semiconductor pillar in the third direction in the first direction. A size of the bit line in the third direction is smaller than a size of the semiconductor pillar in the third direction, so that two adjacent bit lines have a larger spacing in the third direction, reducing interference between the bit lines and improving the stability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figures 1 to 3 is a schematic structural diagram of a memory device shown according to an embodiment of the present disclosure;

[0050] Figure 4 and Figure 5 is a schematic diagram of a capacitor structure shown according to an embodiment of the present disclosure;

[0051] Figure 6 is a schematic flowchart of a manufacturing method of a memory device shown according to an embodiment of the present disclosure;

[0052] Figures 7 to 29 is a schematic diagram of a manufacturing method of a memory device shown according to an embodiment of the present disclosure;

[0053] Figure 30 and Figure 31 is a schematic diagram of an exemplary system shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art.

[0055] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure can be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of actual embodiments are described here, and well-known functions and structures are not described in detail.

[0056] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0057] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not imply that there must be a first element, component, region, layer or part in the present disclosure.

[0058] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0060] In order to more fully understand the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration purposes only and are not intended to limit the embodiments of the present disclosure.

[0061] It should be understood that the "some embodiments" or "an embodiment" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the "in some embodiments" or "in an embodiment" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitude of the serial numbers of the above processes does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0062] The memory device in the embodiments of the present disclosure can be a DRAM, or at least a part of the devices in the DRAM, and can be applicable to double data rate synchronous dynamic random access memories using DDR4 memory specifications and DDR5 memory specifications, and low power double data rate synchronous dynamic random access memories using LPDDR5 memory specifications. It should be noted that the embodiments of the present disclosure are not limited to DRAM, but in the following introduction, for the sake of clarity, only DRAM is taken as an example for description.

[0063] In a DRAM, a memory array can be arranged in rows and columns so that memory cells can be addressed by specifying the rows and columns of its array. The memory array includes a plurality of word lines and a plurality of bit lines. The word lines and bit lines cross each other. The memory cell at the intersection of the selected word line and the selected bit line is selected, and read, write or refresh operations are performed. The memory cells in the memory array can include capacitors and transistors. A memory cell can include a transistor and a capacitor. The word line serves as the gate of the transistor. One controlled end (source) of the transistor is coupled to one electrode (the first electrode) of the capacitor, and the other controlled end (drain) of the transistor is coupled to the bit line. The other electrode (the second electrode) of the capacitor can be grounded or applied with other voltages (such as vdd / 2). When performing read or write operations, the corresponding word line can be selected by using the word line selection signal, and the corresponding bit line can be selected according to the column selection signal. When the word line and the bit line are selected simultaneously, the selected memory cell can be located. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, so that read, write or refresh operations can be performed on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase change memory structures, resistive change memory structures or magnetic change memory structures, etc.

[0064] In some embodiments, a capacitor represents logically 1 and 0 by the amount of charge stored therein, or rather, by the high and low voltage differences across the capacitor. A voltage signal on the word line is applied to the gate to control the conduction or cutoff of the transistor, thereby realizing the selection and non-selection of the capacitor. Furthermore, data information stored in the capacitor is read through the bit line, or data is written into the capacitor through the bit line for storage.

[0065] According to some aspects of the embodiments of the present disclosure, referring to Figure 1 as shown, a memory device 100 is provided, including a first semiconductor structure 101. The first semiconductor structure 101 includes: a semiconductor pillar 111 extending along a first direction (z direction), the semiconductor pillar 111 having a first end and a second end oppositely arranged in the first direction; a bit line 112 located on one side of the semiconductor pillar 111 close to the first end and coupled to the first end; the bit line 112 extends along a second direction (x direction) perpendicular to the first direction.

[0066] Referring to Figure 2 as shown, a first side of the bit line 112 in a third direction (y direction) is aligned with a first side of the semiconductor pillar 111 in the third direction in the first direction, and the size of the bit line 112 in the third direction is smaller than the size of the semiconductor pillar 111 in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with the second direction. Figure 1 and Figure 2 are respectively cross-sectional schematic views of the memory device 100 in different directions. Some structures of the memory device 100 are shown in Figure 1 and some other structures are shown in Figure 2 for the sake of explanation.

[0067] The first direction in the embodiments of the present disclosure may be the z direction provided in the drawings, and the z direction may be the thickness direction of the memory device 100; the second direction may be the x direction, and the third direction may be the y direction; the x and y directions are both perpendicular to the z direction, and the x and y directions intersect, and may be perpendicular to each other or have other included angles. For example Figure 1The word line 113 shown extends in the y direction. The word line 113 and the bit line 112 may be perpendicular, or the word line 113 and the bit line 112 may intersect and not be perpendicular. In the embodiments of the present disclosure, there are no restrictions on the number of semiconductor columns 111 and the array manner, nor on the number of bit lines 112 and word lines 113. One bit line 112 may be coupled to the first ends of multiple semiconductor columns 111. The first end may be the end in the negative z direction, and the second end may be the end in the positive z direction. The first end and the second end of the semiconductor column 111 may have the same type of doping and serve as the active region (source or drain of the transistor, and the source and drain can be swapped) of the transistor. The region of the semiconductor column 111 between the first end and the second end may serve as the channel of the transistor, and the region of the semiconductor column 111 between the first end and the second end may have a different type of doping from the first end.

[0068] Referring to Figure 1 As shown, multiple word lines 113 may be arranged in the x direction. One word line 113 may correspond to multiple semiconductor columns 111 and serve as the gate of the multiple semiconductor columns 111. The word line 113 is located on the side of the semiconductor column 111, and there is a gate dielectric layer 114 between the word line 113 and the side of the semiconductor column 111. One semiconductor column 111, its corresponding part of the word line 113, and the gate dielectric layer 114 may form a transistor. The word line 113 applies an operating voltage to control the on and off of the transistor. The word line 113 may cover one side of the semiconductor column 111, or cover two sides of the semiconductor column 111, or cover three sides of the semiconductor column 111. Figure 1 The word line 113 shown in [reference] covers two sides of the semiconductor column 111 in the x direction. One semiconductor column 111 corresponds to two word lines 113, and both of the two word lines 113 can control the on and off of the transistor, reducing the risk that some memory cells cannot be accessed due to the damage of one word line 113. The double word lines 113 can carry a larger operating voltage, improving the device stability and expanding the setting margin of the operating voltage of the word line 113. Referring to Figure 2 As shown, multiple bit lines 112 may be arranged in the y direction. Each bit line 112 may be coupled to multiple semiconductor columns 111. The word line 113 may be blocked by the yoz cross-sectional view of the memory device 100. The word line 113 shown in the figure is a perspective schematic diagram of the yoz cross-section, and the word line 113 does not penetrate the semiconductor column 111.

[0069] Taking a bit line 112 and a semiconductor pillar 111 coupled thereto as an example, the first side and the second side of the bit line 112 are opposite sides of the bit line 112 in the y direction, and the first side and the second side of the semiconductor pillar 111 are opposite sides of the semiconductor pillar 111 in the y direction. The first side of the bit line 112 can be its left side, and the second side of the bit line 112 can be its right side; the first side of the semiconductor pillar 111 can be its left side, and the second side of the semiconductor pillar 111 can be its right side. The left side of the bit line 112 is aligned with the left side of the semiconductor pillar 111 in the z direction, or is substantially aligned within a certain process control range. For example, the left side of the bit line 112 protrudes from the left side of the semiconductor pillar 111 by a small distance in the negative y direction, or the left side of the semiconductor pillar 111 protrudes from the left side of the bit line 112 by a small distance in the negative y direction. For example, this distance can be less than 5% or less of the size of the bit line 112 in the y direction. The size of the bit line 112 in the y direction is smaller than the size of the semiconductor pillar 111 in the y direction, and the right side of the bit line 112 is not aligned with the right side of the semiconductor pillar 111, so that there is a larger spacing between two adjacent bit lines 112, reducing the interference between the bit lines 112 and improving the device stability.

[0070] In some embodiments, the second side of the bit line 112 along the third direction is located between the first side and the second side of the semiconductor pillar 111 along the third direction. Figure 2 As shown, the right side of the bit line 112 is located between the left side and the right side of the semiconductor pillar 111, and the positive projection of the right side of the semiconductor pillar 111 on the first plane perpendicular to the z direction falls between the positive projections of the left side and the right side of the semiconductor pillar 111 on the first plane.

[0071] In some embodiments, there is an offset in the third direction between the projection of the bit line 112 on the first plane and the projection of the semiconductor pillar 111 on the first plane; wherein, the first plane is perpendicular to the first direction. Figure 2 As shown, the edge of the positive projection of the bit line 112 on the first plane does not completely coincide with the edge of the positive projection of the semiconductor pillar 111 on the first plane. The positive projection of the first side (e.g., the left side) of the bit line 112 on the first plane can coincide with the positive projection of the first side (the left side) of the semiconductor pillar 111 on the first plane, and the positive projection of the second side (e.g., the right side) of the bit line 112 on the first plane can have an offset and not coincide with the positive projection of the second side (e.g., the right side) of the semiconductor pillar 111 on the first plane. There is an offset between the positive projection of the geometric center of the bit line 112 on the first plane and the positive projection of the geometric center of the semiconductor pillar 111 on the first plane. The geometric center of the bit line 112 can be the midline of the bit line 112 in the y direction, and the geometric center of the semiconductor pillar 111 can be the midline of the semiconductor pillar 111 in the y direction.

[0072] In some other embodiments, the first side of the bit line 112 can be its right side, the first side of the semiconductor pillar 111 can be its right side, the right side of the bit line 112 is aligned with the right side of the semiconductor pillar 111 in the z direction, and the left side of the bit line 112 is not aligned with the left side of the semiconductor pillar 111 in the z direction.

[0073] Exemplarily, the constituent materials of the bit line 112 and the word line 113 may include, but are not limited to: conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum. The constituent materials of the semiconductor pillar 111 may include, but are not limited to: elemental semiconductor materials (such as silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

[0074] In some embodiments, referring to Figure 2 as shown, the memory device 100 further includes: a dielectric layer 160, located between two adjacent bit lines 112 in the third direction. The dielectric layer 160 may include a single film layer structure or may include multiple film layer structures. At least a part of the dielectric layer 160 is located between two adjacent bit lines 112, and the dielectric layer 160 may be Figure 2 the L shape as shown, a part is located between two adjacent semiconductor pillars 111, and a part is located between two adjacent bit lines 112. The dielectric layer 160 is used to electrically isolate adjacent bit lines 112, the dielectric layer 160 is used to electrically isolate adjacent semiconductor pillars 111, and the dielectric layer 160 is used to support the device structure. In some other embodiments, the dielectric layer 160 includes a plurality of film layer structures formed in sequence, the constituent materials of the plurality of film layer structures are the same or similar, there may be no obvious physical boundary between the film layer structures, and the plurality of film layer structures may exhibit the morphological features of an integral film layer structure.

[0075] In some embodiments, referring to Figure 2 as shown, the dielectric layer 160 includes: a first dielectric layer 161, a second dielectric layer 162, a third dielectric layer 163, and a fourth dielectric layer 164 arranged in sequence along the third direction; wherein, the first dielectric layer 161 is located at one end of the semiconductor pillar 111 close to the first end, and the sum of the dimensions of the first dielectric layer 161 and the bit line 112 in the third direction is smaller than the dimension of the semiconductor pillar 111 in the third direction; the projection of the first dielectric layer 161 on the second plane overlaps with the projection of the bit line 112 on the second plane; the second plane is perpendicular to the third direction; the second dielectric layer 162 includes a first part extending along the first direction and a second part extending along the third direction, the second part is located between the first dielectric layer 161 and the first part, and the projection of the second part on the second plane overlaps with the projection of the bit line 112 on the second plane; the third dielectric layer 163 and the fourth dielectric layer 164 both extend along the first direction.

[0076] In Figure 2Among them, the dielectric layer 160 may include a plurality of film layer structures arranged in sequence along the y direction. The first dielectric layer 161 is relatively close to the first end of the semiconductor pillar 111 and may be located under the semiconductor pillar 111 in the figure. The first dielectric layer 161 extends in the y direction. The two sides of the first dielectric layer 161 are within the left and right sides of the semiconductor pillar 111. The orthographic projection of the first dielectric layer 161 on the second plane perpendicular to the y direction falls within or overlaps with the orthographic projection of the bit line 112 on the second plane. The orthographic projection of the first dielectric layer 161 on the first plane perpendicular to the z direction overlaps with the orthographic projection of the semiconductor pillar 111 on the first plane. The second dielectric layer 162 may be L-shaped. The first part of the second dielectric layer 162 extends in the z direction, and the second part extends along the y direction toward the first dielectric layer 161. The second part is located between the first part and the first dielectric layer 161. The orthographic projection of the second part on the second plane falls within or overlaps with the orthographic projection of the bit line 112 on the second plane. The orthographic projection of the second part on the first plane overlaps with the orthographic projection of the semiconductor pillar 111 on the first plane. The second dielectric layer 162 covers a part of the bottom of the semiconductor pillar 111 ( Figure 2 the bottom of the semiconductor pillar 111 in), and the right side of the semiconductor pillar 111. The third dielectric layer 163 is located between the second part of the second dielectric layer 162 and the fourth dielectric layer 164. The first part and the second part of the second dielectric layer 162 are only for explanation, and there is no obvious physical boundary between the two parts.

[0077] In some embodiments, the constituent materials of the first dielectric layer 161 and the fourth dielectric layer 164 include: silicon oxide; the constituent materials of the second dielectric layer 162 and the third dielectric layer 163 both include: aluminum oxide or silicon nitride. In the semiconductor manufacturing process, some processes have high selectivity parameters for the film layer structure. For example, in the etching process, the first dielectric layer 161, the second dielectric layer 162, the third dielectric layer 163, and the fourth dielectric layer 164 can select different material combinations to meet the different selectivities of different etchants. Different film layer materials can also help reduce stress concentration and improve the stability of the device structure. Exemplarily, the constituent materials of the first dielectric layer 161 and the fourth dielectric layer 164 may be the same and may include silicon oxide; the second dielectric layer 162 and the third dielectric layer 163 may both include aluminum oxide, or both include silicon nitride; or the materials of the second dielectric layer 162 and the third dielectric layer 163 are different. For example, the second dielectric layer 162 may include aluminum oxide, and the third dielectric layer 163 may include silicon nitride. Also, for example, the second dielectric layer 162 may include silicon nitride, and the third dielectric layer 163 may include aluminum oxide.

[0078] In some embodiments, referring to Figure 1As shown, the memory device 100 further includes: a word line 113 located on at least one side of the semiconductor pillar 111, and at least a part of the word line 113 extends in the third direction; a gate dielectric layer 114 located between the word line 113 and the semiconductor pillar 111. In some embodiments, the word line 113 includes a first word line 113a and a second word line 113b; the first word line 113a and the second word line 113b are respectively located on two opposite sides of the semiconductor pillar 111 along the second direction.

[0079] Figure 1 As shown in [the figure], the first word line 113a and the second word line 113b respectively cover two sides of the semiconductor pillar 111 in the x direction. One semiconductor pillar 111 corresponds to two word lines 113. There is a gate dielectric layer 114 between the first word line 113a and one side surface of the semiconductor pillar 111, and there is a gate dielectric layer 114 between the second word line 113b and the other side surface of the semiconductor pillar 111 that is oppositely arranged along the x direction. The first word line 113a can be the word line on the right side of the semiconductor pillar 111, and the second word line 113b can be the word line on the left side of the semiconductor pillar 111. Both word lines can control the on and off of the transistor, reducing the risk that some memory cells cannot be accessed due to the damage of one word line. The dual word lines can carry a larger operating voltage, improving the device stability and expanding the margin of the word line operating voltage setting. In some other embodiments, one semiconductor pillar 111 can correspond to one word line 113, and the word line 113 is arranged on one side of the semiconductor pillar 111. Exemplarily, the constituent materials of the gate dielectric layer 114 can include, but are not limited to, insulating materials such as silicon oxide, silicon oxynitride, or aluminum oxide.

[0080] In some embodiments, referring to Figure 3 As shown, the first word line 113a and / or the second word line 113b includes a protrusion 123, and the protrusion 123 is located at one end of the first word line 113a and / or the second word line 113b close to the bit line 112; the protrusion 123 extends in a direction away from the semiconductor pillar 111. Taking two adjacent semiconductor pillars 111 as an example, the protrusion 123 at the bottom of the first word line 113a on the right side of one semiconductor pillar 111 extends away from the semiconductor pillar 111 in the positive x direction, and the protrusion 123 at the bottom of the second word line 113b on the left side of the other semiconductor pillar 111 extends away from the semiconductor pillar 111 in the negative x direction, and the two protrusions 123 do not contact. It should be noted that the protrusion 123 can be located on one side of any semiconductor pillar 111. The protrusions 123 do not contact each other, and the first word line 113a and the second word line 113b are still electrically isolated. Compared with the solution where there is strictly no protrusion 123, the embodiments of the present disclosure can reduce the manufacturing difficulty of the word line 113, which is beneficial to expanding the manufacturing process window of the word line 113, such as increasing the etching process window.

[0081] In some embodiments, the word line 113 covers one side surface of the semiconductor pillar 111 perpendicular to the first direction; alternatively, the word line 113 covers two side surfaces of the semiconductor pillar 111 perpendicular to the first direction; alternatively, the word line 113 covers three side surfaces of the semiconductor pillar 111 perpendicular to the first direction. In combination with Figure 2 As shown, one side surface of the semiconductor pillar 111 in the y direction is covered by the dielectric layer 160, and the word line 113 can cover any one of the remaining three side surfaces of the semiconductor pillar 111 not covered by the dielectric layer 160. The semiconductor pillar 111 can correspond to any one of the first word line 113a and the second word line 113b. The word line 113 extends in the y direction and covers one side surface of the semiconductor pillar 111 in the x direction along the x direction. Alternatively, one semiconductor pillar 111 corresponds to two word lines 113, the first word line 113a and the second word line 113b, and covers two side surfaces of the semiconductor pillar 111 along the x direction. Alternatively, a bridging structure 1132 is disposed between the first word line 113a and the second word line 113b corresponding to one semiconductor pillar 111. The bridging structure 1132 extends in the x direction and covers one opposite side surface of the dielectric layer 160 along the y direction. The bridging structure 1132 can be a part of the word line 113. The bridging structure 1132 is shown in the following Figure 26 as shown.

[0082] In some embodiments, with reference to Figure 1 and Figure 2 as shown, the memory device 100 further includes: a capacitor structure 115 located on a side of the semiconductor pillar 111 away from the bit line 112; the capacitor structure 115 is coupled to the second end.

[0083] In some embodiments, the size of the end of the capacitor structure 115 away from the bit line 112 in the second direction and / or the third direction is greater than the size of the end of the capacitor structure 115 close to the bit line 112 in the second direction and / or the third direction.

[0084] In some embodiments, the capacitor structure 115 includes: a first electrode 1151, and a fifth dielectric layer 1152 and a second electrode 1153 surrounding the first electrode 1151; the fifth dielectric layer 1152 is located between the first electrode 1151 and the second electrode 1153.

[0085] Figure 4 and Figure 5 show a cross-sectional view of the exemplary capacitor structure 115 in the xoz plane, and also show a cross-sectional view of the capacitor structure 115 in the xoy plane. With reference to Figure 4 and Figure 5As shown, the capacitor structure 115 may include a columnar structure. The size of the end of the capacitor structure 115 away from the bit line 112 in the x direction and / or in the y direction is equal to or greater than the size of the end of the capacitor structure 115 close to the bit line 112. Figure 4 In [description], along the x direction, the capacitor structure 115 includes: a first electrode 1151, a fifth dielectric layer 1152 surrounding the first electrode 1151, and a second electrode 1153; the fifth dielectric layer 1152 is located between the first electrode 1151 and the second electrode 1153. The first electrode 1151 may be a columnar structure, and the fifth dielectric layer 1152 and the second electrode 1153 are film layer structures surrounding the first electrode 1151. Figure 5 In [description], along the x direction, the capacitor structure 115 may further include a core 1154, and the first electrode 1151, the fifth dielectric layer 1152, and the second electrode 1153 are disposed around the core 1154. The core 1154 may be a columnar structure, and the first electrode 1151, the fifth dielectric layer 1152, and the second electrode 1153 are all film layer structures. The second electrode 1153 of the capacitor structure 115 may be coupled to the end of the corresponding semiconductor pillar 111 away from the bit line 112, and the first electrodes 1151 of multiple capacitor structures 115 may be coupled to an interconnect structure to achieve grounding or access to other operating voltages.

[0086] Exemplarily, the constituent materials of the first electrode 1151 and the second electrode 1153 may include, but are not limited to: conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel. The constituent materials of the fifth dielectric layer 1152 and the core 1154 may include, but are not limited to: insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0087] In some embodiments, referring to Figure 1 and Figure 2 as shown, the memory device 100 further includes: a second semiconductor structure 102, which includes a peripheral circuit 140 and is located on the side of the capacitor structure 115 away from the semiconductor pillar 111; the second semiconductor structure 102 is bonded to the first semiconductor structure 101. The capacitor structure 115 is located between the peripheral circuit 140 and the semiconductor pillar 111, and the semiconductor pillar 111 is located between the bit line 112 and the capacitor structure 115.

[0088] Devices such as the semiconductor pillar 111, the bit line 112, the word line 113, and the capacitor structure 115 are located in the first semiconductor structure 101, and the peripheral circuit 140 is located in the second semiconductor structure 102; the second semiconductor structure 102 may include various devices including a CMOS structure for constructing the peripheral circuit 140, and the bonding method between the first semiconductor structure 101 and the second semiconductor structure 102 may include hybrid bonding.

[0089] Before bonding is completed, the bonding planes of the first semiconductor structure 101 and the second semiconductor structure 102 respectively have bonding contacts 131a and bonding contacts 131b, which lead out the electrical signals of the semiconductor structures to the bonding planes respectively. The bonding contacts 131 may include conductive structures such as pads and conductive plugs. Bond the bonding planes of the first semiconductor structure 101 and the second semiconductor structure 102. The interface where the bonding planes of the two semiconductor structures contact is the bonding interface. The bonding contacts 131a and 131b of the first semiconductor structure 101 and the second semiconductor structure 102 contact at the bonding interface to achieve electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. After the bonding contacts 131a and 131b are bonded, they may not have a physical dividing line and can be regarded as the bonding contact 131, which penetrates the bonding interface.

[0090] In some embodiments, the memory device 100 further includes Figure 1 the first contact structure 121 coupled to the bit line 112 as shown. The first contact structure 121 leads out the electrical signal of the bit line 112 to the bonding interface and is coupled to the bonding contact 131, and realizes electrical signal interconnection with the second semiconductor structure 102 through the bonding contact 131, for example, realizes electrical signal interconnection with the peripheral circuit 140. The memory device 100 further includes as Figure 2 the second contact structure 122 coupled to the word line 113 as shown. The second contact structure 122 leads out the electrical signal of the word line 113 and realizes electrical signal interconnection with the second semiconductor structure 102.

[0091] In some other embodiments, the second semiconductor structure 102 may not be connected to the first semiconductor structure 101 by bonding. The second semiconductor structure 102 is formed on the basis of the structure of the first semiconductor structure 101. The bonding contact 131 serves as a conductive contact, or the bonding contact 131 is not provided. The first contact structure 121 and the second contact structure 122 are coupled to the interconnection structure in the peripheral circuit 140 to complete electrical signal interconnection.

[0092] Exemplarily, the peripheral circuit 140 may include, but is not limited to: a sense amplifier circuit, a row decoding circuit, a column decoding circuit, a voltage generation circuit, etc. The sense amplifier circuit is coupled to the bit line 112, and the sense amplifier circuit may be configured to capture weak voltage fluctuations on the bit line 112 and locally restore the capacitance voltage of the memory cell according to the situation of the voltage fluctuations. A latch may be included in the sense amplifier circuit to latch the restored capacitance voltage value, so that the information stored in the memory cell is transferred from the capacitance to the amplifier circuit. The sense amplifier circuit may include a differential sense amplifier circuit, which is coupled to two bit lines 112 and operates using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuit is configured to perform row addressing on the memory array and apply an operating voltage to the word line 113. The column decoding circuit is configured to perform column addressing on the memory array, apply the bit line 112 voltage or receive the bit line 112 voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0093] In some embodiments, referring to Figure 1 and Figure 2 as shown, the second semiconductor structure 102 further includes: a first interconnection layer 141 and a pad 142 located on the surface of the second semiconductor structure 102 away from the first semiconductor structure 101, and the first interconnection layer 141 and the pad 142 are coupled to the second semiconductor structure 102. The first interconnection layer 141 may be coupled to the devices in the peripheral circuit 140 to provide power supply or communication for the devices in the peripheral circuit 140, and the pad 142 may serve as an IO interface of the memory device 100 for external power supply or external communication of the memory device 100.

[0094] Exemplarily, the constituent materials of the first contact structure 121, the second contact structure 122, the bonding contact 131, and the pad 142 may include, but are not limited to: conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, or nickel.

[0095] According to some aspects of the embodiments of the present disclosure, a memory device 100 is provided, including: referring to Figure 1 as shown, a semiconductor column 111 extending along a first direction (z direction), the semiconductor column 111 having a first end and a second end disposed opposite to each other in the first direction; a bit line 112, located on one side of the semiconductor column 111 close to the first end and coupled to the first end; the bit line 112 extends along a second direction (x direction) perpendicular to the first direction;

[0096] Referring to Figure 2As shown, a first side of the bit line 112 along a third direction (y direction) is aligned with a first side of the semiconductor pillar 111 along the third direction in a first direction, and a dimension of the bit line 112 in the third direction is smaller than a dimension of the semiconductor pillar 111 in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with a second direction; a capacitor structure 115, located on a side of the semiconductor pillar 111 away from the bit line 112, and coupled to the second end; a peripheral circuit 140, located on a side of the capacitor structure 115 away from the semiconductor pillar 111; wherein, the peripheral circuit 140 is coupled to at least the capacitor structure 115 and the bit line 112. The capacitor structure 115 is located between the peripheral circuit 140 and the semiconductor pillar 111, and the semiconductor pillar 111 is located between the bit line 112 and the capacitor structure 115.

[0097] In some embodiments, the memory device 100 further includes a word line 113 extending along the y direction. Devices such as the semiconductor pillar 111, the capacitor structure 115, the bit line 112, the word line 113, and the peripheral circuit 140 may be located in the same semiconductor structure. In some other embodiments, the semiconductor pillar 111, the capacitor structure 115, the bit line 112, and the word line 113 may be located in one semiconductor structure, and the peripheral circuit 140 may be located in another semiconductor structure, and the two semiconductor structures may be electrically interconnected through bonding.

[0098] In some embodiments, a second side of the bit line 112 along the third direction is located between a first side and a second side of the semiconductor pillar 111 along the third direction.

[0099] In some embodiments, a projection of the bit line 112 on a first plane is offset from a projection of the semiconductor pillar 111 on the first plane along the third direction; wherein, the first plane is perpendicular to the first direction.

[0100] In some embodiments, the memory device 100 further includes: a dielectric layer, located between two adjacent bit lines 112 in the third direction.

[0101] In some embodiments, the dielectric layer includes: a first dielectric layer 161, a second dielectric layer 162, a third dielectric layer 163, and a fourth dielectric layer 164 sequentially arranged along the third direction; wherein, the first dielectric layer 161 is located at an end of the semiconductor pillar 111 close to the first end, and a sum of dimensions of the first dielectric layer 161 and the bit line 112 in the third direction is smaller than a dimension of the semiconductor pillar 111 in the third direction; a projection of the first dielectric layer 161 on a second plane overlaps with a projection of the bit line 112 on the second plane; the second plane is perpendicular to the third direction; the second dielectric layer 162 includes a first portion extending along the first direction and a second portion extending along the third direction, the second portion is located between the first dielectric layer 161 and the first portion, and a projection of the second portion on the second plane overlaps with a projection of the bit line 112 on the second plane; both the third dielectric layer 163 and the fourth dielectric layer 164 extend along the first direction.

[0102] In some embodiments, the constituent materials of the first dielectric layer 161 and the fourth dielectric layer 164 include: silicon oxide; the constituent material of the second dielectric layer 162 includes: aluminum oxide or silicon nitride; the constituent materials of the third dielectric layer 163 and the third dielectric layer 163 both include: aluminum oxide or silicon nitride.

[0103] In some embodiments, the memory device 100 further includes: a word line 113 located on at least one side of the semiconductor pillar 111, and at least a part of the word line 113 extends in the third direction; a gate dielectric layer 114 located between the word line 113 and the semiconductor pillar 111.

[0104] In some embodiments, the word line 113 includes a first word line 113a and a second word line 113b; the first word line 113a and the second word line 113b are respectively located on two opposite sides of a semiconductor pillar 111 along the second direction.

[0105] In some embodiments, the first word line 113a and / or the second word line 113b includes a protrusion 123, and the protrusion 123 is located at one end of the first word line 113a and / or the second word line 113b close to the bit line 112; the protrusion 123 extends in a direction away from the semiconductor pillar 111.

[0106] In some embodiments, the word line 113 covers one side of the semiconductor pillar 111 perpendicular to the first direction; alternatively, the word line 113 covers two sides of the semiconductor pillar 111 perpendicular to the first direction; alternatively, the word line 113 covers three sides of the semiconductor pillar 111 perpendicular to the first direction.

[0107] In some embodiments, the size of the end of the capacitor structure 115 away from the bit line 112 in the second direction and / or the third direction is larger than the size of the end of the capacitor structure 115 close to the bit line 112 in the second direction and / or the third direction.

[0108] In some embodiments, the capacitor structure 115 includes: a first electrode 1151, and a fifth dielectric layer 1152 and a second electrode 1153 surrounding the first electrode 1151; the fifth dielectric layer 1152 is located between the first electrode 1151 and the second electrode 1153.

[0109] In some embodiments, the semiconductor pillar 111, the bit line 112, and the capacitor structure 115 are located in the first semiconductor structure 101; the peripheral circuit 140 is located in the second semiconductor structure 102; the first semiconductor structure 101 is bonded to the second semiconductor structure 102.

[0110] In some embodiments, the memory device 100 further includes: a first interconnect layer 141 and pads 142 located on a surface of the second semiconductor structure 102 away from the first semiconductor structure 101, and the first interconnect layer 141 and the pads 142 are coupled to the second semiconductor structure 102.

[0111] According to some aspects of the embodiments of the present disclosure, Figure 6 A schematic flow chart of a method for manufacturing a memory device 100 is provided, including forming a first semiconductor structure 101. Refer to Figure 6 As shown, the manufacturing method of the first semiconductor structure 101 includes:

[0112] Forming a semiconductor pillar extending along a first direction, the semiconductor pillar having a first end and a second end disposed opposite to each other in the first direction;

[0113] Forming bit lines extending along a second direction perpendicular to the first direction on a side of the semiconductor pillar close to the first end; the bit lines are coupled to the first end, a first side of the bit lines along a third direction is aligned with a first side of the semiconductor pillar along the third direction in the first direction, and a dimension of the bit lines in the third direction is smaller than a dimension of the semiconductor pillar in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with the second direction. In some embodiments, the manufacturing method may include: providing a first substrate structure 13 and forming the first semiconductor structure 101 in the first substrate structure 13.

[0114] Specifically, in some embodiments, the manufacturing method of the first substrate structure 13 includes: Refer to Figure 7 As shown, providing a first substrate 11 including a first insulating layer 1102 and a second substrate 12 including a second insulating layer 1202; bonding the first insulating layer 1102 and the second insulating layer 1202 to form a first dielectric layer 161, and thinning a surface of the first substrate 11 away from the first dielectric layer 161 to form a semiconductor layer 1111, obtaining Figure 8The first substrate structure 13 shown. The first insulating layer 1102 and the second insulating layer 1202 may include silicon oxide. The first insulating layer 1102 and the second insulating layer 1202 can be bonded through a thermal compression bonding process, and there may be no obvious physical boundary after bonding. The first insulating layer 1102 can be formed on the first substrate 1101 by a deposition method, or the first insulating layer 1102 can also be an oxide layer formed by furnace tube oxidation or natural oxidation in air. The second insulating layer 1202 can be formed on the second substrate 1201 by a deposition method, and other film layers may be included between the second insulating layer 1202 and the second substrate 1201, such as a stop layer 151. The first substrate 1101 and the second substrate 1201 can be semiconductor wafers or parts of semiconductor wafers after being cut. The surface of the first substrate 1101 away from the first dielectric layer 161 is thinned, and the remaining first substrate 1101 after thinning is the semiconductor layer 1111. The thinning process may include chemical mechanical polishing, lapping, or a combination thereof.

[0115] The constituent materials of the first substrate 1101 and the second substrate 1201 may include, but are not limited to: elemental semiconductor materials (such as silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. In some other embodiments, Figure 8 The first substrate structure 13 shown can be a well-known SOI substrate or an SOI (Silicon-On-Insulator) wafer in the art.

[0116] In some embodiments, the method of forming the bit line 112 includes: providing Figure 8 The first substrate structure 13 shown; wherein, the first substrate structure 13 includes a first dielectric layer 161 and a semiconductor layer 1111 stacked; forming a first trench 171 penetrating through the semiconductor layer 1111 and the first dielectric layer 161 along a first direction; the first trench 171 extends along a second direction; the first trench 171 divides the semiconductor layer 1111 into semiconductor strips 1112; reducing the size of the first dielectric layer 161 in a third direction, and forming a bit line 112 extending along the second direction on one side of the semiconductor strip 1112 close to the first dielectric layer 161.

[0117] In some embodiments, the method of forming bit line 112 further includes: removing a portion of the first dielectric layer 161, reducing the size of the first dielectric layer 161 in the third direction to form a first opening 172 with an opening direction towards the third direction, the first opening 172 extending along the second direction; filling the first opening 172 to form a second dielectric layer 162, the second dielectric layer 162 covering the sidewalls of the first trench 171; the second dielectric layer 162 and the first dielectric layer 161 surrounding the side surfaces of the semiconductor strip 1112 and surrounding the surface of the semiconductor strip 1112 close to the first dielectric layer 161, exposing the surface of the semiconductor strip 1112 away from the first dielectric layer 161; filling the remaining cavity of the first trench 171 to form a third dielectric layer 163; removing the second dielectric layer 162 on one side of the first dielectric layer 161 to form a second trench 173; wherein the second trench 173 exposes the first dielectric layer 161, exposes the side surface of the semiconductor strip 1112, and exposes the surface of the semiconductor strip 1112 close to the first dielectric layer 161; forming the bit line 112 in the portion of the second trench 173 extending towards the first dielectric layer 161.

[0118] Referring Figure 9 As shown, the semiconductor layer 1111 and the first dielectric layer 161 are etched to form a first trench 171 penetrating through the semiconductor layer 1111 and the first dielectric layer 161. The first trench 171 exposes the stop layer 151. The stop layer 151 serves as an etching stop layer for this etching and may not be etched or may be partially etched. The bottom of the first trench 171 may stop at the upper surface of the stop layer 151, and the bottom of the first trench 171 may extend into the stop layer 151 but does not penetrate the stop layer 151. The etching process may include dry etching, wet etching, or a combination thereof. Exemplarily, the semiconductor layer 1111 may include silicon, the first dielectric layer 161 may include silicon oxide, the stop layer 151 may include silicon oxide denser than the silicon oxide of the first dielectric layer 161, or the stop layer 151 may include silicon nitride. Thus, when etching the semiconductor layer 1111 and the first dielectric layer 161, the stop layer 151 has a good etching stop or blocking effect.

[0119] Referring Figure 10 As shown, the first dielectric layer 161 exposed from the sidewalls of the first trench 171 is etched to remove a portion of the first dielectric layer 161 and reduce the size of the first dielectric layer 161 in the y direction to form a first opening 172 with openings towards the positive y and negative y directions; a portion of the thickness (or, a portion of the length) of the first dielectric layer 161 is retained in the y direction to prevent the semiconductor strip 1112 from losing support and collapsing. Figure 10 The etching process for removing the first dielectric layer 161 may include gas etching or wet etching, and the etching amount may be controlled by controlling the etching duration to form the first opening 172 without causing the collapse of the semiconductor strip 1112.

[0120] ReferringFigure 11 As shown, a second dielectric layer 162 covering the sidewalls on both sides of the first trench 171 is formed in the first opening 172. The second dielectric layer 162 extends into the first opening 172 to fill the first opening 172. The morphology of the second dielectric layer 162 can be L-shaped. One part extends along the z direction and covers one side of the semiconductor strip 1112 in the y direction, and the other part extends along the y direction and is located at the bottom of the semiconductor strip 1112. The second dielectric layer 162 can be in contact with the first dielectric layer 161. Two L-shaped second dielectric layers 162 and the first dielectric layer 161 surround the bottom of the semiconductor strip 1112 and both sides of the semiconductor strip 1112 in the y direction, exposing the top surface of the semiconductor strip 1112 away from the first dielectric layer 161. After the second dielectric layer 162 is formed, a third dielectric layer 163 extending along the z direction is formed in the remaining cavity of the first trench 171, and the third dielectric layer 163 can fill the remaining space of the first trench 171.

[0121] Exemplarily, the second dielectric layer 162 and the third dielectric layer 163 can be formed by deposition, and the deposition process includes but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0122] Refer to Figure 12 As shown, a patterned mask layer 153 is formed. Refer to Figure 13 As shown, using the mask layer 153 as an etching mask, the second dielectric layer 162 on one side of the first dielectric layer 161 is etched away, and the second dielectric layer 162 on the other side is retained to form a second trench 173. For example, the second dielectric layer 162 on the left side of the first dielectric layer 161 is removed, and the second dielectric layer 162 on the right side of the first dielectric layer 161 and the third dielectric layer 163 are retained. The morphology of the second trench 173 can be L-shaped. The second trench 173 exposes the left side of the semiconductor strip 1112 in the y direction, and the bottom of the second trench 173 also exposes the bottom surface of the semiconductor strip 1112. The bottom surface of the semiconductor strip 1112 exposed at the bottom of the second trench 173 is only the bottom surface on the left side of the first dielectric layer 161, and the bottom of the second trench 173 exposes the left surface of the first dielectric layer 161 in the y direction. A bit line 112 is formed in the part of the bottom of the second trench 173 extending towards the first dielectric layer 161 (for example Figure 16The bit line 112 shown has its left side aligned with the left side of the semiconductor strip 1112 in the z direction, and its right side in contact with the first dielectric layer 161. In some other embodiments, by adjusting the pattern position of the mask layer 153, the second dielectric layer 162 on the right side of the first dielectric layer 161 can be etched away, while the second dielectric layer 162 on the left side of the first dielectric layer 161 and the third dielectric layer 163 are retained, such that the right side of the formed bit line 112 is aligned with the right side of the semiconductor strip 1112 in the z direction.

[0123] In some embodiments, the method of forming the second trench 173 further includes: removing a partial thickness of the third dielectric layer 163 to reduce the size of the third dielectric layer 163 in the third direction. Referring to Figure 13 As shown, when removing the second dielectric layer 162, a part of the third dielectric layer 163 can also be removed to expand the size of the second trench 173 in the y direction by reducing the size of the third dielectric layer 163 in the y direction, providing more space for depositing a conductive material in the second trench 173 to form the bit line 112 later and improving the manufacturing yield of the bit line 112.

[0124] In some embodiments, the material compositions of the first dielectric layer 161, the second dielectric layer 162, and the third dielectric layer 163 can be selected according to the selectivity of the etchant for different materials, and a suitable etchant can be selected for different film layers. For example, the semiconductor strip 1112 can include silicon, the first dielectric layer 161 can include silicon oxide, the second dielectric layer 162 can include aluminum oxide, and the third dielectric layer 163 can include silicon nitride. When etching away the second dielectric layer 162, an etchant including acidic liquids or gases such as hydrochloric acid and sulfuric acid can be used, and the second dielectric layer 162 is removed by the isotropic diffusion of the etchant to form Figure 13 the L-shaped second trench 173 shown. When etching the second dielectric layer 162, the semiconductor strip 1112 and the third dielectric layer 163 are substantially not etched. Also for example, the semiconductor strip 1112 can include silicon, the first dielectric layer 161 can include silicon oxide, the second dielectric layer 162 can include silicon nitride, and the third dielectric layer 163 can include aluminum oxide. When etching away the second dielectric layer 162, an etchant including phosphoric acid can be used, and the second dielectric layer 162 is removed by the isotropic diffusion of the etchant to form Figure 13 the L-shaped second trench 173 shown.

[0125] In some embodiments, the method of forming the bit line 112 includes:

[0126] Referring to Figure 14 As shown, filling the second trench 173 to form a first conductive layer 1121, the first conductive layer 1121 including portions extending along the first direction and the third direction respectively; wherein, the portion of the first conductive layer 1121 extending along the third direction extends towards the first dielectric layer 161; Referring toFigure 15 As shown, a part of the first conductive layer 1121 extending in the first direction is removed to form a third trench 174; wherein, the third trench 174 exposes the third dielectric layer 163 and one side surface of the semiconductor strip 1112; the remaining first conductive layer 1121 forms the bit line 112.

[0127] In some embodiments, referring to Figure 15 As shown, the portion of the first conductive layer 1121 extending in the z direction is etched away, and the remaining first conductive layer 1121 serves as the bit line 112. The left side of the bit line 112 in the y direction is aligned with the left side of the semiconductor pillar 111 in the z direction, and the size of the bit line 112 in the y direction is smaller than the size of the semiconductor strip 1112 in the y direction. During the etching process, parameters such as the etching time can be controlled so that the left side of the bit line 112 is completely aligned with the left side of the semiconductor pillar 111 in the z direction. Alternatively, in some examples, because the side surface of the semiconductor strip 1112 is partially over-etched, the left side of the bit line 112 protrudes from the left side of the semiconductor strip 1112 in the negative y direction. Or, in some examples, because the bit line 112 is over-etched, the left side of the semiconductor strip 1112 protrudes from the left side of the semiconductor strip 1112 in the negative y direction. The above protrusion distance is within the process control range of the embodiments of the present disclosure. For example, the distance that the left side of the bit line 112 protrudes from the semiconductor strip 1112 can be less than 5% of the size of the bit line 112 in the y direction.

[0128] In some embodiments, referring to Figure 16 As shown, the method for fabricating the first semiconductor structure 101 further includes: filling the third trench 174 to form a fourth dielectric layer 164. Figure 17 Shows Figure 16 A top view of the device structure in

[0129] In some embodiments, the method for forming the semiconductor pillar 111 further includes: referring to Figure 18 As shown, a fourth trench 175 is formed through the semiconductor strip 1112, and the fourth trench 175 divides the semiconductor strip 1112 into semiconductor pillars 111; the fourth trench 175 extends in the third direction; the method for fabricating the first semiconductor structure 101 further includes: sequentially forming a gate dielectric layer 114 and a word line 113 on at least one side surface of the semiconductor pillar 111. Figure 18 The bottom of the fourth trench 175 in Figure 19 Shows Figure 18 A top view of the device structure inFigure 19 Only the first dielectric layer 161 with two fourth trenches 175 extending in the y direction exposed is shown. Figure 19 The first dielectric layer 161 in [this figure] can indicate the position of the fourth trenches 175. The manufacturing steps for forming the fourth trenches 175 can be carried out after the bit lines 112 are formed or before the bit lines 112 are formed, and there is no restriction on the manufacturing sequence; the manufacturing steps for the gate dielectric layer 114 and the word lines 113 can be carried out after the fourth trenches 175 are formed.

[0130] In some embodiments, the method for forming the word lines 113 includes: referring to Figure 20 As shown, a sixth dielectric layer 152 is formed at the bottom of the fourth trenches 175, and the size of the sixth dielectric layer 152 in the first direction is smaller than the size of the semiconductor pillar 111 in the first direction; referring to Figure 21 As shown, a gate dielectric layer 114 and a second conductive layer 1131 are sequentially formed on the sidewalls of the fourth trenches 175 and the sixth dielectric layer 152; Figure 22 As shown, the second conductive layer 1131 is penetrated along the first direction to form a first word line 113a and a second word line 113b on two opposite side surfaces of the semiconductor pillar 111 along the second direction.

[0131] Figure 20 In [this figure], the formation of the sixth dielectric layer 152 can increase the distance between the word lines 113 and the first dielectric layer 161, so that the word lines 113 are located in the middle of the semiconductor pillar 111. In some other embodiments, the sixth dielectric layer 152 may not be formed, and the word lines 113 are directly formed based on Figure 18 the fourth trenches 175.

[0132] Figure 21 In [this figure], the deposited gate dielectric layer 114 covers the sidewalls and the bottom surface of the fourth trenches 175, and the deposited second conductive layer 1131 covers the gate dielectric layer 114, and the morphology of the second conductive layer 1131 is U-shaped. Figure 22 In [this figure], the second conductive layer 1131 is etched along the z direction, penetrating the second conductive layer 1131 on the bottom surface of the fourth trenches 175, and the bottom of the U-shaped second conductive layer 1131 is broken to form two word lines 113, and one semiconductor pillar 111 corresponds to two word lines 113. When etching through the second conductive layer 1131, it can penetrate the gate dielectric layer 114 along the z direction or not etch the gate dielectric layer 114.

[0133] Referring to Figure 23 As shown, the remaining space of the fourth trenches 175 is filled with a dielectric material to electrically isolate adjacent word lines 113. The constituent materials of the gate dielectric layer 114 and the dielectric material can be the same, and can both be silicon oxide, and there may not be an obvious physical boundary between the gate dielectric layer 114 and the dielectric material.

[0134] In some embodiments, referring toFigure 24 As shown, when passing through the second conductive layer 1131, a part of the second conductive layer 1131 remaining on the sixth dielectric layer 152 forms a protrusion 123 at one end of the first word line 113a and / or the second word line 113b close to the bit line 112, and the protrusion 123 extends in a direction away from the semiconductor pillar 111. Figure 24 The device structure shown is a schematic diagram of the structure after the word line 113 is formed and the fourth trench 175 is filled with dielectric material. When passing through the second conductive layer 1131 along the z direction, due to the loading effect of etching, there will be some residual parts at the bottom of the second conductive layer 1131 that are not completely removed, forming a protrusion 123 at one end of the first word line 113a and / or the second word line 113b close to the bit line 112, such as the protrusion 123 extending along the positive x direction on the first word line 113a, and / or the protrusion 123 extending along the negative x direction on the second word line 113b.

[0135] In some embodiments, the word line 113 covers one side of the semiconductor pillar 111 along a direction perpendicular to the first direction; alternatively, the word line 113 covers two sides of the semiconductor pillar 111 along a direction perpendicular to the first direction; alternatively, the word line 113 covers three sides of the semiconductor pillar 111 along a direction perpendicular to the first direction.

[0136] Figure 25 Shows Figure 23 A top view of the device structure in, one side of the semiconductor pillar 111 in the y direction is covered by the second dielectric layer 162, and the word line 113 can cover any one of the remaining three sides of the semiconductor pillar 111 that are not covered by the dielectric layer. Figure 25 One semiconductor pillar 111 in corresponds to two word lines 113, the first word line 113a and the second word line 113b, covering two sides of the semiconductor pillar 111 along the x direction. Alternatively, the semiconductor pillar 111 can correspond to any one of the first word line 113a and the second word line 113b, the word line extends along the y direction, and covers one side of the semiconductor pillar 111 in the x direction along the x direction. Alternatively, in some embodiments, referring to Figure 26 As shown, a bridging structure 1132 is provided between the first word line 113a and the second word line 113b corresponding to one semiconductor pillar 111, the bridging structure 1132 extends along the x direction, and covers a relative side of the second dielectric layer 162 along the y direction. The bridging structure 1132 can be a part of the word line 113.

[0137] In some embodiments, the manufacturing method of the first semiconductor structure 101 further includes: forming a capacitor structure 115 on a side of the semiconductor pillar 111 away from the bit line 112, and the capacitor structure 115 is coupled to the second end of the semiconductor pillar 111.

[0138] In some embodiments, the dimension of the end of the capacitor structure 115 away from the bit line 112 in the second direction and / or the third direction is greater than the dimension of the end of the capacitor structure 115 close to the bit line 112 in the second direction and / or the third direction.

[0139] In some embodiments, the capacitor structure 115 includes: a first electrode 1151, and a fifth dielectric layer 1152 and a second electrode 1153 surrounding the first electrode 1151; the fifth dielectric layer 1152 is located between the first electrode 1151 and the second electrode 1153.

[0140] Referring to Figure 27 As shown, a dielectric material layer can be formed on the semiconductor pillar 111, the dielectric material layer is etched to form an opening exposing the end of the semiconductor pillar 111 away from the bit line 112, and a first electrode 1151, a fifth dielectric layer 1152 surrounding the first electrode 1151, and a second electrode 1153 are sequentially formed in the opening; the fifth dielectric layer 1152 is located between the first electrode 1151 and the second electrode 1153. Due to the loading effect of etching, the size of the top of the opening for forming the capacitor structure 115 is larger than the size of the bottom, and the dimension of the end of the formed capacitor structure 115 away from the bit line 112 in the x direction is greater than the dimension of the end of the capacitor structure 115 close to the bit line 112 in the x direction. For the specific structure of the capacitor structure 115, reference can be made to Figure 4 and Figure 5 .

[0141] Referring to Figure 28 As shown, a first contact structure 121 coupled to the bit line 112 is formed, and a bonding contact 131a is formed on the side of the first semiconductor structure 101 away from the bit line 112, and the first contact structure 121 is coupled to at least one bonding contact 131a. A second contact structure 122 coupled to the word line 113 is formed, and the second contact structure 122 is coupled to at least one bonding contact 131b. The second contact structure 122 is not shown in Figure 28 due to the sectional view angle, and reference can be made to Figure 2 .

[0142] Devices such as the bit line 112, the word line 113, the semiconductor pillar 111, and the capacitor structure 115 in the embodiments of the present disclosure can all be formed on one side surface (front side) of the first substrate 13, without bonding and carrying the wafer on the front side of the wafer, and using the backside process of the wafer after flipping the carrying wafer to form the bit line, avoiding the extrusion deformation of the devices by the carrying wafer, such as avoiding the extrusion deformation of the bonding contacts 131a, the first contact structure 121, and the second contact structure 122, improving the bonding alignment accuracy, and improving the manufacturing yield.

[0143] In some embodiments, the manufacturing method of the memory device 100 includes: referring to Figure 29As shown, a second semiconductor structure 102 is provided; on a side of the capacitor structure 115 away from the bit line 112, the second semiconductor structure 102 and the first semiconductor structure 101 are bonded.

[0144] Before bonding, the second semiconductor structure 102 further includes a bonding contact 131b to bond the bonding planes of the first semiconductor structure 101 and the second semiconductor structure 102. The interface where the bonding planes of the two semiconductor structures contact is the bonding interface. The bonding contacts 131a and 131b of the first semiconductor structure 101 and the second semiconductor structure 102 contact at the bonding interface to achieve electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. After the bonding contacts 131a and 131b are bonded, they may not have a physical dividing line and can be regarded as the bonding contact 131, which penetrates the bonding interface. When bonding the first semiconductor structure 101 and the second semiconductor structure 102, it may be to bond the wafer including the first semiconductor structure 101 and the wafer including the second semiconductor structure 102.

[0145] In some other embodiments, the second semiconductor structure 102 and the first semiconductor structure 101 may not be connected by bonding. The second semiconductor structure 102 is formed on the basis of the structure of the first semiconductor structure 101. The bonding contact 131 serves as a conductive contact, or the bonding contact 131 is not provided, and the first contact structure 121 and the second contact structure 122 are coupled to the interconnection structure in the peripheral circuit 140 to complete electrical signal interconnection.

[0146] In some embodiments, refer to Figure 1 and Figure 2As shown, the manufacturing method further includes: forming a first interconnection layer 141 and a pad 142 on a side surface of the second semiconductor structure 102 away from the first semiconductor structure 101, and the first interconnection layer 141 and the pad 142 are coupled to the second semiconductor structure 102. The first interconnection layer 141 can be coupled to the device in the peripheral circuit 140 to provide power supply or communication for the device in the peripheral circuit 140, and the pad 142 can be used as an IO interface of the memory device 100 for external power supply or external communication of the memory device 100. The lead structures such as the first interconnection layer 141 and the pad 142 of the embodiment of the present disclosure are formed after bonding. Compared with forming before bonding, the front side of the second semiconductor structure 102 can be bonded without using a carrier wafer, and then flipped to form the first interconnection layer 141 and the pad 142 and other lead structures, which can avoid the compression deformation of the carrier wafer on the device, for example, avoid the compression deformation of the bonding contact 131b, improve the bonding alignment accuracy, and improve the manufacturing yield. In some embodiments, the first interconnect layer 141 and the pad 142 may be formed before bonding, and the second semiconductor structure 102 including the first interconnect layer 141 and the pad 142 is bonded to the first semiconductor structure 101 .

[0147] The disclosed embodiment forms a bit line in the first substrate structure, and the bit line can be pre-buried under the semiconductor column before forming the semiconductor column, and then the semiconductor column, word line and capacitor structure are formed on the bit line; compared with the solution of first forming the semiconductor column, forming the word line along the front of the wafer, and forming the bit line along the back of the wafer, the bit line and word line of the disclosed embodiment can be formed on the front of the wafer, and the process size is easier to control, which is conducive to improving the manufacturing yield. The disclosed embodiment does not need to perform back-side process production on wafers with capacitor structures and wafers with peripheral circuits, and does not need to use a carrier wafer to perform front-side bonding and then flip the wafer with related device structures, so as to avoid the compression and deformation of the device structure by the carrier wafer, and improve the manufacturing yield.

[0148] According to some aspects of the embodiments of the present disclosure, Figure 30 A memory system 202 is provided, including a memory device 204, the memory device 204 including the memory device 100, and a memory controller 206, which is coupled to the memory device 204 and controls the memory device 204. The memory device 100 of the embodiment of the present disclosure can be used as the memory device 204, or at least a part of the memory device.

[0149] Reference Figure 30As shown, an embodiment of the present disclosure provides a system 200 including a host 208. The system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 30 As shown in Figure 30 , the system 200 may include a host 208 and a memory system 202 having one or more memory devices 204 and a memory controller 206. The host 208 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 208 may be configured to send data to or receive data from the memory device 204.

[0150] According to some embodiments, the memory controller 206 is coupled to the memory device 204 and the host 208 and is configured to control the memory device 204 to perform read, write, or refresh operations. The memory controller 206 may manage the data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure. The memory system 202 may serve as the memory of the host 208 in the system 200 or the cache of the system 200. In some specific examples, the memory system 202 may be used in an auxiliary manner in a solid-state drive, which can bring improvements in read and write operations to the solid-state drive. Currently, most high-end solid-state drive products choose to embed DRAM to improve product performance and random read and write speeds. Exemplarily, when writing files, especially small files, the small files are processed by DRAM and then stored in flash memory, making the solid-state drive more efficient and faster. Flash includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory.

[0151] In some other embodiments, referring to Figure 31 As shown in Figure 31 , the system 200 may only include the host 208 and the memory device 204 coupled thereto. The controller for controlling the memory device 204 may be located inside the host 208, such as a memory controller integrated in a central processing unit (CPU), or a northbridge or southbridge chip integrated on the motherboard of the system 200. The memory device 204 may include, but is not limited to, double data rate synchronous dynamic random access memory with DDR4 memory specifications, DDR5 memory specifications, or low-power double data rate synchronous dynamic random access memory with LPDDR5 memory specifications.

[0152] In some embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the direct or indirect coupling between the components shown or discussed. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0153] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory device, characterized in that, it includes a first semiconductor structure, and the first semiconductor structure includes: a semiconductor pillar extending along a first direction, the semiconductor pillar having a first end and a second end oppositely arranged in the first direction; a bit line located on one side of the semiconductor pillar close to the first end and coupled to the first end; the bit line extends along a second direction perpendicular to the first direction; a first side of the bit line along a third direction is aligned with a first side of the semiconductor pillar along the third direction in the first direction, and a dimension of the bit line in the third direction is smaller than a dimension of the semiconductor pillar in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with the second direction.

2. The memory device according to claim 1, characterized in that, a second side of the bit line along the third direction is located between a first side and a second side of the semiconductor pillar along the third direction.

3. The memory device according to claim 1, characterized in that, a projection of the bit line on a first plane has an offset from a projection of the semiconductor pillar on the first plane along the third direction; wherein, the first plane is perpendicular to the first direction.

4. The memory device according to claim 3, characterized in that, the memory device further includes: a dielectric layer located between two adjacent bit lines in the third direction.

5. The memory device according to claim 4, characterized in that, the dielectric layer includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer arranged in sequence along the third direction; wherein, the first dielectric layer is located at an end of the semiconductor pillar close to the first end, and a sum of dimensions of the first dielectric layer and the bit line in the third direction is smaller than a dimension of the semiconductor pillar in the third direction; a projection of the first dielectric layer on a second plane overlaps with a projection of the bit line on the second plane; the second plane is perpendicular to the third direction; the second dielectric layer includes a first part extending along the first direction and a second part extending along the third direction, the second part is located between the first dielectric layer and the first part, and a projection of the second part on the second plane overlaps with a projection of the bit line on the second plane; both the third dielectric layer and the fourth dielectric layer extend along the first direction.

6. The memory device according to claim 5, characterized in that, composition materials of the first dielectric layer and the fourth dielectric layer include: silicon oxide; composition materials of the second dielectric layer and the third dielectric layer both include: aluminum oxide or silicon nitride.

7. The memory device according to claim 1, characterized in that, the memory device further includes: a word line located on at least one side surface of the semiconductor pillar, and at least a part of the word line extends along the third direction; a gate dielectric layer located between the word line and the semiconductor pillar.

8. The memory device according to claim 7, characterized in that, The word line includes a first word line and a second word line; the first word line and the second word line are respectively located on two opposite side surfaces of the semiconductor pillar along the second direction.

9. The memory device according to claim 8, wherein, the first word line and / or the second word line includes a protrusion, and the protrusion is located at one end of the first word line and / or the second word line close to the bit line; the protrusion extends in a direction away from the semiconductor pillar.

10. The memory device according to claim 7, wherein, the word line covers one side surface of the semiconductor pillar along a direction perpendicular to the first direction; alternatively, the word line covers two side surfaces of the semiconductor pillar along a direction perpendicular to the first direction; alternatively, the word line covers three side surfaces of the semiconductor pillar along a direction perpendicular to the first direction.

11. The memory device according to claim 1, wherein, the memory device further includes: a capacitor structure, located on a side of the semiconductor pillar away from the bit line; the capacitor structure is coupled to the second end.

12. The memory device according to claim 11, wherein, a dimension of an end of the capacitor structure away from the bit line in the second direction and / or the third direction is greater than a dimension of an end of the capacitor structure close to the bit line in the second direction and / or the third direction.

13. The memory device according to claim 11, wherein, the capacitor structure includes: a first electrode, and a fifth dielectric layer and a second electrode surrounding the first electrode; the fifth dielectric layer is located between the first electrode and the second electrode.

14. The memory device according to claim 11, wherein, the memory device further includes: a second semiconductor structure, the second semiconductor structure includes a peripheral circuit, located on a side of the capacitor structure away from the semiconductor pillar; the second semiconductor structure is bonded to the first semiconductor structure.

15. The memory device according to claim 14, wherein, the second semiconductor structure further includes: a first interconnection layer and a pad located on a surface of the second semiconductor structure away from the first semiconductor structure, and the first interconnection layer and the pad are coupled to the second semiconductor structure.

16. A memory device, wherein, comprising: a semiconductor pillar extending along a first direction, the semiconductor pillar having a first end and a second end oppositely arranged in the first direction; a bit line, located on a side of the semiconductor pillar close to the first end, and coupled to the first end; the bit line extends along a second direction perpendicular to the first direction; a first side of the bit line in a third direction is aligned with a first side of the semiconductor pillar in the third direction in the first direction, and a dimension of the bit line in the third direction is smaller than a dimension of the semiconductor pillar in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with the second direction; a capacitor structure, located on a side of the semiconductor pillar away from the bit line, and coupled to the second end; The peripheral circuit is located on a side of the capacitive structure away from the semiconductor pillar; wherein, the peripheral circuit is coupled to at least the capacitive structure and the bit line.

17. The memory device according to claim 16, wherein, a second side of the bit line along the third direction is located between a first side and a second side of the semiconductor pillar along the third direction.

18. The memory device according to claim 16, wherein, a projection of the bit line on a first plane and a projection of the semiconductor pillar on the first plane are offset along the third direction; wherein, the first plane is perpendicular to the first direction.

19. The memory device according to claim 18, wherein, the memory device further comprises: a dielectric layer located between two adjacent bit lines in the third direction.

20. The memory device according to claim 19, wherein, the dielectric layer comprises: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer arranged in sequence along the third direction; wherein, the first dielectric layer is located at an end of the semiconductor pillar close to the first end, and a sum of dimensions of the first dielectric layer and the bit line in the third direction is smaller than a dimension of the semiconductor pillar in the third direction; a projection of the first dielectric layer on a second plane overlaps with a projection of the bit line on the second plane; the second plane is perpendicular to the third direction; the second dielectric layer comprises a first portion extending along the first direction and a second portion extending along the third direction, the second portion is located between the first dielectric layer and the first portion, and a projection of the second portion on the second plane overlaps with a projection of the bit line on the second plane; both the third dielectric layer and the fourth dielectric layer extend along the first direction.

21. The memory device according to claim 20, wherein, the first dielectric layer and the fourth dielectric layer are made of silicon oxide; the second dielectric layer is made of aluminum oxide or silicon nitride; both the third dielectric layer and the third dielectric layer are made of aluminum oxide or silicon nitride.

22. The memory device according to claim 16, wherein, the memory device further comprises: a word line located on at least one side surface of the semiconductor pillar, and at least a part of the word line extends along the third direction; a gate dielectric layer located between the word line and the semiconductor pillar.

23. The memory device according to claim 22, wherein, the word line comprises a first word line and a second word line; the first word line and the second word line are respectively located on two opposite side surfaces of a semiconductor pillar along the second direction.

24. The memory device according to claim 23, wherein, the first word line and / or the second word line comprises a protrusion, the protrusion is located at an end of the first word line and / or the second word line close to the bit line; the protrusion extends in a direction away from the semiconductor pillar.

25. The memory device according to claim 22, Characterized in that, the word line covers one side surface of the semiconductor pillar along a direction perpendicular to the first direction; alternatively, the word line covers two side surfaces of the semiconductor pillar along a direction perpendicular to the first direction; alternatively, the word line covers three side surfaces of the semiconductor pillar along a direction perpendicular to the first direction.

26. The memory device according to claim 16, characterized in that, the size of the end of the capacitor structure far from the bit line in the second direction and / or the third direction is larger than the size of the end of the capacitor structure close to the bit line in the second direction and / or the third direction.

27. The memory device according to claim 26, characterized in that, the capacitor structure includes: a first electrode, and a fifth dielectric layer and a second electrode surrounding the first electrode; the fifth dielectric layer is located between the first electrode and the second electrode.

28. The memory device according to claim 16, characterized in that, the semiconductor pillar, the bit line and the capacitor structure are located in a first semiconductor structure; the peripheral circuit is located in a second semiconductor structure; the first semiconductor structure is bonded to the second semiconductor structure.

29. The memory device according to claim 28, characterized in that, the memory device further includes: a first interconnection layer and a pad located on a surface of the second semiconductor structure far from the first semiconductor structure, and the first interconnection layer and the pad are coupled to the second semiconductor structure.

30. A manufacturing method of a memory device, characterized in that, forming a first semiconductor structure, and the manufacturing method of the first semiconductor structure includes: forming a semiconductor pillar extending along a first direction, and the semiconductor pillar has a first end and a second end oppositely arranged in the first direction; forming a bit line extending along a second direction perpendicular to the first direction on a side of the semiconductor pillar close to the first end; the bit line is coupled to the first end, a first side of the bit line along a third direction is aligned with a first side of the semiconductor pillar along the third direction in the first direction, and the size of the bit line in the third direction is smaller than the size of the semiconductor pillar in the third direction; wherein, the third direction is perpendicular to the first direction and intersects with the second direction.

31. The manufacturing method according to claim 30, characterized in that, the method for forming the bit line includes: providing a first substrate structure; wherein, the first substrate structure includes a first dielectric layer and a semiconductor layer stacked; forming a first trench penetrating through the semiconductor layer and the first dielectric layer along the first direction; the first trench extends along the second direction; the first trench divides the semiconductor layer into semiconductor strips; reducing the size of the first dielectric layer in the third direction, and forming a bit line extending along the second direction on a side of the semiconductor strip close to the first dielectric layer.

32. The manufacturing method according to claim 31, characterized in that, the manufacturing method of the first substrate structure includes: providing a first substrate including a first insulating layer, and providing a second substrate including a second insulating layer; Bond the first insulating layer and the second insulating layer to form the first dielectric layer, and thin the surface of the first substrate on the side away from the first dielectric layer to form the semiconductor layer.

33. The manufacturing method according to claim 31, wherein, the method of forming the bit line further includes: Removing a part of the first dielectric layer and reducing the size of the first dielectric layer in the third direction to form a first opening with an opening direction facing the third direction, and the first opening extends along the second direction; Filling the first opening to form a second dielectric layer, and the second dielectric layer covers the side wall of the first trench; the second dielectric layer and the first dielectric layer surround the side surface of the semiconductor strip and the side surface of the semiconductor strip close to the first dielectric layer, and expose the side surface of the semiconductor strip away from the first dielectric layer; Filling the remaining cavity of the first trench to form a third dielectric layer; Removing the second dielectric layer on one side of the first dielectric layer to form a second trench; wherein, the second trench exposes the first dielectric layer, exposes the side surface of the semiconductor strip, and exposes the side surface of the semiconductor strip close to the first dielectric layer; Form the bit line in the part of the second trench extending towards the first dielectric layer.

34. The manufacturing method according to claim 33, wherein, the method of forming the second trench further includes: Removing a part of the thickness of the third dielectric layer and reducing the size of the third dielectric layer in the third direction.

35. The manufacturing method according to claim 33, wherein, the method of forming the bit line includes: Filling the second trench to form a first conductive layer, and the first conductive layer includes parts extending along the first direction and the third direction respectively; wherein, the part of the first conductive layer extending along the third direction extends towards the first dielectric layer; Removing a part of the first conductive layer extending along the first direction to form a third trench; wherein, the third trench exposes the third dielectric layer and exposes one side surface of the semiconductor strip; the remaining first conductive layer forms the bit line.

36. The manufacturing method according to claim 35, wherein, the manufacturing method of the first semiconductor structure further includes: Filling the third trench to form a fourth dielectric layer.

37. The manufacturing method according to any one of claims 31 to 36, wherein, the method of forming the semiconductor pillar further includes: Forming a fourth trench penetrating the semiconductor strip, and the fourth trench divides the semiconductor strip into semiconductor pillars; the fourth trench extends along the third direction; the manufacturing method of the first semiconductor structure further includes: Sequentially forming a gate dielectric layer and a word line on at least one side surface of the semiconductor pillar.

38. The manufacturing method according to claim 37, wherein, the method of forming the word line includes: Forming a sixth dielectric layer at the bottom of the fourth trench, and the size of the sixth dielectric layer in the first direction is smaller than the size of the semiconductor pillar in the first direction; On the sidewalls of the fourth trench and on the sixth dielectric layer, a gate dielectric layer and a second conductive layer are sequentially formed; Penetrate the second conductive layer along the first direction to form a first word line and a second word line on two opposite sides of the semiconductor pillar along the second direction.

39. The manufacturing method according to claim 38, characterized in that, When penetrating the second conductive layer, a remaining part of the second conductive layer on the sixth dielectric layer forms a protrusion at one end of the first word line and / or the second word line close to the bit line, and the protrusion extends in a direction away from the semiconductor pillar.

40. The manufacturing method according to claim 37, characterized in that, The word line covers one side surface of the semiconductor pillar along a direction perpendicular to the first direction; Or, the word line covers two side surfaces of the semiconductor pillar along a direction perpendicular to the first direction; Or, the word line covers three side surfaces of the semiconductor pillar along a direction perpendicular to the first direction.

41. The manufacturing method according to claim 30, characterized in that, The manufacturing method of the first semiconductor structure further includes: Forming a capacitor structure on a side of the semiconductor pillar away from the bit line, and the capacitor structure is coupled to the second end of the semiconductor pillar.

42. The manufacturing method according to claim 41, characterized in that, The size of one end of the capacitor structure away from the bit line in the second direction and / or the third direction is larger than the size of one end of the capacitor structure close to the bit line in the second direction and / or the third direction.

43. The manufacturing method according to claim 42, characterized in that, The capacitor structure includes: a first electrode, and a fifth dielectric layer and a second electrode surrounding the first electrode; the fifth dielectric layer is located between the first electrode and the second electrode.

44. The manufacturing method according to claim 41, characterized in that, The manufacturing method of the memory device includes: Providing a second semiconductor structure; bonding the second semiconductor structure and the first semiconductor structure on a side of the capacitor structure away from the bit line.

45. The manufacturing method according to claim 44, characterized in that, The manufacturing method further includes: Forming a first interconnection layer and a pad on a surface of the second semiconductor structure away from the first semiconductor structure, and the first interconnection layer and the pad are coupled to the second semiconductor structure.

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