Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device includes a channel structure including a first side portion and a second side portion arranged along a first direction; the connecting part is connected to the first end parts, in the second direction, of the first side part and the second side part; the first dielectric layer is located on the surfaces, opposite to each other, of the first side part and the second side part; the gate layer is located on the surface of the first dielectric layer and extends in the third direction; wherein the first direction, the second direction and the third direction intersect with one another.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In the iterative development process of semiconductor devices (e.g., DRAM memories), it is desired to have a smaller planar footprint and a higher unit storage density. However, the existing process technologies impose limitations on the above design requirements, making it difficult to obtain semiconductor devices with a small planar footprint and a high unit storage density. Summary of the Invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems existing in the related art or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a channel structure including a first side portion and a second side portion arranged along a first direction; and a connecting portion connecting the first ends of the first side portion and the second side portion in a second direction; a first dielectric layer located on the surfaces of the first side portion and the second side portion facing away from each other; and a gate layer located on the surface of the first dielectric layer and extending along a third direction; wherein the first direction, the second direction, and the third direction intersect with each other.

[0005] In some embodiments, the channel structures are arranged at intervals in the first direction, and the connecting portions in each channel structure are not connected to each other.

[0006] In some embodiments, along the direction opposite to the second direction, the distance between the first side portion and the second side portion in the first direction gradually increases.

[0007] In some embodiments, on a plane perpendicular to the second direction, the surfaces of the gate layer close to the first side portion and the second side portion are concave-convex shaped.

[0008] In some embodiments, the semiconductor device further includes: a shielding structure located between the first side portion and the second side portion, including: a conductive structure extending along the third direction; and a second dielectric layer located between the conductive structure and the first side portion, and between the conductive structure and the second side portion.

[0009] In some embodiments, along the direction opposite to the second direction, the size of the conductive structure in the first direction gradually increases.

[0010] In some embodiments, the material of the conductive structure is polysilicon or amorphous silicon.

[0011] In some embodiments, the second dielectric layer is also located on the end face of the conductive structure facing away from the connecting portion.

[0012] In some embodiments, the semiconductor device further includes: a first isolation structure, located between the first side portion and the second side portion, and on the side of the conductive structure facing away from the connecting portion; and a second isolation structure, located between the connecting portion and the conductive structure, and on the side of the conductive structure close to the connecting portion.

[0013] In some embodiments, the material of the second isolation structure is a non-silicon oxide material.

[0014] In some embodiments, the non-silicon oxide material is silicon nitride.

[0015] In some embodiments, the semiconductor device further includes: a capacitor connection structure, respectively connected to the second ends of the first side portion and the second side portion facing away from the connecting portion.

[0016] In some embodiments, the channel structure further includes extension portions located at the second ends, the extension portions respectively extend along the first direction and away from the first side portion and the second side portion, and are respectively in contact with the capacitor connection structure.

[0017] In some embodiments, the gate layer includes a first bonding layer and a metal layer that are bonded to each other, the first bonding layer is in contact with the first dielectric layer, and extends to the end face of the metal layer close to the capacitor connection structure.

[0018] In some embodiments, the semiconductor device further includes: an outer electrode layer, located on the side of the capacitor connection structure facing away from the channel structure; an inner electrode, located in the outer electrode layer; and an insulating layer, located between the outer electrode layer and the inner electrode; wherein, the capacitor connection structure is connected to the inner electrode.

[0019] In some embodiments, the inner electrode is a columnar structure and at least partially penetrates the outer electrode layer; wherein, along the direction opposite to the second direction, the size of the inner electrode in the plane perpendicular to the second direction gradually decreases.

[0020] In some embodiments, the semiconductor device further includes: a bit line, extending along the first direction and connected to the connecting portion.

[0021] In some embodiments, the first side portion, the second side portion and the connecting portion are an integral structure.

[0022] In some embodiments, the materials of the first side portion, the second side portion and the connecting portion include metal oxide semiconductor.

[0023] In some embodiments, the metal oxide semiconductor is indium gallium zinc oxide (IGZO).

[0024] In some embodiments, the dimensions of the first side portion and the second side portion in the first direction are 3 - 10 nm respectively.

[0025] In some embodiments, the channel structures are arranged at intervals in the third direction, and the semiconductor device further includes: a third isolation structure located between adjacent channel structures, wherein the material of the third isolation structure is silicon nitride.

[0026] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes: a memory including the semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory for controlling the memory to store data.

[0027] In a third aspect, some embodiments of the present application provide a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device includes: forming a support structure extending along the third direction, wherein the support structure has a first side wall and a second side wall facing away from each other in the first direction, and an end face in the second direction; forming an initial channel structure covering the first side wall, the second side wall, and the end face, and forming an initial first dielectric layer on the surface of the initial channel structure; discontinuously removing a part of the initial channel structure and a part of the initial first dielectric layer in the third direction to form a plurality of channel structures; forming a gate layer extending along the third direction on the surface of the initial first dielectric layer facing away from the first side wall and the second side wall; and removing a part of the initial first dielectric layer corresponding to the end face to expose the channel structures; wherein the first direction, the second direction, and the third direction intersect with each other.

[0028] In some embodiments, forming a support structure extending along the third direction includes: forming a first isolation structure, a conductive structure, and a second isolation structure arranged in sequence along the second direction, wherein the first isolation structure, the conductive structure, and the second isolation structure all extend along the third direction; and forming a second dielectric layer on the side walls of the conductive structure facing away from each other in the first direction to form the support structure.

[0029] In some embodiments, forming a support structure extending along the third direction includes: etching a sacrificial layer to form a trench extending along the third direction, wherein a first isolation structure is formed at the bottom of the trench; forming a second dielectric layer on the side walls of the trench and the top surface of the first isolation structure, and forming a conductive structure inside the second dielectric layer; and forming a second isolation structure on the top of the trench to form the support structure.

[0030] In some embodiments, before forming a support structure extending along the third direction, the manufacturing method further includes: forming an outer electrode layer on one side of the substrate; forming a plurality of inner electrodes in the outer electrode layer; and respectively forming a plurality of insulating layers between the outer electrode layer and the plurality of inner electrodes.

[0031] In some embodiments, the manufacturing method further includes: forming a capacitive dielectric layer covering a plurality of inner electrodes and a plurality of insulating layers; and forming a plurality of capacitive connection structures penetrating the capacitive dielectric layer and respectively connected to the plurality of inner electrodes, wherein at least part of the support structure is located between the capacitive connection structures adjacent in a first direction.

[0032] In some embodiments, in the first direction, adjacent support structures are spaced apart by two capacitive connection structures; wherein forming an initial channel structure covering a first sidewall, a second sidewall, and an end face, and forming an initial first dielectric layer on the surface of the initial channel structure includes: forming an initial channel structure on the surfaces of the capacitive dielectric layer and the capacitive connection structures; wherein discontinuously removing a part of the initial channel structure and a part of the initial first dielectric layer in a third direction to form a plurality of channel structures further includes: removing at least a part of the surface of the initial channel structure covering the capacitive dielectric layer and the capacitive connection structures, so that the initial channel structure covering the capacitive connection structures is disconnected in the first direction.

[0033] In some embodiments, removing at least a part of the surface of the initial channel structure covering the capacitive dielectric layer and the capacitive connection structures, so that the initial channel structure covering the capacitive connection structures is disconnected in the first direction includes: making the remaining initial channel structure cover the surface of the capacitive connection structures.

[0034] In some embodiments, after removing a part of the initial first dielectric layer corresponding to the end face to expose the channel structure, the manufacturing method further includes: forming a bit line connected to a part of the channel structure corresponding to the end face, wherein the bit line extends in the first direction.

[0035] In some embodiments, the material of the channel structure includes metal oxide semiconductor.

[0036] In some embodiments, forming an initial channel structure covering a first sidewall, a second sidewall, and an end face includes: forming the initial channel structure by a thin film deposition process.

[0037] According to at least one embodiment of the present application, the semiconductor device, the memory system, and the manufacturing method of the semiconductor device provided by the present application, the channel structure includes a first side portion and a second side portion arranged in a first direction, and a first end portion connecting the first side portion and the second side portion in a second direction. Using the first side portion and the second side portion as the channels of the transistor respectively can make the transistor structure more compact, effectively reduce the planar occupation area, improve the storage density, and is also beneficial to improving the iterative miniaturization ability of the feature size of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of the non-limiting embodiments with reference to the following drawings. Among them:

[0039] Figure 1A and Figure 1B are schematic structural diagrams of semiconductor devices provided by embodiments of the present application;

[0040] Figure 2 is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application;

[0041] Figure 3 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0042] Figure 4 is a schematic flow diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0043] Figures 5A to 5K is a schematic structural diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application; and

[0044] Figures 6A to 6K is a schematic structural diagram of a semiconductor device during the manufacturing process provided by another embodiment of the present application. Detailed Description of the Embodiments

[0045] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another feature and do not represent any limitation on the feature, especially not any order. Therefore, without departing from the teachings of the present application, the first side portion discussed in the present application may also be referred to as the second side portion, and vice versa.

[0047] In the accompanying drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation and not as terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0048] It should also be understood that expressions such as "including", "comprising", "having", "containing" and / or "comprising of" in this specification are open-ended rather than closed-ended expressions, which mean the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just an individual element in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0049] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It should also be understood that unless clearly stated in this application, words defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0050] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments may be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the recorded order, but may be executed in any order or executed in parallel.

[0051] In addition, when using "connected" or "coupled" in this application, it may mean direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0052] The present application will be described in detail below with reference to the drawings and in conjunction with embodiments.

[0053] Figure 1A and Figure 1B are schematic structural diagrams of semiconductor devices provided by embodiments of the present application.

[0054] Among them, Figure 1A is a perspective schematic diagram of the semiconductor device 100. Figure 1B is a partial cross-sectional schematic diagram of the semiconductor device 100. For example, the semiconductor device 100 may be a part of a dynamic random access memory (DRAM).

[0055] It should be noted that hereinafter, the directions D1, D2, and D3 in the respective drawings illustrate the spatial relationships of the components in the semiconductor device. For example, the D2 direction is the direction in which the capacitor faces the transistor, and the D1 direction and the D3 direction are two directions that intersect (e.g., are perpendicular) to each other in a plane intersecting (e.g., perpendicular) to the D2 direction. For example, the D1 direction is the bit line direction, and the D3 direction is the word line direction. The same concept will be adopted throughout this application to describe the spatial relationships of the components in the semiconductor device.

[0056] As Figure 1A and Figure 1B shown, the semiconductor device 100 includes a channel structure 111. Among them, the channel structure 111 includes a first side portion 1111, a second side portion 1112, and a connecting portion 1113. The first side portion 1111 and the second side portion 1112 are arranged in the D1 direction, and the connecting portion 1113 is connected to the first ends of the first side portion 1111 and the second side portion 1112 in the D2 direction.

[0057] In some embodiments, the first side portion 1111 and the second side portion 1112 may extend respectively in the plane formed by the D2 direction and the D3 direction. Among them, the two ends of the first side portion 1111 and the second side portion 1112 in the D2 direction may be the first end and the second end respectively. The extension dimensions of the first side portion 1111 and the second side portion 1112 in the D2 direction or the D3 direction may be greater than their dimensions in the D1 direction. For example, the first side portion 1111 and the second side portion 1112 may have substantially the same dimensions (e.g., the error is less than ±10%), and viewed from the D1 direction, the first side portion 1111 and the second side portion 1112 overlap. The first side portion 1111 and the second side portion 1112 may be substantially flat. For example, the dimensions of the first side portion 1111 and the second side portion 1112 in the D1 direction may be 3 - 10 nm respectively.

[0058] In some embodiments, the connecting portion 1113 may extend in the plane formed by the D1 direction and the D3 direction, and the extension dimensions of the connecting portion 1113 in the D1 direction and the D3 direction may be greater than its dimension in the D2 direction. The connecting portion 1113 may be substantially flat. For example, the dimension of the connecting portion 1113 in the D3 direction may be the same as the dimensions of the first side portion 1111 and the second side portion 1112 in the D3 direction, the dimension of the connecting portion 1113 in the D1 direction may be the spacing distance between the first side portion 1111 and the second side portion 1112 in the D1 direction, and the dimension of the connecting portion 1113 in the D2 direction may be the same as the dimensions of the first side portion 1111 and the second side portion 1112 respectively in the D1 direction. For example, viewed from the D3 direction, the first side portion 1111, the second side portion 1112, and the connecting portion 1113 may be substantially in an inverted U shape, and the connecting portion 1113 may serve as the closed end of the inverted U-shaped structure.

[0059] In some embodiments, the channel structure 111 may further include an extension portion 1114 located at the second end. The extension portion 1114 extends along the D1 direction and away from the first side portion 1111 and the second side portion 1112, respectively. For example, the extension portion 1114 may be substantially parallel to the connecting portion 1113. The extension dimension of the extension portion 1114 in the D3 direction may be the same as the extension dimensions of the first side portion 1111, the second side portion 1112, and the connecting portion 1113 in the D3 direction, respectively, and the dimension of the extension portion 1114 in the D2 direction may be the same as the dimension of the connecting portion 1113 in the D2 direction and the dimensions of the first side portion 1111 and the second side portion 1112 in the D1 direction, respectively.

[0060] In some embodiments, along the direction opposite to the second direction D2, the spacing distance between the first side portion 1111 and the second side portion 1112 in the D1 direction gradually increases. For example, at a position close to the connecting portion 1113, the spacing distance d2 between the first side portion 1111 and the second side portion 1112 in the D1 direction may be smaller than the spacing distance d1 between the first side portion 1111 and the second side portion 1112 in the D1 direction at a position far from the connecting portion 1113.

[0061] In some embodiments, the first side portion 1111, the second side portion 1112, and the connecting portion 1113 may be an integral structure. For example, the first side portion 1111, the second side portion 1112, and the connecting portion 1113 (i.e., the channel structure 111) may be formed by the same process (e.g., a thin film deposition process). The specific formation method of the channel structure 111 will be described in detail below. For example, when the materials of the first side portion 1111, the second side portion 1112, and the connecting portion 1113 are the same, there is no obvious boundary between the three. Exemplarily, the materials of the first side portion 1111, the second side portion 1112, and the connecting portion 1113 (i.e., the channel structure 111) may include one or more of semiconductor materials such as polycrystalline silicon (Poly-Si), amorphous silicon (α-Si), metal oxide semiconductors (e.g., indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO)). When the material of the channel structure 111 is a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), the channel leakage current can be significantly reduced, the data retention characteristics can be improved, and a better sense margin can also be achieved. Optionally, the extension portion 1114, as a part of the channel structure 111, may have the same material as the first side portion 1111, the second side portion 1112, and the connecting portion 1113.

[0062] In some embodiments, multiple channel structures 111 may be arranged in an array in the D1 direction and the D2 direction. Exemplarily, the channel structures 111 may be spaced apart in the D1 direction, and the connecting portions 1113 in each of the channel structures 111 are not connected to each other. Exemplarily, the channel structures 111 may also be spaced apart in the D3 direction. Wherein, the semiconductor device 100 may further include a third isolation structure 122 (for example, Figure 5F the third isolation structure 522 shown). The third isolation structure 122 may be located between the channel structures 111 adjacent in the D3 direction. For example, viewed from the D3 direction, each third isolation structure 122 may be generally inverted U-shaped. The size of the third isolation structure 122 in the D1 direction may be greater than the size of the channel structure 111 in the D1 direction. For example, the material of the third isolation structure 122 may be silicon nitride (Si 3 N 4 ). Continuing to refer to Figure 1A and Figure 1B , the semiconductor device 100 further includes a first dielectric layer 112 located on the surfaces of the first side portion 1111 and the second side portion 1112 facing away from each other. In some embodiments, the first dielectric layer 112 may extend in a plane formed by the D2 direction and the D3 direction. For example, the first dielectric layer 112 and the first side portion 1111 and the second side portion 1112 have the same size in the D3 direction. In the D2 direction, the size of the first dielectric layer 112 is smaller than the sizes of the first side portion 1111 and the second side portion 1112. Exemplarily, the material of the first dielectric layer 112 may include one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), high-k dielectric materials, or any other suitable insulating materials. For example, the material of the first dielectric layer 112 may be a high-k dielectric material such as aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ).

[0063] In the semiconductor device 100, a gate layer 113 is further included. The gate layer 113 is located on the surface of the first dielectric layer 112 and extends in the D3 direction (e.g., continuously extends). For example, the gate layer 113 may be located on the surface of the first dielectric layer 112 of a column of channel structures 111 arranged in the D3 direction. In some examples, the gate layer 113 may include a first adhesive layer 1131 and a metal layer 1132 that are attached to each other. The first adhesive layer 1131 is in direct contact with the first dielectric layer 112 and extends to the end face of the metal layer 1132 close to the capacitor connection structure 114. The capacitor connection structure 114 will be described in detail below. For example, viewed from the D3 direction, the first adhesive layer 1131 may be generally L-shaped, and the portion of the first adhesive layer 1131 extending to the end face of the metal layer 1132 is closer to the second end portions of the first side portion 1111 and the second side portion 1112. A part of the first adhesive layer 1131 is located between the metal layer 1132 and the first dielectric layer 112, which helps to improve the bonding performance between the metal layer 1132 and the first dielectric layer 112. Exemplarily, the material of the first adhesive layer 1131 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. The material of the metal layer 1132 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. In other examples, the gate layer 113 may not have a composite structure but is composed of a single conductive material, and the present application does not make specific limitations thereon.

[0064] In some embodiments, in a plane perpendicular to the D2 direction, the surface of the gate layer 113 (e.g., Figure 5I the illustrated gate layer 513) close to the first side portion 1111 and the second side portion 1112 is concave-convex shaped. For example, viewed from the D2 direction, the surface of the gate layer 113 in contact with the first dielectric layer 112 and the third isolation structure 122 is concave-convex shaped, wherein the surface of the gate layer 113 in contact with the first dielectric layer 112 is convex, and the surface in contact with the third isolation structure 122 is concave. Since the third isolation structure 122 is located between the channel structures 111 adjacent in the D3 direction, the surface of the gate layer 113 has a concave-convex shape.

[0065] As described above, in some embodiments, the first side portion 1111 (or the second side portion 1112), the first dielectric layer 112, and the portion of the gate layer 113 corresponding to the first side portion 1111 (or the second side portion 1112) can form a transistor. In the transistor, the first side portion 1111 (or the second side portion 1112) can serve as the channel, the portion of the gate layer 113 corresponding to the first side portion 1111 (or the second side portion 1112) can serve as the gate, and both ends of the first side portion 1111 (or the second side portion 1112) (i.e., the first end portion and the second end portion) can respectively serve as one of the source and the drain. Two transistors respectively including the first side portion 1111 and the second side portion 1112 can be mirror-distributed with respect to the connection portion 1113. The gate layer 113 extending in the D3 direction can be used to control a column of transistors arranged in the D3 direction. Each transistor can be a part of a DRAM memory cell.

[0066] According to the semiconductor device provided in the above embodiments of the present application, the channel structure includes a first side portion and a second side portion arranged along a first direction, and a first end portion connecting the first side portion and the second side portion in a second direction. By using the first side portion and the second side portion as the channels of the transistors respectively, the transistor structure can be made more compact, effectively reducing the planar occupation area, improving the storage density, and also being beneficial to improving the iterative miniaturization ability of the feature size of the semiconductor device.

[0067] In some embodiments, the semiconductor device 100 may further include a capacitor connection structure 114. The capacitor connection structure 114 can be respectively connected to the second end portions of the first side portion 1111 and the second side portion 1112. That is to say, the second end portion of the first side portion 1111 is connected to one capacitor connection structure 114, and the second end portion of the second side portion 1112 is connected to another capacitor connection structure 114. The two capacitor connection structures 114 are electrically isolated from each other. For example, the capacitor connection structure 114 can be generally columnar. Exemplarily, the material of the capacitor connection structure 114 may include tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), metal silicide (e.g., titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ), nickel platinum silicide (NiPtSi)) or one or more of any other suitable conductive materials. Optionally, in the case where the channel structure 111 has an extension portion 1114, the extension portion 1114 can be in direct contact with the capacitor connection structure 114 to increase the contact area between the two, improve the transmission efficiency, and ensure the electrical connection reliability.

[0068] In some embodiments, the semiconductor device 100 may further include an outer electrode layer 115, an insulating layer 116, and an inner electrode 117. The outer electrode layer 115 is disposed on a side of the capacitive connection structure 114 facing away from the channel structure 111. The inner electrode 117 is located in the outer electrode layer 115 and is connected to the capacitive connection structure 114 (e.g., in direct contact). For example, the inner electrode 117 may be generally columnar in structure and at least partially penetrate the outer electrode layer 115. Wherein, along a direction opposite to the D2 direction, the size (e.g., diameter) of the inner electrode 117 in a plane perpendicular to the D2 direction gradually decreases. The insulating layer 116 is located between the outer electrode layer 115 and the inner electrode 117. For example, the insulating layer 116 may be generally barrel-shaped with one end open, the inner electrode 117 is located in the insulating layer 116, and the open end of the insulating layer 116 faces the capacitive connection structure 114 so that the inner electrode 117 is in direct contact with the capacitive connection structure 114. Exemplarily, the materials of the outer electrode layer 115 and the inner electrode 117 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. The material of the insulating layer 116 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials.

[0069] According to the above description, in some embodiments, the inner electrode 117, the insulating layer 116, and the outer electrode layer 115 may form a capacitor. One electrode of the capacitor (e.g., the inner electrode 117) is connected to one of the source or drain of the transistor (e.g., the second end of the first side portion 1111 or the second side portion 1112) through the capacitive connection structure 114. The transistor and the capacitor may form a memory cell (e.g., a DRAM memory cell). The other electrodes (e.g., the outer electrode layer 115) of multiple capacitors may be connected to each other.

[0070] It should be noted that the capacitor may also be implemented as other structural types. For example, the capacitor may be composed of conductive layers, insulating layers, and conductive layers (not shown) stacked in the D2 direction in sequence. The present application does not specifically limit the structure of the capacitor, and the capacitor may be implemented as any known structural type in the art.

[0071] In some embodiments, the semiconductor device 100 may further include bit lines 118. The bit lines 118 extend along the D1 direction and are connected (e.g., in direct contact) to the connection portions 1113. The bit lines 118 may be connected to each of the connection portions 1113 in a row of channel structures 111 arranged along D1. Thus, one of the source or drain electrodes of a row of transistors arranged along the D1 direction is connected to the same bit line 118. The number of bit lines 118 may be multiple, and the multiple bit lines 118 may be arranged along the D3 direction. Exemplarily, the material of the bit lines 118 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0072] In some embodiments, the semiconductor device 100 may further include a shielding structure 119. Among them, the shielding structure 119 may be located between the first side portion 1111 and the second side portion 1112, and the shielding structure 119 may include a conductive structure 1191 and a second dielectric layer 1192. The conductive structure 1191 may extend along the D3 direction (e.g., continuously). The second dielectric layer 1192 may be located between the conductive structure 1191 and the first side portion 1111, and between the conductive structure 1191 and the second side portion 1112. For example, along the direction opposite to the D2 direction, the size of the conductive structure 1191 gradually increases in the D1 direction. Also for example, the second dielectric layer 1192 may extend along the D3 direction (e.g., continuously), and two second dielectric layers 1192 may be respectively located on two sidewalls of the conductive structure 1191 in the D1 direction and are respectively in direct contact with the first side portion 1111 and the second side portion 1112. Exemplarily, the material of the conductive structure 1191 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), amorphous silicon (α-Si), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material, and the material of the second dielectric layer 1192 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), high-k materials, or any other suitable insulating materials. For example, the conductive structure 1191 may be prepared using doped polysilicon (Poly-Si) or doped amorphous silicon (α-Si). The shielding structure 119 may be located on the back side of the channel of the transistor (the side without a gate). For example, by applying a voltage (e.g., a ground voltage) to the shielding structure 119, the coupling effect between adjacent transistors can be improved, and it also helps to reduce the off-state current I offand the subthreshold voltage swing, and adjust the threshold voltage V of the transistor t , thereby comprehensively optimizing the electrical performance of the transistor.

[0073] In some embodiments, the semiconductor device 100 may further include a first isolation structure 120 and a second isolation structure 121. The first isolation structure 120 is located between the first side portion 1111 and the second side portion 1112, and is located on a side of the conductive structure 1191 facing away from the connection portion 1113. The second isolation structure 121 is located between the connection portion 1113 and the conductive structure 1191, and is located on a side of the conductive structure 1191 close to the connection portion 1113. For example, in the D2 direction, the size of the second dielectric layer 1192 may be larger than the size of the conductive structure 1191. The first isolation structure 120 may be located in a space surrounded by the second dielectric layer 1192 and the conductive structure 1191, and a surface thereof facing away from the connection portion 1113 is substantially flush with a surface of the extension portion 1114 facing away from the connection portion 1113 (for example, the error is less than ±10%). The second isolation structure 121 may be located in a space surrounded by the second dielectric layer 1192, the conductive structure 1191, and the connection portion 1113. Exemplarily, the material of the first isolation structure 120 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials. The material of the second isolation structure 121 may be a non-silicon oxide material. In other words, the second isolation structure 121 may be prepared from a material having a different etching selectivity ratio with respect to the same etching material as silicon oxide (SiO 2 ). For example, the material of the second isolation structure 121 may be silicon nitride (Si 3 N 4 ). The first isolation structure 120 and the second isolation structure 121 may be used to adjust the size of the conductive structure 1191 in the D2 direction to match the size of the gate layer 113 in the D2 direction. In addition, the second isolation structure 121 may also be used to electrically isolate the conductive structure 1191 and the connection portion 1113.

[0074] Figure 2 is a schematic structural diagram of a semiconductor device provided in another embodiment of the present application. Among them, Figure 2 Some components of the semiconductor device 200 are omitted for illustration. For the purpose of concise description, the same content as in the previous embodiment will not be repeated herein.

[0075] As Figure 2As shown, in the semiconductor device 200, the shielding structure 219 may be located between the first side portion 2111 and the second side portion 1112, and the shielding structure 219 may include a conductive structure 2191 and a second dielectric layer 2192. The conductive structure 2191 may extend in the D3 direction (e.g., continuously extend). The second dielectric layer 2192 may be located between the conductive structure 2191 and the first side portion 2111, and between the conductive structure 2191 and the second side portion 2112, and the second dielectric layer 2192 is also located on the end face of the conductive structure 2191 facing away from the connection portion 2113. For example, viewed from the D3 direction, the second dielectric layer 2192 may be generally U-shaped and extend in the D3 direction (e.g., continuously extend). The conductive structure 2191 is located in the space surrounded by the second dielectric layer 2192, and its surface close to the connection portion 2113 is substantially flush with the surface of the second dielectric layer 2192 close to the connection portion 2113 (e.g., the error is less than ±10%). Optionally, the conductive structure 2191 may include a second adhesive layer 21911 and a metal structure 21912. For example, viewed from the D3 direction, the second adhesive layer 21911 may be generally U-shaped, and the metal structure 21912 may be located in the space surrounded by the second adhesive layer 21911. Exemplarily, the material of the second adhesive layer 21911 may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any other suitable material. For example, the material of the metal structure 21912 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other suitable metal material. The second adhesive layer 21911 helps to improve the bonding performance between the metal structure 21912 and the second dielectric layer 2192. As another option, the conductive structure 2191 may not have a composite structure but be composed of a single conductive material, and the present application does not make specific limitations in this regard.

[0076] It should be noted that although the shielding structure 119 or 219 has been described in detail above, one or more insulating materials may be filled in the space surrounded by the channel structure to electrically isolate the first side portion 1111 or 2111 from the second side portion 1112 or 2112, and the present application does not make specific limitations in this regard.

[0077] An embodiment of the present application also provides a memory system. Figure 3 is a block diagram of a system having a memory system provided by an embodiment of the present application.

[0078] As Figure 3As shown, the system 300 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (which has a memory system 310 located therein). As Figure 3 As shown, the system 300 can include a host 320 and a memory system 310. The memory system 310 has one or more memories 311 and a controller 312. The host 320 can be a processor of the electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 320 can be configured to send or receive data to and from the memory 311.

[0079] In some embodiments, the controller 312 is coupled to the memory 311 and the host 320 and is configured to control the memory 311. For example, the controller 312 can be configured to control the memory 311 to perform operations such as reading, erasing, and programming. The controller 312 can also manage the data stored in the memory 311 and communicate with the host 320. For example, the controller 312 can communicate with an external device (e.g., the host 320) according to a specific communication protocol.

[0080] The embodiment of the present application also provides a manufacturing method of a semiconductor device. Figure 4 is a flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present application. As Figure 4 As shown, the manufacturing method 400 of the semiconductor device (hereinafter simply referred to as the manufacturing method 400) can include the following steps.

[0081] S410, form a support structure extending in the third direction, where the support structure has a first sidewall and a second sidewall facing away from each other in the first direction, and an end face in the second direction.

[0082] S420, form an initial channel structure covering the first sidewall, the second sidewall, and the end face, and form an initial first dielectric layer on the surface of the initial channel structure.

[0083] S430, discontinuously remove part of the initial channel structure and part of the initial first dielectric layer in the third direction to form a plurality of channel structures.

[0084] S440, form a gate layer extending in the third direction on the surface of the initial first dielectric layer facing away from the first sidewall and the second sidewall.

[0085] S450, remove a part of the initial first dielectric layer corresponding to the end face to expose the channel structure.

[0086] According to the manufacturing method of the semiconductor device provided by this embodiment, first, an initial channel structure covering the first sidewall, the second sidewall, and the end face of the support structure is formed, and an initial first dielectric layer is formed on the surface of the initial channel structure. Next, part of the initial channel structure and part of the initial first dielectric layer are intermittently removed in the third direction to form a plurality of channel structures. Among them, the part of the channel structure covering the first sidewall and the second sidewall can be used as the channel of the transistor, which can make the transistor structure more compact, effectively reduce the planar occupation area, improve the storage density, and is also conducive to improving the iterative miniaturization ability of the feature size of the semiconductor device.

[0087] Figures 5A to 5K It is a schematic structural diagram of the semiconductor device provided by the embodiment of the present application during the manufacturing process. For example, the intermediate structures during the manufacturing process of the semiconductor device in this embodiment can be formed according to Figure 4 the manufacturing method shown, and are used to form Figure 1A and Figure 1B the semiconductor device 100 shown. The following combines Figures 5A to 5K and Figure 4 to illustrate the above steps S410 to S450.

[0088] S410

[0089] Figure 5A It shows an intermediate structure 500a including a substrate 531, an outer electrode layer 515, an insulating layer 516, an inner electrode 517, a capacitive dielectric layer 532, and a capacitive connection structure 514.

[0090] In some embodiments, before forming the support structure 533 (refer to Figure 5C ), the manufacturing method 400 may further include the following steps. First, as Figure 5AAs shown, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to form an outer electrode layer 515 on one side of a substrate 531. For example, the material of the substrate 531 can be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). As another example, the substrate 531 can be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc. Next, a via hole (not shown, the via hole corresponding to the outer contour of the insulating layer 516) penetrating the outer electrode layer 515 can be formed by a photolithography and etching process (e.g., dry etching and / or wet etching). Then, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form an insulating layer 516 on the inner wall of the via hole, and an inner electrode 517 can be formed in the insulating layer 516. For example, the number of via holes can be multiple and arranged in an array in the D1 direction and the D3 direction. As described above, an inner electrode 517, an insulating layer 516, and a part of the outer electrode layer 515 outside the insulating layer 516 can constitute a capacitor. It should be noted that since the via hole is etched in a direction opposite to the D2 direction (e.g., a direction towards the substrate 531), in the direction opposite to the D2 direction, the size (e.g., diameter) of the via hole and the inner electrode 517 in the via hole gradually decreases in a plane perpendicular to the D2 direction. In addition, any known method in the art can also be used to form capacitors of different structural types.

[0091] In some embodiments, first, a capacitive dielectric layer 532 covering multiple inner electrodes 517 and multiple insulating layers 516 can be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the capacitive dielectric layer 532 can be formed on a side of the outer electrode layer 515 facing away from the substrate 531. The material of the capacitive dielectric layer 532 can include one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Then, a plurality of capacitive connection structures 514 penetrating the capacitive dielectric layer 532 and respectively connected to the multiple inner electrodes 517 can be formed by a photolithography and etching process (e.g., dry etching and / or wet etching) and a thin film deposition process. For example, the capacitive connection structures 514 correspond to the inner electrodes 517 one by one.

[0092] Figure 5BThe intermediate structure 500b after forming the first isolation structure 520, the conductive structure 5191, and the second isolation structure 521 is shown. Figure 5C The intermediate structure 500c after forming the second dielectric layer 5192, the initial channel structure 511', the initial first dielectric layer 512', and the first sacrificial layer 534 is shown.

[0093] In some embodiments, as Figure 5B shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a photolithography and etching (e.g., dry etching and / or wet etching) process can be used to form the first isolation structure 520, the conductive structure 5191, and the second isolation structure 521 sequentially arranged along the D2 direction. For example, the first isolation structure 520, the conductive structure 5191, and the second isolation structure 521 can be referred to as the initial support structure 533'. In one example, the step of forming the initial support structure 533' can include: first, a composite layer formed by sequentially stacking the materials of the first isolation structure 520, the conductive structure 5191, and the second isolation structure 521 can be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Then, the composite layer can be patterned by a photolithography and etching (e.g., dry etching and / or wet etching) process to form a plurality of initial support structures 533' spaced apart along the D1 direction. Optionally, when the material of the conductive structure 5191 is polycrystalline silicon (Poly-Si) or amorphous silicon (α-Si), the polycrystalline silicon (Poly-Si) or amorphous silicon (α-Si) can be doped, and an annealing (e.g., laser annealing) process can be used to activate the doping elements. For each initial support structure 533', it can extend along the D3 direction (e.g., continuously extend). For example, viewed from the D3 direction, the initial support structure 533' can be trapezoidal. It should be noted that since the trenches between adjacent initial support structures 533' are etched in a direction opposite to the D2 direction (e.g., the direction towards the substrate 531), along the direction opposite to the D2 direction, the size of the trench in the D1 direction gradually decreases, while the size of the remaining initial support structure 533' (or the conductive structure 5191) in the D1 direction gradually increases. Another example is that during the formation of the initial support structure 533', the layer where the second isolation structure 521 is located (not shown) can be used as a hard mask to prevent the conductive structure 5191 from being damaged.

[0094] Next, a second dielectric layer 5192 can be formed on the sidewalls of the initial support structure 533' that face away from each other in the D1 direction by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, as Figure 5CAs shown. In some examples, when the material of the conductive structure 5191 is polysilicon (Poly-Si) or amorphous silicon (α-Si), an oxidation method (e.g., dry oxidation method and / or wet oxidation method) can be used to form the second dielectric layer 5192 on the sidewalls of the conductive structure 5191 that face away from each other in the D1 direction. The first isolation structure 520, the second isolation structure 521, the conductive structure 5191, and the second dielectric layer 5192 can be referred to as the support structure 533. The support structure 533 can have a first sidewall 535 and a second sidewall 536 that face away from each other in the D1 direction and an end face 537 in the D2 direction. In addition, as described above, the conductive structure 5191 and the second dielectric layer 5192 can be referred to as a shielding structure to improve the coupling effect between adjacent transistors to be formed, which helps to reduce the off-state current I off and the subthreshold swing, and adjust the threshold voltage V t of the transistor, thereby comprehensively optimizing the electrical performance of the transistor.

[0095] In some embodiments, by designing the spacing distance of the support structure 533 in the D1 direction and the size of each support structure 533 in the D1 direction, at least part of the support structure 533 can be located between the capacitor connection structures 514 adjacent in the D1 direction. For example, the capacitor connection structures 514 adjacent in the D1 direction are symmetrically arranged with respect to the support structure 533. For another example, in the D1 direction, two capacitor connection structures 514 are spaced between adjacent support structures 533.

[0096] S420

[0097] Continuing to refer to Figure 5C , an initial channel structure 511' covering the first sidewall 535, the second sidewall 536, and the end face 537 can be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the thickness of the initial channel structure 511' relative to the surface it covers can be 3 - 10 nm. Further, an initial first dielectric layer 512' can be formed on the surface of the initial channel structure 511' by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Forming the initial channel structure 511' by a thin film deposition process and then forming the channel structure 511 in a subsequent process (refer to Figure 5G ), compared with an etching process, is beneficial to reducing the process control difficulty and provides greater possibilities for the iterative miniaturization of the feature size of semiconductor devices.

[0098] In some embodiments, when two capacitor connection structures 514 are spaced between adjacent support structures 533, the initial channel structure 511' can be formed on the surfaces of the capacitor dielectric layer 532 and the capacitor connection structures 514.

[0099] In some embodiments, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill a first sacrificial layer 534 between adjacent support structures 533 on which an initial channel structure 511' and an initial first dielectric layer 512' are formed. The material of the first sacrificial layer 534 may be different from that of the initial first dielectric layer 512'. For example, the material of the initial first dielectric layer 512' may be a high-k material, and the material of the first sacrificial layer 534 may be silicon oxide (SiO 2 ). Optionally, a chemical mechanical polishing (CMP) process may be used to planarize the first sacrificial layer 534 and expose the surface of the initial first dielectric layer 512' facing away from the capacitive connection structure 514.

[0100] S430

[0101] Figure 5D An intermediate structure 500d is shown after discontinuously removing a portion of the initial channel structure 511' and a portion of the initial first dielectric layer 512' in the D3 direction. Figure 5E An intermediate structure 500e is shown after forming the initial third isolation structure 522'. Figure 5F An intermediate structure 500f is shown after removing a portion of the initial third isolation structure 522'. Figure 5G An intermediate structure 500g is shown after forming the channel structure 511 and the second sacrificial layer 539.

[0102] As Figure 5C and 5D shown, a lithography and etching (e.g., wet etching and / or dry etching) process may be used to discontinuously remove a portion of the initial first dielectric layer 512' and a portion of the initial channel structure 511' in the D3 direction. Optionally, during this process, a portion of the first sacrificial layer 534 may be discontinuously removed. When the material of the first isolation structure 521 is silicon nitride (Si 3 N 4 ), and the material of the first sacrificial layer 534 is silicon oxide (SiO 2 ), it is possible to avoid the first isolation structure 521 from also being intermittently removed, which is beneficial for protecting the conductive structure 5191. For example, when there is a support structure 533 in the D1 direction, the remaining portion after discontinuously removing a portion of the initial channel structure 511' and a portion of the initial first dielectric layer 512' in the D3 direction may be the channel structure 511 (refer to Figure 5G ).

[0103] In some embodiments, as Figure 5D and Figure 5EAs shown, in the case of having a plurality of support structures 533 in the D1 direction, the following steps can be performed. First, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form an initial third isolation structure 522' in the space after discontinuously removing a part of the initial first dielectric layer 512', a part of the initial channel structure 511', and a part of the first sacrificial layer 534. The material of the initial third isolation structure 522' can be different from that of the first sacrificial layer 534. For example, the material of the initial third isolation structure 522' can be silicon nitride (Si 3 N 4 ).

[0104] In some embodiments, as shown in Figure 5E and Figure 5F , an etching process (e.g., wet etching) can be used to remove the first sacrificial layer 534, exposing the initial first dielectric layer 512'. Optionally, an etching process (e.g., dry etching) can be used to remove a part of the initial third isolation structure 522', so that the part of the initial third isolation structure 522' located between adjacent support structures 533 is disconnected in the D1 direction, thereby forming a third isolation structure 522. Further, as shown in Figure 5F and Figure 5G , a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a second sacrificial layer 539, and an etching process (e.g., dry etching) can be used to remove a part of the second sacrificial layer 539, so that the part of the second sacrificial layer 539 located between adjacent support structures 533 is disconnected in the D1 direction. The material of the second sacrificial layer 539 can include silicon oxide (SiO 2 ). For example, the second sacrificial layer 539 can be used to determine the size of the extension 5114 in the channel structure 511 in the D1 direction.

[0105] In step S430, continuing to refer to Figure 5G , an etching process (e.g., dry etching) can be used to remove at least a part of the initial first dielectric layer 512' and the initial channel structure 511' covering the surfaces of the capacitor dielectric layer 532 and the capacitor connection structure 514, so that the initial channel structure 511' covering the capacitor connection structure 514 is disconnected in the D1 direction, thereby forming a plurality of channel structures 511 arranged in an array in the D1 direction and the D2 direction. Optionally, during the formation of the channel structure 511, the remaining initial channel structure 511' can be made to cover the surface of the capacitor connection structure 514, that is, the part covering the surface of the capacitor connection structure 514 is the extension 5114 of the channel structure 511, so as to increase the electrical connection reliability between the channel structure 511 and the capacitor connection structure 514 and improve the transmission efficiency.

[0106] S440

[0107] Figure 5H Shows the intermediate structure 500h after the formation of the fourth isolation structure 540. Figure 5I Shows the intermediate structure 500i after the formation of the gate layer 513 and a part of the fifth isolation structure 541.

[0108] In some embodiments, before forming the gate layer 513, as Figure 5H shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof and an etching process may be used to form the fourth isolation structure 540 between adjacent support structures 533 and close to the capacitive connection structure 514. For example, the fourth isolation structure 540 can be used to provide a flat surface facing away from the capacitive connection structure 514 and electrically isolate the gate layer 513 (refer to Figure 5I ) to be formed and the channel structure 511.

[0109] In step S440, as Figure 5H and 5I shown, a gate layer 513 extending in the D3 direction is formed on the surface of the initial first dielectric layer 512' facing away from the first sidewall 535 and the second sidewall 536. Exemplarily, a first adhesion layer 5131 can be formed on the surface of the initial first dielectric layer 512' facing away from the first sidewall 535 and the second sidewall 536, the surface of the third isolation structure 522 facing away from the first sidewall 535 and the second sidewall 536, and the surface of the fourth isolation structure 540 facing away from the capacitive connection structure 514 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a metal layer 5132 is formed on the surface of the first adhesion layer 5131. Further, an etching (e.g., punching etching) process can be used to remove a part of the first adhesion layer 5131 and the metal layer 5132 located on the surface of the fourth isolation structure 540 to disconnect the first adhesion layer 5131 and the metal layer 5132 in the D1 direction, thereby forming the gate layer 513.

[0110] In some embodiments, an etching process can be used to remove a part of the gate layer 513 facing away from the capacitive connection structure 514 so that the dimensions of the gate layer 513 and the conductive structure 5191 match in the D2 direction. Optionally, a fifth isolation structure 541 can be formed in the space surrounded by the gate layer 513 and on the side of the gate layer 513 facing away from the fourth isolation structure 540 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof (refer to Figure 5J ). For example, the materials of the fourth isolation structure 540 and the fifth isolation structure 541 can be the same, and there is no obvious boundary between them. As another option, different insulating materials can be selected for the fourth isolation structure 540 and the fifth isolation structure 541, and the present application does not make specific limitations in this regard.

[0111] S450

[0112] Figure 5J shows the intermediate structure 500j after forming the first dielectric layer 512. As Figure 5I and 5J shown, etching (e.g., dry etching and / or wet etching) can be used to remove a portion of the initial first dielectric layer 512' corresponding to the end face 537 to expose the channel structure 511. Optionally, a portion of the initial first dielectric layer 512' located on the first sidewall 535 and the second sidewall 536 and close to the end face 537 can be further removed.

[0113] In some embodiments, the manufacturing method 400 may further include the step of forming bit lines. Figure 5K shows the semiconductor device 500 after forming the bit line 518 and the sixth isolation structure 542. As Figure 5K shown, a bit line 518 connected to a portion of the channel structure 511 corresponding to the end face 537 can be formed, where the bit line 518 can extend in the D1 direction (e.g., continuously extend). Exemplarily, on the top side of the intermediate structure 500j shown in Figure 5J the bit lines 518 and the sixth isolation structure 542 are alternately arranged in the D3 direction. The bit line 518 can be in direct contact with a row of channel structures 511 arranged in the D1 direction, and the sixth isolation structure 542 can be used to electrically isolate adjacent bit lines 518. For example, the size of the bit line 518 in the D3 direction can be the same as the size of each channel structure 511 in the D3 direction.

[0114] According to the manufacturing method of the semiconductor device provided in this embodiment, the transistor structure can be made more compact, effectively reducing the planar occupation area, improving the storage density, and also being conducive to improving the iterative miniaturization ability of the feature size of the semiconductor device. In addition, compared with the manufacturing method of forming a transistor first and then a capacitor, the manufacturing method of forming a capacitor first and then a transistor in the embodiments of the present application can omit processes such as backside thinning of the wafer, bonding of the carrier wafer, and backside processing to form bit lines, which can simplify the process and save manufacturing costs.

[0115] Figures 6A to 6K is a schematic structural diagram of a semiconductor device in the manufacturing process provided by another embodiment of the present application. For example, the intermediate structures in the manufacturing process of the semiconductor device in this embodiment can be formed according to the Figure 4 manufacturing method shown and used to form the Figure 2 semiconductor device 200 shown. The following combines Figures 6A to 6K and Figure 4 to illustrate the above steps S410 to S450. For the purpose of concise description, the same content as in the previous embodiment will not be repeated in this embodiment.

[0116] S410

[0117] Figures 6A to 6F Illustrates intermediate structures 600a to 600f of the support structure 633 during the manufacturing process. Figure 6G Illustrates intermediate structure 600g after removing the fourth sacrificial layer 645.

[0118] In some embodiments, first, as Figure 6A shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially form a first isolation layer 643 and a third sacrificial layer 644 on the surfaces of the capacitive dielectric layer 632 and the capacitive connection structure 614. Then, a lithography and etching (e.g., wet etching and / or dry etching) process can be used to pattern the third sacrificial layer 644 and the first isolation layer 643. After patterning, the third sacrificial layer 644 and the first isolation layer 643 are stacked in the D2 direction and extend (e.g., connect and extend) in the D3 direction, as Figure 6B shown. Among them, the patterned first isolation layer 643 can serve as the first isolation structure 620. The size of the first isolation structure 620 in the D2 direction can be used to determine the position of the shielding structure to be formed in the D2 direction. Next, as Figure 6C shown, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form a fourth sacrificial layer 645 on the outer periphery of the third sacrificial layer 644 and the first isolation structure 620. For example, the material of the fourth sacrificial layer 645 is different from that of the third sacrificial layer 644. As an example, the material of the fourth sacrificial layer 645 can be silicon oxide (SiO 2 ), and the material of the third sacrificial layer 644 can be polysilicon (Poly-Si) or amorphous silicon (α-Si). Further, an etching (e.g., wet etching) process can be used to remove the third sacrificial layer 644 to form a trench 646 that extends (e.g., continuously extends) in the D3 direction, as Figure 6D shown. For example, the first isolation structure 620 can be retained at the bottom of the trench 646. It should be noted that since Figure 6B the patterned third sacrificial layer 644 and the first isolation layer 643 shown are etched in a direction opposite to the D2 direction, in the direction opposite to the D2 direction, the sizes of the retained third sacrificial layer 644 and the first isolation layer 643 in the D1 direction gradually increase.

[0119] As another example, the steps shown in Figures 6A to 6C can be omitted, and the fourth sacrificial layer 645 shown in Figure 6D can be patterned to form a trench (not shown) that penetrates the fourth sacrificial layer 645 and extends (e.g., continuously extends) in the D3 direction. Then, a thin film deposition process can be used to form the first isolation structure 620 at the bottom of the trench. This application does not limit the above two specific process methods.

[0120] Further, in some embodiments, as Figure 6D and 6E shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially form a second dielectric layer 6192 and a second adhesion layer 61911 on the sidewalls of the trench 646 and the top surface of the first isolation structure 620, and a metal structure 61912 may be formed inside the second adhesion layer 61911 (e.g., in the enclosed space). Among them, the second adhesion layer 61911 and the metal structure 61912 may be referred to as a conductive structure. In other embodiments, after forming the second dielectric layer 6192, a conductive material may be directly filled inside the second dielectric layer 6192 (e.g., in the enclosed space) to form a conductive structure. In other words, the step of forming the second adhesion layer 61911 may be omitted, and the present application does not make specific limitations thereon. Next, as Figure 6E and Figure 6F shown, an etching process and a thin film deposition process may be used to remove a part of the second dielectric layer 6192, the second adhesion layer 61911, and the metal structure 61912 near the notch of the trench 646 (refer to Figure 6D ), and a second isolation structure 621 may be formed here. The first isolation structure 620, the second isolation structure 621, the conductive structure (e.g., the second adhesion layer 61911 and the metal structure 61912), and the second dielectric layer 6192 may be referred to as a support structure 633. In addition, as described above, the conductive structure (e.g., the second adhesion layer 61911 and the metal structure 61912) and the second dielectric layer 6192 may be referred to as a shielding structure, and the shielding structure can improve the coupling effect between adjacent transistors to be formed, and also helps to reduce the off-state current I off and the subthreshold swing, and adjust the threshold voltage V t of the transistor, thereby comprehensively optimizing the electrical performance of the transistor.

[0121] In some embodiments, an etching (e.g., wet etching) process may be used to remove the fourth sacrificial layer 645 to form an intermediate structure 600g as Figure 6G shown.

[0122] S420

[0123] Figure 6H shows an intermediate structure 600h for forming an initial channel structure 611' and an initial first dielectric layer 612'.

[0124] In this step, as Figure 6HAs shown, an initial channel structure 611' covering the first sidewall 635, the second sidewall 636, and the end face 637 of the support structure 633 can be formed, and an initial first dielectric layer 612' can be formed on the surface of the initial channel structure 611'.

[0125] S430

[0126] Figure 6I An intermediate structure 600i after forming the channel structure 611 is shown.

[0127] In this step, part of the initial channel structure 611' and part of the initial first dielectric layer 612' can be removed discontinuously in the D3 direction. In some embodiments, as Figure 6I shown, an etching (e.g., dry etching) process can be used to remove at least a part of the initial first dielectric layer 612' and the initial channel structure 611' covering the surface of the capacitive dielectric layer 632 and the capacitive connection structure 614, so that the initial channel structure 611' covering the capacitive connection structure 614 is disconnected in the D1 direction, thereby forming the channel structure 611.

[0128] S440

[0129] Figure 6J An intermediate structure 600j after forming the gate layer 613 is shown.

[0130] In this step, as Figure 6J shown, a gate layer 613 extending in the D3 direction (e.g., continuously extending) is formed on the surface of the initial first dielectric layer 612' facing away from the first sidewall 635 and the second sidewall 636.

[0131] S450

[0132] Figure 6K A semiconductor device 600 after forming the first dielectric layer 612 and the bit line 618 is shown.

[0133] In this step, as Figure 6J and 6K shown, an etching (e.g., dry etching and / or wet etching) can be used to remove a part of the initial first dielectric layer 612' corresponding to the end face 637 to expose the channel structure 611.

[0134] In some embodiments, a bit line 618 connected to the part of the channel structure 611 corresponding to the end face 637 can be formed, wherein the bit line 618 can extend in the D1 direction (e.g., continuously extending).

[0135] According to the manufacturing method of the semiconductor device provided by this embodiment, the transistor structure can be made more compact, effectively reducing the planar occupation area, improving the storage density, and also improving the iterative miniaturization ability of the feature size of the semiconductor device. In addition, the manufacturing method of forming the capacitor first and then the transistor can simplify the process and save the manufacturing cost.

[0136] It should be noted that although the process method of forming the support structure 533 or 633 is described in detail above, the support structure can be composed of one or more insulating materials, and any known process method in the art can be used to form the support structure extending along the D3 direction to provide support for the subsequently formed initial channel structure and the initial first dielectric layer. This application does not make specific restrictions on this.

[0137] The above description is only for the implementation mode of this application and the explanation of the applied technical principles. Those skilled in the art should understand that the protection scope involved in this application is not limited to the technical solution formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solution formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that, comprising: A channel structure, comprising: A first side portion and a second side portion arranged along a first direction; and A connecting portion connecting the first end portions of the first side portion and the second side portion in a second direction; A first dielectric layer located on the surfaces of the first side portion and the second side portion facing away from each other; and A gate layer located on the surface of the first dielectric layer and extending along a third direction; wherein the first direction, the second direction, and the third direction intersect with each other.

2. The semiconductor device according to claim 1, wherein, the channel structures are arranged at intervals in the first direction, and the connecting portions in each of the channel structures are not connected to each other.

3. The semiconductor device according to claim 1, wherein, along the direction opposite to the second direction, the distance between the first side portion and the second side portion in the first direction gradually increases.

4. The semiconductor device according to claim 1, wherein, on a plane perpendicular to the second direction, the surfaces of the gate layer close to the first side portion and the second side portion are concave-convex in shape.

5. The semiconductor device according to claim 1, further comprising: A shielding structure located between the first side portion and the second side portion, comprising: A conductive structure extending along the third direction; and A second dielectric layer located between the conductive structure and the first side portion, and between the conductive structure and the second side portion.

6. The semiconductor device according to claim 5, wherein, along the direction opposite to the second direction, the size of the conductive structure in the first direction gradually increases.

7. The semiconductor device according to claim 5, wherein, the material of the conductive structure is polysilicon or amorphous silicon.

8. The semiconductor device according to claim 5, wherein, the second dielectric layer is also located on the end face of the conductive structure facing away from the connecting portion.

9. The semiconductor device according to claim 5, further comprising: A first isolation structure located between the first side portion and the second side portion, and on the side of the conductive structure facing away from the connecting portion; and A second isolation structure located between the connecting portion and the conductive structure, and on the side of the conductive structure close to the connecting portion.

10. The semiconductor device according to claim 9, wherein, the material of the second isolation structure is a non-oxide silicon material.

11. The semiconductor device according to claim 10, wherein, the non-oxide silicon material is silicon nitride.

12. The semiconductor device according to claim 1, further comprising: A capacitor connection structure respectively connected to the second end portions of the first side portion and the second side portion facing away from the connecting portion.

13. The semiconductor device according to claim 12, wherein, the channel structure further includes extension portions located at the second end portions, and the extension portions respectively extend along the first direction and away from the first side portion and the second side portion, and are respectively in contact with the capacitor connection structure.

14. The semiconductor device according to claim 12, wherein, The gate layer includes a first adhesive layer and a metal layer that are attached to each other. The first adhesive layer is in contact with the first dielectric layer and extends to an end face of the metal layer close to the capacitor connection structure.

15. The semiconductor device according to claim 12, further comprising: An outer electrode layer located on a side of the capacitor connection structure facing away from the channel structure; An inner electrode located in the outer electrode layer; and An insulating layer located between the outer electrode layer and the inner electrode; wherein the capacitor connection structure is connected to the inner electrode.

16. The semiconductor device according to claim 15, wherein The inner electrode is a columnar structure and at least partially penetrates the outer electrode layer; wherein, along a direction opposite to the second direction, a dimension of the inner electrode in a plane perpendicular to the second direction gradually decreases.

17. The semiconductor device according to claim 1, further comprising: A bit line extending along the first direction and connected to the connection portion.

18. The semiconductor device according to claim 1, wherein The first side portion, the second side portion, and the connection portion are an integral structure.

19. The semiconductor device according to claim 1 or 18, wherein The materials of the first side portion, the second side portion, and the connection portion include metal oxide semiconductor.

20. The semiconductor device according to claim 19, wherein The metal oxide semiconductor is indium gallium zinc oxide.

21. The semiconductor device according to claim 1, wherein The dimensions of the first side portion and the second side portion in the first direction are 3 - 10 nm respectively.

22. The semiconductor device according to claim 1, wherein The channel structures are arranged at intervals in the third direction, and the semiconductor device further includes: A third isolation structure located between adjacent channel structures, wherein the material of the third isolation structure is silicon nitride.

23. A memory system, characterized in that it includes: A memory including the semiconductor device according to any one of claims 1 to 22; and A controller coupled to the memory for controlling the memory to store data.

24. A manufacturing method of a semiconductor device, characterized in that it includes: Forming a support structure extending along the third direction, wherein the support structure has a first side wall and a second side wall facing away from each other in the first direction, and an end face in the second direction; Forming an initial channel structure covering the first side wall, the second side wall, and the end face, and forming an initial first dielectric layer on a surface of the initial channel structure; Removing part of the initial channel structure and part of the initial first dielectric layer intermittently in the third direction to form a plurality of channel structures; Forming a gate layer extending along the third direction on a surface of the initial first dielectric layer facing away from the first side wall and the second side wall; and Removing a part of the initial first dielectric layer corresponding to the end face to expose the channel structure; wherein the first direction, the second direction, and the third direction intersect with each other.

25. The manufacturing method according to claim 24, wherein Forming a support structure extending in a third direction includes: Forming a first isolation structure, a conductive structure, and a second isolation structure arranged in sequence along the second direction, wherein the first isolation structure, the conductive structure, and the second isolation structure all extend along the third direction; and Forming a second dielectric layer on sidewalls of the conductive structure that face away from each other in the first direction to form the support structure.

26. The manufacturing method according to claim 24, wherein, Forming a support structure extending in a third direction includes: Etching a sacrificial layer to form a trench extending in the third direction, wherein a first isolation structure is formed at the bottom of the trench; Forming a second dielectric layer on sidewalls of the trench and on a top surface of the first isolation structure, and forming a conductive structure inside the second dielectric layer; and Forming a second isolation structure on top of the trench to form the support structure.

27. The manufacturing method according to claim 24, wherein, Before forming a support structure extending in a third direction, the manufacturing method further includes: Forming an outer electrode layer on one side of a substrate; Forming a plurality of inner electrodes in the outer electrode layer; and Forming a plurality of insulating layers respectively between the outer electrode layer and the plurality of inner electrodes.

28. The manufacturing method according to claim 27, wherein, The manufacturing method further includes: Forming a capacitive dielectric layer covering the plurality of inner electrodes and the plurality of insulating layers; and Forming a plurality of capacitive connection structures penetrating the capacitive dielectric layer and respectively connected to the plurality of inner electrodes, wherein at least a part of the support structure is located between the capacitive connection structures adjacent to each other in the first direction.

29. The manufacturing method according to claim 28, wherein, In the first direction, adjacent support structures are spaced apart by two of the capacitive connection structures; wherein forming an initial channel structure covering the first sidewall, the second sidewall, and the end face, and forming an initial first dielectric layer on a surface of the initial channel structure includes: Forming the initial channel structure on surfaces of the capacitive dielectric layer and the capacitive connection structures; wherein discontinuously removing a part of the initial channel structure and a part of the initial first dielectric layer in the third direction to form a plurality of channel structures further includes: Removing at least a part of the initial channel structure covering surfaces of the capacitive dielectric layer and the capacitive connection structures, so that the initial channel structure covering the capacitive connection structures is disconnected in the first direction.

30. The manufacturing method according to claim 28, wherein, Removing at least a part of the initial channel structure covering surfaces of the capacitive dielectric layer and the capacitive connection structures, so that the initial channel structure covering the capacitive connection structures is disconnected in the first direction includes: Making the remaining initial channel structure cover surfaces of the capacitive connection structures.

31. The manufacturing method according to claim 24, wherein, After removing a part of the initial first dielectric layer corresponding to the end face to expose the channel structure, the manufacturing method further includes: Form bit lines connected to a portion of the channel structure corresponding to the end face, wherein the bit lines extend along the first direction.

32. The manufacturing method according to claim 24, wherein, the material of the channel structure 511 includes a metal oxide semiconductor.

33. The manufacturing method according to claim 24, wherein, forming an initial channel structure covering the first sidewall, the second sidewall, and the end face includes: forming the initial channel structure through a thin film deposition process.

Images