Storage array and preparation method thereof, three-dimensional memory and electronic equipment

Abstract

The invention provides a memory array and a preparation method thereof, a three-dimensional memory and electronic equipment, relates to the technical field of semiconductors, and aims to improve the area utilization rate of the memory array. The memory array is provided with an array area and a peripheral area, the memory array comprises a plurality of memory units arranged in the array area and a plurality of resistor structures arranged in the peripheral area, each memory unit comprises a vertical transistor, and each resistor structure comprises a gate structure or an active structure. The memory array further comprises a plurality of contact columns and a plurality of signal lines, one ends of the plurality of contact columns are electrically connected with the plurality of resistor structures, and the signal lines are electrically connected with the other ends of the plurality of contact columns. The memory array can be applied to a three-dimensional memory so as to realize data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a memory array and a method for manufacturing the same, a three-dimensional memory, and an electronic device. Background Art

[0002] Currently, XRAM products are based on the Xtacking architecture, which includes two chips, a bonded memory array and a peripheral circuit.

[0003] However, in the area corresponding to the peripheral circuit of the memory array, some areas are not fully utilized, resulting in a low area utilization rate of the memory array. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory array and a method for manufacturing the same, a three-dimensional memory, and an electronic device, aiming to improve the area utilization rate of the memory array.

[0005] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a memory array is provided. The memory array has an array region and a peripheral region. The memory array includes a plurality of memory cells disposed in the array region, and a plurality of resistance structures disposed in the peripheral region. The memory cells include vertical transistors, and the resistance structures include gate structures or active structures. The memory array further includes a plurality of contact posts and a plurality of signal lines. One end of the plurality of contact posts is electrically connected to the plurality of resistance structures, and the signal lines are electrically connected to the other ends of the plurality of contact posts.

[0007] In the memory array provided by the above embodiments of the present disclosure, the memory array has an array region and a peripheral region. The array region is used to dispose a plurality of memory cells, and the transistors in the memory cells adopt the architecture of vertical transistors. The peripheral region is located outside the array region, and a plurality of resistance structures can be disposed in the peripheral region. The resistance structures include gate structures or active structures, which have stable sheet resistance values. By connecting the plurality of resistance structures in series or parallel through the contact posts and the signal lines, the design requirements of various resistance values can be met, and the area utilization rate of the peripheral region of the memory array can be improved.

[0008] In some embodiments, the resistance structures extend along a first direction. The resistance structures include a first end and a second end opposite to each other along the first direction. The first ends of the plurality of resistance structures are electrically connected to a signal line through a part of the plurality of contact posts, and the second ends of the plurality of resistance structures are electrically connected to another signal line through another part of the plurality of contact posts.

[0009] In some embodiments, the resistance structure extends in the second direction. The resistance structure includes a first end and a second end that are opposite to each other in the second direction. Among a plurality of series-connected resistance structures, the first ends of two adjacent resistance structures are electrically connected to a signal line through two contact posts, or the second ends of two adjacent resistance structures are electrically connected to a signal line through two contact posts.

[0010] In some embodiments, the resistance structure includes a first active layer, a first dielectric layer, and a gate structure. The first active layer extends in the third direction. The gate structure is located on at least one side of the first active layer. The first dielectric layer is located between the first active layer and the gate structure. A plurality of memory cells are arranged in an array, and the third direction is perpendicular to the direction in which the plurality of memory cells are arranged in an array.

[0011] In some embodiments, the memory array further includes an isolation structure. The isolation structure is disposed between two adjacent resistance structures, and the first active layers of two adjacent resistance structures are respectively in contact with the isolation structure.

[0012] In some embodiments, the resistance structure includes an active structure. The memory array further includes a second dielectric layer. The second dielectric layer is disposed between two adjacent resistance structures.

[0013] In some embodiments, the resistance structure further includes a connection structure. The connection structure is electrically connected to the active structure, and the active structure is electrically connected to the contact post through the connection structure.

[0014] In some embodiments, the memory array includes a surface provided with pads. The contact posts and the signal line are located on a side of the resistance structure away from the surface.

[0015] In some embodiments, the vertical transistor includes a second active layer, a gate dielectric layer, and a control gate layer. The second active layer extends in the third direction. The control gate layer is located on at least one side of the second active layer. The gate dielectric layer is located between the second active layer and the control gate layer.

[0016] In some embodiments, the resistance structure includes a gate structure. Along the third direction, the gate structure includes an opposite top surface and bottom surface. Along the third direction, the control gate layer includes an opposite top surface and bottom surface. The top surface of the gate structure and the top surface of the control gate layer are in the same plane, and the bottom surface of the gate structure and the bottom surface of the control gate layer are in the same plane.

[0017] In some embodiments, the resistance structure includes an active structure. Along the third direction, the active structure includes an opposite top surface and bottom surface. Along the third direction, the second active layer includes an opposite top surface and bottom surface. The top surface of the active structure and the top surface of the second active layer are in the same plane, and the bottom surface of the active structure and the bottom surface of the second active layer are in the same plane.

[0018] On the other hand, a method for manufacturing a storage array is provided. The manufacturing method includes: forming a plurality of resistance structures on a substrate, where the resistance structures include gate structures or active structures, and the plurality of resistance structures are located in the peripheral region. Forming a plurality of contact posts, with one end of the plurality of contact posts being electrically connected to the plurality of resistance structures. Forming a plurality of signal lines, with the signal lines being electrically connected to the other ends of the plurality of contact posts.

[0019] In the manufacturing method provided by the above embodiments of the present disclosure, a plurality of resistance structures are formed in the peripheral region. The resistance structures include gate structures or active structures, and they have stable sheet resistance values. By connecting the plurality of resistance structures in series or parallel through contact posts and signal lines, the design requirements for various resistance values can be met, and the area utilization rate of the peripheral region of the storage array can be improved.

[0020] In some embodiments, the resistance structure includes a first active layer, a first dielectric layer, and a gate structure. Forming the resistance structure includes: forming a plurality of first trenches in the peripheral region of the substrate, and the portion of the substrate between two adjacent first trenches is the first active layer. Forming the first dielectric layer on the sidewalls of the first trenches. Forming the gate structure inside the first dielectric layer.

[0021] In some embodiments, during the process of forming a plurality of first trenches in the peripheral region of the substrate, a plurality of second trenches are also formed in the array region of the substrate. During the process of forming the first dielectric layer on the sidewalls of the first trenches, a gate dielectric layer is also formed on the sidewalls of the second trenches. During the process of forming the gate structure inside the first dielectric layer, a control gate layer is also formed inside the gate dielectric layer.

[0022] In some embodiments, the resistance structure includes an active structure. Forming the resistance structure includes: etching the portion of the substrate located in the peripheral region to form a plurality of active structures. Performing element doping on the active structures.

[0023] In some embodiments, during the process of etching the portion of the peripheral region of the substrate, the portion of the substrate located in the array region is also etched.

[0024] On the other hand, a three-dimensional memory is provided. The three-dimensional memory includes the storage array and the peripheral circuit in the above embodiments. The peripheral circuit is bonded to the storage array, and the peripheral circuit is electrically connected to the resistance structures in the storage array.

[0025] In the above embodiments of the present disclosure, the storage array and the peripheral circuit are bonded to form a three-dimensional memory. The plurality of resistance structures connected in series or parallel can be electrically connected to the peripheral circuit. Equivalently, the resistance structures that should originally be disposed in the peripheral circuit are transferred to the storage array, reducing the number of devices on the peripheral circuit, which is beneficial to reducing the area of the peripheral circuit, thereby beneficial to reducing the area of the three-dimensional memory and achieving its miniaturization. Moreover, it can reduce the interference of the parasitic capacitance or parasitic resistance generated by the resistance structures to the peripheral circuit.

[0026] In another aspect, an electronic device is provided, which includes the 3D memory and the processor in the above embodiments. The processor is electrically connected to the 3D memory to control its operation.

[0027] It can be understood that for the electronic device provided in the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the storage array and the 3D memory in the foregoing text, and will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, etc. involved in the embodiments of the present disclosure.

[0029] Figure 1 It is a block diagram of an electronic device provided in some embodiments of the present disclosure;

[0030] Figure 2 It is an architecture diagram of a 3D memory provided in some embodiments of the present disclosure;

[0031] Figure 3 It is a top view of a 3D memory provided in some embodiments of the present disclosure;

[0032] Figure 4 is Figure 3 a cross-sectional view of the 3D memory in along the section line A-A';

[0033] Figure 5 is Figure 3 a partial enlarged view of the 3D memory in at P;

[0034] Figure 6 is Figure 5 a cross-sectional view of the 3D memory in along the section line B-B';

[0035] Figure 7 is Figure 6 a partial enlarged view of the 3D memory in at Q;

[0036] Figures 8A - 8N It is a diagram of each step for preparing a storage array;

[0037] Figure 9 is Figure 3 another partial enlarged view of the 3D memory in at P;

[0038] Figure 10 is Figure 9 a cross-sectional view of the three-dimensional memory in along the section line C-C';

[0039] Figures 11A - 11J is a diagram of each step for preparing a memory array. Specific Embodiments

[0040] Hereinafter, the technical solutions in some embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the present disclosure.

[0041] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present disclosure.

[0042] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0043] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0044] In the content of the present disclosure, the meanings of "on", "above", and "over" should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intermediate features or layers therebetween (i.e., directly on something).

[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0046] Some embodiments of the present disclosure provide an electronic device. Figure 1 It is a block diagram of the electronic device provided by some embodiments of the present disclosure.

[0047] See Figure 1 , the electronic device 1 includes a 3D memory 11 and a processor 12. The processor 12 can be a Central Processing Unit (CPU for short), and the processor 12 is electrically connected to the 3D memory 11 to control the operation of the 3D memory 11.

[0048] The electronic device 1 can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0049] Figure 2 It is an architecture diagram of the 3D memory provided by some embodiments of the present disclosure.

[0050] See Figure 2 , the 3D memory 11 includes a storage array 21 and a peripheral circuit. The peripheral circuit includes a word line driver (also called a row decoder) 22, a page buffer 23, a Power Management IC (PMIC for short) 24, a control circuit 25, a column decoder 26, and an I / O (Input / Output) interface circuit 27.

[0051] Among them, the storage array 21 may include a plurality of memory blocks, and each memory block may include a plurality of storage cells arranged in an array. The plurality of storage cells may be connected to the word line driver 22 through string selection lines, word lines, and ground selection lines, and may be connected to the page buffer 23 through bit lines.

[0052] Exemplarily, a plurality of storage cells arranged along the same row may be connected to the same word line, and a plurality of storage cells arranged along the same column may be connected to the same bit line.

[0053] The word line driver 22 may decode the input address to generate and send one or more drive signals, such as word line voltage signals. The word line driver 22 may provide the word line voltage signal generated by the power management circuit 24 to one or more selected word lines among a plurality of word lines. Under the control of the control circuit 25, the unselected word lines among the plurality of word lines may receive another word line voltage signal.

[0054] The page buffer 23 may be connected to the storage array 21 through bit lines to read or sense the data stored in the storage cells. Depending on the operation mode of the 3D memory 11, the page buffer 23 may also be used to temporarily store the data to be written or programmed into the storage cells. The page buffer 23 is also connected to the column decoder 26, and the column decoder 26 may selectively activate the bit lines of the storage array 21.

[0055] The power management circuit 24 may use an external voltage to generate the voltages required for internal operations, such as programming voltage, reading voltage, erasing voltage, etc. The voltages generated by the power management circuit 24 may be transmitted to the storage array 21 through the word line driver 22.

[0056] The control circuit 25 may control the overall operations of the word line driver 22 and the page buffer 23, may receive control signals and external voltages sent from an external entity, and may operate depending on the received control signals, and may also control read, write, and / or erase operations in response to the control signals.

[0057] The I / O interface circuit 27 may receive write data during a programming operation and send the write data to the page buffer 23, may output the read data received from the page buffer 23 to an external entity during a read operation, and may also send an input address or instruction to the control circuit 25.

[0058] Exemplarily, the three-dimensional memory 11 further includes a volatile memory 28, which may be, for example, a Dynamic Random Access Memory (DRAM) or registers, and can be used as a cache for the control circuit 25 to store control programs. When the control circuit 25 operates, high-speed transmission occurs between the two to quickly call the control programs.

[0059] Figure 3 Top view of the three-dimensional memory provided by some embodiments of the present disclosure; Figure 4 is Figure 3 Cross-sectional view of the three-dimensional memory in along the section line A-A'.

[0060] See Figure 3 and Figure 4 As shown, the peripheral circuit 20 is bonded to the storage array 21. The storage array 21 includes a plurality of array regions A1 and a peripheral region A2. The peripheral region A2 is located outside the array regions A1. The peripheral region A2 may include an interval region between the plurality of array regions A1 and a peripheral region on one side of the plurality of array regions A1.

[0061] The storage array 21 includes a plurality of storage units 3 disposed in the array region A1 and a plurality of resistance structures 4 disposed in the peripheral region A2. It can be understood that the resistance structures 4 can be disposed either in the interval region between the plurality of array regions A1 or in the peripheral region on one side of the plurality of array regions A1, and their installation positions are relatively flexible.

[0062] See Figure 4 As shown, along the extension direction of the plane X-Y, the plurality of storage units 3 are arranged in an array. The direction Z is perpendicular to the direction in which the plurality of storage units 3 are arranged in an array. The direction Z is, for example, the vertical direction. Taking the storage unit 3 including a vertical transistor 31 and a storage capacitor 32 as an example, the vertical transistor 31 extends along the vertical direction Z. The vertical transistor 31 includes an active layer 31a, a gate dielectric layer 31b, and a control gate layer 31c. The active layer 31a extends along the direction Z, the control gate layer 31c is located on one side of the active layer 31a, and the gate dielectric layer 31b is located between the active layer 31a and the control gate layer 31c.

[0063] Exemplarily, see Figure 4 As shown, the control gate layer 31c has a stacked structure. For example, the control gate layer 31c includes a first conductive layer and a second conductive layer. The material of the first conductive layer includes titanium nitride, and the material of the second conductive layer includes tungsten. The first conductive layer is in contact with the gate dielectric layer 31b, and the second conductive layer is located on the side of the first conductive layer away from the gate dielectric layer 31b.

[0064] Exemplarily, see Figure 4, the storage array 21 further includes an isolation structure 33 disposed between two adjacent vertical transistors 31, and the active layers 31a of two adjacent vertical transistors 31 are respectively in contact with the isolation structure 33, and the isolation structure 33 can reduce the crosstalk between two adjacent vertical transistors 31.

[0065] The isolation structure 33 also has a stacked structure. For example, the isolation structure 33 includes a first isolation layer and a second isolation layer. The material of the first isolation layer includes a dielectric material, and the material of the second isolation layer includes a metal material. The first isolation layer wraps around the outside of the second isolation layer, and the first isolation layer is in contact with the active layer 31a of the vertical transistor 31.

[0066] Please continue to refer to Figure 4 , a storage capacitor 32 is disposed above the vertical transistor 31. The storage capacitor 32 includes a first electrode 32a, a dielectric layer 32b, and a second electrode 32c. Along the direction Z, the dielectric layer 32b is located between the first electrode 32a and the second electrode 32c. The first electrode 32a is electrically connected to the active layer 31a of the vertical transistor 31, and the second electrodes 32c of multiple storage capacitors 32 can be integrally formed into a plate line.

[0067] Exemplarily, refer to Figure 4 , the storage array 21 further includes a first conductive structure 34. The first conductive structure 34 is electrically connected to the plate line, and the plate line can be connected to the peripheral circuit 20 through the first conductive structure 34.

[0068] Refer to Figure 4 , the storage array 21 further includes a plurality of word lines WL and a plurality of bit lines BL. The word lines WL can extend along the direction X, and the bit lines BL can extend along the direction Y. Along the direction X, the control gate layers 31c of the vertical transistors 31 in multiple storage units 3 are integrally formed into a word line WL. Along the direction Y, the active layers 31a of the vertical transistors 31 in multiple storage units 3 are electrically connected to a bit line BL.

[0069] Refer to Figure 4 , the storage array 21 further includes a second conductive structure 35 and a pad 36. The second conductive structure 35 is electrically connected to the pad 36, and the storage array 21 can be connected to an external circuit through the second conductive structure 35 and the pad 36.

[0070] Figure 5 For Figure 3 a partial enlarged view of the three-dimensional memory in at P; Figure 6 For Figure 5 a cross-sectional view of the three-dimensional memory in along the section line B-B'; Figure 7 For Figure 6 a partial enlarged view of the three-dimensional memory in at Q.

[0071] Refer to Figures 5 - 7, the resistance structure 4 includes an active layer 41, a first dielectric layer 42, and a gate structure 43. The gate structure 43 is located on one side of the active layer 41, and the first dielectric layer 42 is located between the active layer 41 and the gate structure 43. It can be seen that the structure of the resistance structure 4 is substantially the same as that of the vertical transistor 31.

[0072] Exemplarily, referring to Figure 6 and Figure 7 , along the direction Z, the gate structure 43 includes opposite top surface 431 and bottom surface 432. Please refer back to Figure 4 , the control gate layer 31c also includes opposite top surface 311 and bottom surface 312. The top surface 431 of the gate structure 43 is in the same plane as the top surface 311 of the control gate layer 31c, and the bottom surface 432 of the gate structure 43 is also in the same plane as the bottom surface 312 of the control gate layer 31c. That is to say, the gate structure 43 can be fabricated in the same process step as the control gate layer 31c. Since the control gate layer 31c is part of the word line WL, therefore, when the resistance structure 4 includes the gate structure 43, the resistance structure 4 is also referred to as a "word line resistor (WL resistor)".

[0073] Exemplarily, referring to Figure 7 , the gate structure 43 also has a stacked structure. For example, the gate structure 43 includes a first conductive layer and a second conductive layer. The material of the first conductive layer includes titanium nitride, and the material of the second conductive layer includes tungsten. The first conductive layer is in contact with the first dielectric layer 42, and the second conductive layer is located on the side of the first conductive layer away from the first dielectric layer 42.

[0074] Exemplarily, referring to Figure 7 , the isolation structure 33 is also disposed between two adjacent resistance structures 4, and the active layers 41 of two adjacent resistance structures 4 are respectively in contact with the isolation structure 33.

[0075] Please continue to refer to Figures 5 - 7 , the memory array 21 further includes a plurality of contact posts 5 and a plurality of signal lines 6. One end of the contact post 5 is electrically connected to the resistance structure 4, and the other end is electrically connected to the signal line 6.

[0076] Exemplarily, referring to Figure 5 , the resistance structure 4 extends along the direction X. The resistance structure 4 includes a first end 4a and a second end 4b opposite to each other along the direction X. The first ends 4a of a plurality of resistance structures 4 are electrically connected to a signal line 6 through a plurality of contact posts 5, and the second ends 4b of a plurality of resistance structures 4 are electrically connected to another signal line 6 through a plurality of contact posts 5 to realize the parallel connection of a plurality of resistance structures 4.

[0077] For example, referring to Figure 5, along the direction Y, among the plurality of resistor structures 4, a first resistor structure 4A and a second resistor structure 4B are alternately arranged. The first ends 4a of the plurality of first resistor structures 4A are electrically connected to a signal line 6 through a plurality of contact posts 5, and the second ends 4b of the plurality of first resistor structures 4A are electrically connected to another signal line 6 through a plurality of contact posts 5, so as to realize the parallel connection of the plurality of first resistor structures 4A.

[0078] The first ends 4a of the plurality of second resistor structures 4B are electrically connected to a signal line 6 through a plurality of contact posts 5, and the second ends 4b of the plurality of second resistor structures 4B are electrically connected to another signal line 6 through a plurality of contact posts 5, so as to realize the parallel connection of the plurality of second resistor structures 4B.

[0079] It can be understood that Figure 5 in, according to the design requirements, the number of resistor structures 4 connected in parallel can be set.

[0080] In addition, Figure 5 in, the plurality of resistor structures 4 can also be connected in series through the contact posts 5 and the signal lines 6, and according to the design requirements, the number of resistor structures 4 connected in series can be set.

[0081] Exemplarily, referring to Figure 6 , taking the surface 8 of the memory array 21 provided with the pads 36 as a reference, the contact posts 5 and the signal lines 6 are located on the side of the resistor structure 4 away from the surface 8. Along the direction Z, the memory array 21 further includes a surface opposite to the surface 8, and this surface is the surface where the memory array 21 is bonded to the peripheral circuit 20.

[0082] The peripheral circuit 20 is electrically connected to the resistor structure 4 in the memory array 21. For example, the signal line 6 can be electrically connected to the peripheral circuit 20 through a third conductive structure 7, so as to realize the electrical connection between the resistor structure 4 and the peripheral circuit 20.

[0083] In the above embodiments of the present disclosure, the memory array 21 includes an array region A1 and a peripheral region A2. The array region A1 is used to arrange a plurality of memory cells 3, and the transistors in the memory cells 3 adopt the architecture of vertical transistors 31. The peripheral region A2 is located outside the array region A1. A plurality of resistor structures 4 can be arranged in the peripheral region A2. The resistor structure 4 includes a gate structure 43, which has a stable sheet resistance value. By connecting a plurality of resistor structures 4 in series or in parallel through the contact posts 5 and the signal lines 6, the design requirements of various resistance values can be met, and the area utilization rate of the peripheral region A2 of the memory array 21 can be improved.

[0084] Moreover, the storage array 21 is bonded to the peripheral circuit 20 to form the three-dimensional memory 11. A plurality of resistor structures 4 in series or parallel can be electrically connected to the peripheral circuit 20. Equivalently, the resistor structures 4 that should originally be disposed in the peripheral circuit 20 are transferred onto the storage array 21, reducing the number of devices on the peripheral circuit 20, which is beneficial to reducing the area of the peripheral circuit 20, and thus beneficial to reducing the area of the three-dimensional memory 11, achieving its miniaturization. Moreover, the parasitic capacitance or parasitic resistance generated by the resistor structures 4 can be reduced to interfere with the peripheral circuit 20.

[0085] Some embodiments of the present disclosure also provide a method for manufacturing the above storage array 21. Figures 8A - 8N The figures are the process diagrams of each step for manufacturing the storage array 21.

[0086] See Figure 8A and Figure 8B , a plurality of first trenches S1 are formed in the peripheral region A2 of the substrate S. The first trenches S1 extend along the direction X. The portion of the substrate S between two adjacent first trenches S1 serves as the active layer 41 of the resistor structure 4.

[0087] Exemplarily, during the process of forming a plurality of first trenches S1 in the peripheral region A2 of the substrate S, a plurality of second trenches are also formed in the array region A1 of the substrate S. The second trenches also extend along the direction X. The second trenches are used to form Figure 4 the vertical transistors 31 in

[0088] See Figure 8C and Figure 8D , a first dielectric layer 42 of the resistor structure 4 is formed on the sidewalls of the first trenches S1.

[0089] Exemplarily, during the process of forming the first dielectric layer 42 on the sidewalls of the first trenches S1, a gate dielectric layer 31b of the vertical transistor 31 is also formed on the sidewalls of the second trenches.

[0090] See Figure 8E and Figure 8F , a gate structure 43 of the resistor structure 4 is formed inside the first dielectric layer 42.

[0091] Exemplarily, during the process of forming the gate structure 43 inside the first dielectric layer 42, a control gate layer 31c of the vertical transistor 31 is also formed inside the gate dielectric layer 31b.

[0092] It can be seen that the resistor structure 4 is compatible with the process of the vertical transistor 31 and can be fabricated in the same process step without additional process costs. Moreover, the fabrication process of the resistor structure 4 is relatively mature, which is conducive to controlling the dimensional parameters such as the length, width, or height of the resistor structure 4, so as to facilitate the resistor structure 4 to obtain an accurate sheet resistance value.

[0093] Exemplarily, referring to Figure 8G and Figure 8H , after forming the gate structure 43, an isolation structure 33 is formed between two adjacent resistor structures 4, and the active layers 41 of the two resistor structures 4 are respectively in contact with the isolation structure 33. Moreover, an isolation structure 33 is also formed between two adjacent vertical transistors 31, and the active layers 31a of the two vertical transistors 31 are respectively in contact with the isolation structure 33.

[0094] Exemplarily, after forming the control gate layer 31c of the vertical transistor 31, a storage capacitor 32 is further formed above the vertical transistor 31.

[0095] Referring to Figure 8I , after forming the storage capacitor 32, the structure in Figure 8H is inverted and bonded to the transfer substrate C, and the top of the substrate S is removed. For example, a Chemical Mechanical Polishing (CMP) process can be used to grind the top of the substrate S.

[0096] Referring to Figure 8J and Figure 8K , a plurality of contact posts 5 are formed, and one end of the plurality of contact posts 5 is electrically connected to the plurality of resistor structures 4.

[0097] Referring to Figure 8L and Figure 8M , a plurality of signal lines 6 are formed, and the signal lines 6 are electrically connected to the other ends of the plurality of contact posts 5. The series or parallel connection of the plurality of resistor structures 4 can be realized through the contact posts 5 and the signal lines 6.

[0098] Exemplarily, during the formation of the signal lines 6, a bit line BL is also formed, and the active layer 31a of the vertical transistor 31 is electrically connected to the bit line BL.

[0099] Referring to Figure 8N , a third conductive structure 7 is formed, and the third conductive structure 7 is electrically connected to the signal lines 6. Then, the memory array 21 is bonded to the peripheral circuit 20, and the signal lines 6 can be electrically connected to the peripheral circuit 20 through the third conductive structure 7 to realize the electrical connection between the resistor structure 4 and the peripheral circuit 20. Finally, a second conductive structure 35 and a pad 36 are formed, and the pad 36 is exposed on the surface 8 of the memory array 21.

[0100] Exemplarily, during the formation of the third conductive structure 7, a first conductive structure 34 is also formed. The first conductive structure 34 is the lead-out structure of the plate line, and further, the lead-out structures of the word line WL and the bit line BL are also formed.

[0101] Figure 9 For Figure 3 Another partial enlarged view of the 3D memory in Figure 10 For Figure 9 The cross-sectional view of the 3D memory in

[0102] See Figure 9 And Figure 10 , the resistance structure 4 includes an active structure 44, and the memory array 21 further includes a second dielectric layer 9. The second dielectric layer 9 is disposed between two adjacent resistance structures 4.

[0103] Exemplarily, see Figure 10 , along the direction Z, the active structure 44 includes opposite top surface 441 and bottom surface 442. Please refer back to Figure 4 , the active layer 31a also includes opposite top surface 313 and bottom surface 314. The top surface 441 of the active structure 44 is in the same plane as the top surface 313 of the active layer 31a, and the bottom surface 442 of the active structure 44 is also in the same plane as the bottom surface 314 of the active layer 31a. That is to say, the active structure 44 can be fabricated in the same process step as the active layer 31a.

[0104] Exemplarily, the resistance structure 4 further includes a plurality of connection structures 10. The bottom surface 442 of the active structure 44 is electrically connected to the connection structures 10. The connection structures 10 can be fabricated in the same process step as the bit line BL. Therefore, when the resistance structure 4 further includes a plurality of connection structures 10, the resistance structure 4 is also referred to as a "bit line resistor (BL resistor)".

[0105] Please continue to refer to Figure 9 And Figure 10 , the memory array 21 further includes a plurality of contact posts 5 and a plurality of signal lines 6. One end of the contact post 5 is electrically connected to the connection structures 10, and the other end is electrically connected to the signal lines 6.

[0106] Exemplarily, see Figure 9 And Figure 10 , the resistance structure 4 extends along the direction Y. The resistance structure 4 includes opposite first end 4a and second end 4b along the direction Y. The first ends 4a of two adjacent resistance structures 4 are electrically connected to a signal line 6 through two contact posts 5, or the second ends 4b of two adjacent resistance structures 4 are electrically connected to a signal line 6 through two contact posts 5, so that a plurality of resistance structures 4 are connected in series.

[0107] For example, seeFigure 9 Along the direction X, among the plurality of resistor structures 4, a first resistor structure 4A and a second resistor structure 4B are alternately arranged. The first ends 4a of two adjacent first resistor structures 4A are electrically connected to a signal line 6 through two contact posts 5, so as to realize the series connection of the plurality of first resistor structures 4A.

[0108] The second ends 4b of two adjacent second resistor structures 4B are electrically connected to a signal line 6 through two contact posts 5, so as to realize the series connection of the plurality of second resistor structures 4B.

[0109] It can be understood that Figure 9 in, the number of series-connected resistor structures 4 is not limited to two, and the number of series-connected resistor structures 4 can be set according to design requirements.

[0110] In addition, Figure 9 in, the plurality of resistor structures 4 can also be connected in parallel through the contact posts 5 and the signal line 6, and the number of resistor structures 4 connected in parallel can be set according to design requirements.

[0111] Exemplarily, referring to Figure 10 , taking the surface 8 of the storage array 21 provided with the pads 36 as a reference, the contact posts 5 and the signal line 6 are located on the side of the resistor structure 4 away from the surface 8. Along the direction Z, the storage array 21 further includes a surface opposite to the surface 8, and this surface is the surface where the storage array 21 is bonded to the peripheral circuit 20.

[0112] The peripheral circuit 20 is electrically connected to the resistor structure 4 in the storage array 21. For example, the signal line 6 can be electrically connected to the peripheral circuit 20 through the third conductive structure 7, so as to realize the electrical connection between the resistor structure 4 and the peripheral circuit 20.

[0113] In the above embodiments of the present disclosure, also based on the architecture of the vertical transistor 31, by arranging a plurality of resistor structures 4 in the peripheral area A2, the resistor structure 4 includes an active structure 44, which has a stable sheet resistance value. By connecting a plurality of resistor structures 4 in series or in parallel through the contact posts 5 and the signal line 6, the design requirements of various resistance values can be met, and the area utilization rate of the peripheral area A2 of the storage array 21 can be improved.

[0114] Some embodiments of the present disclosure also provide a preparation method for the above storage array 21, Figures 11A - 11J which are step diagrams for preparing the storage array 21.

[0115] Referring to Figure 11A and Figure 11B , etch the portion of the substrate S located in the peripheral area A2 to form a plurality of active structures 44. Then, form a second dielectric layer 9, and the second dielectric layer 9 is located between the plurality of active structures 44.

[0116] Exemplarily, during the process of etching the portion of the substrate S located in the peripheral region A2, the portion of the substrate S located in the array region A1 is also etched to form the active layer 31a of the vertical transistor 31.

[0117] It can be seen that the active structure 44 is compatible with the active layer 31a of the vertical transistor 31 in terms of process and can be fabricated in the same process step without additional process costs. Moreover, the fabrication process of the active structure 44 is relatively mature, which is conducive to controlling dimensional parameters such as the length, width, or height of the active structure 44, so as to facilitate the active structure 44 to obtain an accurate sheet resistance value.

[0118] After forming the active layer 31a of the vertical transistor 31, the gate dielectric layer 31b and the control gate layer 31c of the vertical transistor 31 are also formed, and a storage capacitor 32 is formed above the vertical transistor 31.

[0119] See Figure 11C , after forming the storage capacitor 32, the structure in Figure 11B is inverted and bonded to the transfer substrate C, and the top of the substrate S is removed. For example, a chemical mechanical polishing process can be used to grind the top of the substrate S.

[0120] See Figure 11D and Figure 11E , element doping is performed on the active structure 44. For example, cobalt elements can be doped into the active structure 44. By adjusting the concentration of the doping elements, the resistivity of the material of the active structure 44 is adjusted, thereby facilitating the adjustment of the resistance of the resistance structure 4. Then, a connection structure 10 is formed on the active structure 44, and the connection structure 10 is electrically connected to the active structure 44.

[0121] Exemplarily, during the process of forming the connection structure 10, a bit line BL is also formed, and the active layer 31a of the vertical transistor 31 is electrically connected to the bit line BL.

[0122] See Figure 11F and Figure 11G , a plurality of contact posts 5 are formed, and one end of the plurality of contact posts 5 is electrically connected to the plurality of resistance structures 4.

[0123] See Figure 11H and Figure 11I , a plurality of signal lines 6 are formed, and the signal lines 6 are electrically connected to the other ends of the plurality of contact posts 5. The series or parallel connection of the plurality of resistance structures 4 can be realized through the contact posts 5 and the signal lines 6.

[0124] See Figure 11J, a third conductive structure 7 is formed, and the third conductive structure 7 is electrically connected to the signal line 6. Then, the memory array 21 is bonded to the peripheral circuit 20, and the signal line 6 can be electrically connected to the peripheral circuit 20 through the third conductive structure 7 to achieve the electrical connection between the resistive structure 4 and the peripheral circuit 20. Finally, a second conductive structure 35 and a pad 36 are formed, and the pad 36 is exposed on the surface 8 of the memory array 21.

[0125] Exemplarily, during the process of forming the third conductive structure 7, a first conductive structure 34 is further formed. The first conductive structure 34 is an extraction structure of the plate line, and an extraction structure of the word line WL and the bit line BL is further formed.

[0126] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A storage array, characterized in that, it includes an array region and a peripheral region; The storage array includes: a plurality of storage units disposed in the array region, and the storage units include vertical transistors; a plurality of resistance structures disposed in the peripheral region, and the resistance structures include gate structures or active structures; a plurality of contact posts, one ends of the plurality of contact posts are electrically connected to the plurality of resistance structures; a plurality of signal lines, and the signal lines are electrically connected to the other ends of the plurality of contact posts.

2. The storage array according to claim 1, characterized in that, the resistance structure extends along a first direction, and the resistance structure includes a first end and a second end opposite to each other along the first direction; the first ends of the plurality of resistance structures are electrically connected to one of the signal lines through a part of the plurality of contact posts, and the second ends of the plurality of resistance structures are electrically connected to another one of the signal lines through another part of the plurality of contact posts.

3. The storage array according to claim 1, characterized in that, the resistance structure extends along a second direction, and the resistance structure includes a first end and a second end opposite to each other along the second direction; in a series of a plurality of the resistance structures, the first ends of two adjacent resistance structures are electrically connected to one of the signal lines through two of the contact posts, or the second ends of two adjacent resistance structures are electrically connected to one of the signal lines through two of the contact posts.

4. The storage array according to claim 1, characterized in that, the resistance structure includes a first active layer, a first dielectric layer and the gate structure, the first active layer extends along a third direction, the gate structure is located on at least one side of the first active layer, and the first dielectric layer is located between the first active layer and the gate structure; the plurality of storage units are arranged in an array, and the third direction is perpendicular to the direction in which the plurality of storage units are arranged in an array.

5. The storage array according to claim 4, characterized in that, the storage array further includes an isolation structure, the isolation structure is disposed between two adjacent resistance structures, and the first active layers of two adjacent resistance structures are respectively in contact with the isolation structure.

6. The storage array according to claim 1, characterized in that, the resistance structure includes the active structure; the storage array further includes a second dielectric layer, and the second dielectric layer is disposed between two adjacent resistance structures.

7. The storage array according to claim 6, characterized in that, the resistance structure further includes a connection structure, and the connection structure is electrically connected to the active structure; the active structure is electrically connected to the contact post through the connection structure.

8. The storage array according to any one of claims 1 to 7, characterized in that, the storage array includes a surface provided with pads, and the contact posts and the signal lines are located on a side of the resistance structure away from the surface.

9. The storage array according to claim 1, characterized in that, The vertical transistor includes a second active layer, a gate dielectric layer, and a control gate layer. The second active layer extends in a third direction. The control gate layer is located on at least one side of the second active layer, and the gate dielectric layer is located between the second active layer and the control gate layer; The multiple memory cells are arranged in an array, and the third direction is perpendicular to the direction in which the multiple memory cells are arranged in an array.

10. The memory array according to claim 9, wherein, The resistance structure includes the gate structure. Along the third direction, the gate structure includes an opposite top surface and bottom surface; Along the third direction, the control gate layer includes an opposite top surface and bottom surface; The top surface of the gate structure is in the same plane as the top surface of the control gate layer; the bottom surface of the gate structure is in the same plane as the bottom surface of the control gate layer.

11. The memory array according to claim 9, wherein, The resistance structure includes the active structure. Along the third direction, the active structure includes an opposite top surface and bottom surface; Along the third direction, the second active layer includes an opposite top surface and bottom surface; The top surface of the active structure is in the same plane as the top surface of the second active layer; the bottom surface of the active structure is in the same plane as the bottom surface of the second active layer.

12. A method for manufacturing a memory array, wherein, includes: Forming a plurality of resistance structures on a substrate. The resistance structure includes a gate structure or an active structure; the substrate includes an array region and a peripheral region, and the plurality of resistance structures are located in the peripheral region; Forming a plurality of contact posts, one end of the plurality of contact posts being electrically connected to the plurality of resistance structures; Forming a plurality of signal lines, the signal lines being electrically connected to the other ends of the plurality of contact posts.

13. The manufacturing method according to claim 12, wherein, The resistance structure includes a first active layer, a first dielectric layer, and the gate structure. Forming the resistance structure includes: Forming a plurality of first trenches in the peripheral region of the substrate, and the portion of the substrate located between two adjacent first trenches is the first active layer; Forming the first dielectric layer on the sidewalls of the first trenches; Forming the gate structure inside the first dielectric layer.

14. The manufacturing method according to claim 13, wherein, During the process of forming a plurality of first trenches in the peripheral region of the substrate, a plurality of second trenches are also formed in the array region of the substrate; During the process of forming the first dielectric layer on the sidewalls of the first trenches, a gate dielectric layer is also formed on the sidewalls of the second trenches; During the process of forming the gate structure inside the first dielectric layer, a control gate layer is also formed inside the gate dielectric layer.

15. The manufacturing method according to claim 12, wherein, The resistance structure includes an active structure. Forming the resistance structure includes: Etching the portion of the substrate located in the peripheral region to form a plurality of the active structures; Performing element doping on the active structures.

16. The manufacturing method according to claim 15, wherein, During the process of etching a part of the peripheral region of the substrate, a part of the substrate located in the array region is also etched.

17. A three-dimensional memory, characterized in that it includes: a storage array as described in any one of claims 1 to 11; a peripheral circuit bonded to the storage array, the peripheral circuit being electrically connected to the resistance structure in the storage array.

18. An electronic device, characterized in that it includes: a three-dimensional memory as described in claim 17; a processor electrically connected to the three-dimensional memory.

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