Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a first substrate; forming a bottom dielectric layer on the upper surface of the first substrate; bit line grooves are formed in the bottom dielectric layer and the first substrate, and the bit line grooves extend in the first direction; forming a bit line in the bit line trench; providing a second substrate; bonding a second substrate on the upper surface of the bottom dielectric layer; a word line is formed in the second substrate. According to the invention, the contact resistance between the transistor and the bit line can be reduced, and the preparation process of the bit line is simplified.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technologies, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] A memory is composed of multiple memory cells, and each memory cell generally includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line (abbreviated as WL), the source or drain of the transistor is electrically connected to a bit line (abbreviated as BL), and the drain or source of the transistor is electrically connected to the capacitor. The voltage on the word line controls the turning on and off of the transistor, so as to read the data information stored in the capacitor through the bit line, or write the data information into the capacitor.

[0003] With the development of semiconductor technologies, the device structure size of memories is gradually decreasing. Therefore, the manufacturing difficulty of memories is increasing accordingly. In particular, the process of manufacturing bit lines in traditional processes is relatively complex. Moreover, as the size of memories decreases, the influence of the contact resistance between transistors and bit lines on the performance of memories is becoming increasingly severe. Therefore, how to simplify the bit line manufacturing process and reduce the contact resistance between transistors and bit lines has become a problem that urgently needs to be solved at present. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for manufacturing the same, which can reduce the contact resistance between transistors and bit lines and simplify the bit line manufacturing process.

[0005] According to some embodiments, one aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method including:

[0006] Providing a first substrate;

[0007] Forming a bottom dielectric layer on the upper surface of the first substrate;

[0008] Forming a bit line trench in the bottom dielectric layer and the first substrate, the bit line trench extending along a first direction;

[0009] Forming a bit line in the bit line trench;

[0010] Providing a second substrate;

[0011] Bonding the second substrate to the upper surface of the bottom dielectric layer;

[0012] Forming a word line in the second substrate.

[0013] In some embodiments, the second substrate includes a doped substrate; providing the second substrate includes:

[0014] Providing an initial substrate;

[0015] Dope the bottom surface of the initial substrate;

[0016] Perform a first annealing process on the doped initial substrate to obtain a second substrate.

[0017] In some embodiments, after bonding the second substrate to the upper surface of the bottom dielectric layer and before forming word lines in the second substrate, it further includes:

[0018] Thin the second substrate.

[0019] In some embodiments, thinning the second substrate includes:

[0020] Perform ion implantation into the second substrate from its upper surface;

[0021] Perform a second annealing process on the obtained structure;

[0022] Thin the second substrate after the second annealing process by using a chemical mechanical polishing process and / or a wet etching process.

[0023] In some embodiments, forming word lines in the second substrate includes:

[0024] Form word line gaps in the second substrate;

[0025] Form word lines in the word line gaps.

[0026] In some embodiments, forming word line gaps in the second substrate includes:

[0027] Etch the second substrate to obtain a plurality of active strips extending in a first direction, and the plurality of active strips are arranged at intervals in a second direction, where the second direction intersects the first direction;

[0028] Form a first sacrificial layer between adjacent active strips;

[0029] Etch the first sacrificial layer and the active strips to obtain word line trenches extending in the second direction and divide the plurality of active strips into a plurality of active pillars arranged in an array;

[0030] Form word line gaps based on the word line trenches.

[0031] In some embodiments, forming word line gaps based on the word line trenches includes:

[0032] Form a second sacrificial layer on the sidewalls and bottom of the word line trenches;

[0033] Form a word line isolation structure in the word line trenches;

[0034] Remove a part of the first sacrificial layer and a part of the second sacrificial layer, so that the upper surfaces of the remaining first sacrificial layer and the second sacrificial layer are both lower than the upper surface of the word line isolation structure and the upper surface of the active pillar;

[0035] Form a dielectric protection layer, the dielectric protection layer covering the upper surface of the active pillar, the upper surface of the first sacrificial layer and the upper surface of the second sacrificial layer;

[0036] Remove the dielectric protection layer located on the upper surface of the active pillar and on the upper surface of the first sacrificial layer;

[0037] Remove at least a part of the first sacrificial layer and at least a part of the second sacrificial layer to form a word line gap.

[0038] In some embodiments, the word line gap includes a word line groove and a word line slit extending in the second direction, the word line groove being located between adjacent active pillars along the second direction; removing at least a part of the first sacrificial layer and at least a part of the second sacrificial layer to form a word line gap includes:

[0039] Remove at least a part of the first sacrificial layer to form a word line groove, the word line groove exposing the second sacrificial layer on opposite sides of the word line isolation structure;

[0040] Remove at least a part of the second sacrificial layer on opposite sides of the word line isolation structure to form a word line slit, the word line slit communicating with the word line groove.

[0041] In some embodiments, after forming the word line, the manufacturing method further includes: forming a covering dielectric layer, the covering dielectric layer covering the upper surface of the active pillar, the upper surface of the dielectric protection layer and the upper surface of the word line.

[0042] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, the semiconductor structure including a first substrate, a bottom dielectric layer, a bit line, a second substrate and a word line; the bottom dielectric layer is formed on the upper surface of the first substrate; the bit line is formed in the bottom dielectric layer and the first substrate, the bit line extending in the first direction; the second substrate is bonded to the upper surface of the bottom dielectric layer; the word line is formed in the second substrate.

[0043] In some embodiments, the second substrate includes a doped substrate.

[0044] In some embodiments, the second substrate includes a plurality of active pillars arranged in an array; the semiconductor structure further includes a word line isolation structure and a dielectric protection layer; the word line isolation structure is at least located between adjacent active pillars along the first direction; the dielectric protection layer at least covers the upper sidewall surface of the active pillar.

[0045] In some embodiments, the semiconductor structure further includes a covering dielectric layer, the covering dielectric layer covering the upper surface of the active pillar, the upper surface of the dielectric protection layer and the upper surface of the word line.

[0046] According to some embodiments, another aspect of the present disclosure provides a memory including the semiconductor structure described above.

[0047] According to some embodiments, yet another aspect of the present disclosure provides an electronic device including the memory described above.

[0048] The embodiments of the present disclosure have the following advantages:

[0049] In the semiconductor structure and its manufacturing method in the above embodiments, bit lines are formed in the first substrate, word lines are formed in the second substrate, and then the second substrate is bonded to the first substrate. In this way, when forming the bit lines, only a bottom dielectric layer needs to be formed on the upper surface of the first substrate, bit line trenches are formed in the bottom dielectric layer and the first substrate, and bit lines are formed in the bit line trenches. Compared with the related art, the manufacturing method of the embodiments of the present disclosure effectively reduces the manufacturing difficulty of the bit lines and simplifies the manufacturing process of the bit lines. Moreover, since the bit lines are separately manufactured on a substrate and are directly formed in the bit line trenches formed in the first substrate, the manufacturing difficulty of the bit lines is reduced, and the formed bit lines have better morphology and quality, thereby reducing the resistance of the bit lines themselves and the contact resistance between the bit lines and other structures. Description of the Drawings

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0051] Figure 1 It is a schematic flowchart of the manufacturing method of the semiconductor structure provided in an embodiment of the present disclosure;

[0052] Figure 2 It is a schematic three-dimensional structure diagram of the structure obtained in step S10 in the manufacturing method of the semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 3 It is a schematic three-dimensional structure diagram of the structure obtained in step S20 in the manufacturing method of the semiconductor structure provided in an embodiment of the present disclosure;

[0054] Figure 4 It is a schematic three-dimensional structure diagram of the structure obtained in step S30 in the manufacturing method of the semiconductor structure provided in an embodiment of the present disclosure;

[0055] Figure 5 It is a schematic three-dimensional structure diagram of the structure obtained in step S40 in the manufacturing method of the semiconductor structure provided in an embodiment of the present disclosure;

[0056] Figure 6 Schematic three-dimensional structure diagrams of the structures obtained in step S50 and step S60 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0057] Figure 7 Schematic three-dimensional structure diagram of the structure obtained in step S711 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0058] Figure 8 Schematic three-dimensional structure diagrams of the structures obtained in step S712 and step S713 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0059] Figure 9 In figure (a), it is a schematic three-dimensional structure diagram of the structures obtained in step S7141 and step S7142 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and in figure (b), it is a schematic three-dimensional structure diagram of the structures obtained in step S7141 and step S7142 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction;

[0060] Figure 10 In figure (a), it is a schematic three-dimensional structure diagram of the structure obtained in step S7143 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and in figure (b), it is a schematic three-dimensional structure diagram of the structure obtained in step S7143 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction;

[0061] Figure 11 In figure (a), it is a schematic three-dimensional structure diagram of the structure obtained in step S7144 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and in figure (b), it is a schematic three-dimensional structure diagram of the structure obtained in step S7144 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction;

[0062] Figure 12 In figure (a), it is a schematic three-dimensional structure diagram of the structure obtained in step S7145 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and in figure (b), it is a schematic three-dimensional structure diagram of the structure obtained in step S7145 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction;

[0063] Figure 13 In figure (a), it is a schematic three-dimensional structure diagram of the structure obtained in step S7146 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and in figure (b), it is a schematic three-dimensional structure diagram of the structure obtained in step S7146 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction;

[0064] Figure 14 Figure (a) is a schematic three-dimensional structure diagram of the structure obtained in step S72 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and figure (b) is a schematic three-dimensional structure diagram of the structure obtained in step S72 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction;

[0065] Figure 15 Figure (a) is a schematic three-dimensional structure diagram of the structure obtained in step S80 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along one direction, and figure (b) is a schematic three-dimensional structure diagram of the structure obtained in step S80 in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure along another direction.

[0066] Description of reference numerals:

[0067] 10. First substrate; 101. Bottom dielectric layer; 20. Second substrate; 21. Active strip; 22. Active column; BL. Bit line; 30. Bit line trench; WL. Word line; 40. Word line gap; 40a. Word line trench; 401. Word line groove; 402. Word line slit; 41. Word line isolation structure; 411. Word line isolation material layer; 42. Dielectric protection layer; 51. First sacrificial layer; 52. Second sacrificial layer; 60. Covering dielectric layer. Detailed embodiments

[0068] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0070] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0071] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0072] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0073] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0074] This application provides a semiconductor structure and a method for manufacturing the same, and the detailed content will be elaborated in subsequent embodiments.

[0075] According to some embodiments, the present disclosure provides a method for manufacturing a semiconductor structure.

[0076] Please refer to Figure 1 , the manufacturing method includes:

[0077] Step S10: Provide a first substrate;

[0078] Step S20: Form a bottom dielectric layer on the upper surface of the first substrate;

[0079] Step S30: Form bit line trenches in the bottom dielectric layer and the first substrate, and the bit line trenches extend along a first direction;

[0080] Step S40: Form bit lines in the bit line trenches;

[0081] Step S50: Provide a second substrate;

[0082] Step S60: Bond the second substrate to the upper surface of the bottom dielectric layer;

[0083] Step S70: Form word lines in the second substrate.

[0084] In the method for preparing the semiconductor structure in the above embodiments, bit lines are formed in the first substrate, word lines are formed in the second substrate, and then the second substrate is bonded to the first substrate. In this way, when forming the bit lines, only a bottom dielectric layer needs to be formed on the upper surface of the first substrate, bit line trenches are formed in the bottom dielectric layer and the first substrate, and bit lines are formed in the bit line trenches. Compared with the related art, the preparation method of the embodiments of the present disclosure effectively reduces the preparation difficulty of the bit lines and simplifies the preparation process of the bit lines. Moreover, since the bit lines are separately prepared on one substrate and are directly formed in the bit line trenches formed in the first substrate, the preparation difficulty of the bit lines is reduced, and the formed bit lines have better morphology and quality, thereby reducing the resistance of the bit lines themselves and the contact resistance between the bit lines and other structures.

[0085] In some embodiments, the second substrate includes a doped substrate; step S50 of providing the second substrate includes:

[0086] Step S51: Provide an initial substrate;

[0087] Step S52: Dope the bottom surface of the initial substrate;

[0088] Step S53: Perform a first annealing treatment on the doped initial substrate to obtain the second substrate.

[0089] In some embodiments, after bonding the second substrate to the upper surface of the bottom dielectric layer, that is, after step S60 and before forming the word lines in the second substrate, that is, before step S70, it further includes:

[0090] Step S600: Thin the second substrate.

[0091] In some embodiments, thinning the second substrate includes:

[0092] Step S601: Perform ion implantation into the second substrate from the upper surface of the second substrate;

[0093] Step S602: Perform a second annealing treatment on the obtained structure;

[0094] Step S603: Thin the second substrate after the second annealing treatment by using a chemical mechanical polishing process and / or a wet etching process.

[0095] In some embodiments, step S70 of forming word lines in the second substrate includes:

[0096] Step S71: Form word line gaps in the second substrate;

[0097] Step S72: Form word lines in the word line gaps.

[0098] In some embodiments, step S71 of forming a word line gap in the second substrate includes:

[0099] Step S711: Etch the second substrate to obtain a plurality of active strips extending in a first direction, and the plurality of active strips are arranged at intervals in a second direction, and the second direction intersects the first direction;

[0100] Step S712: Form a first sacrificial layer between adjacent active strips;

[0101] Step S713: Etch the first sacrificial layer and the active strips to obtain word line trenches extending in the second direction, and divide the plurality of active strips into a plurality of active pillars arranged in an array;

[0102] Step S714: Form a word line gap based on the word line trenches.

[0103] In some embodiments, step S714 of forming a word line gap based on the word line trenches includes:

[0104] Step S7141: Form a second sacrificial layer on the sidewalls and bottom of the word line trenches;

[0105] Step S7142: Form a word line isolation structure in the word line trenches;

[0106] Step S7143: Remove a part of the first sacrificial layer and a part of the second sacrificial layer, so that the upper surfaces of the remaining first sacrificial layer and the second sacrificial layer are both lower than the upper surfaces of the word line isolation structure and the active pillars;

[0107] Step S7144: Form a dielectric protection layer, and the dielectric protection layer covers the upper surfaces of the active pillars, the upper surface of the first sacrificial layer, and the upper surface of the second sacrificial layer;

[0108] Step S7145: Remove the dielectric protection layer located on the upper surface of the active pillars and on the upper surface of the first sacrificial layer;

[0109] Step S7146: Remove at least part of the first sacrificial layer and at least part of the second sacrificial layer to form a word line gap.

[0110] In some embodiments, the word line gap includes a word line groove and a word line slit extending in the second direction, and the word line groove is located between adjacent active pillars along the second direction; step S7146 of removing at least part of the first sacrificial layer and the located at least part of the second sacrificial layer to form a word line gap includes:

[0111] Step S71461: Remove at least part of the first sacrificial layer to form a word line groove, and the word line groove exposes the second sacrificial layer on opposite sides of the word line isolation structure;

[0112] Step S71462: Remove at least a part of the second sacrificial layer on opposite sides of the word line isolation structure to form a word line gap, and the word line gap communicates with the word line groove.

[0113] In some embodiments, after forming the word line, i.e., step S70, the manufacturing method further includes:

[0114] Step S80: Form a covering dielectric layer that covers the upper surface of the active pillar, the upper surface of the dielectric protection layer, and the upper surface of the word line.

[0115] It should be understood that although Figure 1 each step in the flowchart is shown sequentially according to the indication of the arrow, these steps are not necessarily executed sequentially according to the order indicated by the arrow. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limitation, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0116] To more clearly illustrate the manufacturing method of the storage unit provided in the above embodiments, please refer to the following in combination with Figures 2 to 15 to understand some embodiments of the present application.

[0117] The present application does not specifically limit the constituent materials of the first substrate 10 and the second substrate 20. As an example, the first substrate 10 and the second substrate 20 can be made of semiconductor materials, insulating materials, conductor materials, or any combination of their material types. The first substrate 10 and the second substrate 20 can be a single-layer structure or a multi-layer structure. For example, the first substrate 10 and the second substrate 20 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the first substrate 10 and the second substrate 20 can be a laminated substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI), or a silicon germanium-on-insulator.

[0118] It should be noted that the first direction is the Figure 2 Y direction shown in Figure 2The X direction shown in the figure, the first direction intersects with the second direction, and both are perpendicular to the thickness direction of the first substrate 10, and the thickness direction of the first substrate 10 is Figure 2 the Z direction shown in the figure.

[0119] As Figure 2 shown, in step S10, the first substrate 10 is provided.

[0120] As Figure 3 shown, in step S20, a bottom dielectric layer 101 is formed on the upper surface of the first substrate 10. The bottom dielectric layer 101 can be used for isolation between the first substrate 10 and the subsequent structure, thereby reducing leakage current.

[0121] Exemplarily, the bottom dielectric layer 101 can be a silicon oxide layer.

[0122] Exemplarily, in step S20, the upper surface of the first substrate 10 can be processed by a heat treatment process to form the bottom dielectric layer 101, or the bottom dielectric layer 101 can be formed on the upper surface of the first substrate 10 by a deposition process.

[0123] As Figure 4 shown, in step S30, bit line trenches 30 are formed in the bottom dielectric layer 101 and the first substrate 10, and the bit line trenches 30 extend along the first direction.

[0124] Exemplarily, in step S30, a photoresist layer (not shown) can be first formed on the top surface of the bottom dielectric layer 101, and through a series of steps such as exposure and development, a pattern defining the position and shape of the bit line trenches 30 is formed in the photoresist layer, and the bottom dielectric layer 101 and the first substrate 10 are etched based on the pattern of the photoresist layer to form the bit line trenches 30.

[0125] Exemplarily, in step S30, a first hard mask stack (not shown) can also be formed on the bottom dielectric layer 101, and the self-aligned double patterning (SADP) process is used to form the bit line trenches 30 in the bottom dielectric layer 101 and the first substrate 10 based on the first hard mask stack.

[0126] Exemplarily, the first hard mask stack can include a sequentially stacked oxide layer, a polysilicon layer, a first silicon oxynitride layer, a first spin on hard mask (SOH) layer, and a second silicon oxynitride layer, etc.

[0127] It can be understood that the remaining bottom dielectric layer 101 is located between two adjacent bit line trenches 30, and the remaining bottom dielectric layer 101 can be used as a bit line isolation structure, which is beneficial to the mutual isolation between the subsequently formed bit lines BL.

[0128] As shown Figure 5 in FIG. 3, in step S40, a bit line BL is formed in the bit line trench 30.

[0129] It can be understood that the bit line trench 30 is a trench provided for embedding the bit line BL, and one bit line BL is disposed in one bit line trench 30. A plurality of bit line trenches 30 are arranged at intervals in sequence along the second direction, and each bit line trench 30 extends along the first direction. Therefore, a plurality of bit lines BL are arranged at intervals in sequence along the second direction, and each bit line BL extends along the first direction to respectively control the transistors corresponding to different rows formed subsequently.

[0130] Exemplarily, the constituent material of the bit line BL includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes tungsten silicide (WSi); the metal can be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN). For example, ruthenium, tungsten, gold, or silver all belong to low-resistance metals, which can reduce the resistance of the bit line BL and improve the operation speed of the device.

[0131] Exemplarily, step S40 may further include the following steps:

[0132] Step S41: Form a stacked oxide layer (not shown), an adhesion layer (not shown), and a first barrier layer (not shown). The first barrier layer conformally covers the surface of the bit line trench 30 and is located between the bit line BL and the adhesion layer. Thus, the oxide layer can reduce the leakage risk between the bit lines, the adhesion layer can increase the adhesion between the bit line BL and the first substrate 10 to each other, and the first barrier layer can effectively prevent the diffusion between the bit line BL and the first substrate 10 to each other.

[0133] Exemplarily, in step S41, the oxide layer, the adhesion layer, and the first barrier layer may be formed by atomic layer deposition process. Since the atomic layer deposition process has excellent conformality and uniformity when depositing on a three-dimensional complex surface, a uniform oxide layer, adhesion layer, and first barrier layer can be formed on the surface of the bit line trench 30, improving the step coverage and conformal coverage.

[0134] Exemplarily, the first barrier layer includes one of a titanium nitride (TiN) layer and a tantalum nitride (TaN) layer, and the adhesion layer includes a metal layer. For example, the metal layer may include one of a titanium (Ti) layer, a cobalt (Co) layer, a nickel (Ni) layer, and a tantalum (Ta) layer.

[0135] Exemplarily, a second barrier layer (not shown) can also be added outside the adhesive layer, which can prevent the metal in the adhesive layer from diffusing into the first substrate 10 during subsequent thermal processes to form a high-resistance region, and thus is more conducive to reducing the contact resistance between the first substrate 10 and the bit line BL.

[0136] In some embodiments, the thickness of the second barrier layer is less than the thickness of the adhesive layer.

[0137] It can be understood that the smaller thickness of the second barrier layer can not only prevent the metal in the adhesive layer from diffusing into the first substrate 10 during subsequent thermal processes to form a high-resistance region, but also avoid affecting the adhesion of the adhesive layer.

[0138] In some embodiments, the material of the second barrier layer is the same as that of the first barrier layer. Since the material of the second barrier layer is the same as that of the first barrier layer, it can be formed by the same process, which is simple and convenient.

[0139] Exemplarily, the metal in the second barrier layer is the same as the metal in the adhesive layer, which is beneficial to the lattice matching between the second barrier layer and the adhesive layer.

[0140] As Figure 6 shown, in step S50 and step S60, a second substrate 20 is provided and the second substrate 20 is bonded to the upper surface of the bottom dielectric layer 101.

[0141] In some embodiments, the second substrate 20 includes a doped substrate; step S50 of providing the second substrate 20 includes:

[0142] Step S51: Provide an initial substrate (not shown);

[0143] Step S52: Dope the initial substrate;

[0144] Step S53: Perform a first annealing process on the doped initial substrate to obtain the second substrate 20.

[0145] It can be understood that, in order to reduce the contact resistance, usually two methods can be adopted. Among them, the first method is to form an ohmic contact by selecting the work function difference between the metal and the semiconductor. However, research shows that the barrier height is almost independent of the work function difference, so the feasibility of the above method is relatively poor. The second method is to change the barrier width so that electrons or holes can tunnel. Since in a PN junction, the width of the space charge region depends on the doping concentration, therefore, by doping and annealing the initial substrate, a doped second substrate 20 is obtained, that is, the ohmic contact region between the second substrate 20 and the bit line BL is heavily doped, so that the barrier width becomes narrower, and electrons or holes can easily tunnel or be thermally excited under the drive of voltage, thereby reducing the contact resistance between the second substrate 20 and the bit line BL.

[0146] Exemplarily, the doping concentration of the second substrate 20 gradually increases in the direction close to the bit line BL. Therefore, the doping concentration of a part of the second substrate 20 close to the bit line BL is relatively large, which can more effectively reduce the contact resistance between the second substrate 20 and the bit line BL.

[0147] For example, in step S52, a phosphorus doped epitaxial process can be used to dope the initial substrate. The incorporation of phosphorus atoms increases the free electron concentration of the material. The process of phosphorus doped epitaxy is usually to introduce a phosphorus compound gas (such as triphosphide) into the epitaxial reaction chamber, decompose it at high temperature and deposit it on the initial substrate. In this way, phosphorus atoms can be incorporated into the initial substrate, thereby changing the conductivity of the material and more effectively reducing the contact resistance.

[0148] Exemplarily, in step S60, the second substrate 20 can be bonded to the upper surface of the bottom dielectric layer 101 by a hybrid bonding process. In the hybrid bonding process, in addition to the metal film layer that sinks at room temperature to complete the bonding, the other non-conductive parts of the two substrates facing each other also need to be adhered. Therefore, the structure formed by the hybrid bonding process has no voids between die and die or wafer and wafer, and does not need to be filled with epoxy resin. The hybrid bonding process is simple and environmentally friendly, and the obtained structure has good quality.

[0149] In some embodiments, after bonding the second substrate 20 to the surface of the bottom dielectric layer 101 away from the first substrate 10, that is, after step S60 and before forming the word line WL in the second substrate 20, that is, step S70, it further includes:

[0150] Step S600: Thinning the second substrate 20.

[0151] In some embodiments, the thinning process of the second substrate 20 includes:

[0152] Step S601: Ion implant from the upper surface of the second substrate 20 into the second substrate 20;

[0153] Step S602: Perform a second annealing process on the obtained structure;

[0154] Step S603: Thinning the second substrate 20 after the second annealing process by using a chemical mechanical polishing process and / or a wet etching process.

[0155] It should be noted that steps S601 to S603 can be repeatedly executed until the second substrate 20 is thinned to a preset thickness.

[0156] Exemplarily, the preset thickness of the second substrate 20 is 180 nm to 220 nm, such as 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, etc.

[0157] In some embodiments, step S70, forming a word line WL in the second substrate 20, includes:

[0158] Step S71: As Figures 7 to 13 shown, form a word line gap 40 in the second substrate 20;

[0159] Step S72: As Figure 14 shown, form a word line WL in the word line gap 40.

[0160] In some embodiments, step S71, forming a word line gap 40 in the second substrate 20, includes:

[0161] Step S711: As Figure 7 shown, etch the second substrate 20 to obtain a plurality of active strips 21 extending in a first direction, and the plurality of active strips 21 are arranged at intervals in a second direction, and the second direction intersects the first direction;

[0162] Step S712: As Figure 8 shown, form a first sacrificial layer 51 between adjacent active strips 21;

[0163] Step S713: As Figure 8 shown, etch the first sacrificial layer 51 and the active strips 21 to obtain a word line trench 40a extending in the second direction, and divide the plurality of active strips 21 into a plurality of active pillars 22 arranged in an array;

[0164] Step S714: As Figures 9 to 13 shown, form a word line gap 40 based on the word line trench 40a.

[0165] Exemplarily, the active pillar 22 includes a drain (not shown), a channel layer (not shown), and a source (not shown) sequentially arranged from bottom to top. The drain is electrically connected to the bit line BL, so as to further form a transistor with a vertical channel. Using a transistor with a vertical channel can further miniaturize the semiconductor device.

[0166] Exemplarily, the doping concentration of the active pillar 22 gradually increases in the direction close to the bit line BL. Therefore, the doping concentration of the drain is relatively high, which can more effectively reduce the contact resistance between the active pillar 22 and the bit line BL.

[0167] In some embodiments, step S714 of forming the word line gap 40 based on the word line trench 40a includes:

[0168] Step S7141: As Figure 9 shown, a second sacrificial layer 52 is formed on the sidewalls and bottom of the word line trench 40a;

[0169] Step S7142: As Figure 9 shown, a word line isolation structure 41 is formed in the word line trench 40a;

[0170] Step S7143: As Figure 10 shown, a part of the first sacrificial layer 51 and a part of the second sacrificial layer 52 are removed, so that the upper surfaces of the remaining first sacrificial layer 51 and the second sacrificial layer 52 are both lower than the upper surfaces of the word line isolation structure 41 and the active pillar 22;

[0171] Step S7144: As Figure 11 shown, a dielectric protection layer 42 is formed, and the dielectric protection layer 42 covers the upper surface of the active pillar 22, the upper surface of the first sacrificial layer 51, and the upper surface of the second sacrificial layer 52;

[0172] Step S7145: As Figure 12 shown, the dielectric protection layer 42 located on the upper surface of the active pillar 22 and on the upper surface of the first sacrificial layer 51 is removed;

[0173] Step S7146: As Figure 13 shown, at least a part of the first sacrificial layer 51 and at least a part of the second sacrificial layer 52 are removed to form the word line gap 40.

[0174] Exemplarily, in step S7141, the second sacrificial layer 52 also covers the top surface of the active pillar 22 and the top surface of the first sacrificial layer 51. Step S7142 includes filling a word line isolation material layer 411 in the word line trench 40a. The word line isolation material layer 411 covers the second sacrificial layer 52, and the word line isolation material layer 411 and the second sacrificial layer 52 are etched back until the top surface of the active pillar 22 is exposed. The remaining word line isolation material layer 411 constitutes the word line isolation structure 41.

[0175] Exemplarily, in step S7143, the upper surface of the reserved first sacrificial layer 51 and the upper surface of the second sacrificial layer 52 are flush with each other and both are flush with the top surface of the channel layer.

[0176] Exemplarily, in step S7144, the dielectric protection layer 42 conformally covers the upper surface of the active pillar 22, the upper surface of the first sacrificial layer 51, and the upper surface of the second sacrificial layer 52, so that in step S7145, after removing the dielectric protection layer 42 located on the upper surface of the active pillar 22 and on the upper surface of the first sacrificial layer 51, the top surface of the active pillar 22 and the top surface of the first sacrificial layer 51 can be exposed simultaneously.

[0177] In some embodiments, the word line gap 40 includes a word line groove 401 and a word line slit 402 extending along the second direction. The word line groove 401 is located between adjacent active pillars 22 along the second direction; step S7146, removing at least part of the first sacrificial layer 51 and at least part of the second sacrificial layer 52 located on opposite sides of the word line isolation structure 41 to form the word line gap 40, includes:

[0178] Step S71461: Removing at least part of the first sacrificial layer 51 to form the word line groove 401, and the word line groove 401 exposes the second sacrificial layer 52 located on opposite sides of the word line isolation structure 41;

[0179] Step S71462: Removing at least part of the second sacrificial layer 52 located on opposite sides of the word line isolation structure 41 to form the word line slit 402, and the word line slit 402 communicates with the word line groove 401.

[0180] Exemplarily, in step S71461 and step S71462, removing at least part of the first sacrificial layer 51 and removing at least part of the second sacrificial layer 52 located on opposite sides of the word line isolation structure 41 can be completed based on a single etching process. For example, a single wet etching process can be used to simultaneously remove at least part of the first sacrificial layer 51 and remove at least part of the second sacrificial layer 52 located on opposite sides of the word line isolation structure 41 to form the word line slit 402.

[0181] It can be understood that the word line slit 402 communicates with the word line groove 401, so that the word line gap 40 can expose the periphery of the active pillar 22, which is beneficial to further forming a transistor with a fully surrounding channel (Channel-All-Around, abbreviated as CAA) structure subsequently, thereby saving the structural size, increasing the distribution density, and increasing the storage density of the device.

[0182] Such as Figure 14As shown, in step S72, a conductive material can be filled in the word line groove 401 and the word line gap 402 simultaneously to form the word line WL.

[0183] Exemplarily, the material of the word line WL is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicon nitride or a combination thereof.

[0184] Exemplarily, after forming the word line gap 402, i.e., step S71, and before forming the word line WL, i.e., step S72, the following steps can further be included:

[0185] Step S710: Form a word line dielectric layer (not shown) on the exposed surfaces of the word line groove 401 and the word line gap 402.

[0186] Exemplarily, the material of the word line dielectric layer can include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanate (SrTiO3).

[0187] In some embodiments, after forming the word line WL, i.e., step S70, the preparation method further includes:

[0188] Step S80: As Figure 15 shown, form a covering dielectric layer 60 that covers the upper surface of the active pillar 22, the upper surface of the dielectric protection layer 42 and the upper surface of the conductive pillar.

[0189] Please refer to Figure 15 , according to some embodiments, the present application further provides a semiconductor structure, which includes a first substrate 10, a bottom dielectric layer 101, a bit line BL, a second substrate 20 and a word line WL; the bottom dielectric layer 101 is formed on the upper surface of the first substrate 10; the bit line BL is formed in the bottom dielectric layer 101 and the first substrate 10, and the bit line BL extends along a first direction; the second substrate 20 is bonded to the upper surface of the bottom dielectric layer 101; the word line WL is formed in the second substrate 20.

[0190] It should be noted that the semiconductor structure can be prepared by using the preparation method of the semiconductor structure provided in the above some embodiments. Therefore, the beneficial effects possessed by the above embodiments are also possessed by the semiconductor structure, which will not be elaborated herein.

[0191] In some embodiments, the second substrate 20 includes a doped substrate. It can be understood that the barrier width of the ohmic contact region between the doped substrate and the bit line BL becomes narrower, and electrons or holes can easily tunnel or be thermally excited under the drive of voltage, thereby reducing the contact resistance between the second substrate 20 and the bit line BL.

[0192] In some embodiments, a plurality of active pillars 22 arranged in an array are included in the second substrate 20; the semiconductor structure further includes a word line isolation structure 41 and a dielectric protection layer 42; the word line isolation structure 41 is at least located between the adjacent active pillars 22 along the first direction; the dielectric protection layer 42 at least covers the upper sidewall surface of the active pillars 22.

[0193] In some embodiments, the semiconductor structure further includes a covering dielectric layer 60, and the covering dielectric layer covers the upper surface of the active pillars 22, the upper surface of the dielectric protection layer 42, and the upper surface of the word line WL.

[0194] In some embodiments, a first barrier layer, an adhesive layer, and a second barrier layer are sequentially stacked between the first substrate 10 and the bit line BL.

[0195] Exemplarily, the thickness of the first barrier layer (not shown) is 2 nm to 3 nm, such as 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, etc. The thickness of the adhesive layer is 2 nm to 6 nm, such as 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, etc.

[0196] Exemplarily, the thickness of the second barrier layer is 40% to 80% of the thickness of the adhesive layer, such as 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, etc.

[0197] It can be understood that the thickness of the second barrier layer being 40% to 80% of the thickness of the adhesive layer can both prevent the second barrier layer from being too thin to prevent the metal in the adhesive layer from diffusing into the first substrate 10 during subsequent thermal processes to form a high-resistance region, and prevent the second barrier layer from being too thick to affect the adhesion of the adhesive layer.

[0198] For example, the thickness of the second barrier layer is 1 nm to 2 nm, such as 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm.

[0199] In the above embodiments, the thickness of the second barrier layer being 1 nm to 2 nm can provide an appropriate barrier effect on the adhesion layer, such that the adhesion layer just breaks through the second barrier layer to contact the surface of the first substrate 10 during subsequent thermal processes. The adhesion layer can both play an adhesion role and not diffuse into the first substrate 10 to increase the contact resistance.

[0200] Exemplarily, the thickness of the adhesive layer 43 is 2 nm to 3 nm, such as 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, 3 nm, etc.

[0201] Exemplarily, the thickness of the first barrier layer 42 is 0.5 nm to 1.5 nm, such as 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, etc.

[0202] Exemplarily, the active column 22 includes a drain (not shown), a channel layer (not shown), and a source (not shown) sequentially arranged from bottom to top. The drain is electrically connected to the bit line BL. The active column 22 and the word line WL covering the sidewall of the channel layer can form a transistor, so as to further form a transistor with a vertical channel. Using a transistor with a vertical channel can further miniaturize the semiconductor device.

[0203] It can be understood that the channel layer, as the active area (Active Area, abbreviated as AA), can be a P-type active area or an N-type active area. When the second substrate 20 includes a P-type substrate, the channel layer is a P-type active area, and the source and drain are formed by implanting N-type ions, thereby forming a Negative channel Metal Oxide Semiconductor (NMOS) device. When the substrate 10 includes an N-type substrate, the channel layer is an N-type active area, and the source and drain are formed by implanting P-type ions, thereby forming a Positive channel Metal Oxide Semiconductor (PMOS) device. As an example, the P-type ions can include but are not limited to any one or several of boron ions, gallium ions, indium ions, etc., and the N-type ions can include but are not limited to one or several of phosphorus ions, arsenic ions, or ions, etc.

[0204] Exemplarily, the doping concentration of the active column 22 gradually increases in the direction close to the bit line BL. Therefore, the doping concentration of the drain is relatively high, which can more effectively reduce the contact resistance between the active column 22 and the bit line BL.

[0205] For example, the dimension of the drain in the substrate thickness direction is 400 Å to 500 Å, such as 400 Å, 410 Å, 420 Å, 430 Å, 440 Å, 450 Å, 460 Å, 470 Å, 480 Å, 490 Å, 500 Å, etc. The dimension of the channel layer in the substrate thickness direction is 550 Å to 650 Å, such as 550 Å, 560 Å, 570 Å, 580 Å, 590 Å, 600 Å, 610 Å, 620 Å, 630 Å, 640 Å, 650 Å, etc. The dimension of the source in the substrate thickness direction is 400 Å to 500 Å, such as 400 Å, 410 Å, 420 Å, 430 Å, 440 Å, 450 Å, 460 Å, 470 Å, 480 Å, 490 Å, 500 Å, etc.

[0206] In some embodiments, a memory is provided, including the above semiconductor structure.

[0207] In some embodiments, an electronic device is provided, including the above memory. Since a memory with better performance and reliability is adopted, the electronic device of this embodiment has more beneficial performance and higher reliability.

[0208] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0209] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0210] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, the preparation method includes: providing a first substrate; forming a bottom dielectric layer on the upper surface of the first substrate; forming bit line trenches in the bottom dielectric layer and the first substrate, the bit line trenches extending along a first direction; forming bit lines in the bit line trenches; providing a second substrate; bonding the second substrate to the upper surface of the bottom dielectric layer; forming word lines in the second substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, the second substrate includes a doped substrate; the providing of the second substrate includes: providing an initial substrate; doping the bottom surface of the initial substrate; performing a first annealing process on the doped initial substrate to obtain the second substrate.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, after bonding the second substrate to the upper surface of the bottom dielectric layer and before forming word lines in the second substrate, further includes: thinning the second substrate.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, the thinning of the second substrate includes: performing ion implantation into the second substrate from its upper surface; performing a second annealing process on the obtained structure; thinning the second substrate after the second annealing process by using a chemical mechanical polishing process and / or a wet etching process.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, the forming of word lines in the second substrate includes: forming word line gaps in the second substrate; forming the word lines in the word line gaps.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, the forming of word line gaps in the second substrate includes: etching the second substrate to obtain a plurality of active strips extending along the first direction, the plurality of active strips being spaced apart along a second direction, the second direction intersecting the first direction; forming a first sacrificial layer between adjacent active strips; etching the first sacrificial layer and the active strips to obtain word line trenches extending along the second direction and dividing the plurality of active strips into a plurality of active pillars arranged in an array; forming the word line gaps based on the word line trenches.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, the forming of the word line gaps based on the word line trenches includes: forming a second sacrificial layer on the sidewalls and bottom of the word line trenches; forming a word line isolation structure in the word line trenches; removing part of the first sacrificial layer and part of the second sacrificial layer such that the upper surfaces of the remaining first sacrificial layer and the second sacrificial layer are both lower than the upper surfaces of the word line isolation structure and the active pillars; forming a dielectric protection layer that covers the upper surfaces of the active pillars, the upper surface of the first sacrificial layer, and the upper surface of the second sacrificial layer; Remove the dielectric protection layer located on the upper surface of the active pillar and on the upper surface of the first sacrificial layer; Remove at least part of the first sacrificial layer and at least part of the second sacrificial layer to form the word line gap.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein, the word line gap includes a word line groove and a word line slit extending along the second direction, and the word line groove is located between the active pillars adjacent along the second direction; the removing at least part of the first sacrificial layer and at least part of the second sacrificial layer to form the word line gap includes: removing at least part of the first sacrificial layer to form the word line groove, and the word line groove exposes the second sacrificial layer located on opposite sides of the word line isolation structure; removing at least part of the second sacrificial layer located on opposite sides of the word line isolation structure to form the word line slit, and the word line slit communicates with the word line groove.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein, after forming the word line, further includes: forming a covering dielectric layer, and the covering dielectric layer covers the upper surface of the active pillar, the upper surface of the dielectric protection layer and the upper surface of the word line.

10. A semiconductor structure, wherein, includes: a first substrate; a bottom dielectric layer formed on the upper surface of the first substrate; a bit line formed in the bottom dielectric layer and the first substrate, and the bit line extends along a first direction; a second substrate bonded to the upper surface of the bottom dielectric layer; a word line formed in the second substrate.

11. The semiconductor structure according to claim 10, wherein, the second substrate includes a doped substrate.

12. The semiconductor structure according to claim 10 or 11, wherein, the second substrate includes a plurality of active pillars arranged in an array; the semiconductor structure further includes: a word line isolation structure located at least between the active pillars adjacent along the first direction; a dielectric protection layer covering at least the upper sidewall surface of the active pillar.

13. The semiconductor structure according to claim 12, wherein, further includes: a covering dielectric layer covering the upper surface of the active pillar, the upper surface of the dielectric protection layer and the upper surface of the word line.

14. A memory, wherein, includes: the semiconductor structure according to any one of claims 10-13.

15. An electronic device, wherein, includes: the memory according to claim 14.

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