Semiconductor structure and forming method thereof

Abstract

The invention relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the storage unit is located on the substrate and comprises a transistor area and a capacitor area, the storage unit further comprises oxide semiconductor layers continuously distributed in the transistor area and the capacitor area, the oxide semiconductor layer in the transistor area serves as an active layer of a transistor, and the oxide semiconductor layer in the capacitor area serves as a capacitor. The oxide semiconductor layer in the capacitance area is used as a lower electrode layer of the capacitor, and the resistance of the lower electrode layer is lower than that of the active layer. The manufacturing process of the semiconductor structure is simplified, and the manufacturing yield of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in electronic devices such as computers. It is composed of multiple memory cells, and each memory cell usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that data information stored in the capacitor can be read through the bit line, or data information can be written into the capacitor.

[0003] Semiconductor structures such as DRAM mostly adopt a 6F2 layout and a manufacturing process of buried word lines. However, with the further miniaturization of the size of semiconductor structures such as DRAM, the performance of the semiconductor structure will be greatly reduced. In order to meet the requirements of continuous shrinking of the size of semiconductor structures such as DRAM and continuous increase of the storage capacity, semiconductor structures such as DRAM with a three-dimensional stacked structure have emerged as the times require. However, the current process for manufacturing semiconductor structures such as DRAM with a three-dimensional stacked structure is relatively complex. For example, the formation processes of transistors and capacitors in DRAM are carried out separately, the operation is relatively cumbersome, and the steps are relatively complex, resulting in a reduction in the manufacturing yield and production efficiency of the semiconductor structure.

[0004] Therefore, how to simplify the manufacturing process of the semiconductor structure and improve the performance of the semiconductor structure at the same time is a technical problem to be solved urgently at present. Summary of the Invention

[0005] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, which are used to simplify the manufacturing process of the semiconductor structure and improve the performance of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a semiconductor structure, including:

[0007] A substrate;

[0008] A memory cell, located on the substrate, including a transistor region and a capacitor region. The memory cell further includes an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer in the transistor region serves as the active layer of the transistor, and the oxide semiconductor layer in the capacitor region serves as the lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than that of the active layer.

[0009] In some embodiments, the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, both extending along a first direction and arranged at intervals along a second direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction;

[0010] The first oxide semiconductor layer in the transistor region serves as a first active layer, the second oxide semiconductor layer in the transistor region serves as a second active layer, and the first active layer and the second active layer together constitute the active layer;

[0011] The first oxide semiconductor layer in the capacitor region serves as a first lower electrode layer, the second oxide semiconductor layer in the capacitor region serves as a second lower electrode layer, and the first lower electrode layer and the second lower electrode layer together constitute the lower electrode layer.

[0012] In some embodiments, a projection of the first active layer on the top surface of the substrate, a projection of the second active layer on the top surface of the substrate, a projection of the first lower electrode layer on the top surface of the substrate, and a projection of the second lower electrode layer on the top surface of the substrate are all L-shaped.

[0013] In some embodiments, the transistor further includes a gate structure, the gate structure including a first gate layer and a second gate layer, the first gate layer is located between the first active layer and the second active layer, and the second gate layer is located on a side of the first active layer away from the first gate layer and a side of the second active layer away from the first gate layer;

[0014] The capacitor also includes a dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer, the upper electrode layer includes a first upper electrode layer and a second upper electrode layer electrically connected to each other, the first upper electrode layer is located between the first lower electrode layer and the second lower electrode layer, and the second upper electrode layer is located on a side of the first lower electrode layer facing away from the first upper electrode layer and a side of the second lower electrode layer facing away from the first upper electrode layer.

[0015] In some embodiments, a material of the second upper electrode layer is the same as a material of the second gate layer, and the second upper electrode layer and the second gate layer are disposed in the same layer.

[0016] In some embodiments, it also includes:

[0017] A word line lead-out structure is located above the transistor. The word line lead-out structure includes a first lead-out plug, a second lead-out plug, and a word line lead. One end of the first lead-out plug is electrically connected to the first gate layer, and the other end is electrically connected to the word line lead. One end of the second lead-out plug is electrically connected to the second gate layer, and the other end is electrically connected to the word line lead.

[0018] In some embodiments, the first active layer includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along the first direction. The first lower electrode layer is in contact electrical connection with the first drain region;

[0019] The second active layer includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the first direction. The second lower electrode layer is in contact electrical connection with the second drain region;

[0020] The semiconductor structure further includes bit lines. The bit lines extend along the second direction, and the bit lines are electrically connected to the first source region and the second source region.

[0021] In some embodiments, the number of the memory cells is multiple, and the multiple memory cells are arranged in an array along the second direction and the third direction. The third direction is perpendicular to the top surface of the substrate;

[0022] Multiple bit lines are arranged at intervals along the third direction, and each bit line is electrically connected to the active layer in the multiple memory cells arranged at intervals along the second direction;

[0023] The gate structures in the multiple memory cells arranged at intervals along the third direction are electrically connected.

[0024] In some embodiments, the concentration of oxygen vacancies in the lower electrode layer is greater than the concentration of oxygen vacancies in the active layer.

[0025] According to some other embodiments, the present disclosure further provides a method for forming a semiconductor structure, including the following steps:

[0026] Provide a substrate;

[0027] Form memory cells on the substrate. The memory cells include a transistor region and a capacitor region. The memory cells further include an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer in the transistor region serves as the active layer of the transistor, and the oxide semiconductor layer in the capacitor region serves as the lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than the resistance of the active layer.

[0028] In some embodiments, the specific steps of forming a memory cell on the substrate include:

[0029] Form a stacked layer on the substrate, the stacked layer includes an interlayer isolation layer and a sacrificial layer alternately stacked along a third direction, and the stacked layer includes a transistor region and a capacitor region arranged along a first direction, the first direction being parallel to the top surface of the substrate;

[0030] Form a first trench that penetrates the transistor region and the capacitor region of the stacked layer along the third direction;

[0031] Form an oxide semiconductor layer covering the inner wall of the first trench;

[0032] Reduce the resistance of the oxide semiconductor layer in the capacitor region to form an active layer in the transistor region and a lower electrode layer in the capacitor region.

[0033] In some embodiments, the specific steps of forming a first trench that penetrates the transistor region and the capacitor region of the stacked layer along the third direction include:

[0034] Remove the sacrificial layer in the capacitor region to form a second trench between adjacent interlayer isolation layers in the capacitor region;

[0035] Form a first isolation layer filling the second trench;

[0036] Etch the stacked layer and the first isolation layer to form a first trench that penetrates the transistor region and the capacitor region of the stacked layer along the third direction and penetrates the first isolation layer along the third direction.

[0037] In some embodiments, the specific steps of reducing the resistance of the oxide semiconductor layer in the capacitor region include:

[0038] Treat the oxide semiconductor layer in the capacitor region with plasma to increase the oxygen vacancies in the oxide semiconductor layer in the capacitor region; or;

[0039] Inject doping ions into the oxide semiconductor layer in the capacitor region to enhance the conductivity of the oxide semiconductor layer in the capacitor region.

[0040] In some embodiments, the specific steps of forming an active layer in the transistor region and a lower electrode layer in the capacitor region include:

[0041] Remove the oxide semiconductor layer between adjacent sacrificial layers, and the remaining oxide semiconductor layers in the capacitor region form a plurality of initial lower electrode layers arranged at intervals along the third direction, and the remaining oxide semiconductor layers in the transistor region form a plurality of initial active layers arranged at intervals along the third direction;

[0042] Divide the initial lower electrode layer and the initial active layer to form a lower electrode layer including a first lower electrode layer and a second lower electrode layer distributed at intervals along the second direction, and form an active layer including a first active layer and a second active layer distributed at intervals along the second direction, where the second direction is parallel to the top surface of the substrate, and the second direction intersects with the first direction.

[0043] In some embodiments, after forming a lower electrode layer including a first lower electrode layer and a second lower electrode layer distributed at intervals along the second direction, and forming an active layer including a first active layer and a second active layer distributed at intervals along the second direction, the following steps are further included:

[0044] Form a dielectric layer covering the first lower electrode layer and the second lower electrode layer, and form a gate dielectric layer covering the first active layer and the second active layer;

[0045] Form an upper electrode layer covering the dielectric layer, and form a gate structure covering the gate dielectric layer to form the capacitor including the lower electrode layer, the dielectric layer and the upper electrode layer, and form the transistor including the first active layer, the second active layer, the gate dielectric layer and the gate structure.

[0046] Some embodiments of the present disclosure provide a semiconductor structure and a method for forming the same. By providing an oxide semiconductor layer continuously distributed in a transistor region and a capacitor region in a storage unit, using the oxide semiconductor layer in the transistor region as the active layer of the transistor, using the oxide semiconductor layer in the capacitor region as the lower electrode layer of the capacitor, and making the resistance of the lower electrode layer lower than that of the active layer, part of the manufacturing process of the transistor and part of the manufacturing process of the capacitor can be synchronized, simplifying the manufacturing process of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure. Some other embodiments of the present disclosure improve the conductivity of the oxide semiconductor layer used to form the lower electrode layer by using a resistance reduction treatment, so that while ensuring good conductivity of the lower electrode layer, the resistance value of the lower electrode layer can be flexibly adjusted, which helps to further improve the performance of the semiconductor structure and improve the manufacturing yield of the semiconductor structure. Description of the Drawings

[0047] Appendix Figure 1It is a top view schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure;

[0048] Attached Figure 2 It is a three-dimensional schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure;

[0049] Attached Figure 3 It is a flowchart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure;

[0050] Attached Figure 4 - Attached Figure 18 It is a schematic diagram of the main process structure in the process of forming a semiconductor structure in a specific embodiment of the present disclosure. Specific embodiment

[0051] The following will describe in detail the specific embodiments of the semiconductor structure and its forming method provided by the present disclosure with reference to the accompanying drawings.

[0052] This specific embodiment provides a semiconductor structure, attached Figure 1 It is a top view schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure, attached Figure 2 It is a three-dimensional schematic diagram of a semiconductor structure in a specific embodiment of the present disclosure. As Figure 1 and Figure 2 shown, the semiconductor structure includes:

[0053] A substrate 71;

[0054] A memory cell, located on the substrate 71, includes a transistor region and a capacitor region. The memory cell further includes an oxide semiconductor layer 80 continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer 80 in the transistor region serves as the active layer 19 of the transistor 17, and the oxide semiconductor layer 80 in the capacitor region serves as the lower electrode layer 29 of the capacitor 18. The resistance of the lower electrode layer 29 is lower than the resistance of the active layer 19.

[0055] The semiconductor structure described in this specific embodiment may be, but is not limited to, DRAM. This specific embodiment takes the semiconductor structure as DRAM as an example for illustration. The substrate 71 may be, but is not limited to, a silicon substrate. This specific embodiment takes the substrate 71 as a silicon substrate as an example for illustration. In other embodiments, the substrate 71 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 71 is used to support the device structure above it, and the top surface of the substrate 71 is the surface of the substrate 71 facing the memory cell. The memory cell is located on the top surface of the substrate 71, and the memory cell includes the transistor 17 located in the transistor region and the capacitor 18 electrically connected to the transistor 17 and located in the capacitor region. When performing a write operation on the memory cell, data can be stored in the capacitor 18 by turning on the transistor 17. When performing a read operation on the memory cell, the data stored in the capacitor 18 can be read by turning on the transistor 17. The transistor 17 includes the active layer 19, and the active layer 19 includes a channel region and source and drain regions distributed on opposite sides of the channel region along the first direction D1. The capacitor 18 is located at the end of the transistor 17 along the first direction D1, and the lower electrode layer 29 is in electrical contact with the end of the active layer 19 along the first direction D1 (for example, the drain region in the active layer 19). Among them, the first direction D1 is parallel to the top surface of the substrate 71. Among them, the material of the oxide semiconductor layer 80 includes oxide semiconductor materials.

[0056] In this specific embodiment, by continuously distributing the oxide semiconductor layer 80 in the transistor region and the capacitor region, and using the oxide semiconductor layer 80 in the transistor region as the active layer 19 of the transistor 17, and the oxide semiconductor layer 80 in the capacitor region as the lower electrode layer 29 of the capacitor 18, the manufacturing process of the active layer 19 in the transistor 17 and the manufacturing process of the lower electrode layer 29 in the capacitor 18 can be synchronized, thereby simplifying the manufacturing process of the memory cell and the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure. Moreover, in this specific embodiment, the oxide semiconductor layer 80 is used as the lower electrode layer 29 and the active layer 19, and the resistance of the lower electrode layer 29 is lower than that of the active layer 19, which not only improves the anti-leakage characteristics of the transistor 17 but also ensures that the lower electrode layer 29 has good electrical conductivity, thereby contributing to further improving the performance of the semiconductor structure and increasing the manufacturing yield of the semiconductor structure. The material of the oxide semiconductor layer 80 in this specific embodiment is In 2 O 3Any one or a combination of two or more of (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxide nitride). In one example, the material of the oxide semiconductor layer 80 is IGZO.

[0057] In one example, the semiconductor structure includes a plurality of the memory cells, and the plurality of the memory cells are arranged in a three-dimensional array along a first direction D1, a second direction D2, and a third direction D3 on the substrate 71, which helps to further increase the storage capacity of the semiconductor structure and helps to further miniaturize the size of the semiconductor structure. Wherein, the second direction D2 is parallel to the top surface of the substrate 71, and the second direction D2 intersects with the first direction D1 (for example, obliquely intersects or perpendicularly intersects), and the third direction D3 is perpendicular to the top surface of the substrate 71.

[0058] In some embodiments, the oxide semiconductor layer 80 includes a first oxide semiconductor layer and a second oxide semiconductor layer that both extend along a first direction D1 and are spaced apart along a second direction D2. The first direction D1 and the second direction D2 are both parallel to the top surface of the substrate 71, and the first direction D1 intersects with the second direction D2;

[0059] The first oxide semiconductor layer in the transistor region serves as a first active layer 101, the second oxide semiconductor layer in the transistor region serves as a second active layer 102, and the first active layer 101 and the second active layer 102 together constitute the active layer 19;

[0060] The first oxide semiconductor layer in the capacitor region serves as a first lower electrode layer 111, the second oxide semiconductor layer in the capacitor region serves as a second lower electrode layer 112, and the first lower electrode layer 111 and the second lower electrode layer 112 together constitute the lower electrode layer 29.

[0061] Specifically, the first active layer 101 is in contact electrical connection with the first lower electrode layer 111, and the second active layer 102 is in contact electrical connection with the second lower electrode layer 112. Moreover, the materials of the first active layer 101, the second active layer 102, the first lower electrode layer 111, and the second lower electrode layer 112 are all composed of the oxide semiconductor layer 80 including an oxide semiconductor material, such that the first active layer 101, the second active layer 102, the first lower electrode layer 111, and the second lower electrode layer 112 are arranged in the same layer. By forming the first active layer 101 and the second active layer 102 which are arranged at intervals along the second direction D2, and the first electrode layer 111 and the second electrode layer 112 which are arranged at intervals along the second direction D2 through the oxide semiconductor layer 80, on the one hand, the surface area of the lower electrode layer 29 can be increased, and further the area of the capacitor 18 including the lower electrode layer 29 can be increased, that is, the storage capacity of the capacitor 18 is increased; on the other hand, it helps to shorten the channel length of the transistor 17, thereby improving the response speed of the transistor 17. In an example, the materials and compositions of the first active layer 101 are the same as those of the second active layer 102, and the materials and compositions of the first lower electrode layer 111 are the same as those of the second lower electrode layer 112.

[0062] In some embodiments, the projections of the first active layer 101, the second active layer 102, the first lower electrode layer 111, and the second lower electrode layer 112 on the top surface of the substrate 71 are all L-shaped.

[0063] For example, as Figure 1 shown, the projections of the first active layer 101 and the second active layer 102 on the top surface of the substrate 71 are both L-shaped, so that the contact area between the first active layer 101 and the second active layer 102 and the bit line 14 can be increased, and the contact resistance between the transistor 17 and the bit line 14 can be reduced, thereby further improving the performance of the semiconductor structure. The projections of the first lower electrode layer 111 and the second lower electrode layer 112 on the top surface of the substrate 71 are both L-shaped, so that the area of the capacitor 18 can be further increased to further improve the storage capacity of the capacitor 18. In an example, as Figure 1As shown, the corner of the L-shaped first active layer 101 is located on the side of the first active layer 101 away from the first lower electrode layer 111, and the corner of the L-shaped first lower electrode layer 111 is located on the side of the first lower electrode layer 111 away from the first active layer 101. The corner of the L-shaped second active layer 102 is located on the side of the second active layer 102 away from the second lower electrode layer 112, and the corner of the L-shaped second lower electrode layer 112 is located on the side of the second lower electrode layer 112 away from the second active layer 102, thereby further simplifying the manufacturing process of the semiconductor structure.

[0064] In some embodiments, the transistor 17 further includes a gate structure, and the gate structure includes a first gate layer 131 and a second gate layer 133. The first gate layer 131 is located between the first active layer 101 and the second active layer 102, and the second gate layer 133 is located on the side of the first active layer 101 away from the first gate layer 131 and on the side of the second active layer 102 away from the first gate layer 131.

[0065] The capacitor 18 further includes a dielectric layer 16 covering the surface of the lower electrode layer 29 and an upper electrode layer covering the surface of the dielectric layer 16. The upper electrode layer includes a first upper electrode layer 151 and a second upper electrode layer 152 that are electrically connected to each other. The first upper electrode layer 151 is located between the first lower electrode layer 111 and the second lower electrode layer 112, and the second upper electrode layer 112 is located on the side of the first lower electrode layer 111 away from the first upper electrode layer 111 and on the side of the second lower electrode layer 112 away from the first upper electrode layer 111.

[0066] For example, such as Figure 1 and Figure 2As shown, the semiconductor structure further includes a first gate dielectric layer 121 covering the first active layer 101 and the second active layer 102, a gate contact layer 132 covering the first gate dielectric layer 121, the first gate layer 131 covering the gate contact layer 132, a second gate dielectric layer 122 covering the first active layer 101 and the second active layer 102, and the second gate layer 133 covering the second gate dielectric layer 122. The first gate dielectric layer 121 and the second gate dielectric layer 122 are distributed on opposite sides of the first active layer 101 and opposite sides of the second active layer 102 along the second direction D2. In this specific embodiment, by dividing the gate structure into the first gate layer 131 and the second gate layer 133, it helps to further improve the gate control performance of the transistor 17. In one example, the materials of the first gate dielectric layer 121 and the second gate dielectric layer 122 are the same, such as oxide materials (e.g., silicon dioxide). The material of the gate contact layer 132 can be polysilicon material, and the gate contact layer 132 is in electrical contact with the first gate layer 131 to further reduce the contact resistance inside the transistor 17. The first upper electrode layer 151 and the second upper electrode layer 152 in the capacitor are electrically connected.

[0067] In some embodiments, the material of the second upper electrode layer 152 is the same as the material of the second gate layer 133, and the second upper electrode layer 152 and the second gate layer 133 are disposed in the same layer, so that the second upper electrode layer 152 and the second gate layer 133 can be formed synchronously, thereby further simplifying the manufacturing process of the semiconductor structure.

[0068] In some embodiments, the semiconductor structure further includes:

[0069] A word line lead-out structure located above the transistor 17. The word line lead-out structure includes a first lead-out plug, a second lead-out plug 26, and a word line lead 28. One end of the first lead-out plug is electrically connected to the first gate layer 131, and the other end is electrically connected to the word line lead 28. One end of the second lead-out plug 26 is electrically connected to the second gate layer 133, and the other end is electrically connected to the word line lead 28.

[0070] Specifically, as Figure 1 and Figure 2As shown, the word line lead-out structure is located above the memory cell along the third direction D3. The word line lead-out structure includes the first lead plug electrically connected to the first gate layer 131, the second lead plug electrically connected to the second gate layer 133, a word line bridge wiring 27 electrically connecting the first lead plug and the second lead plug 26, and a word line lead 28 electrically connected to the word line bridge wiring 27. The word line control signal from the outside is synchronously transmitted to the first lead plug and the second lead plug 26 through the word line lead 28 and the word line bridge wiring 27 in sequence, and then transmitted to the first gate layer 131 by the first lead plug and synchronously transmitted to the second gate layer 133 by the second lead plug 26. Wherein, the third direction D3 is perpendicular to the top surface of the substrate 71.

[0071] In some embodiments, the first active layer 101 includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along the first direction D1. The first lower electrode layer 111 is in contact electrical connection with the first drain region;

[0072] The second active layer 102 includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the first direction D1. The second lower electrode layer 112 is in contact electrical connection with the second drain region;

[0073] The semiconductor structure further includes a bit line 14. The bit line 14 extends along the second direction D2, and the bit line 14 is electrically connected to the first source region and the second source region.

[0074] Specifically, the bit line 14 extends along the second direction D2 and is electrically connected to the first source region and the second source region in the memory cell at the same time. Above the bit line 14, there is also a bit line lead-out structure. The bit line lead-out structure includes a bit line plug 24 and a bit line lead 25. One end of the bit line plug 24 is electrically connected to the bit line 14, and the other end is electrically connected to the bit line lead 25. In an example, both the bit line lead 25 and the word line lead 28 extend along the first direction D1.

[0075] In some embodiments, the number of memory cells is multiple, and the multiple memory cells are arranged in an array along the second direction D2 and the third direction D3. The third direction D3 is perpendicular to the top surface of the substrate 71;

[0076] Multiple bit lines 14 are arranged at intervals along the third direction D3, and each bit line 14 is electrically connected to the active layer 19 in the multiple memory cells arranged at intervals along the second direction D2;

[0077] The gate structures in a plurality of the memory cells arranged at intervals along the third direction D3 are electrically connected.

[0078] For example, the semiconductor structure includes a plurality of the memory cells arranged in a three-dimensional array along the second direction D2 and the third direction D3. A plurality of the bit lines 14 are arranged at intervals along the third direction D3, and each of the bit lines 14 is electrically connected to the active layer 19 in a plurality of the memory cells arranged at intervals along the second direction D2. A plurality of the bit line lead-out structures are respectively electrically connected to the plurality of the bit lines 14 for leading out signals of the plurality of the bit lines 14. The first gate layers 131 in a plurality of the memory cells arranged at intervals along the third direction D3 are electrically connected, and the second gate layers 133 in a plurality of the memory cells arranged at intervals along the third direction D3 are also electrically connected.

[0079] In one example, the semiconductor structure further includes an upper electrode lead-out structure, which includes a third lead-out plug 21, a fourth lead-out plug 22, an upper electrode bridge wiring 20, and an upper electrode lead 23. One end of the third lead-out plug 21 is electrically connected to the first upper electrode layer 151, and the other end is electrically connected to the upper electrode bridge wiring 20. One end of the fourth lead-out plug 22 is electrically connected to the second upper electrode layer 152, and the other end is electrically connected to the upper electrode bridge wiring 20. The upper electrode bridge wiring 20 is electrically connected to the upper electrode lead 23.

[0080] In some embodiments, the concentration of oxygen vacancies in the lower electrode layer 29 is greater than the concentration of oxygen vacancies in the active layer 19. In one example, the metal-oxygen bonds in the oxide semiconductor material in the oxide semiconductor layer 80 (i.e., the lower electrode layer 29) in the capacitor region can be broken by means of plasma treatment or the like, so as to increase the oxygen vacancies in the lower electrode layer 29, thereby reducing the resistance of the lower electrode layer 29 and increasing the conductivity of the lower electrode layer 29. In other embodiments, the conductivity of the lower electrode layer 29 can also be increased by means of ion doping. This specific embodiment increases the conductivity of the lower electrode layer 29 by increasing the concentration of oxygen vacancies or ion doping, so that while ensuring good electrical conductivity of the lower electrode layer, the resistance value of the lower electrode layer can be flexibly adjusted, which helps to further improve the performance of the semiconductor structure and improve the manufacturing yield of the semiconductor structure.

[0081] This specific embodiment also provides a method for forming a semiconductor structure, as shown in Figure 3 the flowchart of the method for forming a semiconductor structure in the specific embodiment of the present disclosure, as shown in Figure 4 - as shown in Figure 18This is a schematic diagram of the main process structure in the process of forming a semiconductor structure according to a specific embodiment of the present disclosure. For the schematic diagram of the semiconductor structure formed by this specific embodiment, reference can be made to Figure 1 and Figure 2 . As Figures 1-18 shown, the method for forming the semiconductor structure includes the following steps:

[0082] Step S31: Provide a substrate 71;

[0083] Step S32: Form a memory cell on the substrate 71. The memory cell includes a transistor region PT and a capacitor region PC. The memory cell further includes an oxide semiconductor layer 80 continuously distributed in the transistor region PT and the capacitor region PC. The oxide semiconductor layer 80 in the transistor region PT serves as the active layer 19 of the transistor 17, and the oxide semiconductor layer 80 in the capacitor region PCT serves as the lower electrode layer 29 of the capacitor 18. The resistance of the lower electrode layer 29 is lower than the resistance of the active layer 19.

[0084] In some embodiments, the specific steps of forming a memory cell on the substrate 71 include:

[0085] Form a stacked layer on the substrate 71. The stacked layer includes an interlayer isolation layer 40 and a sacrificial layer 41 alternately stacked along the third direction D3, and the stacked layer includes a transistor region PT and a capacitor region PC arranged along the first direction D1. The first direction D1 is parallel to the top surface of the substrate 71, as Figure 4 shown;

[0086] Form a first trench 70 that penetrates the transistor region PT and the capacitor region PC of the stacked layer along the third direction D3, as Figure 7 shown, where Figure 7 (a) in is a top view schematic diagram after forming the first trench 70, Figure 7 (b) in is Figure 7 a cross-sectional schematic diagram of (a) in at the A-A position;

[0087] Form an oxide semiconductor layer 80 covering the inner wall of the first trench 70, as Figure 8 shown, where Figure 8 (a) in is a top view schematic diagram after forming the oxide semiconductor layer 80, Figure 8 (b) in is Figure 8 a cross-sectional schematic diagram of (a) in at the A-A position;

[0088] Reduce the resistance of the oxide semiconductor layer 80 of the capacitor region PC, and form the active layer 19 in the transistor region PT and the lower electrode layer 29 in the capacitor region PC.

[0089] In some embodiments, the specific steps of forming the first trench 70 that penetrates the transistor region PT and the capacitor region PC of the stacked layer along the third direction D3 include:

[0090] Remove the sacrificial layer 41 in the capacitor region PC, and form a second trench 50 between adjacent interlayer isolation layers 40 in the capacitor region PC, as Figure 5 shown;

[0091] Form a first isolation layer 60 that fills the second trench 50, as Figure 6 shown;

[0092] Etch the stacked layer and the first isolation layer 60 to form a first trench 70 that penetrates the transistor region PT and the capacitor region PC of the stacked layer along the third direction D3 and penetrates the first isolation layer 60 along the third direction D3, as Figure 7 shown.

[0093] For example, the interlayer isolation layer 40 and the sacrificial layer 41 can be alternately deposited on the top surface of the substrate 71 by chemical vapor deposition process, physical vapor deposition process or atomic layer deposition process to form the stacked layer, as Figure 4 shown. In one example, the material of the interlayer isolation layer 40 can be an oxide material, such as silicon dioxide. The material of the sacrificial layer 41 can be a polysilicon material including doped ions (such as P-type ions), for example, the ion doping concentration is 1×10 21 per cm 3 ~1×10 23 per cm 3 of polysilicon material to enhance the conductivity of the sacrificial layer 41. In one example, after forming the stacked layer, a protective layer 42 is formed above the stacked layer to protect the polysilicon on the topmost layer of the stacked layer. In one example, the material of the protective layer 42 is a nitride material, such as silicon nitride. In one example, the stacked layer further includes a bit line region PB, and the bit line region PB and the capacitor region PC are distributed on opposite sides of the transistor region PT along the first direction D1. Then, a lateral etching process can be used to selectively remove the sacrificial layer 41 in the capacitor region PC of the stacked layer, and a second trench 50 is formed between adjacent interlayer isolation layers 40 in the capacitor region PC, as Figure 5As shown. Next, an insulating dielectric material such as silicon nitride is filled into the second trench 50 to form the first isolation layer 60 in the capacitor region PC between the adjacent interlayer isolation layers 40, as Figure 6 shown. Then, a dry etching process can be used to etch the stacked layer and the first isolation layer 60 to form a first trench 70 that penetrates the transistor region PT and the capacitor region PC of the stacked layer along the third direction D3 and penetrates the first isolation layer 60 along the third direction D3, as Figure 7 shown.

[0094] In one example, after forming the first trench 70, the sacrificial layer 41 on the exposed portion of the sidewall of the first trench 70, so an in-situ steam generation (ISSG) or deposition process can be used to form a second dielectric layer 72 covering the sidewall of the first trench 70 to avoid the impact of subsequent processes on the sacrificial layer 41. In one example, the material of the second dielectric layer 72 is an oxide material, such as silicon dioxide.

[0095] In some embodiments, the specific steps of reducing the resistance of the oxide semiconductor layer 80 in the capacitor region PC include:

[0096] Using plasma to process the oxide semiconductor layer 80 in the capacitor region PC to increase the oxygen vacancies in the oxide semiconductor layer 80 in the capacitor region PC; or;

[0097] Injecting doping ions into the oxide semiconductor layer 80 in the capacitor region PC to enhance the conductivity of the oxide semiconductor layer 80 in the capacitor region PC.

[0098] In one example, after forming the first trench 70 and the second dielectric layer 72 in the first trench 70, an oxide semiconductor material can be deposited on the inner wall of the first trench 70 by chemical vapor deposition, physical vapor deposition or atomic layer deposition processes to form the oxide semiconductor layer 80, as Figure 8 shown. Then, a first filling layer 90 that fills the first trench 70 and covers the oxide semiconductor layer 80 is formed, as Figure 9 shown, where Figure 9 in (a) is a top view schematic diagram after forming the first filling layer 90, Figure 9 in (b) is Figure 9Schematic cross-sectional view of (a) at the A-A position in []. In one example, the first filling layer 90 may be a low-K dielectric material. Then, the first filling layer 90 in the capacitor region PC is removed to expose the oxide semiconductor layer 80 in the capacitor region PC. Next, a resistance reduction treatment is performed on the exposed oxide semiconductor layer 80 in the capacitor region PC. In one example, the resistance reduction treatment is to use plasma to treat the oxide semiconductor layer 80 in the capacitor region PC, so that at least part of the metal-oxygen bonds in the oxide semiconductor layer 80 in the capacitor region PC are broken, thereby reducing the oxygen content in the oxide semiconductor layer 80 in the capacitor region PC and increasing the oxygen vacancies in the oxide semiconductor layer 80 in the capacitor region PC, thereby enhancing the conductivity of the oxide semiconductor layer 80 in the capacitor region PC and forming an initial lower electrode layer 100 in the capacitor region PC. In another example, the resistance reduction treatment is to inject doping ions into the oxide semiconductor layer 80 in the capacitor region PC to enhance the conductivity of the oxide semiconductor layer 80 in the capacitor region PC and form a first oxide semiconductor layer 100 in the capacitor region PC. The remaining oxide semiconductor layer 80 in the transistor region PT that has not undergone the resistance reduction treatment serves as the second oxide semiconductor layer 103, as Figure 10 shown.

[0099] In one example, when removing the first filling layer 90 in the capacitor region PC, the interlayer isolation layer 40 and the first isolation layer 60 between adjacent first trenches 70 in the capacitor region PC are also removed, so as to expose two opposite sidewalls of the oxide semiconductor layer 80 in the capacitor region PC along the second direction D2. While improving the resistance reduction effect of the oxide semiconductor layer 80 in the capacitor region PC, it also helps to increase the storage capacity of the capacitor 18 formed subsequently in the capacitor region PC.

[0100] After performing the resistance reduction treatment on the oxide semiconductor layer 80 in the capacitor region PC, a low-K material is filled again into the first trenches 70 in the capacitor region PC and the gaps between adjacent first trenches 70 to form a second filling layer 110. Then, the first filling layer 90 and the second filling layer 110 in the first trenches 70 are removed, and only the second filling layer 110 between adjacent first trenches 70 in the capacitor region PC is retained, as Figure 11 shown. Among them, Figure 11 (a) in [] is a top view schematic diagram after only retaining the second filling layer 110 between adjacent first trenches 70 in the capacitor region PC by etching, Figure 11 (b) in [] is Figure 11 (a) in [] is a cross-sectional view at the A-A position.

[0101] Next, a lateral etching process can be employed to remove the first oxide semiconductor layer 100 between adjacent sacrificial layers 41. The remaining first oxide semiconductor layer 100 in the capacitor region PC forms a plurality of initial lower electrode layers 201 arranged at intervals along the third direction D3, and the remaining second oxide semiconductor layer 103 in the transistor region PT forms a plurality of initial active layers 202 arranged at intervals along the third direction D3. Refer to Figure 12 .

[0102] In some embodiments, the specific steps of forming the active layer 19 in the transistor region PT and the lower electrode layer 29 in the capacitor region PC include:

[0103] Remove the oxide semiconductor layer 80 between adjacent sacrificial layers 41. The remaining oxide semiconductor layer 80 in the capacitor region PC forms a plurality of initial lower electrode layers 201 arranged at intervals along the third direction D3, and the remaining oxide semiconductor layer 80 in the transistor region PT forms a plurality of initial active layers 202 arranged at intervals along the third direction D3, as Figure 12 shown;

[0104] Divide the initial lower electrode layer 201 and the initial active layer 202 to form a lower electrode layer 29 including a first lower electrode layer 111 and a second lower electrode layer 112 distributed at intervals along the second direction D2, and form an active layer 19 including a first active layer 101 and a second active layer 102 distributed at intervals along the second direction D2. The second direction D2 is parallel to the top surface of the substrate 71, and the second direction D2 intersects the first direction D1.

[0105] In some embodiments, the specific steps of dividing the initial lower electrode layer 201 and the initial active layer 202 include:

[0106] Form a first dielectric layer 120 covering the initial lower electrode layer 201 and the initial active layer 202 in the first trench 70, as Figure 12 shown;

[0107] Form a first conductive material layer 130 filling the first trench 70 and covering the first dielectric layer 120, as Figure 13 shown;

[0108] Form a second isolation layer 142 that penetrates the first dielectric layer 120 and the first conductive material layer 130 along the first direction D1, and form a third isolation layer 141 that penetrates the first dielectric layer 120 and the first conductive material layer 130 along the second direction D2. The second isolation layer 142 separates the initial active layer 202 into a first active layer 101 and a second active layer 102. The second isolation layer 142 also separates the initial lower electrode layer 201 into a first lower electrode layer 111 and a second lower electrode layer 112. The third isolation layer 141 separates the first dielectric layer 120 into a second gate dielectric layer 122 covering the first active layer and a dielectric layer 16 covering the first lower electrode layer 111. The third isolation layer 141 also separates the first conductive material layer 130 into a second gate layer 133 located on the second gate dielectric layer 122 and a second upper electrode layer 152 located on the dielectric layer 16, as Figure 14 shown.

[0109] In some embodiments, after forming a lower electrode layer 29 including a first lower electrode layer 111 and a second lower electrode layer 112 spaced apart along the second direction D2, and forming an active layer 19 including a first active layer 101 and a second active layer 102 spaced apart along the second direction D2, the following steps are further included:

[0110] Form a dielectric layer covering the first lower electrode layer 111 and the second lower electrode layer 112, and form a gate dielectric layer covering the first active layer 101 and the second active layer 102;

[0111] Form an upper electrode layer covering the dielectric layer, and form a gate structure covering the gate dielectric layer to form the capacitor 28 including the lower electrode layer 29, the dielectric layer, and the upper electrode layer, and form the transistor 17 including the first active layer 101, the second active layer 102, the gate dielectric layer, and the gate structure.

[0112] Specifically, the initial active layer 202 in each of the first trenches 70 is separated into the first active layer 101 and the second active layer 102 arranged along the second direction D2, and the initial lower electrode layer 201 in each of the first trenches 70 is separated into the first lower electrode layer 111 and the second lower electrode layer 112 arranged along the second direction D2. The first conductive material layer 130 in each of the first trenches 70 is separated into the first upper electrode layer and the second gate layer 133 arranged along the second direction D2. In two adjacent first trenches 70 along the second direction D2, the first active layer 101 in one first trench 70 and the second active layer 102 in the other first trench 70 together form the active layer 19 of the transistor 17 in one memory cell, and the first lower electrode layer 111 in one first trench 70 and the second lower electrode layer 112 in the other first trench 70 together form the lower electrode layer 29 of the capacitor 18 in one memory cell. See Figure 18 。

[0113] In some embodiments, after forming the second isolation layer 142 that penetrates the first dielectric layer 120 and the first conductive material layer 130 along the first direction D1 and forming the third isolation layer 141 that penetrates the first dielectric layer 120 and the first conductive material layer 130 along the second direction D2, the following steps are further included:

[0114] A first gate layer 131 is formed in the gap between two adjacent first trenches 70 in the transistor region PT. The first gate layer 131 and the second gate layers 133 distributed on opposite sides of the first gate layer 131 along the second direction D2 and adjacent to the first gate layer 131 together form a gate structure of one transistor 17, as Figure 16 shown;

[0115] A first upper electrode layer 151 is formed in the gap between two adjacent first trenches 70 in the capacitor region PC. The first upper electrode layer 151 and the second upper electrode layers 152 distributed on opposite sides of the first upper electrode layer 151 along the second direction D2 and adjacent to the first upper electrode layer 151 together form an upper electrode layer of one capacitor 18, as Figure 18 shown.

[0116] For example, a dry etching process can be used to etch the gap between two adjacent first trenches 70 in the transistor region PT to form a third trench 150 that penetrates the stacked layer, as Figure 15As shown, a conductive material such as tungsten for filling metal is filled in the third trench 150 to form the first gate layer 131, as Figure 16 shown. The remaining sacrificial layer 41 on the surface of the first gate layer 131 serves as the gate contact layer 132, and the remaining second dielectric layer 72 on the surface of the gate contact layer 132 serves as the first gate dielectric layer 121 of the transistor 17. Then, the second filling layer 110 between the adjacent first trenches 70 in the capacitor region PC is removed to form a fourth trench 170 exposing the first lower electrode layer 111 and the second lower electrode layer 112, as Figure 17 shown. Next, a dielectric layer covering the inner wall of the fourth trench 170 and the first upper electrode layer 151 covering the dielectric layer are formed again, as Figure 18 shown.

[0117] After forming the structure as Figure 18 shown, the sacrificial layer 41 in the bit line region PB of the stacked layer can also be removed, and a bit line trench located between the adjacent interlayer isolation layers 40 is formed in the bit line region PB. A conductive material such as metal is filled in the bit line trench to form a bit line 14, as Figure 1 and Figure 2 shown.

[0118] For the semiconductor structure and its forming method provided by some embodiments of this specific implementation manner, by providing an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region in the memory cell, using the oxide semiconductor layer in the transistor region as the active layer of the transistor, using the oxide semiconductor layer in the capacitor region as the lower electrode layer of the capacitor, and making the resistance of the lower electrode layer lower than that of the active layer, part of the manufacturing process of the transistor and part of the manufacturing process of the capacitor can be synchronized, thus simplifying the manufacturing process of the semiconductor structure and improving the manufacturing efficiency of the semiconductor structure. In other embodiments of this specific implementation manner, by adopting a resistance reduction treatment method to improve the conductivity of the oxide semiconductor layer used to form the lower electrode layer, while ensuring that the lower electrode layer has good conductive performance, the resistance value of the lower electrode layer can be flexibly adjusted, which helps to further improve the performance of the semiconductor structure and improve the manufacturing yield of the semiconductor structure.

[0119] The above are only the preferred embodiments of the present disclosure. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present disclosure, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present disclosure.

Claims

1. A semiconductor structure, It is characterized in that include: substrate; A storage unit is located on the substrate and includes a transistor region and a capacitor region. The storage unit also includes an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer in the transistor region serves as an active layer of the transistor, and the oxide semiconductor layer in the capacitor region serves as a lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than the resistance of the active layer.

2. The semiconductor structure according to claim 1, It is characterized in that The oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer, both extending along a first direction and arranged at intervals along a second direction, the first direction and the second direction are both parallel to the top surface of the substrate, and the first direction intersects with the second direction; The first oxide semiconductor layer in the transistor region serves as a first active layer, the second oxide semiconductor layer in the transistor region serves as a second active layer, and the first active layer and the second active layer together constitute the active layer; The first oxide semiconductor layer in the capacitor region serves as a first lower electrode layer, the second oxide semiconductor layer in the capacitor region serves as a second lower electrode layer, and the first lower electrode layer and the second lower electrode layer together constitute the lower electrode layer.

3. The semiconductor structure according to claim 2, It is characterized in that The projection of the first active layer on the top surface of the substrate, the projection of the second active layer on the top surface of the substrate, the projection of the first lower electrode layer on the top surface of the substrate, and the projection of the second lower electrode layer on the top surface of the substrate are all L-shaped.

4. The semiconductor structure according to claim 2, It is characterized in that The transistor further includes a gate structure, the gate structure including a first gate layer and a second gate layer, the first gate layer is located between the first active layer and the second active layer, the second gate layer is located on a side of the first active layer away from the first gate layer and on a side of the second active layer away from the first gate layer; The capacitor also includes a dielectric layer covering the surface of the lower electrode layer and an upper electrode layer covering the surface of the dielectric layer, the upper electrode layer includes a first upper electrode layer and a second upper electrode layer electrically connected to each other, the first upper electrode layer is located between the first lower electrode layer and the second lower electrode layer, and the second upper electrode layer is located on a side of the first lower electrode layer facing away from the first upper electrode layer and a side of the second lower electrode layer facing away from the first upper electrode layer.

5. The semiconductor structure according to claim 4, It is characterized in that The material of the second upper electrode layer is the same as that of the second gate layer, and the second upper electrode layer and the second gate layer are arranged in the same layer.

6. The semiconductor structure according to claim 4, It is characterized in that Also includes: A word line lead-out structure is located above the transistor. The word line lead-out structure includes a first lead-out plug, a second lead-out plug, and a word line lead. One end of the first lead-out plug is electrically connected to the first gate layer, and the other end is electrically connected to the word line lead. One end of the second lead-out plug is electrically connected to the second gate layer, and the other end is electrically connected to the word line lead.

7. The semiconductor structure according to claim 4, wherein, the first active layer includes a first channel region, and a first source region and a first drain region distributed on opposite sides of the first channel region along the first direction. The first lower electrode layer is in contact electrical connection with the first drain region; the second active layer includes a second channel region, and a second source region and a second drain region distributed on opposite sides of the second channel region along the first direction. The second lower electrode layer is in contact electrical connection with the second drain region; the semiconductor structure further includes bit lines, the bit lines extend along the second direction, and the bit lines are electrically connected to the first source region and the second source region.

8. The semiconductor structure according to claim 7, wherein, the number of the memory cells is multiple, and the multiple memory cells are arranged in an array along the second direction and the third direction, and the third direction is perpendicular to the top surface of the substrate; multiple bit lines are arranged at intervals along the third direction, and each bit line is electrically connected to the active layer in the multiple memory cells arranged at intervals along the second direction; The gate structures in the multiple memory cells arranged at intervals along the third direction are electrically connected.

9. The semiconductor structure according to claim 1, wherein, the concentration of oxygen vacancies in the lower electrode layer is greater than the concentration of oxygen vacancies in the active layer.

10. A method for forming a semiconductor structure, wherein, includes the following steps: providing a substrate; forming memory cells on the substrate. The memory cells include a transistor region and a capacitor region. The memory cells further include an oxide semiconductor layer continuously distributed in the transistor region and the capacitor region. The oxide semiconductor layer in the transistor region serves as the active layer of the transistor, and the oxide semiconductor layer in the capacitor region serves as the lower electrode layer of the capacitor. The resistance of the lower electrode layer is lower than the resistance of the active layer.

11. The method for forming a semiconductor structure according to claim 10, wherein, the specific steps of forming memory cells on the substrate include: forming a stacked layer on the substrate. The stacked layer includes an interlayer isolation layer and a sacrificial layer alternately stacked along the third direction, and the stacked layer includes a transistor region and a capacitor region arranged along the first direction, and the first direction is parallel to the top surface of the substrate; forming a first trench penetrating through the transistor region and the capacitor region of the stacked layer along the third direction; forming an oxide semiconductor layer covering the inner wall of the first trench; reducing the resistance of the oxide semiconductor layer in the capacitor region to form the active layer in the transistor region and the lower electrode layer in the capacitor region.

12. The method for forming a semiconductor structure according to claim 11, wherein, the specific steps of forming a first trench that penetrates through the transistor region and the capacitor region of the stacked layer along the third direction include: removing the sacrificial layer in the capacitor region, and forming a second trench in the capacitor region between adjacent interlayer isolation layers; forming a first isolation layer that fills the second trench; etching the stacked layer and the first isolation layer to form a first trench that penetrates through the transistor region and the capacitor region of the stacked layer along the third direction and penetrates through the first isolation layer along the third direction.

13. The method for forming a semiconductor structure according to claim 11, wherein, the specific steps of reducing the resistance of the oxide semiconductor layer in the capacitor region include: treating the oxide semiconductor layer in the capacitor region with plasma to increase oxygen vacancies in the oxide semiconductor layer in the capacitor region; or; injecting doping ions into the oxide semiconductor layer in the capacitor region to enhance the conductivity of the oxide semiconductor layer in the capacitor region.

14. The method for forming a semiconductor structure according to claim 11, wherein, the specific steps of forming the active layer in the transistor region and the lower electrode layer in the capacitor region include: removing the oxide semiconductor layer between adjacent sacrificial layers, and the remaining oxide semiconductor layer in the capacitor region forms a plurality of initial lower electrode layers arranged at intervals along the third direction, and the remaining oxide semiconductor layer in the transistor region forms a plurality of initial active layers arranged at intervals along the third direction; dividing the initial lower electrode layer and the initial active layer to form a lower electrode layer including a first lower electrode layer and a second lower electrode layer distributed at intervals along the second direction, and forming an active layer including a first active layer and a second active layer distributed at intervals along the second direction, the second direction is parallel to the top surface of the substrate, and the second direction intersects with the first direction.

15. The method for forming a semiconductor structure according to claim 14, wherein, after forming a lower electrode layer including a first lower electrode layer and a second lower electrode layer distributed at intervals along the second direction, and forming an active layer including a first active layer and a second active layer distributed at intervals along the second direction, the following steps are further included: forming a dielectric layer covering the first lower electrode layer and the second lower electrode layer, and forming a gate dielectric layer covering the first active layer and the second active layer; forming an upper electrode layer covering the dielectric layer, and forming a gate structure covering the gate dielectric layer to form the capacitor including the lower electrode layer, the dielectric layer and the upper electrode layer, and forming the transistor including the first active layer, the second active layer, the gate dielectric layer and the gate structure.

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