Semiconductor device

Abstract

A semiconductor device includes: a substrate including a cell array region and a peripheral circuit region; the peripheral gate structure comprises a peripheral gate dielectric layer, a peripheral gate electrode located on the peripheral gate dielectric layer, peripheral source electrodes / drain electrodes located on the two sides of the peripheral gate electrode, and a peripheral gate covering pattern located on the peripheral gate electrode; the first peripheral interlayer insulating layer is positioned on the side surface of the peripheral gate structure; a peripheral interconnect on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer on the peripheral interconnect; a connection structure including a pad pattern and a first peripheral contact plug penetrating the insulating pattern layer and electrically connecting the pad pattern to the peripheral interconnect; and a guard ring structure surrounding the cell array region between the cell array region and the peripheral circuit region. A portion of the guard ring of the guard ring structure is at the same height as a portion of the first peripheral contact plug.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to semiconductor devices. Background Art

[0002] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices increases, the demand for the integration density of semiconductor devices also increases. In the process of manufacturing semiconductor devices in response to the trend of high integration density of semiconductor devices, research has continued to reduce the complexity of circuits in the peripheral circuit region. Summary of the Invention

[0003] Example embodiments of the inventive concept provide a semiconductor device with improved reliability.

[0004] Some example embodiments of the inventive concept provide a semiconductor device including: a substrate including a cell array region and a peripheral circuit region; a peripheral gate structure located on the peripheral circuit region of the substrate and including a peripheral gate dielectric layer, a peripheral gate electrode located on the peripheral gate dielectric layer, peripheral source / drains located on both sides of the peripheral gate electrode, and a peripheral gate capping pattern located on the peripheral gate electrode; a first peripheral interlayer insulating layer at least a part of which is located on a side surface of the peripheral gate structure; peripheral interconnects located on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer located on the peripheral interconnects; a connection structure including a pad pattern and a first peripheral contact plug, the pad pattern being located on the insulating pattern layer, and the first peripheral contact plug penetrating the insulating pattern layer and electrically connecting the pad pattern to a corresponding one of the peripheral interconnects; and a guard ring structure including a guard ring and surrounding the cell array region between the cell array region and the peripheral circuit region of the substrate. At least a part of the guard ring of the guard ring structure is at the same height as at least a part of the first peripheral contact plug of the connection structure.

[0005] Some example embodiments of the inventive concept also provide a semiconductor device including: a substrate including a cell array region and a peripheral circuit region; a conductive region located in the cell array region; a peripheral gate structure located on the peripheral circuit region of the substrate, the peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode on the peripheral gate dielectric layer, peripheral source / drains on both sides of the peripheral gate electrode, and a peripheral gate capping pattern on the peripheral gate electrode; a first peripheral interlayer insulating layer at least a part of which is located on a side surface of the peripheral gate structure; a peripheral interconnect located on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer located on the peripheral interconnect; a stop layer located on the conductive region in the cell array region and located between the peripheral interconnect and the insulating pattern layer in the peripheral circuit region; a guard ring structure including a guard ring surrounding the cell array region, and a lower region of the guard ring penetrating the stop layer at a part of the stop layer between the cell array region and the peripheral circuit region of the substrate; and a connection structure located on the peripheral circuit region of the substrate, the connection structure including a pad pattern and a first peripheral contact plug, the pad pattern being located on the insulating pattern layer, and the first peripheral contact plug penetrating the insulating pattern layer and the stop layer and electrically connecting the pad pattern to a corresponding one of the peripheral interconnects.

[0006] Some example embodiments of the inventive concept provide a semiconductor device including: a substrate including a cell array region and a peripheral circuit region; a memory structure including a word line, a bit line, and a data storage structure located on the cell array region; a peripheral gate structure located on the peripheral circuit region of the substrate, the peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode located on the peripheral gate dielectric layer, peripheral source / drains located on both sides of the peripheral gate electrode, and a peripheral gate capping pattern located on the peripheral gate electrode; a first peripheral interlayer insulating layer, at least a part of which is located on a side surface of the peripheral gate structure; a peripheral interconnect located on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer located on the peripheral interconnect; a pad pattern located on the insulating pattern layer; a first peripheral contact plug penetrating the insulating pattern layer and electrically connecting the pad pattern to a corresponding one of the peripheral interconnects; an insulating pad covering the insulating pattern layer and the pad pattern; a second peripheral interlayer insulating layer located on the insulating pad; a second peripheral contact plug penetrating the second peripheral interlayer insulating layer and the insulating pad, the second peripheral contact plug being electrically connected to the pad pattern; a guard ring surrounding the cell array region between the cell array region and the peripheral circuit region of the substrate; and a dummy guard pattern located on the guard ring and extending horizontally toward the peripheral circuit region. Heights of the word line and the bit line are lower than a height of the guard ring. The data storage structure includes a first electrode structure, a second electrode structure, and a dielectric layer located between the first electrode structure and the second electrode structure. At least one of the first electrode structure and the second electrode structure includes a lower surface having a height lower than a height of an upper surface of the guard ring and an upper surface having a height higher than the height of the upper surface of the guard ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features, and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a top view showing a semiconductor device according to some example embodiments of the inventive concept;

[0009] Figure 2A and Figure 2B is an enlarged view showing a part of a semiconductor device according to some example embodiments of the inventive concept when viewed from the side;

[0010] Figure 3A and Figure 3B is a cross-sectional view of a semiconductor device showing some example embodiments according to the inventive concept when observed from above;

[0011] Figure 4 is an enlarged view of a part of a semiconductor device showing some example embodiments according to the inventive concept;

[0012] Figure 5A 、 Figure 5B and Figure 5C is an enlarged view of a part of a semiconductor device showing some example embodiments according to the inventive concept;

[0013] Figure 6A 、 Figure 6B and Figure 6C is an enlarged view of a part of a semiconductor device showing some example embodiments according to the inventive concept; and

[0014] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 and Figure 15 is a cross-sectional view of a method of manufacturing a semiconductor device showing some example embodiments according to the inventive concept. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0016] When the terms “about” or “substantially” are used in connection with a numerical value in this specification, the associated numerical value is intended to include manufacturing or operational tolerances around the stated numerical value (e.g., ±10%). Further, when the words “about” and “substantially” are used in connection with a geometry, it means that the exactness of the geometry is not required, but the range of variation of the shape is within the scope of the present disclosure. Further, whether or not the numerical value or shape is modified by “about” or “substantially”, it should be understood that these numerical values and shapes should be interpreted as including manufacturing or operational tolerances around the stated numerical value or shape (e.g., ±10%). When a range is specified, the range includes all values therebetween, such as increments of 0.1%.

[0017] In addition, for example, “at least one of A, B, and C” and similar language (e.g., “at least one selected from the group consisting of A, B, and C”) can be interpreted to mean only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0018] Figure 1 is a top view showing a semiconductor device 100 according to some example embodiments.

[0019] Referring Figure 1 , a semiconductor device 100 according to some example embodiments may include a cell region (also referred to as a cell array region) CA and a peripheral circuit region PA. The peripheral circuit region PA may be disposed to surround the cell region CA. The cell region CA may refer to a region where memory cells of a dynamic random access memory (DRAM) device are provided, and a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit may be provided in the peripheral circuit region PA. A semiconductor device according to some example embodiments may further include an interface region IA disposed between the cell region CA and the peripheral circuit region PA. The interface region IA may electrically connect the cell region CA to the peripheral circuit region PA. A semiconductor device according to some example embodiments may include a guard ring structure GRS disposed to surround the cell region CA on the interface region IA.

[0020] Figure 2A and Figure 2B is an enlarged view showing a semiconductor device 100 according to some example embodiments. Figure 2A is an enlarged view showing regions “A” and “B”, and Figure 2B is an enlarged view showing region “C”. Figure 3A and Figure 3B is a vertical cross-sectional view showing a semiconductor device 100 according to some example embodiments. Figure 3A is showing Figure 2A a vertical cross-sectional view of the semiconductor device shown taken along lines I-I’ and II-II’. Figure 3B is showing Figure 2B a vertical cross-sectional view of the semiconductor device shown taken along line III-III’. Figure 4 is an enlarged view showing a semiconductor device according to some example embodiments. Figure 4 is showing Figure 3A an enlarged view of regions “D” and “E” in

[0021] Referring Figure 2A , Figure 2B , Figure 3A and Figure 3B, the semiconductor device 100 may include a substrate 101 having a cell active region ACTc disposed on a cell region CA, a device isolation layer 110 defining the cell active region ACTc in the substrate 101, a bit line structure BLS disposed on the substrate 101 and including a bit line BL, and a data storage structure CAP located on the bit line structure BLS. The data storage structure CAP may store data and may be configured, for example, as a capacitor structure of a DRAM. According to some example embodiments, a partial region of the cell region CA may be referred to as a dummy pattern region DA. The dummy pattern region DA may not include the data storage structure CAP and may be in contact with an interface region IA of the cell region CA.

[0022] In the cell region CA, the semiconductor device 100 may further include a lower conductive pattern 150 located on the cell active region ACTc, an upper conductive pattern 160 located on the lower conductive pattern 150, and an insulating pattern 165 penetrating the upper conductive pattern 160.

[0023] Although not shown, the semiconductor device 100 may further include a word line WL disposed in the cell region CA and buried in the substrate 101.

[0024] The semiconductor device 100 may include a cell array such as a dynamic random access memory (DRAM). For example, the bit line BL may be connected to a first cell impurity region SDc1 of the cell active region ACTc, and a second cell impurity region SDc2 of the cell active region ACTc may be electrically connected to the data storage structure CAP located on the upper conductive pattern 160 through the lower conductive pattern 150 and the upper conductive pattern 160. The bit line BL may be disposed at a height lower than the height of the guard ring structure GRS. Although not shown, the word line WL buried in the substrate 101 may also be disposed at a height lower than the height of the guard ring structure GRS.

[0025] The data storage structure CAP may be configured as a capacitor that can store data in a memory such as a DRAM. The data storage structure CAP may be electrically connected to a conductive region on a lower structure including, for example, the lower conductive pattern 150 and the upper conductive pattern 160. Here, the lower structure may include the substrate 101, the word line, and the bit line structure BLS.

[0026] The data storage structure CAP may include a first electrode structure 170, a dielectric layer 172 located on the first electrode structure 170, and a second electrode structure 174 located on the dielectric layer 172. The data storage structure CAP may further include support layers SP1, SP2, and SP3. The first electrode structure 170 may be a lower electrode, and the second electrode structure 174 may be an upper electrode.

[0027] Refer togetherFigure 3A and Figure 3B ,at least one of the first electrode structure 170 and the second electrode structure 174 may have a lower surface disposed at a height lower than the upper surface of the guard ring structure GRS and an upper surface disposed at a height higher than the upper surface of the guard ring structure GRS. For example, each of the first electrode structure 170 and the second electrode structure 174 may have a lower surface disposed at a height lower than the upper surface of the guard ring GR and an upper surface disposed at a height higher than the upper surface of the guard ring GR.

[0028] The substrate 101 may include a semiconductor material, such as a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI compound semiconductor. For example, the Group-IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 101 may further include impurities. The substrate 101 may be configured as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, or a substrate including an epitaxial layer.

[0029] The device isolation layer 110 may define a unit active region ACTc in the substrate 101. The unit active region ACTc may have a first unit impurity region SDc1 and a second unit impurity region SDc2 at a desired (and / or predetermined) depth from the upper surface of the substrate 101. The first unit impurity region SDc1 and the second unit impurity region SDc2 may be spaced apart from each other. The first unit impurity region SDc1 and the second unit impurity region SDc2 may be provided as source / drain regions of a transistor configured by a word line. The source region and the drain region may be formed by doping or ion implanting substantially the same impurities into the first unit impurity region SDc1 and the second unit impurity region SDc2, and may be used interchangeably according to the circuit configuration of the finally formed transistor. The impurities may include impurities having a conductivity type opposite to that of the substrate 101. In some example embodiments, the depths of the first unit impurity region SDc1 and the second unit impurity region SDc2 in the source region and the drain region may be different.

[0030] The device isolation layer 110 may be formed by a shallow trench isolation (STI) process. The device isolation layer 110 may surround the unit active region ACTc and may electrically isolate these regions from each other. The device isolation layer 110 may be formed of an insulating material, such as silicon oxide, silicon nitride, or a combination thereof.

[0031] Although not shown, the word line WL may be provided to extend in a first direction X through the unit active region ACTc. For example, a pair of adjacent word lines may be provided to span one unit active region ACTc. The word line may be included in the gate of a buried channel array transistor (BCAT), but some example embodiments thereof are not limited thereto.

[0032] The bit line structure BLS can extend perpendicular to the word line in one direction (e.g., the second direction Y). The bit line structure BLS can include a bit line BL and a bit line capping pattern BC located on the bit line BL.

[0033] The bit line BL can include a first conductive pattern 141, a second conductive pattern 142, and a third conductive pattern 143 stacked in sequence. The bit line capping pattern BC can be disposed on the third conductive pattern 143. A buffer insulating layer 128 can be disposed between the first conductive pattern 141 and the substrate 101, and a part of the first conductive pattern 141 (hereinafter referred to as a bit line contact pattern DC) can be in contact with a first cell impurity region SDc1 of the cell active region ACTc. The bit line BL can be electrically connected to the first cell impurity region SDc1 through the bit line contact pattern DC. The lower surface of the bit line contact pattern DC can be disposed at a height lower than the upper surface of the substrate 101 and can be disposed at a height higher than the upper surface of the word line. In some exemplary embodiments, the bit line contact pattern DC can be formed in the substrate 101 and can be locally disposed in a bit line contact hole exposing the first cell impurity region SDc1.

[0034] The first conductive pattern 141 can include a semiconductor material such as polysilicon. The first conductive pattern 141 can be in direct contact with the first cell impurity region SDc1. The second conductive pattern 142 can include a metal semiconductor compound. For example, the metal semiconductor compound can be a layer that silicidizes a part of the first conductive pattern 141. For example, the metal semiconductor compound can include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. The third conductive pattern 143 can include a metal material such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). In some exemplary embodiments, the number of conductive patterns included in the bit line BL, its material type, and / or its stacking order can vary.

[0035] The bit line covering pattern BC may include a first covering pattern 146, a second covering pattern 147, and a third covering pattern 148 stacked in sequence on the third conductive pattern 143. Each of the first to third covering patterns 146, 147, and 148 may include an insulating material, such as a silicon nitride film. The first to third covering patterns 146, 147, and 148 may be formed of different materials, and even if the first to third covering patterns 146, 147, and 148 include the same material, the boundaries may be distinct due to differences in physical properties. The thickness of the second covering pattern 147 may be less than the thickness of each of the first covering pattern 146 and the third covering pattern 148. In some example embodiments, the number and / or the type of materials of the covering patterns included in the bit line covering pattern BC may vary.

[0036] Although not shown, spacer structures may be provided on two sidewalls of each bit line structure BLS. The spacer structures may extend in one direction (e.g., the Y direction) on two sidewalls of each bit line structure BLS. The spacer structures may be provided between the bit line structure BLS and the lower conductive pattern 150. The spacer structures may be arranged to extend along the sidewalls of the bit line BL and the sidewalls of the bit line covering pattern BC. The pair of spacer structures provided on both sides of one bit line structure BLS may have an asymmetric shape with respect to the bit line structure BLS. Each spacer structure may include a plurality of spacer layers and may further include air spacers in some example embodiments.

[0037] The lower conductive pattern 150 may be connected to a region of the cell active region ACTc, such as the second cell impurity region SDc2. The lower conductive pattern 150 may be provided between the bit lines BL. The lower conductive pattern 150 may penetrate the buffer insulating layer 128 and may be connected to the second cell impurity region SDc2 of the cell active region ACTc. The lower conductive pattern 150 may be in direct contact with the second cell impurity region SDc2. The lower surface of the lower conductive pattern 150 may be provided at a height lower than the upper surface of the substrate 101 and may be provided at a height higher than the lower surface of the bit line contact pattern DC. The lower conductive pattern 150 may be insulated from the bit line contact pattern DC by the spacer structure SS. The lower conductive pattern 150 may be formed of a conductive material, such as at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In an example embodiment, the lower conductive pattern 150 may include a plurality of layers.

[0038] The metal-semiconductor compound layer 155 may be disposed between the lower conductive pattern 150 and the upper conductive pattern 160. For example, when the lower conductive pattern 150 may include a semiconductor material, the metal-semiconductor compound layer 155 may be obtained by siliciding a part of the lower conductive pattern 150. The metal-semiconductor compound layer 155 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides. In some exemplary embodiments, the metal-semiconductor compound layer 155 may not be provided.

[0039] The upper conductive pattern 160 may be disposed on the lower conductive pattern 150. The upper conductive pattern 160 may extend into the regions between the spacer structures SS and may cover the upper surface of the metal-semiconductor compound layer 155. The upper conductive pattern 160 may include a barrier layer 162 and a conductive layer 164. The barrier layer 162 may cover the lower surface and the side surfaces of the conductive layer 164. The barrier layer 162 may include a metal nitride, such as at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). The conductive layer 164 may include a conductive material, such as at least one of polysilicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

[0040] The insulating pattern 165 may be provided to penetrate the upper conductive pattern 160. The upper conductive pattern 160 may be isolated into a plurality of parts by the insulating pattern 165. The insulating pattern 165 may include at least one insulating material, such as silicon oxide, silicon nitride, and silicon oxynitride.

[0041] The etch stop layer 168 (or “stop layer”) may cover the insulating pattern 165 between the first electrode structures 170. The etch stop layer 168 may contact the lower region of the side surfaces of the first electrode structures 170. The etch stop layer 168 may be disposed below the support layers SP1, SP2, and SP3. The upper surface of the etch stop layer 168 may include a part that is in direct contact with the dielectric layer 172. The etch stop layer 168 may include, for example, at least one of silicon nitride and silicon oxynitride. The etch stop layer 168 may further extend from the cell region CA to the peripheral circuit region PA (see Figure 3A ). For example, the etch stop layer 168 may extend from the cell region CA (or “dummy pattern region DA”) to the peripheral circuit region PA in the horizontal direction (X direction). Here, the etch stop layer 168 may have the same height over the cell region CA, the interface region IA, and the peripheral circuit region PA.

[0042] The first electrode structure 170 may be disposed on the upper conductive pattern 160. The first electrode structure 170 may penetrate the etch stop layer 168 and may be in contact with the upper conductive pattern 160. The first electrode structure 170 may have a columnar shape, but some example embodiments thereof are not limited thereto. Each first electrode structure 170 may include at least one of niobium nitride (NbN), niobium oxide (NbOx), polysilicon (Si), iridium (Ir), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al), or a combination thereof, metal nitrides, and metal compounds.

[0043] The dielectric layer 172 may cover the side surfaces and upper surfaces of each of the first electrode structures 170 on the surface of the first electrode structure 170. The dielectric layer 172 may be disposed between the first electrode structure 170 and the second electrode structure 174. The dielectric layer 172 may cover the upper and lower surfaces of the support layers SP1, SP2, and SP3. The dielectric layer 172 may cover the upper surface of the etch stop layer 168.

[0044] The dielectric layer 172 may include a high-k dielectric material, silicon oxide, silicon nitride, or a combination thereof. However, in some example embodiments, the dielectric layer 172 may include at least one of titanium (Ti), tantalum (Ta), hafnium (Hf), aluminum (Al), zirconium (Zr), and lanthanum (La) doped with fluorine (F), or an oxide, nitride, silicide, oxynitride, or silicon oxynitride including a combination thereof.

[0045] The second electrode structure 174 may be disposed on the dielectric layer 172. The second electrode structure 174 may fill the space between the plurality of first electrode structures 170 and the space between the support layers SP1, SP2, and SP3. In some example embodiments, the dielectric layer 172 and the second electrode structure 174 may further extend into the interface region IA. The second electrode structure 174 may include a conductive material.

[0046] The second electrode structure 174 may be formed of a single layer or multiple layers. In some example embodiments, the second electrode structure 174 may be in direct contact with the dielectric layer 172 and may include a first material layer formed along the dielectric layer 172 and a second material layer covering the first material layer. The first material layer may include a doped semiconductor, metal, conductive metal nitride, metal semiconductor compound, conductive metal oxide, or a combination thereof. The second material layer may include a silicon material or a silicon germanium material. For example, the second material layer may include a doped silicon material or a doped silicon germanium material.

[0047] The support layers SP1, SP2, and SP3 may include a first support layer SP1, a second support layer SP2 located on the first support layer SP1, and a third support layer SP3 located on the second support layer SP2. The support layers SP1, SP2, and SP3 may be spaced apart from the substrate 101 in a direction perpendicular to the upper surface of the substrate 101. The support layers SP1, SP2, and SP3 may be in contact with the first electrode structure 170 and may extend in a direction parallel to the upper surface of the substrate 101.

[0048] The support layers SP1, SP2, and SP3 may support the first electrode structure 170 having a high aspect ratio. Each of the support layers SP1, SP2, and SP3 may include at least one of, for example, silicon nitride, silicon oxynitride, or a similar material. The number, thickness, and / or arrangement relationship of the support layers SP1, SP2, and SP3 are not limited to the illustrated examples and may vary in the exemplary embodiments.

[0049] Reference Figure 2B , in a top view, the first electrode structures 170 may be arranged in a regular manner. In some exemplary embodiments, the first electrode structures 170 may be separated by an expected (and / or predetermined) distance in a first direction X and may be arranged in a zigzag pattern in a second direction Y. The arrangement of the first electrode structures 170 is not limited thereto.

[0050] Reference Figure 3A and Figure 3B , the semiconductor device 100 may further include a second electrode structure 174 located on the cell region CA (see Figure 3B ), and may further include a guard ring structure GRS located on the interface region IA, an interlayer insulating layer 186 disposed on a connection structure CS in the peripheral circuit region PA, and an upper interlayer insulating layer 188 located on the interlayer insulating layer 186 (see Figure 3A ). Although not shown, the interlayer insulating layer 186 may be in contact with the side surface of the second electrode structure 174. The interlayer insulating layer 186 may also be in contact with the dielectric layer 172. The upper interlayer insulating layer 188 may be disposed on the interlayer insulating layer 186. In some exemplary embodiments, an interlayer insulating pattern layer 184 may be further included, and the interlayer insulating pattern layer 184 includes an interlayer insulating pattern layer 184_2 covering one side surface of the guard ring structure GRS in the interface region IA and an interlayer insulating pattern layer 184_1 covering the side surface of the connection structure CS in the peripheral circuit region PA.

[0051] The interlayer insulating pattern layer 184, the lower interlayer insulating layer 186, and the upper interlayer insulating layer 188 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some example embodiments, the interlayer insulating pattern layer 184, the lower interlayer insulating layer 186, and the upper interlayer insulating layer 188 may include silicon oxide. Even if the lower interlayer insulating layer 186 may include the same material as the upper interlayer insulating layer 188, the boundary therebetween may be distinct. The upper surface of the upper interlayer insulating layer 188 may be flat, e.g., parallel to the upper surface of the substrate 101.

[0052] The semiconductor device 100 may further include a cell contact plug CCP, an interlayer insulating layer ILD, and a plurality of upper contact plugs 92. The cell contact plug CCP may penetrate the upper interlayer insulating layer 188 and may be connected to the data storage structure CAP. For example, the cell contact plug CCP may penetrate the upper interlayer insulating layer 188 and may be connected to the second electrode structure 174. The lower surface of the cell contact plug CCP may be disposed at a height lower than the height of the upper surface of the second electrode structure 174. The upper surface of the cell contact plug CCP may be coplanar with the upper surface of the upper interlayer insulating layer 188. The cell contact plug CCP may include a barrier layer CCPa and a conductive layer CCPb disposed on the barrier layer CCPa. The side surfaces of the cell contact plug CCP may contact the lower interlayer insulating layer 186 and the upper interlayer insulating layer 188.

[0053] The interlayer insulating layer ILD may be disposed on the upper interlayer insulating layer 188. The interlayer insulating layer ILD may cover the cell contact plug CCP and the upper interlayer insulating layer 188. The interlayer insulating layer ILD may include silicon oxide.

[0054] The plurality of upper contact plugs 92 may penetrate the interlayer insulating layer ILD, and at least one of the plurality of upper contact plugs may be connected to the cell contact plug CCP. The plurality of upper contact plugs 92 may each include a barrier layer 90 and a conductive layer 91 disposed on the barrier layer 90. The lower surfaces of the plurality of upper contact plugs 92 may be flat, e.g., parallel to the upper surface of the substrate 101. The lower surfaces of the plurality of upper contact plugs 92 may be disposed at the same height.

[0055] The barrier layer CCPa and the barrier layer 90 may include a metal nitride such as titanium nitride (TiN). The conductive layer CCPb and the conductive layer 91 may include a conductive material such as tungsten (W) and tungsten nitride (WN).

[0056] In the peripheral circuit region PA, the semiconductor device 100 may include a device isolation layer 10 that defines a peripheral active region ACTp. The device isolation layer 10 may be configured as an insulating layer extending downward from the upper surface of the substrate 101. In the upper region of the peripheral active region ACTp, peripheral source / drain regions SDp and a peripheral channel region CHp may be provided. The peripheral source / drain regions SDp may include a first peripheral source / drain region SDp1 and a second peripheral source / drain region SDp2, and the first peripheral source / drain region SDp1 and the second peripheral source / drain region SDp2 may be spaced apart from each other with a peripheral gate structure 40 therebetween. The peripheral channel region CHp may be provided between the peripheral source / drain regions SDp.

[0057] The device isolation layer 10 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may be configured as a single layer or multiple layers. The peripheral source / drain regions SDp may be provided as the source / drain regions of a transistor formed by the peripheral gate structure 40. The peripheral source / drain regions SDp may include impurities having a conductivity type opposite to that of the substrate 101.

[0058] The semiconductor device 100 may further include a peripheral gate dielectric layer 30 and a peripheral gate structure 40 provided on the substrate 101 in the peripheral circuit region PA. The peripheral gate structure 40 may have a structure similar to that of the bit line BL and may be formed of a material similar to that of the bit line BL.

[0059] The peripheral gate structure 40 may include a first conductive pattern 41, a second conductive pattern 42, and a third conductive pattern 43 stacked in sequence on the peripheral gate dielectric layer 30 on the substrate 101. The peripheral gate dielectric layer 30 may include silicon oxide, silicon nitride, or a high-k material. The high-k material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide. The first conductive pattern 41, the second conductive pattern 42, and the third conductive pattern 43 of the peripheral gate structure 40 may include materials the same as those of the first conductive pattern 141, the second conductive pattern 142, and the third conductive pattern 143 of the bit line BL, respectively. A first peripheral capping pattern 46 may be provided on the peripheral gate structure 40. The first peripheral capping pattern 46 may include a material the same as that of the first capping pattern 146 of the bit line capping pattern BC.

[0060] The semiconductor device 100 may further include a peripheral gate spacer SSP, a second peripheral capping pattern 47, a peripheral interlayer insulating layer 45, and a third peripheral capping pattern 48 in the peripheral circuit region PA. The peripheral gate spacer SSP may cover the side surfaces of the peripheral gate structure 40. For example, the peripheral gate spacers SSP may be spaced apart from each other with the peripheral gate structure 40 therebetween, and may cover the side surfaces of the first conductive pattern 41, the second conductive pattern 42, the third conductive pattern 43, and the first peripheral capping pattern 46.

[0061] The second peripheral capping pattern 47 may cover the substrate 101, the peripheral gate spacer SSP, and the peripheral gate structure 40, and may be formed conformally. The peripheral interlayer insulating layer 45 may partially cover the second peripheral capping pattern 47. The upper surface of the peripheral interlayer insulating layer 45 may be coplanar with the upper surface of the second peripheral capping pattern 47. The third peripheral capping pattern 48 may cover the peripheral interlayer insulating layer 45 and the second peripheral capping pattern 47.

[0062] The second peripheral capping pattern 47 and the third peripheral capping pattern 48 may include materials identical to the second capping pattern 147 and the third capping pattern 148 of the bit line capping pattern BC, respectively, and may include, for example, silicon nitride. The peripheral interlayer insulating layer 45 may include silicon oxide.

[0063] The semiconductor device 100 may further include a peripheral plug 63 and a peripheral interconnect 60 electrically connected to the peripheral source / drain region SDp in the peripheral circuit region PA. The peripheral plug 63 may penetrate the third peripheral capping pattern 48 and the peripheral interlayer insulating layer 45, may be disposed adjacent to the peripheral gate structure 40, and may contact the peripheral source / drain region SDp. The peripheral interconnect 60 may be disposed on the third peripheral capping pattern 48 and the peripheral plug 63, and may extend in the first direction X.

[0064] The semiconductor device 100 may further include an insulating pattern 65 disposed between the peripheral interconnects 60. The insulating pattern 65 may spatially isolate the peripheral interconnects 60 and may electrically insulate the peripheral interconnects 60 from each other.

[0065] The semiconductor device 100 may further include an etch stop layer 68 disposed on the peripheral interconnect 60. The etch stop layer 68 may be formed integrally with the etch stop layer 168. For example, the etch stop layer 68 may be formed by extending the etch stop layer 168 into the peripheral circuit region PA. Thus, the etch stop layer 68 in the peripheral circuit region PA and the etch stop layer 168 in the cell region CA may be disposed at the same height.

[0066] Refer together Figure 3A and Figure 4, in the peripheral circuit region PA, the semiconductor device 100 may further include an interlayer insulating pattern layer 184_1, a connection structure CS, and an insulating spacer 185 disposed between the peripheral interconnect 60 and the lower interlayer insulating layer 186.

[0067] The interlayer insulating pattern layer 184_1 may be disposed on the peripheral interconnect 60 and may extend into the interface region IA. Thus, in the interface region IA, the interlayer insulating pattern layer 184_2 may contact at least a portion of the guard ring structure GRS. The interlayer insulating pattern layer 184_2 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some example embodiments, the interlayer insulating pattern layer 184_2 may include silicon oxide. On the peripheral circuit region PA, the interlayer insulating pattern layer 184_1 may have upper surfaces at different heights. For example, the upper surface of the interlayer insulating pattern layer 184_1 disposed on the peripheral gate structure 40 may be disposed at a height higher than the height of the upper surface of the interlayer insulating pattern layer 184_1 not disposed on the peripheral gate structure 40. On the interface region IA, the interlayer insulating pattern layer 184_2 may have upper surfaces disposed at the same height.

[0068] The connection structure CS may be disposed on the interlayer insulating pattern layer 184_1. The connection structure CS may include a pad pattern CSa and a contact plug CSb (or "first peripheral contact plug"). According to some example embodiments, a peripheral interconnect circuit including multiple layers may be implemented by forming the connection structure CS including the pad pattern CSa and the contact plug CSb on the peripheral interconnect 60 in the peripheral circuit region (PA). Thus, the complexity of the circuit may be reduced, the area of the peripheral circuit region PA may be decreased, and the peripheral contact plug PCP penetrating the interlayer insulating layer 186 may be easily formed. The pad pattern CSa may be disposed on the interlayer insulating pattern layer 184_1 disposed on the peripheral gate structure 40. The contact plug CSb may penetrate the interlayer insulating pattern layer 184_1 and the etch stop layer 68 disposed on the peripheral gate structure 40. The upper region of the contact plug CSb may be configured as a region continuously extending from the lower region of the pad pattern CSa. The lower region of the contact plug CSb may be disposed in the peripheral interconnect 60, and the lower surface of the contact plug CSb may contact at least a portion of the peripheral interconnect 60. Thus, the contact plug CSb may electrically connect the pad pattern CSa to the peripheral interconnect 60.

[0069] The contact plug CSb may include a barrier layer CSb1 and a conductive layer CSb2 located on the barrier layer CSb1. The barrier layer CSb1 may be disposed along the sidewall of the contact plug CSb, and the conductive layer CSb2 may be disposed in the contact plug CSb. The barrier layer CSb1 may include an insulating material such as silicon oxycarbide, silicon nitride, and silicon oxynitride. The conductive layer CSb2 of the contact plug CSb and the pad pattern CSa may include the same conductive material. For example, the pad pattern CSa and the conductive layer CSb2 may include a conductive material such as tungsten (W) and tungsten nitride (WN). For example, the pad pattern CSa and the conductive layer CSb2 may have a continuous shape. For example, the upper region of the conductive layer CSb2 may extend from the lower region of the pad pattern CSa, and for example, the boundary surface between the lower surface of the pad pattern CSa and the upper surface of the conductive layer CSb2 may not be distinct.

[0070] The insulating liner 185 may cover at least a portion of the surface of the interlayer insulating pattern layer 184_1 and the surface of the pad pattern CSa of the connection structure CS. The insulating liner 185 may extend into the interface region IA. Thus, in the interface region IA, the insulating liner 185 may form a component of the guard ring structure GRS. For example, the insulating liner 185 may correspond to the second pattern GDb of the dummy guard pattern GD of the guard ring structure GRS. The insulating liner 185 may include an insulating material such as silicon oxide, silicon oxycarbide, and silicon nitride. In some example embodiments, the insulating liner 185 may include silicon nitride.

[0071] The semiconductor device 100 may further include a peripheral contact plug PCP (or "second peripheral contact plug") and an upper contact plug 95 disposed on the connection structure CS. The peripheral contact plug PCP may penetrate the upper interlayer insulating layer 188, the lower interlayer insulating layer 186, and the insulating liner 185, and may contact the pad pattern CSa. The peripheral contact plug PCP may be electrically connected to the first peripheral source / drain region SDp1 or the second peripheral source / drain region SDp2 through the pad pattern CSa, the contact plug CSb, the peripheral interconnect 60, and the peripheral plug 63. The upper surface of the peripheral contact plug PCP may be coplanar with the upper surface of the cell contact plug CCP and the upper interlayer insulating layer 188. The peripheral contact plug PCP may include a barrier layer PCPa and a conductive layer PCPb located on the barrier layer PCPa.

[0072] The upper contact plug 95 may penetrate the interlayer insulating layer ILD, and the upper contact plug 95 may be connected to the peripheral contact plug PCP. The upper contact plug 95 may include a barrier layer 93 and a conductive layer 94 located on the barrier layer 93. The lower surface of the upper contact plug 95 may be flat, for example, parallel to the upper surface of the substrate 101. The lower surfaces of the upper contact plug 95 and the plurality of upper contact plugs 92 may be disposed at the same height.

[0073] The barrier layer PCPa and the barrier layer 93 may include a metal nitride such as titanium nitride (TiN). The conductive layer PCPb and the conductive layer 94 may include a conductive material such as tungsten (W) and tungsten nitride (WN).

[0074] In the interface region IA, the semiconductor device 100 may include a dummy pattern extension portion 145, a device isolation layer 115 disposed in the substrate 101, a plurality of dummy pattern layers disposed on the substrate 101, a barrier layer 162, a dummy conductive pattern 166, and an etch stop layer 168.

[0075] The device isolation layer 115 may include a buried insulating layer 115a, an insulating liner 115b, and a gap-fill insulating layer 115c sequentially disposed in a desired (and / or predetermined) trench. The dummy pattern extension portion 145 may be configured as an extension of the plurality of conductive patterns 141, 142, and 143 and the plurality of covering patterns 146, 147, and 148 of the dummy pattern region DA extending into the interface region IA. Similarly, the barrier layer 162 and the dummy conductive pattern 166 may be patterns in which the barrier layer 162 and the upper conductive pattern 164 of the dummy pattern region DA extend into the interface region IA, respectively.

[0076] In the interface region IA, the semiconductor device 100 may further include an etch stop layer 168 disposed on the dummy conductive pattern 166. As described above, the etch stop layer 168 may extend from the cell region CA to the peripheral circuit region PA, and the etch stop layer 168 may have the same height over the cell region CA, the interface region IA, and the peripheral circuit region PA.

[0077] Refer together Figure 3A and Figure 4 , in the interface region IA, the semiconductor device 100 may further include a guard ring structure GRS disposed on the etch stop layer 168 and surrounding the cell region CA. The guard ring structure GRS may include a guard ring GR and a dummy guard pattern GD disposed on the guard ring GR. According to some example embodiments, by implementing the guard ring structure GRS in the cell region CA (which may be formed together with the connection structure CS in the peripheral circuit region PA), a separate process for forming the connection structure CS may be reduced.

[0078] In a top view, the guard ring GR may have an annular shape surrounding the cell region CA (see Figure 1 ), and in a cross-sectional view, the guard ring GR may have a columnar shape with a horizontal width increasing from a lower region to an upper region (see Figure 3A)。The guard ring GR may include a barrier layer GRa and a conductive layer GRb disposed on the barrier layer GRa. The barrier layer GRa may be disposed along the sidewall of the guard ring GR, and the conductive layer GRb may be disposed in the guard ring GR. The barrier layer GRa of the guard ring GR may include the same material as the barrier layer CSb1 of the contact plug CSb of the connection structure CS. Similarly, the conductive layer GRb of the guard ring GR may also include the same material as the conductive layer CSb2 of the contact plug CSb of the connection structure CS.

[0079] The semiconductor device 100 may further include an interlayer insulating pattern layer 184_2 disposed on one side of the guard ring GR. The interlayer insulating pattern layer 184_2 in the interface region IA may be integrated with and physically connected to (not shown) the interlayer insulating pattern layer 184_1 in the peripheral circuit region PA.

[0080] The dummy protection pattern GD may be configured as a plurality of dummy patterns disposed on the guard ring GR. The dummy protection pattern GD may extend horizontally (in the X direction) toward the peripheral circuit region PA on the guard ring GR and the interlayer insulating pattern layer 184_2.

[0081] The dummy protection pattern GD may include a first pattern GDa and a second pattern GDb disposed on the first pattern GDa. The first pattern GDa may be disposed on the upper surfaces of the guard ring GR and the interlayer insulating pattern layer 184_2, and may include a conductive material. For example, the first pattern GDa may include the same conductive material as the conductive layer GRb of the guard ring GR. For example, the boundary surface between the lower surface of the first pattern GDa and the upper surface of the conductive layer GRb may not be obvious. In addition, the first pattern GDa may include the same conductive material as the conductive layer CSb2 of the contact plug CSb of the connection structure CS. The second pattern GDb may be configured as a pattern in which the insulating pad 185 of the peripheral circuit region PA extends into the interface region IA. Therefore, the second pattern GDb may include the same insulating material as the insulating pad 185.

[0082] At least a part of the guard ring structure GRS may be at the same height as at least a part of the connection structure CS. For example, the upper surface of the guard ring GR of the guard ring structure GRS may be at substantially the same height as the upper surface of the contact plug CSb of the connection structure CS. In addition, the upper surface of the first pattern GDa of the dummy protection pattern GD of the guard ring structure GRS may be at substantially the same height as the upper surface of the pad pattern CSa of the connection structure CS. Viewed from a different perspective, the upper surface of the second pattern GDb of the dummy protection pattern GD of the guard ring structure GRS may be at substantially the same height as the upper surface of the insulating pad 185.

[0083] ReferenceFigure 4 , in a cross-sectional view, one side surface of the dummy protection pattern GD may have a linear shape in the vertical direction (Z direction). Further, this one side surface of the dummy protection pattern GD may perpendicularly overlap with an edge of the upper surface of the protection ring GR.

[0084] Figure 5A , Figure 5B and Figure 5C are enlarged views showing a part of a semiconductor device according to some example embodiments.

[0085] Referring to Figure 5A , except for a configuration in which the horizontal width of the protection ring GR is smaller than the horizontal width of the contact plug CSb, the semiconductor device 100A may be the same as or similar to the example described with reference to Figures 1 to 4 .

[0086] Referring to Figure 7 , a first horizontal width W1 of a first opening OP1 of the protection ring GR formed around the cell region CA may be smaller than a second horizontal width W2 of a second opening OP2 for forming the contact plug CSb in the peripheral circuit region PA. Accordingly, an insulating film (or "barrier layer CSb1") may be formed on sidewalls of the second opening OP2, and a conductive material (or "conductive layer CSb2") may fill the second opening OP2, while an inner portion including sidewalls of the first opening OP1 may be completely filled with an insulating material. For example, the inside of the protection ring GR and sidewalls of the protection ring GR may include an insulating material (the inside of the protection ring GR is filled with an insulating material and sidewalls of the protection ring GR may be covered with an insulating material).

[0087] Accordingly, the first pattern GDa of the dummy protection pattern GD and the protection ring GR may include different materials, such that a boundary surface between an upper region of the protection ring GR and a lower region of the dummy protection pattern GD may be distinct.

[0088] Referring to Figure 5B , except for a configuration in which there is no pad pattern on sidewalls of each of the protection ring GR and the contact plug CSb, the semiconductor device 100B may be the same as or similar to the example described with reference to Figures 1 to 4 .

[0089] Referring to Figure 7, the inner portions of the first opening OP1 and the second opening OP2 can be filled with only a conductive material. Accordingly, on the sidewall of the guard ring GR, there may be no pad pattern different from the interlayer insulating layer 186 provided on one side of the guard ring GR and the interlayer insulating pattern layer 184_2 provided on the other side of the guard ring GR. Similarly, on the sidewall of the contact plug CSb, there may be no pad pattern different from the interlayer insulating pattern layer 184_1 provided on both sides of the contact plug CSb.

[0090] Reference Figure 5C , except that the barrier layer GRa' of the guard ring GR and the barrier layer CSb1' of the contact plug CSb are configured to include a conductive film of a conductive material, the semiconductor device 100C can be the same as or similar to the example Figures 1 to 4 described.

[0091] Refer together to Figure 7 and Figure 8 , a conductive material can be formed on each of the sidewalls and the lower surface of the first opening OP1 and the second opening OP2, and for example, an anisotropic etching process may not be performed subsequently.

[0092] Accordingly, referring back to Figure 5C , the barrier layer GRa' of the guard ring GR can be provided on the sidewall and the lower surface of the guard ring GR, and can extend along the region between the first pattern GDa of the dummy protection pattern GD and the interlayer insulating pattern layer 184_2 in the upper region of the guard ring GR.

[0093] Similarly, the barrier layer CSb1' of the contact plug CSb can be provided on the sidewall and the lower surface of the contact plug CSb, and can extend along the region between the pad pattern CSa and the interlayer insulating pattern layer 184_1 in the upper region of the contact plug CSb. Accordingly, at least a part of the barrier layer CSb1' can contact at least a part of the insulating pad 185 between the pad pattern Csa and the interlayer insulating pattern layer 184_1.

[0094] According to some example embodiments, each of the barrier layer GRa' and the barrier layer CSb1' can be formed of a material different from the corresponding one of the material of the first pattern GDa of the dummy protection pattern and the pad pattern CSa, and even if the components include the same material, the boundary may become distinct due to differences in physical properties.

[0095] Figures 6A to 6C is an enlarged view showing a part of a semiconductor device according to some example embodiments.

[0096] Reference Figure 6A, except for the configuration in which the side surface GD_SS of the dummy protection pattern GD is inclined with respect to the upper surface GR_US of the guard ring GR, the semiconductor device 100D may be the same as or similar to the example Figures 1 to 5C described.

[0097] Reference Figure 6A , the side surface GD_SS of the dummy protection pattern GD may be inclined toward the upper surface GR_US of the guard ring GR, and thus, at least a part of the upper surface GR_US of the guard ring GR may be exposed and may be in contact with the interlayer insulating layer 186. For example, the side surface GD_SS of the dummy protection pattern may be inclined toward the upper surface GR_US of the guard ring GR such that at least a part of the upper surface of the barrier layer GRa of the guard ring GR may be exposed, but some example embodiments are not limited thereto. For example, the side surface GD_SS of the dummy protection pattern may be inclined with respect to the upper surface GR_US of the guard ring GR such that at least a part of the upper surface of the conductive layer GRb of the guard ring GR is exposed (not shown).

[0098] Reference Figure 6B , except for the configuration in which the dummy protection pattern GD may be arranged to be farther from the cell array region CA than the upper region of the guard ring GR, the semiconductor device 100E may be the same as or similar to the example Figures 1 to 5C described.

[0099] Reference Figure 6B , the side surface GD_SS of the dummy protection pattern may be arranged to be farther from the cell array region CA than one side surface of the upper region of the guard ring GR. For example, an imaginary line X1 extending in the vertical direction (Y direction) from the edge of the upper region of the guard ring GR may be arranged to be closer to the cell array region CA than the side surface GD_SS of the dummy protection pattern.

[0100] Therefore, at least a part of the upper surface of the barrier layer GRa of the guard ring GR may be exposed. Although not shown, at least a part of the upper surface of the conductive layer GRb of the guard ring GR may be exposed.

[0101] Reference Figure 6C , except for the configuration in which the dummy protection pattern GD may be arranged to be closer to the cell array region CA than the upper region of the guard ring GR, the semiconductor device 100F may be the same as or similar to the example Figures 1 to 5C described.

[0102] Reference Figure 6C, the side surface GD_SS of the dummy protection pattern can protrude horizontally toward the cell array region CA instead of protruding toward a side surface of the upper region of the guard ring GR. Therefore, the side surface GD_SS of the dummy protection pattern can be set to be closer to the cell array region CA than a side surface of the upper region of the guard ring GR. For example, an imaginary line X2 extending in the vertical direction (Y direction) from the side surface GD_SS of the dummy protection pattern can be set to be closer to the cell array region CA than a side surface of the upper region of the guard ring GR.

[0103] Figures 7 to 15 is a cross-sectional view showing a method of manufacturing a semiconductor device according to some example embodiments.

[0104] Reference Figure 7 , a preliminary interlayer insulation pattern layer 184' can be formed on a lower structure including a substrate 101, word lines, and a bit line structure BLS, and a plurality of openings OP1 and OP2 penetrating the preliminary interlayer insulation pattern layer 184' can be formed.

[0105] The preliminary interlayer insulation pattern layer 184' can be formed on the etch stop layers 68 and 168 conformally formed on the lower structure.

[0106] A photomask can be aligned on the preliminary interlayer insulation pattern layer 184', and a first opening OP1 penetrating a part of the dummy conductive pattern 166, the preliminary interlayer insulation pattern layer 184', and the etch stop layer 168 can be formed to expose at least a part of the dummy conductive pattern 166 on the interface area IA (see Figure 1 ).

[0107] A second opening OP2 penetrating at least a part of the peripheral interconnect 62, the preliminary interlayer insulation pattern layer 184', and the etch stop layer 68 can be formed such that at least a part of the peripheral interconnect 62 can be exposed on the peripheral circuit region PA.

[0108] Reference Figure 8 , a preliminary barrier layer 201 conformally covering the inner surfaces of the plurality of openings OP1 and OP2 and the upper surface of the preliminary interlayer insulation pattern layer 184' can be formed.

[0109] The preliminary barrier layer 201 can include an insulating material or a conductive material. When the preliminary barrier layer 201 includes an insulating material, at least a part of the preliminary barrier layer 201 formed in the plurality of openings OP1 and OP2 can be etched and removed (see Figure 4 and Figure 9 ). Different from the above examples, when the preliminary barrier layer 201 includes a conductive material, the preliminary barrier layer 201 formed in the plurality of openings OP1 and OP2 can not be removed (see Figure 5C ).

[0110] Reference Figure 9 As shown in Figure 9 , at least a part of the preliminary barrier layer 201 can be removed by an etching process, and a preliminary conductive layer 202 can be formed to fill the plurality of openings OP1 and OP2 and cover the upper surface of the preliminary interlayer insulating pattern layer 184'.

[0111] The preliminary barrier layer 201 formed on the lower surfaces of the plurality of openings OP1 and OP2 and the upper surface of the preliminary interlayer insulating pattern layer 184' can be removed by anisotropic etching. Accordingly, at least a part of the dummy conductive pattern 166 and at least a part of the peripheral interconnect 62 can be exposed in the vertical direction (Z direction).

[0112] Thereafter, a preliminary conductive layer 202 can be formed to fill the plurality of openings OP1 and OP2 and cover the upper surface of the preliminary interlayer insulating pattern layer 184'.

[0113] Reference Figure 10 As shown in Figure 10 , in the peripheral circuit region PA, a plurality of open regions OR penetrating at least a part of the preliminary conductive layer 202 and the preliminary interlayer insulating pattern layer 184' can be formed.

[0114] The plurality of open regions OR can be formed by aligning a photomask on the preliminary conductive layer 202 and using a photolithography process. A connection structure CS including a pad pattern CSa and a contact plug CSb can be defined by the plurality of open regions OR.

[0115] Reference Figure 11 After the process shown in Figure 11 , an insulating liner 185 can be formed. Figure 10 After the process shown in Figure 10 , an insulating liner 185 can be formed.

[0116] Reference together Figure 15 As shown in Figure 15 , the insulating liner 185 can be a stop layer for forming a peripheral contact plug hole H on the connection structure CS.

[0117] The insulating liner 185 can be formed on the preliminary conductive layer 202 in the cell region CA and the interface region IA, and the insulating liner 185 can be conformally formed along the surfaces of the plurality of open regions OR in the peripheral circuit region PA.

[0118] Reference Figure 12 After the process shown in Figure 12 , a photoresist layer PR can be formed across the cell region CA, the interface region IA, and the peripheral circuit region PA, and the photoresist layer PR on the cell region CA can be removed, whereby a cell open region O_CA can be formed. Figure 11 After the process shown in Figure 11 , a photoresist layer PR can be formed across the cell region CA, the interface region IA, and the peripheral circuit region PA, and the photoresist layer PR on the cell region CA can be removed, whereby a cell open region O_CA can be formed.

[0119] The cell opening region O_CA can be formed by aligning a photomask on the photoresist layer PR and using a photolithography process. The cell opening region O_CA is formed by removing the photoresist layer PR on the cell region CA, and thus, the insulating liner 185 on the cell region CA can be exposed.

[0120] Reference Figure 13 , the insulating liner 185 and the preliminary conductive layer 202 on the cell region CA can be removed by an etching process.

[0121] By an etching process, a guard ring structure GRS including a guard ring GR and a dummy guard pattern GD can be defined. The side surface GD_SS of the dummy guard pattern (e.g., see Figure 5A ) can be formed to be substantially coplanar with the side surface of the photoresist layer PR defined by the cell opening region O_CA.

[0122] Reference Figure 14 , after the process in Figure 13 , the preliminary interlayer insulating pattern layer 184' on the cell region CA can be removed by an etching process.

[0123] The etch stop layer 168 may not be etched by the above etching process and can maintain a conformal thickness at the same horizontal level through the cell region CA and the peripheral circuit region PA.

[0124] Reference Figure 15 , after the process in Figure 14 , at least one of the interlayer insulating layers 186 and 188 and a contact plug hole H penetrating at least a part of the interlayer insulating layers 186 and 188 can be formed on the peripheral circuit region PA.

[0125] The contact plug hole H can be formed to penetrate at least a part of the interlayer insulating layers 186 and 188 and the insulating liner 185 on the connection structure CS. Thereafter, a barrier layer PCPa can be formed on the inner sidewall of the contact plug hole H, and a peripheral contact plug PCP can be formed by forming a conductive layer PCPb on the barrier layer PCPa (see Figure 4 ).

[0126] Although not shown, before forming the peripheral contact plug PCP on the peripheral circuit region PA, a data storage structure CAP can be preferentially formed on the cell region CA (see Figure 3B)。For example, before forming the interlayer insulating layers 186 and 188, a desired (and / or predetermined) molding structure can be formed through the cell region CA and the peripheral circuit region PA. The desired (and / or predetermined) molding structure can be formed on a lower structure including the substrate 101, word lines, bit line structures BLS, guard ring structures GRS, and connection structures CS. The desired (and / or predetermined) molding structure can be formed by alternately stacking a plurality of molding layers and a plurality of preliminary support patterns on the etch stop layer 168. Thereafter, a plurality of openings penetrating the desired (and / or predetermined) molding structure can be formed, and a first electrode structure 170 can be formed in the plurality of openings. Thereafter, the plurality of molding layers can be removed, and a dielectric layer 172 covering the surfaces of the plurality of preliminary support patterns and the first electrode structure 170 can be formed, and a second electrode structure 174 can be formed.

[0127] Thereafter, a cell contact plug CCP connected to the data storage structure CAP can be formed, where the cell contact plug CCP can be formed together with a peripheral contact plug PCP according to Figure 15 . Subsequently, an interlayer insulating layer ILD and a plurality of upper contact plugs 92 and 95 can be formed.

[0128] According to the foregoing exemplary embodiments, a semiconductor device with improved reliability can be provided.

[0129] Although some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, the substrate comprising a cell array region and a peripheral circuit region; A peripheral gate structure, the peripheral gate structure is located on the peripheral circuit area of ​​the substrate and includes a peripheral gate dielectric layer, a peripheral gate electrode located on the peripheral gate dielectric layer, a peripheral source / drain located on both sides of the peripheral gate electrode, and a peripheral gate covering pattern located on the peripheral gate electrode; a first peripheral interlayer insulating layer, at least a portion of which is located on a side surface of the peripheral gate structure; a peripheral interconnect, the peripheral interconnect being located on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer, the insulating pattern layer being located on the peripheral interconnection; a connection structure including a pad pattern and a first peripheral contact plug, the pad pattern being located on the insulating pattern layer, and the first peripheral contact plug penetrating the insulating pattern layer and electrically connecting the pad pattern to the corresponding peripheral interconnect; as well as a guard ring structure, the guard ring structure comprising a guard ring and surrounding the cell array region between the cell array region and the peripheral circuit region of the substrate, Wherein, at least a portion of the guard ring of the guard ring structure is at the same height as at least a portion of the first peripheral contact plug of the connection structure.

2. The semiconductor device according to claim 1, further comprising a word line, a bit line and a data storage structure located on the cell array region of the substrate, in, The heights of the word lines and the bit lines are lower than the height of the guard ring. The data storage structure includes a first electrode structure, a second electrode structure, and a dielectric layer located between the first electrode structure and the second electrode structure, and At least one of the first electrode structure and the second electrode structure includes a lower surface whose height is lower than that of the upper surface of the guard ring and an upper surface whose height is higher than that of the upper surface of the guard ring.

3. The semiconductor device according to claim 1, further comprising: a dummy conductive pattern extending from the cell array region of the substrate to the peripheral circuit region, and Wherein, a lower region of the guard ring of the guard ring structure penetrates at least a portion of the dummy conductive pattern.

4. The semiconductor device according to claim 1, wherein: An upper surface of the guard ring of the guard ring structure is at the same height as an upper surface of the first peripheral contact plug of the connection structure.

5. The semiconductor device according to claim 1, wherein The guard ring and the first peripheral contact plug each include a conductive layer and an insulating layer on a side surface of the conductive layer.

6. The semiconductor device according to claim 5, wherein: The insulating layer includes at least one of silicon oxycarbide, silicon nitride and silicon oxycarbonitride.

7. The semiconductor device according to claim 1, in, The horizontal width of the guard ring is smaller than the horizontal width of the first peripheral contact plug, wherein the interior of the protection ring and the sidewalls of the protection ring comprise insulating material, and The first peripheral contact plug includes a conductive layer and an insulating layer located on a side surface of the conductive layer.

8. The semiconductor device according to claim 1, wherein The guard ring, the sidewall of the guard ring, the first peripheral contact plug, and the sidewall of the first peripheral contact plug all include a conductive material.

9. The semiconductor device according to claim 1, further comprising: an interlayer insulating pattern, wherein the interlayer insulating pattern extends from one side of the guard ring toward the peripheral circuit region in a horizontal direction, The guard ring structure further includes a dummy guard pattern located on the guard ring and the interlayer insulation pattern. The guard ring includes a first conductive layer and a second conductive layer located on the first conductive layer, and The second conductive layer extends along a region between the interlayer insulating pattern and the dummy protection pattern.

10. The semiconductor device according to claim 9, in, The first peripheral contact plug includes a third conductive layer and a fourth conductive layer located on the third conductive layer, and The fourth conductive layer extends along a region between the insulating pattern layer and the pad pattern.

11. The semiconductor device according to claim 10, wherein: The second conductive layer and the fourth conductive layer include the same conductive material.

12. The semiconductor device according to claim 11, wherein The conductive material includes at least one of metal nitride and tungsten.

13. A semiconductor device, comprising: A substrate, the substrate comprising a cell array region and a peripheral circuit region; A conductive region, wherein the conductive region is located in the cell array region; A peripheral gate structure, the peripheral gate structure is located on the peripheral circuit area of ​​the substrate, the peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate electrode located on the peripheral gate dielectric layer, a peripheral source / drain located on both sides of the peripheral gate electrode, and a peripheral gate covering pattern located on the peripheral gate electrode; a first peripheral interlayer insulating layer, at least a portion of which is located on a side surface of the peripheral gate structure; a peripheral interconnect, the peripheral interconnect being located on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer, the insulating pattern layer being located on the peripheral interconnection; a stop layer, the stop layer being located on the conductive region on the cell array region, and the stop layer being located between the peripheral interconnect and the insulating pattern layer on the peripheral circuit region; a guard ring structure, the guard ring structure comprising a guard ring, the guard ring surrounding the cell array region, and a lower region of the guard ring penetrating the stop layer at a portion of the stop layer between the cell array region and the peripheral circuit region of the substrate; as well as A connection structure is located on the peripheral circuit area of ​​the substrate, the connection structure includes a pad pattern and a first peripheral contact plug, the pad pattern is located on the insulating pattern layer, and the first peripheral contact plug penetrates the insulating pattern layer and the stop layer and electrically connects the pad pattern to the corresponding peripheral interconnect.

14. The semiconductor device according to claim 13, wherein: The guard ring structure further includes a dummy protection pattern located on the guard ring, and the dummy protection pattern extends toward the peripheral circuit region along a horizontal direction.

15. The semiconductor device according to claim 14, in, In the cross-sectional view, the side surface of the dummy protection pattern is inclined relative to the upper surface of the protection ring, and Wherein, at least a portion of the upper surface of the guard ring is exposed by the dummy guard pattern.

16. The semiconductor device according to claim 14, in, In the cross-sectional view, a side surface of the upper region of the guard ring is closer to the cell array region than a side surface of the dummy protection pattern, and At least a portion of the upper surface of the guard ring is exposed by the dummy guard pattern.

17. The semiconductor device according to claim 14, wherein: In the cross-sectional view, one side surface of the dummy protection pattern protrudes more toward the cell array region than one side surface of an upper region of the guard ring in the horizontal direction.

18. The semiconductor device according to claim 14, in, The dummy protection pattern includes a first pattern located on the protection ring and a second pattern located on the first pattern. wherein the second pattern extends to the peripheral circuit region, and The second pattern covers at least a portion of a surface of the insulating pattern layer and at least a portion of a surface of the pad pattern of the connection structure.

19. The semiconductor device according to claim 18, wherein: The first pattern of the dummy protection pattern and the pad pattern of the connection structure include the same material.

20. A semiconductor device, comprising: A substrate, the substrate comprising a cell array region and a peripheral circuit region; a memory structure including word lines, bit lines and data storage structures located on the cell array region; A peripheral gate structure, the peripheral gate structure is located on the peripheral circuit area of ​​the substrate, the peripheral gate structure includes a peripheral gate dielectric layer, a peripheral gate electrode located on the peripheral gate dielectric layer, a peripheral source / drain located on both sides of the peripheral gate electrode, and a peripheral gate covering pattern located on the peripheral gate electrode; a first peripheral interlayer insulating layer, at least a portion of which is located on a side surface of the peripheral gate structure; a peripheral interconnect, the peripheral interconnect being located on the first peripheral interlayer insulating layer and the peripheral gate structure; an insulating pattern layer, the insulating pattern layer being located on the peripheral interconnection; A pad pattern, the pad pattern being located on the insulating pattern layer; a first peripheral contact plug that penetrates the insulating pattern layer and electrically connects the pad pattern to the corresponding peripheral interconnect; an insulating liner covering the insulating pattern layer and the pad pattern; a second peripheral interlayer insulating layer, the second peripheral interlayer insulating layer being located on the insulating liner; a second peripheral contact plug penetrating the second peripheral interlayer insulating layer and the insulating liner, the second peripheral contact plug being electrically connected to the pad pattern; A guard ring, the guard ring surrounding the cell array region between the cell array region and the peripheral circuit region of the substrate; as well as a dummy protection pattern, the dummy protection pattern being located on the protection ring and extending toward the peripheral circuit region in a horizontal direction, The heights of the word lines and the bit lines are lower than the height of the guard ring. The data storage structure includes a first electrode structure, a second electrode structure, and a dielectric layer located between the first electrode structure and the second electrode structure, and At least one of the first electrode structure and the second electrode structure includes a lower surface whose height is lower than that of the upper surface of the guard ring and an upper surface whose height is higher than that of the upper surface of the guard ring.

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