Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: a semiconductor substrate; a plurality of storage active regions each having a long axis and a short axis and arranged to maintain a first distance between the storage active regions along the short axis and to maintain a second distance between the storage active regions along the long axis; a plurality of logic active regions, each logic active region including at least a P-channel metal oxide semiconductor transistor and arranged to maintain a third distance between adjacent logic active regions; a first device isolation insulating layer in the first trench, having a first portion corresponding to a region between the memory active regions along the long axis direction, including a first nitride insulating layer; and a second device isolation insulating layer in the second trench between the logic active regions and not including the first nitride insulating layer, where the second distance is substantially the same as the third distance.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a memory cell region and a peripheral region. Background Art

[0002] With the rapid development of the electronics industry and user requirements, electronic products have become smaller and lighter. Therefore, for semiconductor memory devices used in electronic products, high integration may be required. The demand for high integration of semiconductor memory devices applies not only to components in the memory cell region of the semiconductor memory device, but also to components in the peripheral region located around the memory cell region. Therefore, miniaturization and higher integration of semiconductor memory devices are required while maintaining the operational reliability of the semiconductor memory device. Summary of the Invention

[0003] The inventive concept provides a semiconductor memory device having a reduced size while maintaining reliable operation of the semiconductor memory device.

[0004] According to an aspect of the inventive concept, there is provided a semiconductor memory device including: a semiconductor substrate including a cell portion in a cell region, a peripheral portion in a peripheral region disposed around the cell region, and a boundary portion in a boundary region between the cell region and the peripheral region; a plurality of memory active regions defined by first trenches in the cell region, each memory active region having a major axis and a minor axis, wherein each memory active region is arranged to maintain a first distance between adjacent memory active regions in a direction along the minor axis, and each memory active region is arranged to maintain a second distance between adjacent memory active regions in a direction along the major axis; a plurality of logic active regions defined by second trenches in the peripheral region, wherein each logic active region includes at least a P-channel metal oxide semiconductor (PMOS) transistor, and each logic active region is arranged to maintain a third distance between adjacent logic active regions; a first device isolation insulating layer partially formed in the first trenches, wherein a first portion of the first device isolation insulating layer corresponding to a region between memory active regions adjacent to each other in a direction along the major axis includes a first nitride insulating layer; and a second device isolation insulating layer partially formed in the second trenches between the logic active regions and not including the first nitride insulating layer, wherein the second distance is substantially the same as the third distance.

[0005] According to another aspect of the inventive concept, there is provided a semiconductor memory device including: a semiconductor substrate including a cell region, a peripheral region disposed around the cell region, and a boundary region between the cell region and the peripheral region; a plurality of memory active regions defined by first trenches in the cell region, each memory active region having a major axis and a minor axis, wherein each memory active region is arranged to maintain a first distance between adjacent memory active regions along the direction of the minor axis, and each memory active region is arranged to maintain a second distance between adjacent memory active regions along the direction of the major axis; a plurality of logic active regions defined by second trenches in the peripheral region, wherein each logic active region includes at least a PMOS transistor, and each logic active region is arranged to maintain a third distance between adjacent logic active regions; a first device isolation insulating layer partially formed in the first trenches, wherein a first portion of the first device isolation insulating layer corresponding to a region between memory active regions adjacent to each other along the direction of the major axis includes a first nitride insulating layer; and a second device isolation insulating layer partially formed in the second trenches, wherein the second device isolation insulating layer includes a first nitride insulating layer, wherein the second distance is substantially the same as the third distance, and a vertical level of an upper end of the first nitride insulating layer of the second device isolation insulating layer is at half or less of a depth of the second trenches.

[0006] According to another aspect of the inventive concept, there is provided a semiconductor memory device including: a semiconductor substrate including a cell region, a peripheral region disposed around the cell region, and a boundary region between the cell region and the peripheral region; a plurality of memory active regions defined by first trenches in the cell region, each memory active region having a major axis and a minor axis, wherein each memory active region is arranged to maintain a first distance between adjacent memory active regions along the direction of the minor axis, and each memory active region is arranged to maintain a second distance between adjacent memory active regions along the direction of the major axis; a plurality of logic active regions defined by second trenches in the peripheral region, wherein the plurality of logic active regions includes at least a PMOS transistor, and the plurality of logic active regions adjacent to each other are arranged while maintaining a third distance therebetween; a first device isolation insulating layer partially formed in the first trenches and including a first silicon nitride layer formed below an upper end of the first trenches; a second device isolation insulating layer partially formed in second trenches between adjacent logic active regions and not including the first silicon nitride layer; and a third device isolation insulating layer partially formed in third trenches in the boundary region between the outermost memory active region among the plurality of memory active regions and the innermost logic active region among the plurality of logic active regions, wherein the third device isolation insulating layer is asymmetrically formed between the innermost logic active region and the outermost memory active region in a vertical cross section; wherein the second distance is substantially the same as the third distance. Description of the Drawings

[0007] Embodiments will be understood more clearly by the following detailed description in conjunction with the accompanying drawings, wherein:

[0008] Figure 1 is a block diagram for explaining a semiconductor memory device according to some embodiments;

[0009] Figure 2 is a schematic layout of main components of a semiconductor memory device according to some embodiments;

[0010] Figure 3 is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0011] Figure 4 is Figure 3 an enlarged cross-sectional view of the "A" part of;

[0012] Figure 5 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0013] Figure 6 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments.

[0014] Figure 7 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments.

[0015] Figure 8 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments.

[0016] Figure 9 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments.

[0017] Figure 10 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments.

[0018] Figure 11 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments.

[0019] Figure 12 is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0020] Figure 13 is showing corresponding to Figure 15 an enlarged cross-sectional view of another embodiment of the "B" part of;

[0021] Figure 14 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0022] Figure 15 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0023] Figure 16 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0024] Figure 17 is a cross-sectional view of a semiconductor memory device according to some embodiments;

[0025] Figure 18 is Figure 17 an enlarged cross-sectional view of the "C" portion of;

[0026] Figure 19 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0027] Figure 20 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0028] Figure 21 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments;

[0029] Figure 22 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments; and

[0030] Figure 23 is a cross-sectional view showing the state of a semiconductor device during a method of manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0031] Some embodiments will be described in detail below with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are merely examples, and many variations and embodiments without the details provided herein are possible. It should also be emphasized that the present disclosure provides details of alternative examples, but such alternative listings are not exhaustive. Moreover, any detail consistency between various examples should not be construed as requiring such detail - it is not practical to list every possible variation of each feature described herein. When determining the requirements of the present invention, reference should be made to the language of the claims.

[0032] In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same numerals always refer to the same elements. Although the different drawings show variations of exemplary embodiments, these drawings are not necessarily intended to be mutually exclusive. Rather, as will be seen from the context of the following detailed description, when the drawings and their descriptions are considered as a whole, certain features depicted and described in different drawings may be combined with other features from other drawings to yield various embodiments.

[0033] As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and may be abbreviated as " / ". When referring to the relationship between at least one of a plurality of items, it will be understood that, unless otherwise stated, the relationship between individual items among the plurality of items can be one-to-one, many-to-one, one-to-many and / or many-to-many, unless otherwise stated or the context clearly indicates otherwise.

[0034] Although the corresponding plan views and / or perspective views of some cross-sectional views may not be shown, the cross-sectional views of the device structures shown herein provide support for a plurality of device structures that extend in two different directions as would be shown in a plan view and / or in three different directions as would be shown in a perspective view. These two different directions may be orthogonal to each other or may not be orthogonal to each other. These three different directions may include a third direction that is orthogonal to the two different directions. A plurality of device structures may be integrated in the same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is shown in a cross-sectional view, the electronic device may include a plurality of device structures (e.g., a memory cell structure or a transistor structure) as may be shown by the plan view of the electronic device. The plurality of device structures may be arranged in an array and / or a two-dimensional pattern.

[0035] Ordinal numbers, such as "first", "second", "third", etc., may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. Terms not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, a term referred to by a specific serial number (e.g., "first" in a specific claim) may be described elsewhere by a different serial number (e.g., "second" in the specification or another claim).

[0036] Figure 1 is a block diagram for illustrating a semiconductor memory device 1 according to some embodiments.

[0037] Reference Figure 1, the semiconductor memory device 1 may include a cell region CLR in which a plurality of semiconductor memory cells are provided, and a main peripheral region PRR surrounding the cell region CLR.

[0038] According to some embodiments, the cell region CLR may include a plurality of cell blocks SCB, each of which is separated by a sub-peripheral region SPR. Each cell block SCB may include a plurality of semiconductor memory cells. As used herein, the cell block SCB refers to a region where semiconductor memory cells are regularly arranged at a predetermined interval, and the cell block SCB may also be referred to as a sub-cell block.

[0039] A plurality of logic units may be located in the main peripheral region PRR and the sub-peripheral region SPR, and may input (i.e., receive) electrical signals to / output (i.e., send) electrical signals from the semiconductor memory cells. In some embodiments, the main peripheral region PRR may be referred to as a peripheral circuit region, and the sub-peripheral region SPR may be referred to as a core circuit region. The peripheral region PR may include the main peripheral region PRR and the sub-peripheral region SPR. For example, the peripheral region PR may be a circuit region including a peripheral circuit region and a core circuit region. In some embodiments, at least a part of the sub-peripheral region SPR may be provided only as a space for separating the cell blocks SCB.

[0040] Hereinafter, a region where semiconductor memory cells are regularly arranged may be referred to as a "cell region CR" or a "memory cell region CR", a region where logic units are arranged around the cell region CR may be referred to as a "peripheral region PR", and a region between the cell region CR and the peripheral region PR may be referred to as a "boundary region BR".

[0041] Figure 2 is a schematic layout for illustrating main components of the semiconductor memory device 1 according to some embodiments. Figure 2 is shown in Figure 1 a layout of a part of the cell region CR adjacent to the peripheral region PR in the semiconductor memory device 1, and is provided for ease of description.

[0042] Referring to Figure 2 , the semiconductor memory device 1 may include a cell region CR and a peripheral region PR. The semiconductor memory device 1 may include a plurality of memory active regions ACT formed in the cell region CR and a plurality of logic active regions ACTP formed in the peripheral region PR. The cell region CR may include Figure 1 the cell blocks SCB shown in Figure 1 wherein a plurality of semiconductor memory cells are provided, and the peripheral region PR may be

[0043] In some embodiments, the storage active regions ACT provided in the cell region CR may be regularly arranged to have a major axis in a diagonal direction with respect to the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). However, the inventive concept is not limited thereto, and in some embodiments, the storage active regions ACT may be regularly arranged to have a major axis in the X direction or in the Y direction. In addition, in some embodiments, the storage active regions ACT may be arranged side by side in the X or Y direction, or may be arranged in a zigzag manner in the X or Y direction.

[0044] Each of the plurality of storage active regions ACT formed in the cell region CR may be defined by the device isolation insulating layer 14. The device isolation insulating layer 14 may be an insulating layer around each storage active region ACT. The insulating layer may be formed in a trench around each storage active region ACT. The trench may be formed using a shallow trench isolation (STI) process, and the trench may be filled with an insulating layer to electrically isolate the storage active regions ACT from each other. In addition, the plurality of logic active regions ACTP formed in the peripheral region PR may be defined by the device isolation insulating layer 54. The device isolation insulating layer 54 may be a device insulating layer around each logic active region ACTP. The insulating layer may be formed in a trench around each logic active region ACTP. The trench may be formed in the semiconductor substrate around each logic active region ACTP, and an insulating layer may be formed in the trench.

[0045] The inventive concept may be applied to a case where each storage active region ACT has an elongated shape with a major axis and a minor axis, and the pitch between adjacent storage active regions ACT in the major axis direction is different from the pitch between adjacent storage active regions ACT in the minor axis direction. Hereinafter, a description will be made with reference to an embodiment in which the storage active regions ACT may be regularly arranged to have a major axis in a diagonal direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), and the pitch between adjacent storage active regions ACT in the major axis direction is greater than the pitch between adjacent storage active regions ACT in the minor axis direction.

[0046] Refer again to Figure 2, each memory active region ACT may have a major axis length L1 and a minor axis length L2 (where L1 > L2). The distance between memory active regions ACT adjacent to each other in the minor axis direction of the memory active region ACT can be expressed as D1, and the distance between memory active regions ACT adjacent to each other in the major axis direction of the memory active region ACT can be expressed as D2 (where D2 > D1). In addition, the distance in the X direction between each logic active region ACTP formed in the peripheral region PR can be expressed as D3, and the distance between the outermost memory active region ACT among the plurality of memory active regions ACT in the cell region CR facing the peripheral region PR and the innermost logic active region ACTP among the plurality of logic active regions ACTP in the peripheral region PR facing the cell region CR can be expressed as D4.

[0047] The distance D5' can represent the distance between one memory active region ACT and the next memory active region ACT in the minor axis direction of the memory active region ACT (i.e., D5' = 2D1 + L2). The phrase "the next" refers to the item after the next item. For example, if three items are given in the order from the first to the third, referring to the first item, the next item is the second item, and the next item is the third item. In addition, since the memory active region ACT is formed in the diagonal direction at an angle θ with respect to the first horizontal direction (X direction), the distance D5 can represent the distance between one memory active region ACT and the next memory active region ACT in the first horizontal direction (i.e., D5' = D5 × sinθ). Considering that the memory active region ACT is formed in the diagonal direction having an angle θ with respect to the first horizontal direction (X direction), the distance D6 can represent the distance between one memory active region ACT and the adjacent memory active region ACT in the first horizontal direction (i.e., D1 = D6 × sinθ).

[0048] In some embodiments, the semiconductor memory device 1 may be a dynamic random access memory (DRAM) device. For ease of description, Figure 2 is a simplified schematic diagram, which only shows the arrangement of a part of the plurality of memory active regions ACT formed in the cell region CR near the peripheral region PR and a part of the plurality of logic active regions ACTP formed in the peripheral region PR.

[0049] Although not specifically shown, in the case of a DRAM device, a plurality of word lines WL may extend parallel to each other in the first horizontal direction (X direction), crossing the plurality of memory active regions ACT in the memory cell region CR. On the plurality of word lines WL, a plurality of bit lines BL (not shown) may extend parallel to each other in the second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). The plurality of bit lines BL may be connected to the plurality of memory active regions ACT through direct contacts DC (not shown).

[0050] In some embodiments, a plurality of buried contacts BC (not shown) may be formed between adjacent bit lines BL among a plurality of bit lines BL. In some embodiments, the plurality of buried contacts BC may be arranged in a row in a first horizontal direction (X direction) and a second horizontal direction (Y direction), respectively.

[0051] A plurality of landing pads LP (not shown) may be formed on the plurality of buried contacts BC. The plurality of landing pads LP may be arranged to at least partially overlap the plurality of buried contacts BC. In some embodiments, the plurality of landing pads LP may extend over the upper portion of any one of the adjacent bit lines BL.

[0052] A plurality of storage nodes SN (not shown) may be formed on the plurality of landing pads LP. The plurality of storage nodes SN may be formed over the plurality of bit lines BL. Each of the plurality of storage nodes SN may be a lower electrode of a plurality of capacitors (not shown). The storage node SN may be connected to the storage active region ACT through the landing pad LP and the buried contact BC.

[0053] A plurality of gate line patterns GLP (not shown) may be arranged in the peripheral region PR over the logic active region ACTP. The plurality of gate line patterns GLP may extend parallel to each other in the first horizontal direction (X direction) over the logic active region ACTP.

[0054] For write and read operations of the DRAM, a plurality of word lines WL extending parallel to each other in the first horizontal direction (X direction) across a plurality of storage active regions ACT in the memory cell region may be driven by a sub-word line driver SWLD formed in the peripheral region PR. The sub-word line driver SWLD may include a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor.

[0055] In some embodiments, the sub-word line driver SWLD may be formed in a plurality of logic active regions ACTP to drive a plurality of word lines WL extending in the X direction from the cell region CR, and may include PMOS devices. For example, the PMOS devices may include PMOS transistors. Such a sub-word line driver may be referred to as a PMOS sub-word line driver (PSWD).

[0056] Generally, device isolation processes, such as STI processes, can be used for the electrical isolation of adjacent devices in a semiconductor memory device. Specifically, the STI process can be used to electrically isolate the memory active regions ACT formed in the cell region CR from each other, and to electrically isolate the logic active regions ACTP formed in the peripheral region PR from each other, so that a device isolation insulating layer can be formed around each memory active region ACT and each logic active region ACTP. The device isolation insulating layer can be formed by forming trenches in the semiconductor substrate around each of the memory active regions ACT and the logic active regions ACTP, sequentially forming a thin oxide layer and a pad nitride layer in the trenches, and forming an insulating layer for device isolation thereon, for example, forming an oxide layer filling the trenches thereon.

[0057] The oxide layer of the insulating layer for device isolation can have tensile stress, which can cause compressive stress to be applied to the active regions surrounded by the device isolation insulating layer. In the case of NMOS devices, when the channel in the active region is subjected to compressive stress, the mobility of electrons can be reduced, and the operating speed of the NMOS device can be reduced. The nitride layer used in the device isolation insulating layer can play a role in alleviating, offsetting, or preventing the stress generated by the oxide layer. Therefore, in the region where NMOS devices are formed, the nitride layer in the device isolation insulation can play an important role in reducing stress.

[0058] In the region where PMOS devices are formed, according to the characteristics of PMOS transistors, when a PMOS transistor is turned on, electron-hole pairs (EHPs) as hot carriers may be generated, and electrons among the electron-hole pairs may be trapped in the pad nitride layer. Hot electron induced punchthrough (HEIP) can be induced by the electrons trapped in the pad nitride layer, and holes can be induced at the channel edge of the active region of the PMOS transistor by the electrons trapped in the pad nitride layer. Therefore, even when the PMOS transistor is in the off state, the deterioration of the off characteristics may occur, resulting in an increase in current. To alleviate this problem in the region where PMOS devices are formed, when forming the device isolation insulating layer, the formation of the nitride layer can be skipped, or the nitride layer already formed in the device isolation insulating layer can be removed. Alternatively, the nitride layer formed in the device isolation insulating layer can be formed in such a way that it should not be a factor degrading the operating characteristics of the PMOS device.

[0059] When the pitch between the logic active regions in the peripheral region where PMOS devices are formed is narrow, during the STI process for forming the device isolation insulating layer that defines the logic active regions, the nitride layer can remain in the device isolation insulating layer. In this case, as described above, the operating characteristics of the PMOS device may deteriorate, thereby reducing the reliability of the semiconductor memory device.

[0060] On the other hand, when the pitch between the logic active regions in the peripheral region where the PMOS device is formed is wide, a nitride layer may not be formed in the device isolation insulating layer during the STI process for forming the device isolation insulating layer that defines the logic active regions. In order to have no nitride layer in the device isolation insulating layer, the pitch between the logic active regions in the peripheral region was previously formed to be much larger than the pitch between the memory active regions in the cell region. However, although the problem of degrading the operating characteristics of the PMOS device as described above may not occur, the size of the semiconductor memory device may increase due to the widened pitch, which runs counter to the trend of miniaturization of semiconductor memory devices.

[0061] In view of the above problems, an embodiment of the inventive concept may provide a semiconductor memory device and a method of manufacturing the same, in which no nitride layer is present in the device isolation insulating layer that isolates the logic active regions from each other in the peripheral region where the PMOS device is formed.

[0062] Figure 3 is a cross-sectional view showing a semiconductor memory device according to some embodiments. Figure 3 is a cross-sectional view taken along line A-A' of Figure 2 Reference

[0063] and Figure 3 and Figure 2 , a plurality of active regions may be formed on the upper portion of the semiconductor substrate 10. The semiconductor substrate 10 may have a cell portion corresponding to the cell region, a peripheral portion corresponding to the peripheral region, and a boundary portion corresponding to the boundary region. The plurality of memory active regions formed in the cell region CR may include a first memory active region 12a, a second memory active region 12b, a third memory active region 12c, and a fourth memory active region 12d formed in sequence toward the inside (e.g., the center) of the cell region. The plurality of logic active regions formed in the peripheral region PR may include a first logic active region 52a and a second logic active region 52b formed in sequence toward the outside of the semiconductor memory device 1. The first trenches ( Figure 5 T11 and T12 in Figure 5 ) may refer to the trenches surrounding the memory active regions in the cell region CR, the second trench ( Figure 5 T2 in

[0064] ) may refer to the trench surrounding the logic active regions in the peripheral region PR, and the third trench ( Figure 5 T3 in

[0064] ) may refer to the trench formed between the cell region CR and the peripheral region PR. In some embodiments, the cell region CR may be an NMOS region where semiconductor memory cells and mainly NMOS transistors are formed, but is not limited thereto. On the other hand, the peripheral region PR may be a PMOS region where at least one PMOS device, such as a PMOS transistor, is formed.The device isolation insulating layer 14 may be formed in the first trench T11. The first trench T11 between the first storage active region 12a and the second storage active region 12b and between the third storage active region 12c and the fourth storage active region 12d may include a first nitride insulating layer 18a. As Figure 3 shown, the first trench T11 between the first storage active region 12a and the second storage active region 12b and between the third storage active region 12c and the fourth storage active region 12d may be the first trench T11 formed between the storage cell active regions adjacent along the long axis direction of the storage cell active region, as Figure 2 shown. The portion of the device isolation insulating layer formed in the first trench T12 between the second storage active region 12b and the third storage active region 12c may not include the first nitride insulating layer. As Figure 2 shown, the first trench T12 between the second storage active region 12b and the third storage active region 12c may be the first trench T12 formed between the storage cell active regions adjacent along the short axis direction of the storage cell active region.

[0065] According to some embodiments, the first nitride insulating layer 18a may not be present in the device isolation insulating layer formed in the second trench T2 between the first logic active region 52a and the second logic active region 52b in the peripheral region PR. Therefore, in the first logic active region 52a and the second logic active region 52b that are PMOS regions, the deterioration of the operating characteristics of the PMOS device due to the first nitride insulating layer 18a as described above does not occur.

[0066] According to some embodiments, the distance D3 in the X direction between a plurality of logic active regions ACTP formed in the peripheral region PR (for example, the distance D3 between the first logic active region 52a and the second logic active region 52b) may be substantially the same as the distance D2, which is the distance between the storage active regions in the long axis direction of the storage active regions formed in the cell region CR.

[0067] The phrase "substantially the same distance" means that the difference between the distance D3 and the distance D2 is about 20% or less, such as preferably about 10% or less, preferably about 5% or less, preferably about 2% or less, or preferably about 1% or less. As used herein, terms such as "same", "equal", "plane", "coplanar", "parallel", and "perpendicular" include the same or approximately the same, including, for example, variations that may occur due to manufacturing processes. The term "substantially" may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

[0068] As referred to above Figure 2As described above, the distance D5 is the distance in the first horizontal direction between the first storage active region 12a and the second storage active region 12b (which are one storage active region and the next adjacent storage active region in the short-axis direction) (i.e., D5' = D5 × sinθ, where D5' = 2D1 + L2). The distance D5 is not necessarily the same as the distance D5'. However, since the distance D5 is the distance between the next adjacent storage active regions in the short-axis direction, the distance D5 can be the same as or similar to the distance D2. In some embodiments, the distance D5 can also be "substantially the same" as the distance D2. Depending on the angle θ, the distance D6 can be the same as or similar to the distance D1 and is related to the use of the formula D1 = D6 × sinθ.

[0069] According to some embodiments, although the distance D3 in the X direction between adjacent logic active regions (e.g., the distance D3 between the first logic active region 52a and the second logic active region 52b) can be substantially the same as the distance D5 in the X direction between adjacent storage active regions as observed in a cross-section such as Figure 3 the first nitride insulating layer 18a can be formed in the device isolation insulating layer in the first trench T11 provided in the cell region CR, but the first nitride insulating layer 18a may not be formed in the device isolation insulating layer in the second trench T2 provided in the peripheral region PR. Thus, even if the pitch between the logic active regions in the peripheral region PR is reduced to the pitch between the storage active regions in the cell region CR, the first nitride insulating layer 18a is not formed in the device isolation insulating layer in the second trench T2 in the peripheral region PR, and thus the overall size of the semiconductor memory device 1 in the X direction can be reduced without degrading the operating characteristics of the PMOS device. For the same reason, the overall size of the semiconductor memory device 1 in the Y direction can be reduced.

[0070] The semiconductor substrate 10 can be formed of and / or include silicon (Si), crystalline Si, polycrystalline Si, or amorphous Si. In some embodiments, the semiconductor substrate 10 can be formed of a semiconductor element such as germanium (Ge) and at least one compound semiconductor selected from SiGe, SiC, GaAs, InAs, and InP, and / or include a semiconductor element such as germanium (Ge) and at least one compound semiconductor selected from SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the semiconductor substrate 10 can have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate 10 can include a buried oxide (BOX) layer. The semiconductor substrate 10 can include conductive regions, such as impurity-doped wells or impurity-doped structures.

[0071] Device isolation insulating layers formed in the first trenches T11 and T12, the second trench T2, and the third trench T3, respectively, may be formed in different shapes and / or configurations, and portions of the device isolation insulating layers may be formed of different materials and / or include different materials. Generally, the device isolation insulating layer may include at least one of, for example, silicon oxide, silicon nitride, or silicon oxynitride. The device isolation insulating layer may include a single layer composed of one insulating layer, a bilayer composed of two insulating layers, or a multilayer composed of at least three insulating layers.

[0072] A first portion of the device isolation insulating layer formed in the first trench T11 between the memory active regions in the long axis direction of the memory active regions (e.g., between the first memory active region 12a and the second memory active region 12b (or between the third memory active region 12c and the fourth memory active region 12d)) may include a first insulating layer 16, a first nitride insulating layer 18a, a second insulating layer 20a, a third insulating layer 22a, and a fourth insulating layer 26 stacked in sequence. The phrase "stacked in sequence" means that the elements are stacked on top of each other in a given order. In some embodiments, the first insulating layer 16 may include an oxide insulating layer, such as, for example, a silicon oxide insulating layer, but is not limited thereto. The first nitride insulating layer 18a may include, for example, a silicon nitride insulating layer, but is not limited thereto. The second insulating layer 20a may include, for example, a nitride insulating layer, such as a silicon nitride insulating layer, but is not limited thereto. The third insulating layer 22a may include, for example, an oxide insulating layer, such as a silicon oxide insulating layer, but is not limited thereto. The fourth insulating layer 26 may include, for example, an oxide insulating layer, such as a silicon oxide insulating layer, but is not limited thereto.

[0073] A second portion of the device isolation insulating layer formed in the first trench T12 between the memory active regions in the short axis direction of the memory active regions (e.g., between the second memory active region 12b and the third memory active region 12c) may include a first insulating layer 16, a second insulating layer 20a, a third insulating layer 22a, and a fourth insulating layer 26 stacked in sequence. Specifically, compared to the first portion of the device isolation insulating layer in the first trench T11, the second portion of the device isolation insulating layer formed in the first trench T12 does not include (e.g., omits) the first nitride insulating layer 18a, and most of the first trench T12 may be filled with the first insulating layer 16.

[0074] The device isolation insulating layer formed in the second trench T2 between the logic active regions in the peripheral region PR (e.g., between the first logic active region 52a and the second logic active region 52b) may include a first insulating layer 16 and a fourth insulating layer 26 stacked in sequence. Specifically, compared with the first part of the device isolation layer in the first trench, the device isolation insulating layer in the second trench T2 may not include (e.g., omit) the first nitride insulating layer 18a included in the first trench T11, and most of the remaining part of the second trench T2 may be filled with the fourth insulating layer 26.

[0075] The device isolation insulating layer formed in the third trench T3 in the boundary region BR is asymmetrically formed, as Figure 3 and Figure 4 shown, Figure 4 for Figure 3 an enlarged cross-sectional view of the "A" part of. Specifically, the device isolation insulating layer formed on the side of the first memory active region 12a may include a first insulating layer 16, a second insulating layer 20a, a third insulating layer 22a, and a fourth insulating layer 26, and they are stacked in sequence along the sidewall of the first memory active region 12a, which is the outermost memory active region adjacent to the boundary region BR among the memory active regions. The device isolation insulating layer formed on the side of the first logic active region 52a may include a first insulating layer 16 and a fourth insulating layer 26, and they are stacked in sequence along the sidewall of the first logic active region 52a, which is the innermost logic active region adjacent to the boundary region BR among the logic active regions.

[0076] In addition, the device isolation insulating layer formed in the third trench T3 in the boundary region BR may include a fifth insulating layer 28a and a sixth insulating layer 29a on the fourth insulating layer 26. The fifth insulating layer 28a may include, for example, a nitride insulating layer, such as a silicon nitride insulating layer, but is not limited thereto. The sixth insulating layer 29a may be formed of an oxide insulating layer and / or include an oxide insulating layer, such as, for example, a polysilazane layer with the trade name Tonen SilaZene (TOSZ®), but is not limited thereto.

[0077] As Figure 4 shown, the second insulating layer 20a and the third insulating layer 22a in the device isolation insulating layer formed on the side of the first memory active region 12a may protrude in a tail shape toward the central region of the third trench T3 in the horizontal direction (i.e., the X direction). For example, the lower ends of the second insulating layer 20a and the third insulating layer 22a may extend horizontally from the sidewall of the third trench T3 relative to the remaining parts of the second insulating layer 20a and the third insulating layer 22a.

[0078] According to some embodiments, the deterioration of the operating characteristics of the PMOS device due to the nitride insulating layer as described above does not occur in the first logic active region 52a and the second logic active region 52b which are the PMOS regions. In addition, according to some embodiments, even when the pitch between the logic active regions in the peripheral region PR is reduced to the pitch between the storage active regions in the cell region CR, the first nitride insulating layer 18a is not formed in the device isolation insulating layer in the second trench T2 in the peripheral region PR. Therefore, the overall size of the semiconductor memory device 1 in the X and Y directions can be reduced without deteriorating the operating characteristics of the PMOS device.

[0079] Figures 5 to 11 is a cross-sectional view showing the state of the semiconductor memory device during the method of manufacturing a semiconductor memory device according to some embodiments. Figures 5 to 11 is along Figure 2 The cross-sectional view corresponding to the cross-sectional view taken along line A - A' of. Figure 3 is to execute Figure 11 The cross-sectional view after the steps of.

[0080] Reference Figure 5 and Figure 2 , by etching a portion of the semiconductor substrate 10 through a photolithography process using a mask (not shown), trenches T11, T12, T2, and T3 can be formed on the upper portion of the semiconductor substrate 10. Trenches T11, T12, T2, and T3 are shown as being separated from each other in the Figure 5 cross-sectional view, but are connected to each other in a plan view (for example, portions of the trenches can extend horizontally between the trenches in other cross-sections). As a result of forming trenches T11, T12, T2, and T3, a plurality of storage active regions ACT and a plurality of logic active regions ACTP can be formed on the upper portion of the semiconductor substrate 10. The plurality of storage active regions ACT formed in the cell region CR can include a first storage active region 12a, a second storage active region 12b, a third storage active region 12c, and a fourth storage active region 12d formed in sequence toward the inside of the cell region CR. The plurality of logic active regions ACTP formed in the peripheral region PR can include a first logic active region 52a and a second logic active region 52b formed in sequence toward the outside of the semiconductor memory device 1. In addition, the trenches formed in the cell region CR can be identified as the first trenches T11 and T12, the trenches formed in the peripheral region PR can be identified as the second trench T2, and the trenches formed in the boundary region BR can be identified as the third trench T3.

[0081] In some embodiments, the cell region CR can be an NMOS region where semiconductor memory cells are formed, and NMOS transistors can be mainly formed, but are not limited thereto. On the other hand, the peripheral region PR can be a PMOS region where at least one PMOS device, such as a PMOS transistor, is formed.

[0082] According to some embodiments, the distance D3 between the first logic active region 52a and the second logic active region 52b may be substantially the same as the distance D2 in the major axis direction between the memory active regions adjacent to each other in the major axis direction of the plurality of memory active regions formed in the cell region CR. As described above with respect to Figure 2 and Figure 3 stated, the difference between the distance D3 and the distance D2 may be in a range of about 20% or less, such as preferably about 10% or less, preferably about 5% or less, preferably about 2% or less, or preferably about 1% or less. Further, the distance D5 represents the distance between the first memory active region 12a and the second memory active region 12b (i.e., D5' = D5 × sin θ, where D5' = 2D1 + L2, and θ is the tilt angle with respect to the horizontal direction), and the distance D5 may be different from the distance D2. The distance D5 is the distance between the memory active regions in the first horizontal direction and may be the same as or similar to the distance D2 depending on the distance between one memory active region and the next adjacent memory active region in the memory active regions. In some embodiments, the distance D5 may also be "substantially the same" as the distance D2. On the same premise as above, the distance D6 may be the same as or similar to the distance D1 and is related to the formula D1 = D6 × sin θ.

[0083] Subsequently, the first insulating layer 16 may be formed on the exposed surface of the semiconductor substrate 10, on which a plurality of memory active regions and a plurality of logic active regions are formed. The first insulating layer 16 may be formed by performing a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. Specifically, known deposition techniques such as thermal evaporation method, sputtering deposition method, atmospheric CVD (APCVD) method, low pressure CVD (LPCVD) method, plasma enhanced CVD (PECVD) method, high density plasma CVD (HDPCVD) method, metal organic CVD (MOCVD) method, and atomic layer deposition (ALD) method, etc., may be used to form the first insulating layer 16. In some embodiments, the ALD method may be used.

[0084] The first insulating layer 16 may be formed differently according to the size of the trench, e.g., the horizontal distance of the trench or the width of the trench. Specifically, in the first trench T11 between the first storage active region 12a and the second storage active region 12b and between the third storage active region 12c and the fourth storage active region 12d, in the second trench T2 between the first logic active region 52a and the second logic active region 52b, and in the third trench T3 in the boundary region BR, the first insulating layer 16 may be formed along the bottom and sidewalls of its trench without completely filling the trench. However, the first trench T12 between the second storage active region 12b and the third storage active region 12c may be completely filled with the first insulating layer 16, and this second portion has a narrow trench width. The first insulating layer 16 may include an oxide-based insulating layer, such as a silicon oxide insulating layer, and is not limited thereto.

[0085] Reference Figure 6 , the first nitride insulating layer 18 may be formed on the entire surface of the semiconductor substrate 10 on which the first insulating layer 16 is formed. Depending on the size of the trench, e.g., the horizontal distance of the trench or the width of the trench, the first nitride insulating layer 18 may be formed differently. Specifically, the first trench T11 between the first storage active region 12a and the second storage active region 12b, the first trench T11 between the third storage active region 12c and the fourth storage active region 12d, and the second trench T2 between the first logic active region 52a and the second logic active region 52b may be completely filled with the first nitride insulating layer 18. On the other hand, the first nitride insulating layer 18 may be formed along the bottom and sidewalls of the third trench T3 having a relatively large size in the boundary region BR without completely filling the third trench T3. On the other hand, in the first trench T12 between the second storage active region 12b and the third storage active region 12c, where the width of the trench T12 is relatively small and may have been completely filled with the first insulating layer 16, the first nitride insulating layer 18 may not be formed. The first nitride insulating layer 18 may include a nitride-based insulating layer, such as a silicon nitride insulating layer, and is not limited thereto. Depending on the etching conditions, the first nitride insulating layer 18 may have an etching selectivity with respect to the first insulating layer 16.

[0086] Reference Figure 7, an etching process may be performed on the first nitride insulating layer 18 to remove a portion of the first nitride insulating layer 18 to form the first nitride insulating layer 18a. The etching process may be performed using a dry etching method or a wet etching method. For example, a chemical etching method using an etchant, such as a lift-off process, or a known dry etching method, such as a plasma etching method, a sputter etching method, a reactive ion etching (RIE) method, etc., may be used for the etching process. As a result of the etching process, the first nitride insulating layer 18 may remain in the first trench T11 between the first storage active region 12a and the second storage active region 12b, the first trench T11 between the third storage active region 12c and the fourth storage active region 12d, and the second trench T2 between the first logic active region 52a and the second logic active region 52b. On the other hand, in the third trench T3 where the trench size in the boundary region BR is relatively large, the exposed area of the first nitride insulating layer 18 exposed to the etching environment is relatively large, so the first nitride insulating layer 18 may be completely removed.

[0087] Reference Figure 8 , a second insulating layer 20 may be formed on the entire exposed surface of the semiconductor substrate 10 in the state shown in Figure 7 . The second insulating layer 20 may include a nitride-based insulating layer, such as a silicon nitride insulating layer, and is not limited thereto. The second insulating layer 20 may be formed to be relatively thinner than the first nitride insulating layer 18. Depending on the etching conditions, the second insulating layer 20 may have an etching selectivity with respect to the first nitride insulating layer 18. Subsequently, a third insulating layer 22 may be formed on the second insulating layer 20. Depending on the etching conditions, the third insulating layer 22 may have an etching selectivity with respect to the second insulating layer 20. The third insulating layer 22 may include an oxide-based insulating layer, such as a silicon oxide insulating layer. The third insulating layer 22 may be a buffer oxide insulating layer that serves as a buffer layer in a subsequent process when removing the second insulating layer 20, which is a nitride-based insulating layer.

[0088] Reference Figure 9 , a mask pattern 24 may be formed on a portion of the exposed surface of the semiconductor substrate 10 in the state shown in Figure 8 , where the mask pattern 24 may cover the cell region CR and a portion of the boundary region BR and may selectively expose another portion of the boundary region BR and the peripheral region PR. The mask pattern 24 may be formed using a photoresist material by photolithography. Subsequently, using the mask pattern 24 as an etching mask, the third insulating layer 22 serving as a buffer layer in another portion of the boundary region BR and the peripheral region PR may be selectively removed to form the third insulating layer 22a. As a result, a portion of the second insulating layer 20 may be exposed in another portion of the boundary region BR and the peripheral region PR.

[0089] Reference Figure 10 ,the mask pattern 24 can be removed. For example, the removal of the mask pattern 24 can be performed by a dry stripping process (or ashing process). In the dry stripping process, for example, oxygen (O 2 ), or SF 6 / O 2 plasma can be used, where the oxygen plasma can break the connecting chains of the organic matter and the photoresist material, and even break the benzene ring to remove the photoresist material. After the dry stripping process, a cleaning process can be performed to remove the mask pattern 24.

[0090] Subsequently, referring to Figure 10 , by removing the mask pattern 24, the third insulating layer 22a that was previously covered by the mask pattern 24 can be exposed and have the same pattern as the now-removed mask pattern 24. Subsequently, using the exposed third insulating layer 22a as an etch mask, another part of the second insulating layer 20 in the boundary region BR and the part in the peripheral region PR can be etched and removed to form the second insulating layer 20a. Subsequently, the first nitride insulating layer 18a remaining in the second trench T2 in the peripheral region PR can be removed. Preferably, the first nitride insulating layer 18a remaining in the second trench T2 can be completely removed. In some embodiments, as long as any remaining portion of the first nitride insulating layer 18a does not cause the operating characteristics of the PMOS devices in the PMOS regions formed in the first logic active region 52a and the second logic active region 52b to deteriorate, a part of the first nitride insulating layer 18a can be retained near the bottom of the second trench T2.

[0091] Subsequently, after removing the third insulating layer 22a and the first nitride insulating layer 18a from the peripheral region PR and the other part of the boundary region BR, a fourth insulating layer 26 can be formed on the entire surface of the semiconductor substrate 10. Depending on the etching conditions, the fourth insulating layer 26 can have an etching selectivity with respect to the third insulating layer 22a. The fourth insulating layer 26 can be formed on the third insulating layer 22a in the cell region CR and the said part of the boundary region BR, and can be formed on the first insulating layer 16 in the peripheral region PR and the other part of the boundary region BR. At this time, the remaining portion of the second trench T2 can be completely filled with the fourth insulating layer 26. The fourth insulating layer 26 can be formed using various deposition techniques, such as the ALD method. Depending on the etching conditions, the fourth insulating layer 26 can have an etching selectivity with respect to the third insulating layer 22a. The fourth insulating layer 26 can include an oxide-based insulating layer, such as a silicon oxide insulating layer, and is not limited thereto.

[0092] The device isolation insulating layer formed on the left and right sides of the third trench T3 in the boundary region BR may be formed asymmetrically. Specifically, on the sidewalls of the third trench T3 that contact the sidewalls of the first storage active region 12a (i.e., the right sidewall in the figure), the first insulating layer 16, the second insulating layer 20a, the third insulating layer 22a, and the fourth insulating layer 26 may be sequentially stacked. However, on the sidewalls of the third trench T3 that contact the sidewalls of the first logic active region 52a (i.e., the left sidewall in the figure), the first insulating layer 16 and the fourth insulating layer 26 may be sequentially stacked without the second insulating layer 20a and the third insulating layer 22a. In addition, the second insulating layer 20a and the third insulating layer 22a formed on the right sidewall of the third trench T3 may protrude toward the central region of the third trench T3 in a tail shape. The degree of protrusion may depend on Figure 9 the boundary of the mask pattern 24. In some embodiments, depending on the boundary position of the mask pattern 24, the second insulating layer 20a and the third insulating layer 22a may be formed parallel to and along the sidewalls of the first storage active region 12a without any protruding portions. In the absence of protruding portions, a part of the second insulating layer 20a formed under the third insulating layer 22a may horizontally protrude toward the central region of the third trench T3 by a length corresponding to the thickness of the third insulating layer 22a.

[0093] Reference Figure 11 , in Figure 10 the state shown, a fifth insulating layer 28 may be formed on the surface of the semiconductor substrate 10, and then a sixth insulating layer 29 may be formed on the fifth insulating layer 28. Depending on the etching conditions, the fifth insulating layer 28 may have an etching selectivity with respect to the fourth insulating layer 26. Depending on the etching conditions, the sixth insulating layer 29 may have an etching selectivity with respect to the fifth insulating layer 28 and the fourth insulating layer 27. The fifth insulating layer 28 may include a nitride-based insulating layer, such as a silicon nitride insulating layer, and is not limited thereto. The sixth insulating layer 29 may include an oxide-based insulating layer, such as a polysilazane layer that may be identified by the trade name TOSZ®, but is not limited thereto. The sixth insulating layer 29 may completely fill the third trench T3 in the boundary region BR.

[0094] Subsequently, referring to Figure 3 , a portion of the sixth insulating layer 29 and the fifth insulating layer 28 may be removed from Figure 11 the result by an appropriate etching process. Depending on the etching conditions, the sixth insulating layer 29 may have an etching selectivity with respect to the fifth insulating layer 28 and the fourth insulating layer 26, and the fifth insulating layer 28 may have an etching selectivity with respect to the fourth insulating layer 26. Therefore, the sixth insulating layer 29 and the fifth insulating layer 28 may be retained only in the third trench T3 in the boundary region BR while completely filling the third trench T3.

[0095] Figure 12 is a cross-sectional view showing a semiconductor memory device according to some embodiments. Figure 12 is a cross-sectional view taken along line A-A' of Figure 2 . Descriptions that may be repetitive or overlapping with the description of the embodiments of Figures 3 to 11 may be briefly described or omitted.

[0096] Referring to Figure 12 and Figure 2 , in the cell region CR, the plurality of memory active regions formed on the upper portion of the semiconductor substrate 10 may include a first memory active region 12a, a second memory active region 12b, a third memory active region 12c, and a fourth memory active region 12d sequentially formed toward the inside of the cell region CR. In the peripheral region PR, a first logic active region 52a and a second logic active region 52b may be sequentially formed toward the outside of the semiconductor memory device. Although not denoted by reference numerals in Figure 12 , a first trench (T11 and T12 in Figure 5 ), a second trench (T2 in Figure 5 ), and a third trench (T3 in Figure 5 ) may be formed at positions corresponding to the positions in Figure 5 . In addition, distances D3, D4, D5, and D6 are the same as the distances D3, D4, D5, and D6 shown in Figure 5 . The peripheral region PR may be a PMOS region in which at least PMOS devices, such as PMOS transistors, are formed.

[0097] The device isolation insulating layer formed in the first trench T11 between the first memory active region 12a and the second memory active region 12b and the device isolation insulating layer formed in the first trench T11 between the third memory active region 12c and the fourth memory active region 12d may include a first nitride insulating layer 18b having a certain thickness near the bottom of the first trench T11 (for example, the first nitride insulating layer 18b may not completely fill the trench). In addition, the device isolation insulating layer formed in the trench T2 between the first logic active region 52a and the second logic active region 52b in the peripheral region PR may also include a first nitride insulating layer 18b having a certain thickness near the bottom of the second trench T2, where the first nitride insulating layer 18b may include the same material as the first nitride insulating layer 18b formed in the first trench T11 and may have substantially the same shape as the first nitride insulating layer 18b formed in the first trench T11.

[0098] Reference will be made to Figure 15Describe in detail the thickness of the first nitride insulating layer 18b formed near the bottom of the second trench T2. The first nitride insulating layer 18b formed near the bottom of the second trench T2 can be formed to have a thickness within a range that does not deteriorate the operating characteristics of the PMOS devices formed on the upper portions of the plurality of logic active regions 52a and 52b.

[0099] According to some embodiments, even if the pitch between the logic active regions in the peripheral region PR can be reduced to the pitch between the storage active regions in the cell region CR (e.g., D3≒D5), and the first nitride insulating layer 18b can be retained in the device isolation insulating layer in the second trench T2 in the peripheral region PR, the first nitride insulating layer 18b can also be formed to have a thickness within a range that does not deteriorate the operating characteristics of the PMOS devices, so that the overall size of the semiconductor memory device 1 in the X and Y directions can be reduced.

[0100] In some embodiments, the device isolation insulating layers formed in the first trenches T11 and T12, the second trench T2, and the third trench T3 can be formed in different shapes.

[0101] The device isolation insulating layer formed in the first trench T11 between the storage active regions in the long axis direction of the storage active regions, for example, between the first storage active region 12a and the second storage active region 12b (or between the third storage active region 12c and the fourth storage active region 12d), can include a first insulating layer 16, a first nitride insulating layer 18b, and a third insulating layer 30 stacked in sequence. In some embodiments, the first insulating layer 16 can include an oxide-based insulating layer, such as a silicon oxide insulating layer, but is not limited thereto. The first nitride insulating layer 18b can include a nitride-based insulating layer, such as a silicon nitride insulating layer, and is not limited thereto. The third insulating layer 30 can include, for example, an oxide-based insulating layer, such as a silicon oxide insulating layer, but is not limited thereto.

[0102] The device isolation insulating layer formed in the first trench T12 between the storage active regions in the short axis direction of the storage active regions (e.g., between the second storage active region 12b and the third storage active region 12c) can include the first insulating layer 16 and the third insulating layer 30 stacked in sequence.

[0103] The device isolation insulating layer formed in the second trench T2 between the logic active regions in the peripheral region PR (e.g., between the first logic active region 52a and the second logic active region 52b) can include the first insulating layer 16, the first nitride insulating layer 18b, and the third insulating layer 30, which are stacked in sequence in the same manner as the device isolation insulating layer formed in the first trench T11.

[0104] The device isolation insulating layer formed in the third trench T3 in the boundary region BR may be formed to be substantially left - right symmetric, as Figure 12 shown. Specifically, the device isolation insulating layer formed in the third trench T3 may include a first insulating layer 16 and a third insulating layer 30 sequentially stacked from the bottom of the third trench T3. In addition, in the central portion of the third trench T3, a fifth insulating layer 28a and a sixth insulating layer 29a may be formed on the third insulating layer 30 to completely fill the third trench T3. The fifth insulating layer 28a may be a nitride - based insulating layer, such as a silicon nitride insulating layer, and the sixth insulating layer 29a may be an oxide - based insulating layer, such as a TOSZ® layer.

[0105] Figures 14 to 16 is a cross - sectional view showing the state of a semiconductor memory device during a method of manufacturing a semiconductor memory device according to some embodiments. Figures 14 to 16 is a cross - sectional view corresponding to a cross - sectional view taken along the line A - A' of Figure 2 is a cross - sectional view after performing the steps of Figure 12 is a cross - sectional view after performing the steps of Figure 16 After performing the steps of

[0106] Referring to Figure 14 and Figure 2 , when trenches T11, T12, T2, and T3 can be formed on the upper portion of the semiconductor substrate 10, by etching a portion of the semiconductor substrate 10 through a photolithography process, a plurality of memory active regions ACT and a plurality of logic active regions ACTP can be defined. The plurality of memory active regions ACT may include a first memory active region 12a, a second memory active region 12b, a third memory active region 12c, and a fourth memory active region 12d, and the plurality of logic active regions ACTP may include a first logic active region 52a and a second logic active region 52b. The cell region CR may be an NMOS region where semiconductor memory cells are formed and may mainly form NMOS transistors, while the peripheral region PR may be a PMOS region where at least PMOS devices, such as PMOS transistors, can be formed. The meanings and relative sizes of the distances D1, D2, D3, D4, D5, and D6 may be the same as those described in reference Figure 3 . In particular, the distance D3 may be substantially the same as the distance D2 or the distance D5.

[0107] Subsequently, referring to Figure 14, a first insulating layer 16 may be formed on the entire exposed surface of a semiconductor substrate 10, on which a plurality of memory active regions and a plurality of logic active regions are formed. In a first trench T11 between a first memory active region 12a and a second memory active region 12b and between a third memory active region 12c and a fourth memory active region 12d, in a second trench T2 between a first logic active region 52a and a second logic active region 52b, and in a third trench T3 in a boundary region BR, the first insulating layer 16 may be formed along the bottom and sidewalls of its trench without completely filling the trench. However, in a first trench T12 between the second memory active region 12b and the third memory active region 12c and having a narrow width, the trench may be completely filled with the first insulating layer 16. The first insulating layer 16 may include an oxide-based insulating layer, such as a silicon oxide insulating layer, and is not limited thereto.

[0108] Subsequently, a first nitride insulating layer 18 may be formed on the entire surface of the semiconductor substrate 10 on which the first insulating layer 16 is formed. The first trench T11 and the second trench T2 may be completely filled with the first nitride insulating layer 18. On the other hand, in the third trench T3, the first nitride insulating layer 18 may be formed along the bottom and sidewalls of the third trench T3 without completely filling the third trench T3. The first nitride insulating layer 18 may include a nitride-based insulating layer, such as a silicon nitride insulating layer, and is not limited thereto. Depending on the etching conditions, the first nitride insulating layer 18 may have an etching selectivity with respect to the first insulating layer 16.

[0109] Subsequently, referring to Figure 15 , an etching process may be performed on the first nitride insulating layer 18 to remove a portion of the first nitride insulating layer 18 to form a first nitride insulating layer 18b. The etching process may be performed by a chemical etching method using an etchant (such as a lift-off process), and is not limited thereto. As a result of the etching process, the first nitride insulating layer 18b may remain in the first trench T11 between the first memory active region 12a and the second memory active region 12b and between the third memory active region 12c and the fourth memory active region 12d and in the second trench T2 between the first logic active region 52a and the second logic active region 52b. In the third trench T3 in the boundary region BR having a relatively large trench size, the first nitride insulating layer 18 may be completely removed.

[0110] The first nitride insulating layer 18b retained in the first trench T11 and in the second trench T2 between the first logic active region 52a and the second logic active region 52b may be formed to have a certain height (or thickness) from the bottoms of the first trench T11 and the second trench T2. Specifically, the thickness (or height) of the first nitride insulating layer 18b retained in the second trench T2 (i.e., t2 - t1) may be half or less of the depth (or height) h1 of the second trench T2. In some embodiments, the height t2 of the first nitride insulating layer 18b from the bottom of the second trench T2 may be half or less of the depth h1 of the second trench T2. The thickness (or height) of the first nitride insulating layer 18b retained in the second trench T2 may be determined according to whether the operating characteristics of the PMOS device deteriorate, where the PMOS device may be formed on the upper side of the first logic active region 52a or the second logic active region 52b. Therefore, the thickness (or height) of the first nitride insulating layer 18b retained in the second trench T2 may be preferably determined within a range in which the operating characteristics of the PMOS device do not deteriorate.

[0111] According to some embodiments, in the PMOS region including the first logic active region 52a and the second logic active region 52b, there is no deterioration in the operating characteristics of the PMOS device caused by the first nitride insulating layer 18b. At the same time, the pitch between the logic active regions in the peripheral region PR can be reduced to the extent of the pitch between the memory active regions in the cell region CR in the major axis direction. Therefore, even if the first nitride insulating layer 18b may be partially retained in the device isolation insulating layer in the second trench T2, the operating characteristics of the PMOS device do not deteriorate, and the overall size of the semiconductor memory device 1 can also be reduced in its X and / or Y direction.

[0112] As Figure 15 shown, according to the etching conditions of the first nitride insulating layer 18 or the shapes of the first trench T11 and the second trench T2, the surface profile of the first nitride insulating layer 18b formed in the first trench T11 and the second trench T2 may have a downward concave shape. That is, this surface profile may occur when the etching rate of the first nitride insulating layer 18b is relatively fast near the centers of the first trench T11 and the second trench T2.

[0113] Referring to Figure 13 shows the surface profile of another embodiment corresponding to the "B" part of Figure 15 . In Figure 13In , when the etching rate of the first nitride insulating layer 18b is relatively fast near the center of the second trench T2 and relatively slow on two sidewalls of the second trench T2 adjacent to the center of the second trench T2, the surface profile of the first nitride insulating layer 18b may have a shape convex upward toward two sidewalls of the second trench T2 adjacent to the center of the second trench T2.

[0114] Reference Figure 16 , the third insulating layer 30 and the fifth insulating layer 32 may be sequentially formed on the entire exposed surface of the result of Figure 15 . The third insulating layer 30 may include an oxide-based insulating layer, such as a silicon oxide insulating layer. The third insulating layer 30 may be formed to fill all remaining portions of the first trench T11 and the second trench T2. Subsequently, depending on the etching conditions, the fifth insulating layer 32 may have an etching selectivity with respect to the third insulating layer 30. The fifth insulating layer 32 may include a nitride-based insulating layer, such as a silicon nitride insulating layer. The third trench T3 may not be completely filled with the fifth insulating layer 32. On the other hand, device isolation insulating layers formed on the left and right sides of the third trench T3 in the boundary region BR may be formed symmetrically.

[0115] Subsequently, referring again to Figure 12 , the fifth insulating layer 28a may be formed by etching the fifth insulating layer 32, and the sixth insulating layer 29a may be formed to completely fill the third trench T3. Then, by an appropriate etching process, portions of the fifth insulating layer 28a and the sixth insulating layer 29a may be retained only in the central portion of the third trench T3. The fifth insulating layer 28a may be a nitride-based insulating layer, such as a silicon nitride insulating layer, and the sixth insulating layer 29a may be an oxide-based insulating layer, such as a TOSZ layer.

[0116] As described above, according to some embodiments, in the PMOS region including the first logic active region 52a and the second logic active region 52b, even if the first nitride insulating layer 18b may be retained in the first logic active region 52a and the second logic active region 52b, deterioration of the operating characteristics of the PMOS device due to the first nitride insulating layer 18b does not occur. At the same time, the pitch between logic active regions in the peripheral region PR may be reduced to the extent of the pitch between storage active regions in the cell region CR in the long axis direction. Therefore, the total size of the semiconductor memory device 1 in the X and / or Y direction may also be reduced.

[0117] Figure 17 is a cross-sectional view showing a semiconductor memory device according to some embodiments. Figure 17 is a cross-sectional view taken along line A-A' of Figure 2 . It may be redundant or related to Figures 3 to 11Descriptions of related embodiments that overlap may be briefly described or omitted.

[0118] Reference Figure 17 and Figure 2 , in the cell region CR, the plurality of memory active regions formed on the upper portion of the semiconductor substrate 10 may include a first memory active region 12a, a second memory active region 12b, a third memory active region 12c, and a fourth memory active region 12d that are sequentially formed toward the inside of the cell region CR. In the peripheral region PR, a first logic active region 52a and a second logic active region 52b may be sequentially formed toward the outside of the semiconductor memory device. Although not denoted by reference numerals in Figure 12 , the first trenches ( Figure 5 T11 and T12 in Figure 5 ), the second trench ( Figure 5 T2 in Figure 5 ), and the third trench ( Figure 5 T3 in

[0119] The first portion of the device isolation insulating layer formed in the first trench T11 between the first memory active region 12a and the second memory active region 12b and between the third memory active region 12c and the fourth memory active region 12d may include a first nitride insulating layer 44a, the bottom of which is not close to the bottom of the first trench T11 but is located at a relatively large height from the bottom of the first trench T11 with respect to the foregoing example. In addition, the device isolation insulating layer formed in the trench T2 between the first logic active region 52a and the second logic active region 52b in the peripheral region PR may not include a first nitride insulating layer having the same material or substantially the same shape as the first nitride insulating layer 44a formed in the first trench T11.

[0120] Figure 18 is Figure 17 an enlarged cross-sectional view of the "C" portion of Figure 18, in the first trench T11, the thickness t3 of the first insulating layer 17a at the bottom of the first trench T11 may be greater than the thickness t1 of the first insulating layer 17a at the tops of the third storage active region 12c and the fourth storage active region 12d. Accordingly, the lower end of the first nitride insulating layer 44a in the first trench T11 may be at a higher vertical level than the upper end of the horizontal portion of the first insulating layer 17a formed in the third trench T3. Although not specifically shown, in some embodiments, in the first trench T11, the thickness t3 of the first insulating layer 17a at the bottom of the first trench T11 may be less than the thickness t1 of the first insulating layer 17a at the tops of the third storage active region 12c and the fourth storage active region 12d. Accordingly, the lower end of the first nitride insulating layer 44a in the first trench T11 may be at a lower vertical level than the upper end of the horizontal portion of the first insulating layer 17a formed in the third trench T3. In other words, in some embodiments, the vertical level of the first nitride insulating layer 44a formed in the first trench T11 may be arbitrarily adjusted as needed, as described later with respect to the semiconductor memory device.

[0121] According to some embodiments, even if the pitch between the logic active regions in the peripheral region PR can be reduced to the pitch between the storage active regions in the cell region CR (e.g., D3≈D5), since the first nitride insulating layer 44a may not be retained in the device isolation insulating layer in the second trench T2 in the peripheral region PR, the operating characteristics of the PMOS device do not deteriorate, and at the same time, the overall size of the semiconductor memory device 1 in the X and Y directions can be reduced.

[0122] In some embodiments, the device isolation insulating layers formed in the first trench T11, the first trench T12, the second trench T2, and the third trench T3 surrounding the plurality of storage active regions and the plurality of logic active regions may be formed in different shapes.

[0123] The device isolation insulating layer formed in the first trench T11 may include a first insulating layer 17a, a first nitride insulating layer 44a, and a second insulating layer 46 stacked in sequence. In some embodiments, the first insulating layer 17a may include an oxide-based insulating layer, such as a silicon oxide insulating layer, but is not limited thereto. The first nitride insulating layer 44a may include a nitride-based insulating layer, such as a silicon nitride insulating layer, and is not limited thereto. The second insulating layer 46 may include, for example, an oxide-based insulating layer, such as a silicon oxide insulating layer, but is not limited thereto. The device isolation insulating layer formed in the first trench T11 may include the first insulating layer 17a and the second insulating layer 46 stacked in sequence.

[0124] The device isolation insulating layer formed in the second trench T2 in the peripheral region PR may include a first insulating layer 17a and a second insulating layer 46 stacked in sequence in the same manner as the device isolation insulating layer formed in the first trench T12.

[0125] The device isolation insulating layer formed in the third trench T3 in the boundary region BR may be formed to be substantially left - right symmetric. Specifically, the device isolation insulating layer formed in the third trench T3 may include a first insulating layer 17a and a second insulating layer 46 stacked in sequence from the bottom of the third trench T3. In addition, in the central portion of the third trench T3, a fifth insulating layer 28a and a sixth insulating layer 29a may be formed on the second insulating layer 46 to completely fill the third trench T3. The fifth insulating layer 28a may be a nitride - based insulating layer, such as a silicon nitride insulating layer, and the sixth insulating layer 29a may be an oxide - based insulating layer, such as a TOSZ® layer.

[0126] Figures 19 to 23 are cross - sectional views sequentially showing the states of semiconductor devices during a method of manufacturing a semiconductor memory device according to some embodiments. Figures 19 to 23 is along Figure 2 corresponding cross - sectional view taken along line A - A' of the cross - sectional view. Figure 17 is after performing Figure 23 steps of the cross - sectional view.

[0127] Reference Figure 19 and Figure 2 , a first storage active region 12a, a second storage active region 12b, a third storage active region 12c, a fourth storage active region 12d, a first logic active region 52a, and a second logic active region 52b may be formed on the upper portion of the semiconductor substrate 10. The peripheral region PR may be a PMOS region where at least one PMOS device, such as a PMOS transistor, is formed. The meanings and relative magnitudes of the distances D1, D2, D3, D4, D5, and D6 may be the same as those described with reference to Figure 3 . In particular, the distance D3 may be substantially the same as the distance D2 or the distance D5.

[0128] Subsequently, referring to Figure 19 , a first insulating layer 17 may be formed on the entire exposed surface of the semiconductor substrate 10 on which a plurality of storage active regions and a plurality of logic active regions are formed. Except for the third trench T3 formed in the boundary region BR, the first trench T11, the first trench T12, and the second trench T2 may be completely filled with the first insulating layer 17. The first insulating layer 17 may include an oxide - based insulating layer, such as a silicon oxide insulating layer, and is not limited thereto.

[0129] Reference Figure 20 , may be at Figure 19A relatively thick mask material layer 40 is formed on the semiconductor memory device in the state shown, which can be used as an etching mask in subsequent processes. The third trench T3 can be completely filled with the mask material layer 40. The mask material layer 40 can be formed of various material layers that can be used as etching masks in subsequent processes. As the mask material layer 40, for example, a spin-on hard mask (SOH) coating can be used, which can fill gaps such as trenches and can have excellent surface planarization characteristics and etching resistance, as an auxiliary material for realizing semiconductor micropatterns. If necessary, a plasma-enhanced SiON layer can be further deposited on the SOH coating.

[0130] Then, a mask pattern 42 may be formed on the mask material layer 40. The mask pattern 42 may include a photosensitive material for a photolithography process, such as a photoresist. A first opening 43 may be formed in the mask pattern 42 to expose a specific position of the underlying mask material layer 40. The first opening 43 may selectively expose a specific position in the cell region CR, and in some embodiments, the specific position may correspond to a portion of the first trench T11 where the device isolation insulating layer is located in the long axis direction of the storage active region.

[0131] refer to Figure 21 When a portion of the mask material layer 40 is etched using the mask pattern 42 as an etching mask, a second opening 43a may be formed at a position corresponding to the first opening 43 of the mask pattern 42. Subsequently, the mask material layer 40 in which the second opening 43a is formed may be used as an etching mask to etch and remove the first insulating layer 17 exposed to a certain depth by the second opening 43a.

[0132] At this time, as mentioned above Figure 18 As described above, the depth of the first insulating layer 17 to be etched can be arbitrarily adjusted as needed according to the operating characteristics of the semiconductor memory device 1 or its etching conditions. As will be described later, since the etched portion of the first insulating layer 17 may be a portion where the first nitride insulating layer 44a will be formed, the depth of the first insulating layer 17 to be etched can be adjusted in various ways according to the characteristics of the first nitride insulating layer 44a. In some embodiments, the etching depth of the first insulating layer 17 may reach the bottom of the first trench T11. In some embodiments, the lower end of the etched portion of the first insulating layer 17a may be located at a vertical level lower than, equal to, or higher than the top of the first insulating layer 17a formed at the bottom of the third trench T3.

[0133] refer to Figure 22 , can be obtained, for example, by a lift-off process Figure 21The resulting mask material layer 40 is removed, and then a first nitride insulating layer 44 can be formed on the entire surface of the exposed first insulating layer 17a. The first nitride insulating layer 44 can be formed with a certain thickness along the bottom and sidewalls of the third trench T3 while completely filling the first trench T11.

[0134] Reference Figure 23 , the first nitride insulating layer 44 can be removed from other parts, for example, by a lift-off process, so that only the first nitride insulating layer 44a remains in the first trench T11.

[0135] Referring again to Figure 17 , a second insulating layer 46 can be formed on Figure 23 the entire exposed surface of the result. The second insulating layer 46 can include an oxide-based insulating layer, such as a silicon oxide insulating layer. Subsequently, a fifth insulating layer 28a and a sixth insulating layer 29a can be sequentially formed on the second insulating layer 46 to completely fill the third trench T3. Then, by an appropriate etching process, portions of the fifth insulating layer 28a and the sixth insulating layer 29a can be retained only in the central portion of the third trench T3. The fifth insulating layer 28a can be a nitride-based insulating layer, such as a silicon nitride insulating layer, and the sixth insulating layer 29a can be an oxide-based insulating layer, such as a TOSZ® layer.

[0136] As described above, according to some embodiments, in the PMOS region including the first logic active region 52a and the second logic active region 52b, since the first nitride insulating layer 44a does not exist in the device isolation insulating layer between the first logic active region 52a and the second logic active region 52b, deterioration of the operating characteristics of the PMOS device due to the first nitride insulating layer 44a does not occur. At the same time, the pitch (i.e., distance D3) between the logic active regions in the peripheral region PR can be reduced to the extent of the pitch (e.g., distance D5 or D2) between the storage active regions in the cell region CR in the long axis direction. Therefore, the total size of the semiconductor memory device 1 in the X and / or Y direction can also be reduced.

[0137] Although the inventive concept has been specifically shown and described with reference to its embodiments, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.

[0138] This application is based on and claims priority to Korean Patent Application No. 10-2023-0170037, filed with the Korean Intellectual Property Office on November 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a semiconductor substrate including a cell portion in a cell region, a peripheral portion in a peripheral region disposed around the cell region, and a boundary portion in a boundary region between the cell region and the peripheral region; a plurality of storage active regions defined by the first trench in the cell region, each of the storage active regions having a major axis and a minor axis, wherein each of the storage active regions is arranged to maintain a first distance between adjacent storage active regions along the direction of the minor axis, and each of the storage active regions is arranged to maintain a second distance between adjacent storage active regions along the direction of the major axis; a plurality of logic active regions defined by the second trench in the peripheral region, wherein each of the logic active regions includes at least a P-channel metal oxide semiconductor transistor, and each of the logic active regions is arranged to maintain a third distance between adjacent logic active regions; a first device isolation insulating layer partially formed in the first trench, wherein a first portion of the first device isolation insulating layer corresponding to a region between the storage active regions adjacent to each other along the direction of the long axis includes a first nitride insulating layer; as well as a second device isolation insulating layer partially formed in the second trench between the logic active regions and excluding the first nitride insulating layer, and The second distance is substantially the same as the third distance.

2. The semiconductor memory device according to claim 1, wherein A second portion of the first device isolation insulating layer corresponding to a region between the storage active regions adjacent to each other along the direction of the short axis does not include the first nitride insulating layer.

3. The semiconductor memory device according to claim 1, wherein The first portion of the first device isolation insulating layer also includes a first insulating layer, a first nitride insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, wherein the first insulating layer, the first nitride insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are stacked in sequence, and the second device isolation insulating layer partially formed in the second trench between the logic active areas includes the first insulating layer and the fourth insulating layer, wherein the first insulating layer and the fourth insulating layer are stacked in sequence.

4. The semiconductor memory device according to claim 3, wherein The second part of the first device isolation insulating layer formed between the storage active areas adjacent to each other along the direction of the short axis includes the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are stacked in sequence.

5. The semiconductor memory device according to claim 3, further comprising: A third device isolation insulating layer in the boundary area is partially formed in a third trench between an outermost storage active area among the multiple storage active areas and an innermost logic active area among the multiple logic active areas, wherein in a vertical cross-section across the boundary area, the third device isolation insulating layer is asymmetrically formed between the innermost logic active area and the outermost storage active area.

6. The semiconductor memory device according to claim 5, wherein A first portion of the third device isolation insulating layer contacting the outermost storage active area includes the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer, wherein the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer are stacked in sequence, and a second portion of the third device isolation insulating layer contacting the innermost logic active area includes the first insulating layer and the fourth insulating layer without the second insulating layer and the third insulating layer, wherein the first insulating layer and the fourth insulating layer are stacked in sequence.

7. The semiconductor memory device according to claim 6, wherein An end portion of each of the second insulating layer and the third insulating layer in the first portion of the third device isolation insulating layer horizontally protrudes in a tail shape toward a central region of the third trench.

8. The semiconductor memory device according to claim 6, wherein A fifth insulating layer and a sixth insulating layer are sequentially formed on the fourth insulating layer of the first portion of the third device isolation insulating layer and on the fourth insulating layer of the second portion of the third device isolation insulating layer.

9. The semiconductor memory device according to claim 1, wherein The first part of the first device isolation insulating layer also includes a first insulating layer and a second insulating layer, wherein the first insulating layer, the first nitride insulating layer and the second insulating layer are stacked in sequence, and the second device isolation insulating layer between the logic active areas includes the first insulating layer and the second insulating layer, wherein the first insulating layer and the second insulating layer are stacked in sequence.

10. The semiconductor memory device according to claim 9, further comprising: A third device isolation insulating layer in the boundary area is partially formed in a third trench between an outermost storage active area among the multiple storage active areas and an innermost logic active area among the multiple logic active areas, wherein in a vertical cross-section across the boundary area, the third device isolation insulating layer is symmetrically formed between the innermost logic active area and the outermost storage active area.

11. The semiconductor memory device according to claim 10, wherein The third device isolation insulating layer partially formed in the third trench includes the first insulating layer, the second insulating layer, the fifth insulating layer and the sixth insulating layer, wherein the first insulating layer, the second insulating layer, the fifth insulating layer and the sixth insulating layer are sequentially formed to fill the third trench.

12. The semiconductor memory device according to claim 10, wherein A vertical level of a lower end of the first nitride insulating layer of the first portion of the first device isolation insulating layer is higher than a vertical level of an upper end of the first insulating layer of the third device isolation insulating layer formed at the bottom of the third trench.

13. A semiconductor memory device comprising: A semiconductor substrate including a cell region, a peripheral region disposed around the cell region, and a boundary region between the cell region and the peripheral region; a plurality of storage active regions defined by the first trench in the cell region, each of the storage active regions having a major axis and a minor axis, wherein each of the storage active regions is arranged to maintain a first distance between adjacent storage active regions along the direction of the minor axis, and each of the storage active regions is arranged to maintain a second distance between adjacent storage active regions along the direction of the major axis; as well as a plurality of logic active regions defined by the second trench in the peripheral region, wherein each of the logic active regions includes at least a P-channel metal oxide semiconductor transistor, and each of the logic active regions is arranged to maintain a third distance between adjacent logic active regions; a first device isolation insulating layer partially formed in the first trench, wherein a first portion of the first device isolation insulating layer corresponding to a region between the storage active regions adjacent to each other along the direction of the long axis includes a first nitride insulating layer; as well as a second device isolation insulating layer partially formed in the second trench, wherein the second device isolation insulating layer includes the first nitride insulating layer, and wherein the second distance is substantially the same as the third distance, and A vertical level of an upper end of the first nitride insulating layer of the second device isolation insulating layer is located at or below a half of the depth of the second trench.

14. The semiconductor memory device according to claim 13, wherein An upper end of the first nitride insulating layer of the first portion of the first device isolation insulating layer and an upper end of the first nitride insulating layer of the second device isolation insulating layer are located at the same vertical level.

15. The semiconductor memory device according to claim 13, wherein The first portion of the first device isolation insulating layer and the second device isolation insulating layer each further include a first insulating layer and a second insulating layer, wherein the first insulating layer, the first nitride insulating layer and the second insulating layer are sequentially stacked in sequence.

16. The semiconductor memory device according to claim 13, further comprising: A third device isolation insulating layer in the boundary area is partially formed in a third trench between an outermost storage active area among the multiple storage active areas and an innermost logic active area among the multiple logic active areas, wherein in a vertical cross-section across the boundary area, the third device isolation insulating layer is symmetrically formed between the innermost logic active area and the outermost storage active area.

17. The semiconductor memory device according to claim 16, wherein The third device isolation insulating layer includes a first insulating layer, a second nitride insulating layer different from the first nitride insulating layer, and a third insulating layer, wherein the first insulating layer, the second nitride insulating layer and the third insulating layer are sequentially formed to fill the third trench.

18. A semiconductor memory device comprising: A semiconductor substrate including a cell region, a peripheral region disposed around the cell region, and a boundary region between the cell region and the peripheral region; a plurality of storage active regions defined by the first trench in the cell region, each of the storage active regions having a major axis and a minor axis, wherein each of the storage active regions is arranged to maintain a first distance between adjacent storage active regions along the direction of the minor axis, and each of the storage active regions is arranged to maintain a second distance between adjacent storage active regions along the direction of the major axis; a plurality of logic active regions defined by the second trench in the peripheral region, wherein the plurality of logic active regions include at least a P-channel metal oxide semiconductor transistor, and the plurality of logic active regions adjacent to each other are arranged while maintaining a third distance therebetween; a first device isolation insulating layer partially formed in the first trench and including a first silicon nitride layer formed below an upper end of the first trench; a second device isolation insulating layer, partially formed in the second trench between the logic active regions adjacent to each other and excluding the first silicon nitride layer; as well as a third device isolation insulating layer partially formed in a third trench between an outermost storage active region among the plurality of storage active regions and an innermost logic active region among the plurality of logic active regions in the boundary region, wherein the third device isolation insulating layer is asymmetrically formed between the innermost logic active region and the outermost storage active region in a vertical cross section across the boundary region; and The second distance is substantially the same as the third distance.

19. The semiconductor memory device according to claim 18, wherein The first device isolation insulating layer between the storage active areas adjacent to each other along the direction of the long axis includes a first oxide layer, a first silicon nitride layer, a second silicon nitride layer, a second oxide layer and a third oxide layer, wherein the first oxide layer, the first silicon nitride layer, the second silicon nitride layer, the second oxide layer and the third oxide layer are stacked in sequence, and the second silicon nitride layer is thinner than the first silicon nitride layer in the stacking direction, and the second device isolation insulating layer between the logic active areas includes the first oxide layer and the third oxide layer, wherein the first oxide layer and the third oxide layer are stacked in sequence.

20. The semiconductor memory device according to claim 19, wherein Ends of the second silicon nitride layer and the second oxide layer in a portion of the third device isolation insulating layer contacting the outermost storage active region horizontally protrude in a tail shape toward a central region of the third trench.

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