Semiconductor device and method of manufacturing the same

Abstract

A manufacturing method of a semiconductor device includes: forming a dummy channel structure; forming a gate electrode surrounding the dummy channel structure; forming a word line surrounding the gate electrode; removing the dummy channel structure to form an opening; forming a gate dielectric layer in the opening; and forming a channel structure in the opening. Based on this configuration, the stability and efficiency of the semiconductor device may be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] A dynamic random-access memory (DRAM) is a random-access semiconductor memory that stores each bit of data in a memory cell. Dynamic random-access memories are known for their high speed operation, high density, and scalability. However, as the production scale of dynamic random-access memories expands, the manufacturing of dynamic random-access memories becomes more challenging and more prone to defects. These defects may lead to device errors and / or malfunctions. For example, the gate structure may not effectively control the channel structure. Therefore, an effective semiconductor device and a method for manufacturing the same are needed. Summary of the Invention

[0003] Embodiments of the present invention provide a method for manufacturing a semiconductor device, including: forming a dummy channel structure; forming a gate electrode surrounding the dummy channel structure; forming a word line surrounding the gate electrode; removing the dummy channel structure to form an opening; forming a gate dielectric layer in the opening; and forming a channel structure in the opening.

[0004] In some embodiments, the dummy channel structure overlaps with a capacitor.

[0005] In some embodiments, further including forming a dielectric layer on the capacitor, wherein the dummy channel structure is formed on the dielectric layer.

[0006] In some embodiments, the opening exposes the capacitor.

[0007] In some embodiments, the gate dielectric layer vertically extends from the capacitor and along the sidewalls of the opening.

[0008] In some embodiments, further including back-etching the gate electrode such that the top surface of the gate electrode is lower than the top surface of the dummy channel structure.

[0009] In some embodiments, the top surface of the word line is lower than the top surface of the gate electrode.

[0010] In some embodiments, forming the word line includes: forming a word line material surrounding the dummy channel structure; forming a hard mask structure above the word line material; and etching the word line material through the hard mask structure to form the word line.

[0011] In some embodiments, the hard mask structure overlaps with the dummy channel structure.

[0012] In some embodiments, spacers are also formed along the sidewalls of the hard mask structure before etching the character line material.

[0013] A semiconductor device includes: a capacitor; a channel structure extending vertically from the top surface of the capacitor; a gate dielectric layer surrounding the channel structure; a gate electrode surrounding the gate dielectric layer; and a character line surrounding the gate electrode.

[0014] In some embodiments, the gate dielectric layer has a linear cross-sectional profile.

[0015] In some embodiments, the gate dielectric layer extends vertically from the top surface of the capacitor.

[0016] In some embodiments, the bottom surface of the gate dielectric layer is lower than the bottom surface of the gate electrode.

[0017] In some embodiments, the top surface of the gate dielectric layer is higher than the top surface of the gate electrode.

[0018] In some embodiments, a dielectric layer in contact with the sidewalls of the gate dielectric layer is also included.

[0019] In some embodiments, the channel structure is made of a material of an oxide semiconductor.

[0020] In some embodiments, the channel structure is made of indium gallium zinc oxide (IGZO).

[0021] In some embodiments, the gate electrode has an annular top profile.

[0022] In some embodiments, the character line has a bar-shaped top profile. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0024] Figure 1 FIG. is a schematic diagram of a memory array according to some embodiments of the present invention.

[0025] Figure 2 FIG. is a schematic diagram of a memory cell according to some embodiments of the present invention.

[0026] Figure 3 FIG. is a flowchart of a method of manufacturing a semiconductor device according to some embodiments of the present invention.

[0027] Figures 4A to 21BSchematic diagrams of different steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0028] Figures 22A to 23B Schematic diagrams of different steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Description

[0029] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Further, in various examples, the present disclosure may repeat reference numerals and / or letters. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0030] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature of an icon in a figure to another element or feature. In addition to the orientation depicted in the figures, these spatially relative terms are intended to encompass different orientations of the element in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and likewise, the spatially relative descriptors used herein may be interpreted accordingly.

[0031] As used herein, "about", "approximately", "substantially", or "essentially" generally may mean within 20%, or within 10%, or within 5% of a given value or range. The values given herein are approximate, which means that the terms "about", "approximately", "substantially", or "essentially" may be inferred if not explicitly stated. However, those skilled in the art will recognize that the values or ranges recited throughout the description are merely examples and may decrease or vary as the scale of integrated circuits is reduced.

[0032] The terms used herein are for the purpose of describing particular exemplary embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0033] Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic views of idealized exemplary embodiments (and intermediate structures). As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but include, for example, shape deviations resulting from manufacturing. For example, an implantation region illustrated as rectangular will typically have rounded or curved features and / or an implantation concentration gradient at its edges rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0035] Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0036] Figure 1 FIG. is a schematic diagram of a memory array according to some embodiments of the present invention. In some embodiments, the memory array 10 includes a plurality of memory cells 11 arranged in a rectangular matrix. Figure 1 A simple example of a 4×4 cell matrix is shown. The height and width of other memory matrices may have thousands of cells. In some embodiments, the memory array 10 may be a dynamic random-access memory (DRAM).

[0037] Each row of memory cells 11 is connected by a word line 20, and each column of memory cells 11 is connected by a bit line 30. The word lines 20 may extend horizontally. The word lines 20 are parallel to each other. Additionally, the word lines 20 may be spaced apart from each other at substantially equal intervals.

[0038] On the other hand, the bit lines 30 may extend vertically. Similar to the word lines 20, the bit lines 30 are parallel to each other and may be spaced apart from each other at substantially equal intervals.

[0039] Figure 2 Schematic diagram of a memory cell according to some embodiments of the present invention. Specifically, Figure 2 is Figure 1 a close-up view. In some embodiments, the memory cell 11 includes an access transistor 11T and a storage capacitor 11C electrically connected to the access transistor 11T. In some embodiments, the access transistor 11T is an NMOS transistor and is configured to control the access to the memory cell 11 by turning on or off the gate of the access transistor 11T.

[0040] In some embodiments, the storage capacitor 11C is configured to store information according to the state of the charge stored therein. The storage capacitor 11C in an empty state (i.e., not charged) is represented as having a logic value equivalent to 0. The storage capacitor 11C in a fully charged state is represented as having a logic value equivalent to 1. The memory cell 11 stores bit data using two extreme charge states stored in the storage capacitor 11C. In some embodiments, the word line 20 connected to the access transistor 11T is used to control the gate of the access transistor 11T by applying a voltage to the gate of the access transistor 11T. In some embodiments, the bit line 30 is perpendicular to the arrangement of the word line 20 and is also connected to the access transistor 11T. When the gate of the access transistor 11T is turned on, the access transistor 11T connects the storage capacitor 11C to the bit line 30, such that the logic value stored in the storage capacitor 11C will be read on the bit line 30.

[0041] Figure 3 Flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 4A to 21B Schematic diagram of different steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention. Specifically, Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A and Figure 21A are respectively the sectional views along the A-A’ line of the top views of Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B and Figure 21B .

[0042] Figure 3 The manufacturing method M50 of Figures 4A to 21B can be applied to semiconductor devices. The semiconductor devices and the manufacturing method M50 will be discussed in conjunction with Figure 3 . As shown in

[0043] , the manufacturing method M50 may include the following operations: operation S100, operation S200, operation S300, operation S400, operation S500, operation S600, operation S700, operation S800, operation S900, operation S1000, operation S1100, operation S1200, operation S1300, operation S1400, operation S1500, operation S1600, operation S1700, and operation S1800.

[0044] The method M50 starts with operation S100, forms capacitors in the first and second dielectric layers, and deposits the third and fourth dielectric layers on the capacitors. Referring to Figure 4A and Figure 4B , the first dielectric layer 100 and the second dielectric layer 200 are sequentially deposited on a substrate (not shown), a plurality of capacitors 300 are formed in the first dielectric layer 100 and the second dielectric layer 200, and then, the third dielectric layer 400 and the fourth dielectric layer 500 are sequentially deposited on the second dielectric layer 200 and cover the capacitors 300.

[0045] In some embodiments, a first dielectric layer 100 is deposited on a substrate (not shown). In some embodiments, the first dielectric layer 100 is configured to provide electrical isolation between capacitors 300 formed in subsequent steps. The first dielectric layer 100 is made of a dielectric material. In some embodiments, the first dielectric layer 100 is made of silicon oxide (such as SiO 2 ).

[0046] The first dielectric layer 100 can be deposited by using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes.

[0047] In some embodiments, a second dielectric layer 200 is deposited on the first dielectric layer 100. In some embodiments, the second dielectric layer 200 is configured to provide electrical isolation between capacitors 300 formed in subsequent steps. The second dielectric layer 200 is made of a dielectric material. In some embodiments, the first dielectric layer 100 and the second dielectric layer 200 are made of different dielectric materials. In some embodiments, the second dielectric layer 200 is made of silicon nitride (SiN).

[0048] The second dielectric layer 200 can be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the second dielectric layer 200 can be less than the vertical thickness of the first dielectric layer 100.

[0049] In some embodiments, the first dielectric layer 100 and the second dielectric layer 200 can be patterned to form openings. A mask pattern (not shown) can be formed on the second dielectric layer 200. Subsequently, the first dielectric layer 100 and the second dielectric layer 200 are etched through the mask pattern to form openings. In some embodiments, after etching, the group of the first dielectric layer 100 and the second dielectric layer 200 can be separated from each other through the openings, wherein each opening can vertically extend from an underlying structure in the substrate (not shown) and be parallel to each other. In some embodiments, the openings can be regularly arranged horizontally at substantially equal intervals from each other.

[0050] Next, capacitors 300 can be formed into the openings. In other words, the capacitors 300 replace each opening. In some embodiments, the capacitors 300 are parallel to each other and can be regularly arranged at substantially equal intervals from each other.

[0051] The capacitor 300 may include a bottom electrode, a capacitor dielectric layer above the bottom electrode, and a top electrode above the capacitor dielectric layer. In some embodiments, the bottom electrode and the top electrode of the capacitor 300 may include a conductive material. In some embodiments, the bottom electrode and the top electrode may include a metal. In some embodiments, the bottom electrode and the top electrode may include titanium nitride (TiN). In some embodiments, the capacitor dielectric layer of the capacitor 300 may include a dielectric material. The bottom electrode, the capacitor dielectric layer, and the top electrode of the capacitor 300 may be sequentially deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0052] The capacitor 300 may be subjected to a planarization process to make the capacitor 300 flush with the second dielectric layer 200. The capacitor 300 with a reduced surface is coplanar with the second dielectric layer 200 and thus shares the same top surface. That is, the top surface of the capacitor 300 and the top surface of the second dielectric layer 200 may be connected to each other. A chemical mechanical polishing (CMP) process may be used for the planarization process. The CMP process may stop when the second dielectric layer 200 is exposed.

[0053] Next, a third dielectric layer 400 may be deposited on the capacitor 300 and the second dielectric layer 200. In some embodiments, the third dielectric layer 400 covers the capacitor 300. The third dielectric layer 400 is configured to provide electrical isolation between some conductive structures (such as word lines) to be formed in subsequent steps. In some embodiments, a portion of the third dielectric layer 400 also serves as a sacrificial structure for some conductive structures (such as channels) to be formed in subsequent steps.

[0054] The third dielectric layer 400 is made of a dielectric material. In some embodiments, the third dielectric layer 400 and the first dielectric layer 100 are made of the same material. In some embodiments, the third dielectric layer 400 is made of silicon dioxide (SiO 2 )). The third dielectric layer 400 may be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0055] In some embodiments, a fourth dielectric layer 500 is deposited on the third dielectric layer 400. The fourth dielectric layer 500 is made of a dielectric material. In some embodiments, the fourth dielectric layer 500 and the second dielectric layer 200 are made of the same material. In some embodiments, the fourth dielectric layer 500 is made of silicon nitride (SiN). The fourth dielectric layer 500 may be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the fourth dielectric layer 500 may be greater than the vertical thickness of the third dielectric layer 400.

[0056] Method M50 proceeds to operation S200 to pattern the fourth dielectric layer to define dummy channel structures. Refer to Figure 5A and Figure 5B , the fourth dielectric layer 500 can be patterned to define dummy channel structures 502. A mask pattern (not shown) can be formed on the fourth dielectric layer 500. Subsequently, the fourth dielectric layer 500 is etched through the mask pattern.

[0057] In some embodiments, operation S200 can include photolithography. In some embodiments, the mask pattern is formed on the fourth dielectric layer 500 directly above the capacitor 300. Thus, during the etching process, the portion of the fourth dielectric layer 500 overlapping with the capacitor 300 can be not etched, and the dummy channel structures 502 can be defined after the etching process.

[0058] In some embodiments, each dummy channel structure 502 can overlap with a corresponding capacitor 300. In some embodiments, the dummy channel structures 502 are configured to act as placeholders for channel structures to be formed in subsequent steps.

[0059] Method M50 proceeds to operation S300 to deposit a liner layer on the dummy channel structures and the third dielectric layer. Refer to Figure 6A and Figure 6B , a liner layer 600 is deposited on the dummy channel structures 502 and the third dielectric layer 400.

[0060] In some embodiments, the liner layer 600 extends from the top surface of the third dielectric layer 400 to the dummy channel structures 502 and covers the top and sidewalls of the dummy channel structures 502.

[0061] The liner layer 600 can be made of a dielectric material. In some embodiments, the liner layer 600 is made of the same material as the third dielectric layer 400 or the first dielectric layer 100. In some embodiments, the liner layer 600 is made of silicon dioxide (SiO 2 ). The liner layer 600 can be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD or other suitable deposition processes.

[0062] Method M50 proceeds to operation S400 to deposit gate electrode material on the liner layer. Refer to Figure 7A and Figure 7B , gate electrode material 700 is deposited on the liner layer 600. In some embodiments, the gate electrode material 700 extends from the top surface of the liner layer 600 and covers the liner layer 600.

[0063] The gate electrode material 700 can be made of a conductive material. In some embodiments, the gate electrode material 700 can include a metal. In some embodiments, the gate electrode material 700 can include titanium nitride (TiN). The gate electrode material 700 can be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0064] Method M50 proceeds to operation S500 to deposit a word line material on the gate electrode material. Refer to Figure 8A and Figure 8B , a word line material 800 is deposited on the gate electrode material 700.

[0065] The word line material 800 can be made of a conductive material. In some embodiments, the word line material 800 can include a metal. In some embodiments, the word line material 800 can include tungsten (W). The word line material 800 can be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0066] In some embodiments, a planarization process can be performed on the word line material 800 to expose the top surface of the gate electrode material 700. The planarized word line material 800 is coplanar with the gate electrode material 700 and thus shares the same top surface. That is, the top surface of the word line material 800 and the top surface of the gate electrode material 700 can be connected to each other. A chemical mechanical polishing (CMP) process can be used for the planarization process.

[0067] Method M50 proceeds to operation S600 to etch back the word line material. Refer to Figure 9A and Figure 9B , the word line material 800 is etched back to lower the top surface of the word line material 800. As a result, the gate electrode material 700 and a portion of the dummy channel structure 502 can protrude from the top surface of the etched word line material 800.

[0068] Method M50 proceeds to operation S700 to deposit a hard mask structure on the word line material. Refer to Figure 10A and Figure 10B , a hard mask structure 900 is deposited on the exposed portions of the word line material 800 and the gate electrode material 700.

[0069] In some embodiments, the hard mask structure 900 can include a first hard mask layer 901, a second hard mask layer 902, and a third hard mask layer 903. The first hard mask layer 901, the second hard mask layer 902, and the third hard mask layer 903 can be sequentially deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0070] In some embodiments, a first hard mask layer 901 is deposited on the character line material 800 and covers the exposed portion of the gate electrode material 700. In some embodiments, the first hard mask layer 901 may be an under layer film.

[0071] In some embodiments, a second hard mask layer 902 is deposited on the first hard mask layer 901. In some embodiments, the second hard mask layer 902 is made of a dielectric material. In some embodiments, the second hard mask layer 902 may include carbon. In some embodiments, the second hard mask layer 902 may include amorphous carbon (α-carbon).

[0072] In some embodiments, a third hard mask layer 903 is deposited on the second hard mask layer 902. In some embodiments, the third hard mask layer 903 may be a dielectric anti-reflection coating (DARC). In some embodiments, the third hard mask layer 903 may include silicon. In some embodiments, the third hard mask layer 903 may be silicon oxynitride (SiO x N y ) or any suitable anti-reflection material layer. In some embodiments, the third hard mask layer 903 is configured to reduce the reflectivity during photoresist patterning. Additionally, an organic anti-reflection coating (not shown) may be selectively used above the third hard mask layer 903 to enhance the photoresist performance.

[0073] Method M50 proceeds to operation S800 to form a patterned photoresist on the hard mask structure. Referring to Figure 11A and Figure 11B , a patterned photoresist 1000 is formed on the hard mask structure 900. A photoresist material layer (not shown) may be formed on the hard mask structure 900 using a suitable deposition process such as spin coating. Then, the photoresist material layer is exposed to a light source through a photomask having a specific pattern (not shown). In some embodiments, the regions of the photoresist material layer become soluble when exposed to light. As a result, the exposed regions of the photoresist material layer can be washed away to define the patterned photoresist 1000.

[0074] In some embodiments, the patterned photoresist 1000 may be located above the hard mask structure 900 above the dummy channel structure 502. The patterned photoresist 1000 is configured to act as an etch protector for the underlying hard mask structure 900 above the dummy channel structure 502 during subsequent etching processes.

[0075] In some embodiments, the patterned photoresist 1000 may also be located above the hard mask structure 900 above the word line material 800. The patterned photoresist 1000 is also configured to act as an etch protector for the underlying hard mask structure 900 above the word line material 800 during subsequent etching processes.

[0076] Method M50 proceeds to operation S900 to etch the hard mask structure through the photoresist. Refer to Figure 12A and Figure 12B , and etch the hard mask structure 900 through the photoresist 1000. In some embodiments, the dummy channel structure 502 above and the hard mask structure 900 above the word line material 800 can be protected from the etching process by the photoresist 1000.

[0077] In some embodiments, the etching process is configured to etch the hard mask structure 900 and may leave other exposed materials (such as gate electrode material 700 and word line material 800) with little or no etching. In some embodiments, the etching process may include certain etchants for etching the hard mask structure 900, such as carbon tetrafluoride (CF 4 ), sulfur dioxide (SO 2 ), or oxygen (O 2 ).

[0078] In some embodiments, the photoresist 1000 may be removed after the etching process. In some embodiments, the removal of the photoresist 1000 includes a liquid resist stripper (not shown) that chemically alters the photoresist 1000 such that the photoresist 1000 no longer adheres to the hard mask structure 900.

[0079] In some embodiments, the removal of the photoresist 1000 exposes the third hard mask layer 903. In some embodiments, the third hard mask layer 903 may be removed during or after the removal of the photoresist 1000, and the second hard mask layer 902 is exposed. In some embodiments, the remaining hard mask structure 900 includes the first hard mask layer 901 and the second hard mask layer 902.

[0080] Method M50 proceeds to operation S1000 to form spacers along the hard mask structure and the gate electrode material. Refer to Figure 13A and Figure 13B , and form a plurality of spacers 1100 along the sidewalls of the hard mask structure 900 and the sidewalls of the gate electrode material 700.

[0081] In some embodiments, the spacers 1100 are made of a dielectric material. In some embodiments, the spacers 1100 are made of the same material as the liner layer 600, the third dielectric layer 400, or the first dielectric layer 100. In some embodiments, the spacers 1100 are made of silicon dioxide (SiO 2 ).

[0082] In some embodiments, a spacer capping layer (not shown) may be formed over an underlying structure (e.g., hard mask structure 900, gate electrode material 700, and word line material 800). The spacer capping layer may be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Then, an anisotropic etching process is performed on the spacer capping layer to remove the horizontal portions of the spacer capping layer, leaving only the vertical portions of the spacer capping layer. The remaining vertical portions are referred to as spacers 1100.

[0083] Method M50 proceeds to operation S1100 to etch the word line material through the spacers and the hard mask structure. Refer to Figure 14A and Figure 14B , the word line material 800 is etched using the spacers 1100 and the hard mask structure 900 as an etch mask to form a plurality of word lines 802. In some embodiments, the word lines 802 have a bar-shaped top profile.

[0084] Method M50 proceeds to operation S1200 by removing the hard mask structure. Refer to Figure 15A and Figure 15B , the hard mask structure 900 and the spacers 1100 are removed along the sidewalls of the hard mask structure 900. In some embodiments, an appropriate etching process may be used to remove the hard mask structure 900. As a result, portions of the word lines 802 may be exposed. As shown in the top view of Figure 15B , each word line 802 may extend along a first direction and may connect the gate electrodes 702 of the same column along the first direction. The word lines 802 are arranged along a second direction perpendicular to the first direction and may be parallel to each other.

[0085] Method M50 proceeds to operation S1300 by back-etching the gate electrodes. Refer to Figure 16A and Figure 16B , a portion of the gate electrodes 702 is back-etched. Specifically, the top horizontal portion and the upper vertical portion of the gate electrodes 702 are back-etched.

[0086] In some embodiments, the etching process of operation S1300 is configured to etch the material of the gate electrodes 702 until the liner layer 600 is exposed. In some embodiments, the etching process of operation S1300 may also remove a small portion of the spacers 1100.

[0087] In some embodiments, after the etching process of operation S1300, the gate electrodes 702 have an annular top profile. In some embodiments, the top surface of the gate electrodes 702 is at a higher level than the top surface of the word lines 802 and lower than the top surface of the dummy channel structure 502.

[0088] Method M50 proceeds to operation S1400 by refilling the fifth dielectric layer. Refer to Figure 17A and Figure 17B , the fifth dielectric layer 1200 is deposited and refilled on top of the liner layer 600, the spacers 1100, the gate electrodes 702, the dummy channel structures 502, and the word lines 802.

[0089] In some embodiments, the fifth dielectric layer 1200 is made of a dielectric material. In some embodiments, the fifth dielectric layer 1200 is made of the same material as the spacers 1100, the liner layer 600, the third dielectric layer 400, or the first dielectric layer 100. In some embodiments, the fifth dielectric layer 1200 is made of silicon dioxide (SiO 2 ).

[0090] In some embodiments, the fifth dielectric layer 1200 can be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Then, the fifth dielectric layer 1200 can be planarized (e.g., by a CMP process) to remove the excess portion of the fifth dielectric layer 1200 on top of the dummy channel structures 502, so that the fifth dielectric layer 1200 is flush with the dummy channel structures 502. In some embodiments, when the dummy channel structures 502 are exposed, the planarization process can be stopped.

[0091] Method M50 proceeds to operation S1500 by removing the dummy channel structures. Refer to Figure 18A and Figure 18B , the dummy channel structures 502 are removed and openings 1300 are formed in the respective gate electrodes 702.

[0092] In some embodiments, an etching process is performed to remove the dummy channel structures 502. In some embodiments, the etching process is a wet dip process. In some embodiments, the etching process is configured to remove the material of the dummy channel structures 502. In some embodiments, the etching process can also remove the liner layer 600. In some embodiments, the openings 1300 are formed to replace the dummy channel structures 502.

[0093] Method M50 proceeds to operation S1600 by removing the third dielectric layer. Refer to Figure 19A and Figure 19B , a portion of the third dielectric layer 400 on top of the capacitor 300 is removed.

[0094] In some embodiments, an etching process is performed to remove the third dielectric layer 400 on top of the capacitor 300. In some embodiments, the top surface of the capacitor 300 is exposed in the openings 1300.

[0095] In some embodiments, the fifth dielectric layer 1200 can also be etched during the etching process. In other words, the etching process causes a portion of the fifth dielectric layer 1200 to descend. In some embodiments, the etching process can remove a portion of the fifth dielectric layer 1200, but leaves a small portion of the fifth dielectric layer 1200 on the gate electrode 702 intact. In other words, the etching process does not expose the gate electrode 702.

[0096] Method M50 proceeds to operation S1700 to form a gate dielectric layer on the sidewalls of the opening. Refer to Figure 20A and Figure 20B , a gate dielectric layer 1400 is formed on the sidewalls of the opening 1300. Specifically, a gate dielectric layer 1400 is formed that extends upward from the capacitor 300 and along the sidewalls of the opening 1300.

[0097] In some embodiments, the gate dielectric layer 1400 is made of a dielectric material. In some embodiments, the gate dielectric layer 1400 can include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. In some embodiments, the gate dielectric layer 1400 is configured to electrically isolate the gate electrode 702 from the conductive structure (e.g., channel structure) that will be formed in subsequent steps.

[0098] In some embodiments, a gate dielectric material covering layer (not shown) can be formed over the underlying structure (e.g., the fifth dielectric layer 1200 and the capacitor 300). The gate dielectric material covering layer can be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Then, an etching process is performed on the gate dielectric material covering layer to remove the horizontal portion of the gate dielectric material covering layer, leaving only the vertical portion of the gate dielectric material covering layer that remains along the sidewalls of the opening 1300. The remaining vertical portion is referred to as the gate dielectric layer 1400.

[0099] In some embodiments, the top end of the gate dielectric layer 1400 can be substantially flush with the top surface of the fifth dielectric layer 1200. In some embodiments, the top surface of the gate dielectric layer 1400 is higher than the top surface of the gate electrode 702.

[0100] In some embodiments, the bottom surface of the gate dielectric layer 1400 is lower than the bottom surface of the gate electrode 702. In some embodiments, the gate dielectric layer 1400 extends vertically from the top surface of the capacitor 300. In some embodiments, the gate dielectric layer 1400 has a linear cross-sectional profile. In some embodiments, the fifth dielectric layer 1200 contacts the sidewalls of the gate dielectric layer 1400.

[0101] Method M50 proceeds to operation S1800 to form a channel structure in the opening. Refer to Figure 21A andFigure 21B A channel structure 1500 is formed in the opening 1300. Specifically, the channel structure 1500 is formed on the capacitor 300 and is surrounded by the gate dielectric layer 1400.

[0102] In some embodiments, a channel layer (not shown) may be formed above the underlying structure (e.g., the fifth dielectric layer 1200, the gate dielectric layer 1400, and the capacitor 300). The channel layer may be deposited by using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Then, planarization (e.g., a CMP process) may be performed on the channel layer to remove the excess portion of the channel layer on top of the fifth dielectric layer 1200 and to make the channel layer flush with the fifth dielectric layer 1200. In some embodiments, the planarization may be stopped when the fifth dielectric layer 1200 is exposed. The remaining portion of the channel layer is referred to as the channel structure 1500.

[0103] In some embodiments, the channel structure 1500 extends vertically from the capacitor 300. In some embodiments, the channel structure 1500 has a vertical length substantially the same as that of the gate dielectric layer 1400. In some embodiments, the channel structure 1500 may be electrically connected to the underlying capacitor 300. In some embodiments, a bit line structure (not shown) may be located above the channel structure 1500.

[0104] In some embodiments, the channel structure 1500 may include an oxide semiconductor (OS) material. In some embodiments, the channel structure 1500 may include indium gallium zinc oxide (IGZO). In some embodiments, the channel structure 1500 may include a stacked nanowire structure configured such that current flows out-of-plane (e.g., vertically). The vertical channel structure 1500 may increase the storage cell density in the semiconductor device 50.

[0105] In some embodiments, the channel structure 1500 may be wrapped by the gate electrode 702 through the gate dielectric layer 1400. In other words, the gate electrode 702, the gate dielectric layer 1400, and the channel structure 1500 may form a gate-all-around (GAA) configuration. Since it is all-gate, the channel structure 1500 has maximized the contact surface and thus maximized the current passing through the gate dielectric layer 1400 to the gate electrode 702. Therefore, compared with a planar channel structure, the gate electrode 702 may have a higher switching speed performance and may better control the gate-all-around channel structure 1500.

[0106] Figures 22A to 23B are schematic diagrams of different steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention. Refer to Figure 22A and Figure 22B , Figure 22A and Figure 22B andFigure 18A and Figure 18B is similar to Figure 22A and Figure 22B The embodiments of Figure 18A and Figure 18B differ from the embodiments of Figure 22A and Figure 22B in that, in the embodiments of

[0107] an etching process is performed to remove both the dummy channel structure 502 and a portion of the gate electrode 702 to expose the sidewalls of the word line 802.

[0108] Figure 22A and Figure 22B The structure of Figure 19A and Figure 21B can undergo the same process as discussed in Figures 23A to 23B wherein the resulting structure is as shown in Figure 23A and Figure 23B In the embodiments of

[0109] the channel structure 1500 can extend vertically from the capacitor 300.

[0110] In some embodiments, the gate dielectric layer 1400 can extend vertically from the second dielectric layer 200. In some embodiments, the gate dielectric layer 1400 can contact the sidewalls of the spacers 1100, the sidewalls of the word line 802, and the sidewalls of the gate electrode 702. In some embodiments, the top surface of the gate dielectric layer 1400 can be higher than the top surface of the word line 802. In some embodiments, the gate electrode 702 can extend from the bottom surface of the word line 802. In some embodiments, the word line 802 can be used as a gate electrode to control the channel structure 1500.

[0110] In summary, the present invention provides a method for fabricating a vertical surround gate structure, which is beneficial to the reduction of components. On the other hand, the present invention provides a method for forming a channel structure by forming a dummy channel structure and then replacing the dummy channel structure with a channel structure. Therefore, the channel structure can be formed in a self-aligned manner and can have a good shape, wherein the device performance can be improved.

[0111] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure.

[0112]

Symbol Description

[0113] 10: Memory array

[0114] 11: Memory cell

[0115] 11C: Storage capacitor

[0116] 11T: Access transistor

[0117] 20: Word line

[0118] 30: Bit line

[0119] 100: First dielectric layer

[0120] 200: Second dielectric layer

[0121] 300: Capacitor

[0122] 400: Third dielectric layer

[0123] 500: Fourth dielectric layer

[0124] 502:Dummy channel structure

[0125] 600: Buffer layer

[0126] 700: Gate electrode material

[0127] 702: Gate electrode

[0128] 800: Word line material

[0129] 802: Word line

[0130] 900: Hard mask structure

[0131] 901: First hard mask layer

[0132] 902: Second hard mask layer

[0133] 903: Third hard mask layer

[0134] 1000: Photoresist

[0135] 1100: Spacer

[0136] 1200: Fifth dielectric layer

[0137] 1300: Opening

[0138] 1400: Gate dielectric layer

[0139] 1500: Channel structure

[0140] M50: Method

[0141] S100: Operation

[0142] S200: Operation

[0143] S300: Operation

[0144] S400: Operation

[0145] S500: Operation

[0146] S600: Operation

[0147] S700: Operation

[0148] S800: Operation

[0149] S900: Operation

[0150] S1000: Operation

[0151] S1100: Operation

[0152] S1200: Operation

[0153] S1300: Operation

[0154] S1400: Operation

[0155] S1500: Operation

[0156] S1600: Operation

[0157] S1700: Operation

[0158] S1800: Operation.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A virtual channel structure is formed; forming a gate electrode surrounding the dummy channel structure; forming a word line around the gate electrode; removing the dummy channel structure to form an opening; forming a gate dielectric layer in the opening; as well as A channel structure is formed in the opening. The method of claim 1 , wherein the dummy channel structure overlaps a capacitor. 3 . The method of claim 2 , further comprising forming a dielectric layer on the capacitor, wherein the dummy channel structure is formed on the dielectric layer. The method according to claim 2 , wherein the opening exposes the capacitor. 5 . The method of claim 2 , wherein the gate dielectric layer extends vertically from the capacitor and along sidewalls of the opening.

6. The method according to claim 1, wherein: The method also includes etching back the gate electrode so that the top surface of the gate electrode is lower than the top surface of the dummy channel structure. 7 . The method according to claim 1 , wherein a top surface of the word line is lower than a top surface of the gate electrode.

8. The method of claim 1 , wherein forming the word line comprises: forming a word line material around the dummy channel structure; forming a hard mask structure over the word line material; and The word line material is etched through the hard mask structure to form the word line. The method of claim 8 , wherein the hard mask structure overlaps the dummy channel structure.

10. The method according to claim 8, wherein: Also included is forming spacers along sidewalls of the hard mask structure prior to etching the word line material.

11. A semiconductor device, characterized in that: include: Capacitors; a channel structure extending vertically from a top surface of the capacitor; a gate dielectric layer surrounding the channel structure; a gate electrode surrounding the gate dielectric layer; as well as A word line surrounds the gate electrode. 12 . The semiconductor device of claim 11 , wherein the gate dielectric layer has a linear cross-sectional profile. 13 . The semiconductor device of claim 11 , wherein the gate dielectric layer vertically extends from the top surface of the capacitor. 14 . The semiconductor device of claim 11 , wherein a bottom surface of the gate dielectric layer is lower than a bottom surface of the gate electrode. 15 . The semiconductor device of claim 11 , wherein a top surface of the gate dielectric layer is higher than a top surface of the gate electrode.

16. The semiconductor device according to claim 11, wherein A dielectric layer in contact with the sidewall of the gate dielectric layer is also included. 17 . The semiconductor device according to claim 11 , wherein the channel structure is made of an oxide semiconductor material. The semiconductor device according to claim 17 , wherein the channel structure is made of InGaZnO. The semiconductor device according to claim 11 , wherein the gate electrode has a ring-shaped top profile.

20. The semiconductor device of claim 19, wherein the word line has a stripe-shaped top profile.

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