Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a landing pad on a substrate; a lower electrode on and connected to the landing pad, the lower electrode including an outer portion and an inner portion inside the outer portion, the outer portion including a first region and a second region; a dielectric film on the lower electrode to extend along a first region of the outer portion; and an upper electrode on the dielectric film, in which an outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in a first region of the outer portion being different from a concentration of the metal dopant in a second region of the outer portion.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202010552109.1, with the filing date of June 17, 2020 and the invention title of "Semiconductor Device and Method of Manufacturing the Same". Technical Field

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device using a capacitor as a data storage element and a method of manufacturing the semiconductor device. Background Art

[0003] To support the latest trends towards large-capacity and highly integrated semiconductor devices, the design rules and minimum feature sizes of semiconductor devices are constantly decreasing. Such a trend is particularly applicable to semiconductor memory devices, such as dynamic random access memories (DRAMs). For example, in order for a DRAM to operate properly, each cell may require a capacitance exceeding a predetermined level. Summary of the Invention

[0004] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a landing pad on a substrate; a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion and an inner portion inside the outer portion, the outer portion including a first region and a second region; a dielectric film on the lower electrode extending along the first region of the outer portion; and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, and the concentration of the metal dopant in the first region of the outer portion is different from the concentration of the metal dopant in the second region of the outer portion.

[0005] According to another embodiment of the present disclosure, there is provided a semiconductor device including: a landing pad provided on a substrate; a lower electrode provided on the landing pad and connected to the landing pad and extending in the thickness direction of the substrate; at least one support pattern in contact with a portion of the lower electrode; a dielectric film extending along the outer surface of the lower electrode and the outer surface of the at least one support pattern; and an upper electrode provided on the dielectric film, wherein the lower electrode includes a metal dopant, at least a part of the outer surface of the lower electrode is doped with the metal dopant, and the concentration of the metal dopant in the portion of the outer surface of the lower electrode between the lower electrode and the dielectric film is higher than the concentration of the metal dopant in the portion of the outer surface of the lower electrode between the lower electrode and the at least one support pattern.

[0006] According to yet another embodiment of the present disclosure, a semiconductor device is provided, which includes: a landing pad disposed on a substrate; an etch stop film disposed on the landing pad to expose a portion of the landing pad; a first support pattern disposed on the etch stop film and spaced apart from the etch stop film, and having a first thickness; a second support pattern disposed on the first support pattern and spaced apart from the first support pattern, and having a second thickness greater than the first thickness; a lower electrode disposed on the landing pad to contact the etch stop film, the first support pattern, and the second support pattern; a dielectric film extending along the contours of the lower electrode, the first support pattern, and the second support pattern; and an upper electrode disposed on the dielectric film, wherein the lower electrode includes a metal dopant, at least a portion of the sidewall of the lower electrode is doped with the metal dopant, and a portion of the sidewall of the lower electrode between the lower electrode and the second support pattern includes a portion that does not contain the metal dopant.

[0007] According to yet another embodiment of the present disclosure, a method of manufacturing a semiconductor device is provided, which includes: forming a lower electrode on a landing pad; forming a support pattern to contact a portion of the sidewall of the lower electrode; forming an interface layer including a metal dopant along the contours of the lower electrode and the support pattern; diffusing the metal dopant into the lower electrode through a heat treatment process; removing the interface layer after the heat treatment process; forming a dielectric film along the contours of the lower electrode and the support pattern; and forming an upper electrode on the dielectric film. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by referring to the accompanying drawings in detail, in which:

[0009] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown;

[0010] Figure 2 Shows Figure 1 An enlarged cross-sectional view of the lower electrode, the support pattern, and the etch stop film of

[0011] Figure 3 Shows Figure 1 An enlarged cross-sectional view of portion P in

[0012] Figure 4 Shows the change in the concentration of the metal dopant along Figure 2 Line A of

[0013] Figure 5 Shows the change in the concentration of the metal dopant along Figure 2 Line B of

[0014] Figure 6 Shows the change in the concentration of the metal dopant along Figure 2Graph of the change of line C

[0015] Figure 7 Shows a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 8 Shows a semiconductor device according to some embodiments of the present disclosure;

[0017] Figure 9 Shows a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 10 Shows a semiconductor device according to some embodiments of the present disclosure;

[0019] Figure 11 Shows a semiconductor device according to some embodiments of the present disclosure;

[0020] Figure 12 Shows a semiconductor device according to some embodiments of the present disclosure;

[0021] Figure 13 Shows the change in the concentration of the metal dopant near the outer surface of the lower electrode of the semiconductor device at Figure 12 Graph of the change;

[0022] Figure 14 Shows a semiconductor device according to some embodiments of the present disclosure;

[0023] Figure 15 Shows a semiconductor device according to some embodiments of the present disclosure; and

[0024] Figures 16 to 21 Shows a cross-sectional view of a stage in a method of manufacturing a semiconductor device according to some embodiments. Detailed Description

[0025] Figure 1 Is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure. Figure 2 Is to show Figure 1 Cross-sectional view of the lower electrode, support pattern, and etch stop film. Figure 3 Is Figure 1 Magnified cross-sectional view of part P. Figure 4 Is a graph showing the change in the concentration of the metal dopant along Figure 2 Line A. Figure 5 Is a graph showing the change in the concentration of the metal dopant along Figure 2 Line B. Figure 6 Is a graph showing the change in the concentration of the metal dopant along Figure 2 Line C.

[0026] Reference Figures 1 to 3 Referring to Figures 1 to 3 , a semiconductor device according to some embodiments of the present disclosure may include a landing pad 120, an etch stop film 130, a lower support pattern 140, an upper support pattern 150, a lower electrode 200, a capacitor dielectric film 250, and an upper electrode 260.

[0027] The landing pad 120 may be disposed on the substrate 100. The landing pad 120 may be connected to the substrate 100. The landing pad 120 may be electrically connected to a conductive region formed on or in the substrate 100.

[0028] The landing pad 120 may be connected to the substrate 100 via a storage contact 115. The landing pad 120 may be disposed on the storage contact 115.

[0029] The interlayer insulating film 110 may be disposed on the substrate 100. The storage contact 115 and the landing pad 120 may be disposed in the interlayer insulating film 110 on the substrate 100.

[0030] For example, the substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In another example, the substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto. The substrate 100 will be described as a silicon substrate hereinafter.

[0031] The interlayer insulating film 110 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0032] The storage contact 115 may include at least one of, for example, an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. The landing pad 120 may include at least one of, for example, an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. For example, the landing pad 120 may include tungsten (W).

[0033] The etch stop film 130 may be disposed on the interlayer insulating film 110. The etch stop film 130 may at least partially expose the landing pad 120.

[0034] For example, the etch stop film 130 may be disposed on the landing pad 120. The etch stop film 130 may include a lower electrode hole 130h. The lower electrode hole 130h may at least partially expose the landing pad 120.

[0035] The etch stop film 130 may include, for example, one of silicon nitride, silicon carbonate (SiCO), silicon oxide, silicon carbonitride (SiCN), silicon oxynitride, and combinations thereof. The etch stop film 130 may include silicon carbonitride or silicon nitride.

[0036] The lower electrode 200 may be disposed on the landing pad 120. The lower electrode 200 may be connected to the landing pad 120.

[0037] The lower electrode 200 may extend in the thickness direction of the substrate 100, i.e., in the second direction DR2. The length of the lower electrode 200 extending in the second direction DR2 may be greater than the length of the lower electrode 200 extending in the first direction DR1. Alternatively, the length of the lower electrode 200 extending in the second direction DR2 may be greater than the width of the lower electrode 200 in the first direction DR1. The lower electrode 200 may be in the shape of, for example, a column or a cylinder.

[0038] Here, the second direction DR2 may be a direction parallel to the thickness direction of the substrate 100. For example, the second direction DR2 may extend along the normal to the upper surface of the substrate 100. The first direction DR1 may intersect the second direction DR2 and may be a direction parallel to the top surface of the substrate 100 or the top surface of the interlayer insulating film 110.

[0039] The lower electrode 200 may include an outer surface 200s that defines the shape of the lower electrode 200. The outer surface 200s may include a bottom surface 200bs facing the top surface of the landing pad 120, side walls 200ss extending in the second direction DR2, and a top surface 200us facing, for example, a top surface parallel to the bottom surface 200bs. The side walls 200ss may connect the bottom surface 200bs and the top surface 200us. For example, as Figure 1 shown, two lower electrodes 200 may be adjacent to each other in the first direction DR1 such that each of the two lower electrodes 200 may be connected to a corresponding one of the landing pads 120. For example, as Figure 1 further shown, the two lower electrodes 200 may be connected to each other by a lower support pattern 140 and an upper support pattern 150.

[0040] A portion of the lower electrode 200 may be disposed in the lower electrode hole 130h. The lower electrode 200 may pass through the lower electrode hole 130h to connect to the landing pad 120. For example, the lower portion of the lower electrode 200 may fill the lower electrode hole 130h and may directly contact the landing pad 120. For example, a portion of the side wall 200ss of the lower electrode 200 may be in direct contact with the etch stop film 130, for example.

[0041] The lower electrode 200 may include, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, or tungsten nitride), a metal (such as ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (such as iridium oxide), but the present disclosure is not limited thereto. The lower electrode 200 will be described hereinafter as including titanium nitride (TiN).

[0042] The lower electrode 200 may include a metal dopant. The interior and / or exterior of the lower electrode 200 may be doped with a metal dopant.

[0043] The metal dopant may include, for example, at least one of tin (Sn), molybdenum (Mo), niobium (Nb), tantalum (Ta), indium (In), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), vanadium (V), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and ruthenium (Ru). The metal dopant may be different from the metal included in the lower electrode 200. For example, when the lower electrode 200 includes titanium nitride, the lower electrode 200 may be doped with any one of the foregoing metal dopants other than titanium. The lower electrode 200 and the metal dopant will be described in more detail below.

[0044] The lower support pattern 140 may be disposed on the etch stop film 130. The lower support pattern 140 may be spaced apart from the etch stop film 130 in the second direction DR2. The lower support pattern 140 may be in direct contact with the lower electrode 200, for example. The lower support pattern 140 may be in direct contact with a portion of the sidewall 200ss of the lower electrode 200, for example. The lower support pattern 140 may include an outer surface 140s extending in the first direction DR1. The outer surface 140s of the lower support pattern 140 may include a top surface 140us and a bottom surface 140bs facing each other. For example, the top surface 140us and the bottom surface 140bs may be parallel to each other and parallel to the bottom surface 200bs and the top surface 200us of the lower electrode 200.

[0045] The upper support pattern 150 may be disposed on the lower support pattern 140. For example, the lower support pattern 140 may be between the substrate 100 and the upper support pattern 150. The upper support pattern 150 may be spaced apart from the lower support pattern 140 in the second direction DR2. The upper support pattern 150 may be in direct contact with the lower electrode 200, for example. The upper support pattern 150 may be in direct contact with a portion of the sidewall 200ss of the lower electrode 200, for example. The upper support pattern 150 may include an outer surface 150s extending in the first direction DR1. The outer surface 150s of the upper support pattern 150 may include a top surface 150us and a bottom surface 150bs facing each other. For example, the top surface 150us and the bottom surface 150bs may be parallel to each other and parallel to the top surface 140us and the bottom surface 140bs of the lower support pattern 140.

[0046] For example, the top surface 150us of the upper support pattern 150 may be in the same plane as the top surface 200us of the lower electrode 200. For example, the top surface 150us and the top surface 200us may be at the same distance from the top surface of the substrate 100 and may be flush with each other. In another example, the top surface 150us of the upper support pattern 150 may protrude beyond the top surface 200us of the lower electrode 200 in a direction away from the substrate 100, for example, protruding above the top surface 200us of the lower electrode 200. The top surface 150us of the upper support pattern 150 will be described hereinafter as being in the same plane as the top surface 200us of the lower electrode 200.

[0047] The lower support pattern 140 and the upper support pattern 150 may include at least one of, for example, silicon nitride, silicon carbonate, silicon oxide, silicon carbonitride, silicon oxynitride, and combinations thereof. For example, the lower support pattern 140 and the upper support pattern 150 may include silicon carbonitride or silicon nitride.

[0048] The thickness t11 of the lower support pattern 140 in the second direction DR2 may be different from the thickness t12 of the upper support pattern 150 in the second direction DR2. For example, as Figure 1 shown, the thickness t11 of the lower support pattern 140 may be less than the thickness t12 of the upper support pattern 150.

[0049] For example, as Figure 1 shown, a semiconductor device according to an embodiment may include both the lower support pattern 140 and the upper support pattern 150. In another example, a semiconductor device according to an embodiment may include only one of the lower support pattern 140 and the upper support pattern 150. In yet another example, a semiconductor device according to some embodiments may include a third support pattern in addition to the lower support pattern 140 and the upper support pattern 150.

[0050] The capacitor dielectric film 250 may be disposed on the lower electrode 200. The capacitor dielectric film 250 may be formed conformally, for example, along the outer surface 200s of the lower electrode 200, the outer surface 150s of the upper support pattern 150, the outer surface 140s of the lower support pattern 140, and the top surface of the etch stop film 130. The capacitor dielectric film 250 may extend along the contours of the lower electrode 200, the upper support pattern 150, the lower support pattern 140, and the etch stop film 130. For example, as Figure 1 shown, the capacitor dielectric film 250 may be formed conformally, for example, along the outer surfaces 200s of two adjacent lower electrodes 200 without being formed on portions of the surfaces of the two adjacent lower electrodes 200 that face each other.

[0051] Because the lower support pattern 140 and the upper support pattern 150 are in direct contact with the lower electrode 200, for example, the capacitor dielectric film 250 may not extend between the lower support pattern 140 and the lower electrode 200 and between the upper support pattern 150 and the lower electrode 200. In addition, the capacitor dielectric film 250 may not extend between the etch stop film 130 and the lower electrode 200.

[0052] The capacitor dielectric film 250 may be in direct contact with the lower electrode 200, for example. The capacitor dielectric film 250 may be in direct contact with the outer surface 150s of the upper support pattern 150, the outer surface 140s of the lower support pattern 140, and the top surface 130s of the etch stop film 130, for example.

[0053] The capacitor dielectric film 250 may include, for example, at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but the present disclosure is not limited thereto.

[0054] The capacitor dielectric film 250 is shown as a single-layer film, but the present disclosure is not limited thereto. For example, the capacitor dielectric film 250 may have a stacked structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked.

[0055] In another example, the capacitor dielectric film 250 may have a stacked structure in which a ferroelectric material film and a dielectric material film are stacked. The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may have a thickness sufficient to have ferroelectric properties. The thickness of the ferroelectric material film may vary depending on the type of ferroelectric material used to form the ferroelectric material film.

[0056] For example, the ferroelectric material film may include a single metal oxide. The ferroelectric material film may include a single metal oxide film. Here, the single metal oxide may be a binary compound including a single metal and oxygen, for example, composed of a single metal and oxygen.

[0057] For example, the metal included in the single metal oxide film may be hafnium (Hf), and the single metal oxide film may be a hafnium oxide (HfO) film. Here, the hafnium oxide film may have a chemical formula that conforms to or does not conform to stoichiometry.

[0058] In another example, the metal included in the single metal oxide film may be a lanthanide rare earth metal, and the single metal oxide film may be a lanthanide rare earth metal oxide film. Here, the lanthanide rare earth metal oxide film may have a chemical formula that conforms to or does not conform to stoichiometry.

[0059] The ferroelectric material film may further include a dopant incorporated inside the single metal oxide film. The doping concentration of the dopant may vary depending on the type of the dopant, but the doping concentration of the dopant may be 10% or less.

[0060] For example, when the single metal oxide film is a hafnium oxide film, the dopant incorporated inside the single metal oxide film may include at least one of gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum, strontium (Sr), and niobium (Nb). In another example, when the single metal oxide film is a lanthanide rare earth metal oxide film, the dopant incorporated inside the single metal oxide film may include at least one of silicon, aluminum, hafnium, zirconium (Zr), and niobium.

[0061] Alternatively, the ferroelectric material film may not include the dopant incorporated inside the single metal oxide film.

[0062] When the ferroelectric material film includes the single metal oxide film, the ferroelectric material film may have a thickness of, for example, 1 nm or more and 10 nm or less. For example, the ferroelectric material film may include a double metal oxide, such as a double metal oxide film.

[0063] The double metal oxide may be a ternary compound composed of two metals and oxygen. The metals included in the double metal oxide film may be, for example, hafnium and zirconium. The double metal oxide film may be a hafnium zirconium oxide (Hf x Zr (1-x) O, where x is 0.2 or more and 0.8 or less) film. The hafnium zirconium oxide film may have a chemical formula that conforms to or does not conform to stoichiometry.

[0064] For example, the double metal oxide film may further include a dopant incorporated inside the double metal oxide film. For example, the dopant may include at least one of gadolinium, silicon, aluminum, yttrium, lanthanum, scandium, cerium, dysprosium, tantalum, and strontium. In another example, the ferroelectric material film may not include the dopant incorporated inside the double metal oxide film.

[0065] When the ferroelectric material film includes the double metal oxide film, the ferroelectric material film may have a thickness of, for example, 1 nm or more and 20 nm or less.

[0066] The dielectric material has a positive dielectric constant, and the ferroelectric material has a negative dielectric constant. That is, the dielectric material has a positive capacitance, and the ferroelectric material has a negative capacitance.

[0067] Generally, if two or more capacitors having positive capacitance are connected in series, the sum of the capacitances of the two or more capacitors decreases. However, if a capacitor having negative capacitance and a capacitor having positive capacitance are connected in series, the sum of the capacitances of the two capacitors increases.

[0068] The upper electrode 260 may be disposed on the capacitor dielectric film 250. The upper electrode 260 may include, for example, a first sub-upper electrode 261 and a second sub-upper electrode 262. The first sub-upper electrode 261 may be formed along the contour of the capacitor dielectric film 250. The second sub-upper electrode 262 may be disposed on the first sub-upper electrode 261.

[0069] The first sub-upper electrode 261 and the second sub-upper electrode 262 may include, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, or tungsten nitride), a metal (such as ruthenium, iridium, titanium, niobium, nickel, copper (Cu), molybdenum, or tantalum), or a conductive metal oxide (such as iridium oxide or molybdenum oxide), but the present disclosure is not limited thereto. For example, the upper electrode 260 may include only one of the first sub-upper electrode 261 and the second sub-upper electrode 262.

[0070] Referring to Figure 1 and Figure 2 , the lower electrode 200 may include an outer portion 210 and an inner portion 220 within the outer portion 210. In this regard, note that Figure 2 is shown Figure 1 the left lower electrode 200, while it is (at the bottom) connected to a portion of the etch stop film 130 and (above the etch stop film 130) connected to portions of the lower support pattern 140 and the upper support pattern 150. For example, as Figure 2 shown, the outer portion 210 and the inner portion 220 may be integral with each other, for example, formed as a seamless electrode ( Figure 2 the dashed line in

[0071] is only shown for convenience as an imaginary line between the outer portion 210 and the inner portion 220). Figure 2 As

[0072] The outer portion 210 may include a bottom portion 210bp, a top portion 210up, and a side portion 210sp. The side portion 210sp may be a portion of the outer portion 210 that extends from the bottom surface 200bs of the lower electrode 200 to the top surface 200us of the lower electrode 200. For example, the side portion 210sp may include two identical portions that extend along two opposite sidewalls 200ss of the lower electrode 200 and are separated from each other by the inner portion 220.

[0073] The side portion 210sp may include the sidewall 200ss of the lower electrode 200. Since the side portion 210sp extends to the bottom surface 200bs of the lower electrode 200, the bottom portion 210bp may include a portion of the bottom surface 200bs of the lower electrode 200. Since the side portion 210sp also extends to the top surface 200us of the lower electrode 200, the top portion 210up may include a portion of the top surface 200us of the lower electrode 200.

[0074] The side portion 210sp may be in direct contact with, for example, the etch stop film 130, the lower support pattern 140, and the upper support pattern 150. The portion of the side portion 210sp that is not in contact with any of the etch stop film 130, the lower support pattern 140, and the upper support pattern 150 may be the first portion 210sp_1.

[0075] The portion of the side portion 210sp that is in contact with the upper support pattern 150 may be the 2_1 portion 210sp_21. The portion of the side portion 210sp that is in contact with the lower support pattern 140 may be the 2_2 portion 210sp_22. The portion of the side portion 210sp that is in contact with the etch stop film 130 may be the 2_3 portion 210sp_23. For example, as Figure 2 shown, the portion 210sp_1 may be between the portions 210sp_21 and 210sp_22 and between the portions 210sp_22 and 210sp_23. For example, as Figure 2 further shown, the portion 210sp_1 and the portions 210sp_21 to 210sp_23 may have the same width in the first direction DR1 and may be continuous with each other.

[0076] As Figure 1 and Figure 2As shown, the capacitor dielectric film 250 can extend along the top portion 210up and the first portion 210sp_1 of the side portion 210sp. The capacitor dielectric film 250 does not extend along the bottom portion 210bp, nor along the second portion 210sp_22 and the first portion 210sp_21 of the side portion 210sp, that is, the capacitor dielectric film 250 does not extend between each of the outer portion 210 and the lower support pattern 140 and the upper support pattern 150.

[0077] The region where the capacitor dielectric film 250 is formed can correspond to the first region of the outer portion 210. The region where the capacitor dielectric film 250 is not formed can correspond to the second region of the outer portion 210. The first portion 210sp_21 of the side portion 210sp of the outer portion 210 can include the first region and the second region of the outer portion 210. For example, the first portion 210sp_21 of the side portion 210sp of the outer portion 210 can include the first region only where it overlaps with the top portion 210up.

[0078] The portion of the sidewall 200ss of the lower electrode 200 that does not contact any of the etch stop film 130, the lower support pattern 140, and the upper support pattern 150 can be the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200. The portion of the sidewall 200ss of the lower electrode 200 that contacts the upper support pattern 150 can be the second portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The portion of the sidewall 200ss of the lower electrode 200 that contacts the lower support pattern 140 can be the second portion 200ss_22 of the sidewall 200ss of the lower electrode 200. The portion of the sidewall 200ss of the lower electrode 200 that contacts the etch stop film 130 can be the second portion 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0079] The second portion 200ss_21 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the upper support pattern 150. The second portion 200ss_22 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the lower support pattern 140. The second portion 200ss_23 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the etch stop film 130.

[0080] The 2_1 part 210sp_21 of the side part 210sp includes the 2_1 part 200ss_21 of the side wall 200ss of the lower electrode 200. The 2_2 part 210sp_22 of the side part 210sp includes the 2_2 part 200ss_22 of the side wall 200ss of the lower electrode 200. The 2_3 part 210sp_23 of the side part 210sp includes the 2_3 part 200ss_23 of the side wall 200ss of the lower electrode 200.

[0081] The capacitor dielectric film 250 can extend along the first part 200ss_1 of the side wall 200ss of the lower electrode 200 and the top surface 200us of the lower electrode 200. The capacitor dielectric film 250 does not extend along the bottom surface 200bs of the lower electrode 200 and the 2_1 part 200ss_21, 2_2 part 200ss_22, and 2_3 part 200ss_23 of the side wall 200ss of the lower electrode 200.

[0082] The region where the capacitor dielectric film 250 is formed can correspond to the first region of the outer part 210 of the lower electrode 200. The region where the capacitor dielectric film 250 is not formed can correspond to the second region of the outer part 210 of the lower electrode 200.

[0083] Figure 4 The change in the concentration of the metal dopant Md in the side part 210sp of the outer part 210 of the lower electrode 200 is shown. For example, as Figure 4 shown, the change in the concentration of the metal dopant Md can be substantially the same as the change in the concentration of the metal dopant Md in the side wall 200ss of the lower electrode 200. Figure 4 The change in the concentration of the metal dopant Md in the side part 210sp of the outer part 210 of the lower electrode 200 from the top surface 200us to the bottom surface 200bs of the lower electrode 200 is shown.

[0084] Referring to Figure 4 , the concentration of the metal dopant Md in the 2_1 part 210sp_21 of the side part 210sp of the outer part 210 decreases away from the top surface 200us of the lower electrode 200. The concentration of the metal dopant Md can be zero in the 2_1 part 210sp_21 of the side part 210sp of the outer part 210. The 2_1 part 210sp_21 of the side part 210sp of the outer part 210 includes a first sub-region containing the metal dopant Md and a second sub-region not containing the metal dopant Md.

[0085] Here, a zero metal dopant concentration does not necessarily mean that the metal dopant Md is absent, but can mean that the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 is doped with the metal dopant Md to an amount less than a predetermined detection limit.

[0086] The concentration of the metal dopant Md can also be zero in the second_2 portion 210sp_22 and the second_3 portion 210sp_23 of the side portion 210sp of the outer portion 210. The concentration of the metal dopant Md can be C in the first portion 210sp_1 of the side portion 210sp of the outer portion 210 0 , i.e., C in the portion of the side portion 210sp facing, for example, the contact capacitor dielectric film 250 0 .

[0087] In other words, the concentration of the metal dopant Md in the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 decreases away from the top surface 200us of the lower electrode 200. The concentration of the dopant Md can be zero in the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 can include a portion containing the metal dopant Md and a portion not containing the metal dopant Md.

[0088] The concentration of the metal dopant Md can also be zero in the second_2 portion 200ss_22 and the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200. The concentration of the metal dopant Md can be C in the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200 0 .

[0089] The concentration of the metal dopant Md in the top portion 210up of the outer portion 210 can be substantially the same as the concentration of the metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210. Thus, the concentration of the metal dopant Md can be C in the top portion 210up of the outer portion 210 of the lower electrode 200 or at the top surface 200us of the lower electrode 200 0 .

[0090] At least a portion of the outer portion 210 of the lower electrode 200 can include the metal dopant Md. The outer portion 210 of the lower electrode 200 can include a region doped with the metal dopant Md and a region not doped with the metal dopant Md.

[0091] The capacitor dielectric film 250 may extend along a first portion 210sp_1 of a side portion 210sp of the outer portion 210. However, the capacitor dielectric film 250 does not extend along a second portion 210sp_22 and a third portion 210sp_23 of the side portion 210sp of the outer portion 210.

[0092] The concentration of the metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210 may be different from the concentration of the metal dopant Md in a first sub-portion 210sp_21, a second sub-portion 210sp_22, and a third sub-portion 210sp_23 of the side portion 210sp of the outer portion 210. For example, the concentration of the metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210 may be higher than the concentration of the metal dopant Md in the first sub-portion 210sp_21, the second sub-portion 210sp_22, and the third sub-portion 210sp_23 of the side portion 210sp of the outer portion 210.

[0093] The concentration of the metal dopant Md compared between different regions may be the average concentration of the metal dopant Md. That is, there may be a portion in the first sub-portion 210sp_21 of the side portion 210sp of the outer portion 210 where the concentration of the metal dopant Md is particularly high, but the average concentration of the metal dopant Md may be lower in the first sub-portion 210sp_21 of the side portion 210sp of the outer portion 210 than in the first portion 210sp_1 of the side portion 210sp of the outer portion 210.

[0094] The lower electrode 200 may include the metal dopant Md, and at least some of the outer surface 200s of the lower electrode 200 may be doped with the metal dopant Md. The outer surface 200s of the lower electrode 200 may include a region doped with the metal dopant Md and a region not doped with the metal dopant Md.

[0095] The concentration of the metal dopant Md may be higher in a first portion 200ss_1 of the sidewall 200ss of the lower electrode 200 than in a first sub-portion 200ss_21, a second sub-portion 200ss_22, and a third sub-portion 200ss_23 of the sidewall 200ss of the lower electrode 200.

[0096] In other words, the concentration of the metal dopant Md, i.e., C, in the portion of the outer surface 200s of the lower electrode 200 between the lower electrode 200 and the capacitor dielectric film 250 0The concentration of the metal dopant Md in the portions between the lower electrode 200 and the upper support pattern 150, between the lower electrode 200 and the lower support pattern 140, and between the lower electrode 200 and the etch stop film 130 that can be higher than the outer surface 200s of the lower electrode 200.

[0097] Referring to Figure 5 , the upper support pattern 150 may not include the metal dopant Md. The interior of the upper support pattern 150 may not be doped with the metal dopant Md. Similarly, the lower support pattern 140 and the etch stop film 130 may not include the metal dopant Md.

[0098] Figure 6 Shows the change in the concentration of the metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210 where the capacitor dielectric film 250 is formed. The concentration of the metal dopant Md in the outer portion 210 of the lower electrode 200 decreases away from the outer surface 200s of the lower electrode 200, for example, in the direction oriented towards the inner portion 220.

[0099] Figure 6 Shows that the outer portion 210 of the lower electrode 200 includes the metal dopant Md, and the inner portion 220 of the lower electrode 200 does not include the metal dopant Md, but the present disclosure is not limited thereto.

[0100] Figure 7 Shows a semiconductor device according to some embodiments of the present disclosure. Figure 8 Shows a semiconductor device according to some embodiments of the present disclosure. Figure 7 and Figure 8 The semiconductor device of Figures 1 to 6 will be mainly described hereinafter with emphasis on the differences from the semiconductor device of

[0101] Specifically, Figure 7 is a graph showing the change in the concentration of the metal dopant along line A of Figure 2 in a semiconductor device according to some embodiments of the present disclosure, Figure 8 is a graph showing the change in the concentration of the metal dopant along line A of Figure 2 in a semiconductor device according to some embodiments of the present disclosure.

[0102] Referring to Figure 7, portions of the second - 2 part 210sp_22 and the second - 3 part 210sp_23 of the side portion 210sp of the outer portion 210 of the lower electrode 200 may include a metal dopant Md. The second - 2 part 210sp_22 and the second - 3 part 210sp_23 of the side portion 210sp of the outer portion 210 include regions containing the metal dopant Md and regions not containing the metal dopant Md. Portions of the second - 2 part 200ss_22 and the second - 3 part 200ss_23 of the sidewall 200ss of the lower electrode 200 may include a metal dopant Md.

[0103] Reference Figure 8 , the second - 2 part 210sp_22 of the side portion 210sp of the outer portion 210 of the lower electrode 200 may generally include a metal dopant Md. The second - 2 part 200ss_22 of the sidewall 200ss of the lower electrode 200 may generally include a metal dopant Md. The second - 2 part 200ss_22 of the sidewall 200ss of the lower electrode 200 may be generally doped with a metal dopant Md.

[0104] Figure 9 A semiconductor device according to some embodiments of the present disclosure is shown. Figure 9 The semiconductor device will hereinafter mainly focus on the differences from Figures 1 to 6 the semiconductor device to be described.

[0105] Specifically, Figure 9 is a graph showing the variation of the concentration of the metal dopant along Figure 2 line B in a semiconductor device according to some embodiments of the present disclosure.

[0106] Reference Figure 9 , the upper support pattern 150 may include a metal dopant Md. The outer surface 150s of the upper support pattern 150 may be doped with a metal dopant Md.

[0107] The concentration of the metal dopant Md at the outer surface 150s of the upper support pattern 150 may be lower than the concentration of the metal dopant Md in the first part 200ss_1 of the sidewall 200ss of the lower electrode 200 (i.e., C 0 ), where the first part 200ss_1 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the capacitor dielectric film 250.

[0108] Although not specifically shown, the lower support pattern 140 may include a metal dopant Md, and the outer surface 140s of the lower support pattern 140 may be doped with a metal dopant Md. The etch stop film 130 may include a metal dopant Md, and the top surface 130s of the etch stop film 130 may be doped with a metal dopant Md.

[0109] The concentration of the metal dopant Md at the outer surface 140s of the lower support pattern 140 and at the top surface 130s of the etch stop film 130 may be lower than the concentration of the metal dopant Md in the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200, i.e., C 0 .

[0110] The outer surface 150s of the upper support pattern 150, the outer surface 140s of the lower support pattern 140, and / or the top surface 130s of the etch stop film 130 may include the metal dopant Md

[0111] Figure 10 A semiconductor device according to some embodiments of the present disclosure is shown Figure 11 A semiconductor device according to some embodiments of the present disclosure is shown Figure 10 and Figure 11 The semiconductor device of will hereinafter focus mainly on the differences from Figures 1 to 6 the semiconductor device of

[0112] Specifically Figure 10 and Figure 11 are enlarged cross-sectional views of portions of the semiconductor device according to some embodiments of the present disclosure corresponding to the portion P surrounded by the dashed line of Figure 1 the semiconductor device of

[0113] Referring to Figure 10 , a semiconductor device according to some embodiments of the present disclosure may further include an interposed film 255 disposed between the lower electrode 200 and the upper electrode 260. The interposed film 255 may be disposed inside the capacitor dielectric film 250

[0114] The interposed film 255 may promote crystallization of the capacitor dielectric film 250. The capacitor dielectric film 250 may be divided into a first portion 250a and a second portion 250b by the interposed film 255. The interposed film 255 may be in contact with the first portion 250a and the second portion 250b of the capacitor dielectric film 250

[0115] The interposed film 255 may include at least one of, for example, titanium (Ti), niobium (Nb), molybdenum (Mo), tin nitride, and tin oxide. Alternatively, the interposed film 255 may include at least one of ruthenium and ruthenium oxide

[0116] Referring to Figure 11 , a semiconductor device according to some embodiments of the present disclosure may further include a passivation film 265 disposed between the capacitor dielectric film 250 and the upper electrode 260. The passivation film 265 may prevent oxygen atoms included in the capacitor dielectric film 250 from moving to the upper electrode 260

[0117] The passivation film 265 may include a metal oxide. The passivation film 265 may include at least one of, for example, titanium oxide, tantalum oxide, molybdenum oxide, tin oxide, and niobium oxide.

[0118] Figure 12 A semiconductor device according to some embodiments of the present disclosure is shown. Figure 13 is a graph showing the change in the concentration of the metal dopant near the outer surface of the lower electrode of the semiconductor device at Figure 12 The semiconductor device will hereinafter be mainly described focusing on the differences from the semiconductor device at Figure 12 The semiconductor device at Figures 1 to 6 will be described mainly focusing on the differences from the semiconductor device at

[0119] Specifically, Figure 13 is a graph showing the change in the concentration of the metal dopant along Figure 12 line A in the semiconductor device at Figure 2 The semiconductor device at

[0120] Referring to Figure 2 and Figure 12 and Figure 13 the second _ 1 part 210sp_21 and the second _ 2 part 210sp_22 of the side part 210sp of the outer part 210 of the lower electrode 200 may generally include the metal dopant Md. The second _ 1 part 200ss_21 and the second _ 2 part 200ss_22 of the side wall 200ss of the lower electrode 200 may generally include the metal dopant Md. The second _ 1 part 200ss_21 of the side wall 200ss of the lower electrode 200 may generally be doped with the metal dopant Md. The second _ 2 part 200ss_22 of the side wall 200ss of the lower electrode 200 may generally be doped with the metal dopant Md.

[0121] Figure 14 A semiconductor device according to some embodiments of the present disclosure is shown. Figure 14 The semiconductor device at Figures 1 to 6 will hereinafter be mainly described focusing on the differences from the semiconductor device at

[0122] Referring to Figure 14 the lower electrode 200 may include a bottom part 202 extending along the top surface of the landing pad 120 and a side wall part 201 protruding from the bottom part 202. The side wall part 201 of the lower electrode 200 may extend in the second direction DR2.

[0123] The outer surface 200s of the lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2. The outer surface 200s of the lower electrode 200 may further include a top surface 200us connecting the first sidewall 200ss1 and the second sidewall 200ss2. The outer surface 200s of the lower electrode 200 may further include a first bottom surface 200bs_1 connected to the first sidewall 200ss1 and a second bottom surface 200bs_2 connected to the second sidewall 200ss2. The lower electrode 200 may be in the shape of a container.

[0124] The etch stop film 130, the lower support pattern 140, and the upper support pattern 150 may be in contact with the first sidewall 200ss1 of the lower electrode 200.

[0125] The capacitor dielectric film 250 may extend along the first sidewall 200ss1 and the second sidewall 200s2 of the lower electrode 200. The bottom portion 202 of the lower electrode 200 may include an outer portion 210 and an inner portion 220. The sidewall portion 201 of the lower electrode 200 may also include an outer portion 210 and an inner portion 220.

[0126] For example, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 may be greater than 0 and less than 0.5. The width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 may be the distance between the first sidewall 200ss1 and the second sidewall 200ss2 of the lower electrode 200 that face each other.

[0127] Figure 15 A semiconductor device according to some embodiments of the present disclosure is shown. Figure 15 The semiconductor device will hereinafter focus mainly on the differences from Figures 1 to 6 the semiconductor device.

[0128] Refer to Figure 15 , a semiconductor device according to some embodiments of the present disclosure may further include an insulating pattern 160 that contacts the lower electrode 200 and extends in a second direction DR2. The insulating pattern 160 may be disposed on the etch stop film 130. The insulating pattern 160 may include a sidewall 160s and a top surface 160u.

[0129] The landing pad 120 may be disposed in the etch stop film 130. The lower electrode 200 may be disposed on the etch stop film 130.

[0130] The lower electrode 200 may include a bottom portion 202 extending along the top surface of the landing pad 120 and a sidewall portion 201 protruding from the bottom portion 202. The sidewall portion 201 of the lower electrode 200 may extend in the second direction DR2. The sidewall portion 201 of the lower electrode 200 may extend along the sidewall 160s of the insulating pattern 160.

[0131] The outer surface 200s of the lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2. The second sidewall 200ss2 may face the sidewall 160s of the insulating pattern 160. The outer surface 200s of the lower electrode 200 may further include a top surface 200us connecting the first sidewall 200ss1 and the second sidewall 200ss2. The outer surface 200s of the lower electrode 200 may further include a bottom surface 200bs, which is connected to the second sidewall 200ss2 and faces the top surface 130s of the etch stop film 130 and the top surface of the landing pad 120.

[0132] The capacitor dielectric film 250 may extend along the first sidewall 200ss1 of the lower electrode 200, but not along the second sidewall 200ss2 of the lower electrode 200. The capacitor dielectric film 250 is not disposed between the second sidewall 200ss2 of the lower electrode 200 and the sidewall 160s of the insulating pattern 160. The capacitor dielectric film 250 may extend along the top surface 160u of the insulating pattern 160.

[0133] For example, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 may be greater than zero and less than 0.5.

[0134] The concentration of the metal dopant may be higher at the first sidewall 200ss1 of the lower electrode 200 than at the second sidewall 200ss2 of the lower electrode 200. The second sidewall 200ss2 of the lower electrode 200 may include a region doped with the metal dopant and a region not doped with the metal dopant.

[0135] Figures 16 to 21 is a cross-sectional view showing stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0136] Referring to Figure 16 , the storage contact 115 and the landing pad 120 may be formed in the interlayer insulating film 110 on the substrate 100. The etch stop film 130, the lower molding film 111, the lower support film 140p, the upper molding film 112, and the upper support film 150p may be sequentially formed on the interlayer insulating film 110.

[0137] Referring to Figure 17, the lower electrode 200 may be formed on the landing pad 120 to penetrate through the etch stop film 130, the lower molding film 111, the lower support film 140p, the upper molding film 112, and the upper support film 150p. A portion of the lower electrode 200 may be disposed in the lower electrode hole 130h included in the etch stop film 130.

[0138] Referring to Figure 18 , the upper support pattern 150 and the lower support pattern 140 may be formed to connect the lower electrodes 200 adjacent to each other along the first direction DR1. The upper support pattern 150 and the lower support pattern 140 may be in direct contact with, for example, a portion of the sidewall of the lower electrode 200.

[0139] The upper support pattern 150 may be formed by removing a portion of the upper support film 150p. For example, the portion of the upper support film 150p on the outer sidewall of the lower electrode 200 may be removed to retain only the upper support pattern 150 connecting the facing sidewalls of the adjacent lower electrodes 200. The upper molding film 112 may be, for example, completely removed using the region where the upper support pattern 150 is not formed.

[0140] Thereafter, the lower support pattern 140 may be formed by removing a portion of the lower support film 140p. For example, the portion of the lower support film 140p on the outer sidewall of the lower electrode 200 may be removed to retain only the lower support pattern 140 connecting the facing sidewalls of the adjacent lower electrodes 200. The lower molding film 111 may be, for example, completely removed using the region where the lower support pattern 140 is not formed.

[0141] As a result, a gap S, for example, an empty space, may be formed between the upper support pattern 150 and the lower support pattern 140 and between the lower support pattern 140 and the etch stop film 130.

[0142] Referring to Figure 19 , the interface layer 225 may be formed along the contours of the lower electrode 200, the upper support pattern 150, and the lower support pattern 140 and along the top surface of the etch stop film 130. The interface layer 225 may include a metal dopant. The interface layer 225 may include at least one of, for example, tin, molybdenum, niobium, tantalum, indium, nickel, cobalt, tungsten, titanium, vanadium, phosphorus, arsenic, antimony, bismuth, and ruthenium.

[0143] Referring to Figure 20 , the metal dopant included in the interface layer 225 may diffuse into the lower electrode 200 through a heat treatment process 230. As a result, the lower electrode 200 may be doped with the metal dopant. For example, the concentration of the metal dopant may vary within the lower electrode 200 according to the curve graph in Figure 4 depending on the portion of the lower electrode 200 in direct contact with the interface layer 225 containing the metal dopant. For example, the concentration of the metal dopant may vary within the lower electrode 200 according to the diffusion distance of the metal dopant within the lower electrode 200 according toFigure 6 The curve in

[0144] Reference is made to Figure 20 and Figure 21 , after the heat treatment process 230, the interface layer 225 can be removed. Thereafter, the capacitor dielectric film 250 can be formed along the contours of the lower electrode 200, the upper support pattern 150, and the lower support pattern 140, and along the top surface of the etch stop film 130.

[0145] Referring again to Figure 1 , the upper electrode 260 can be formed on the capacitor dielectric film 250. For example, as Figure 1 shown, a single upper electrode 260 can continuously cover two adjacent lower electrodes 200.

[0146] As a summary and review, an increase in capacitance can increase the amount of charge that can be stored in the capacitor, thereby improving the refresh characteristics of the semiconductor device. The improved refresh characteristics of the semiconductor device can increase the yield. To increase the capacitance, a dielectric film having a high dielectric constant is used in the capacitor, or the contact area between the lower electrode and the dielectric film of the capacitor is enlarged.

[0147] Embodiments of the present disclosure provide a semiconductor device having a designed interface between a lower electrode and a capacitor dielectric film to improve the performance and reliability of the capacitor. Embodiments of the present disclosure also provide a method of manufacturing a semiconductor device including the above capacitor.

[0148] Example embodiments have been disclosed herein, and although specific terms have been employed, they will be used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, at the time of filing of the present application, it will be apparent to those of ordinary skill in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0149] Korean Patent Application No. 10-2019-0071903, filed on June 18, 2019, with the Korean Intellectual Property Office and entitled "Semiconductor Device and Method of Manufacturing the Same", is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a substrate; a first insulating layer on the substrate; a contact structure in the first insulating layer; a second insulating layer on the first insulating layer; a lower electrode on the second insulating layer, the lower electrode passing through the second insulating layer and contacting the contact structure, and the lower electrode having a side portion including a metal dopant; a first support pattern above the substrate; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the side portion of the lower electrode includes a first side portion, a second side portion, and a third side portion between the first side portion and the second side portion, wherein the second insulating layer contacts the first side portion of the lower electrode, wherein the first support pattern contacts the second side portion of the lower electrode, wherein the dielectric layer contacts the third side portion of the lower electrode, wherein the metal dopant includes a material different from the lower electrode, and wherein the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in at least one of the first side portion and the second side portion of the lower electrode.

2. The semiconductor device according to claim 1, wherein: each of the lower electrode and the upper electrode includes titanium nitride, the metal dopant includes niobium, and the dielectric layer includes hafnium oxide, aluminum oxide, and zirconium oxide.

3. The semiconductor device according to claim 1, wherein the dielectric layer is spaced apart from the first side portion and the second side portion of the lower electrode.

4. The semiconductor device according to claim 1, wherein the side portion of the lower electrode includes a fourth side portion between the first side portion and the second side portion of the lower electrode.

5. The semiconductor device according to claim 4, further comprising a second support pattern under the first support pattern, the second support pattern contacting the fourth side portion of the lower electrode.

6. The semiconductor device according to claim 4, wherein, the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in the fourth side portion of the lower electrode.

7. The semiconductor device according to claim 4, wherein, the dielectric layer is spaced apart from the fourth side portion of the lower electrode.

8. The semiconductor device according to claim 1, wherein, the lower electrode is a cylindrical shape filled inside.

9. The semiconductor device according to claim 1, wherein, the lower electrode is a cylindrical shape with an upper open end.

10. The semiconductor device according to claim 5, wherein the thickness of the first support pattern is greater than the thickness of the second support pattern.

11. The semiconductor device according to claim 1, wherein the lower electrode includes at least one of a doped semiconductor material, titanium nitride, tantalum nitride, tungsten nitride, ruthenium, iridium, titanium, tantalum, or iridium oxide.

12. The semiconductor device according to claim 1, wherein the metal dopant comprises at least one of tin, molybdenum, niobium, tantalum, indium, nickel, cobalt, tungsten, titanium, vanadium, phosphorus, arsenic, antimony, bismuth, or ruthenium.

13. The semiconductor device according to claim 1, wherein the upper electrode comprises at least one of a doped semiconductor material, titanium nitride, tantalum nitride, tungsten nitride, ruthenium, iridium, titanium, niobium, nickel, copper, molybdenum, tantalum, iridium oxide, or molybdenum oxide.

14. The semiconductor device according to claim 1, wherein the dielectric layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum aluminate, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalate, or lead zinc niobate.

15. A semiconductor device, comprising: a substrate; a first insulating layer on the substrate; a contact structure in the first insulating layer; a second insulating layer on the first insulating layer; a lower electrode on the second insulating layer, the lower electrode passing through the second insulating layer and contacting the contact structure, and the lower electrode having a side portion comprising a metal dopant; a first support pattern above the substrate; a second support pattern above the first support pattern; a dielectric layer on the lower electrode; and an upper electrode on the dielectric layer, wherein the side portion of the lower electrode comprises a first side portion, a second side portion, and a third side portion between the first side portion and the second side portion, wherein the first support pattern contacts the first side portion of the lower electrode, wherein the second support pattern contacts the second side portion of the lower electrode, wherein the dielectric layer contacts the third side portion of the lower electrode, wherein the lower electrode comprises titanium nitride, wherein the metal dopant comprises niobium, and wherein the concentration of the metal dopant in the third side portion of the lower electrode is different from the concentration of the metal dopant in at least one of the first side portion and the second side portion of the lower electrode.

16. The semiconductor device according to claim 15, wherein the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in at least one of the first side portion and the second side portion of the lower electrode.

17. The semiconductor device according to claim 15, wherein the side portion of the lower electrode comprises a fourth side portion below the first side portion of the lower electrode, and the second insulating layer contacts the fourth side portion of the lower electrode.

18. The semiconductor device according to claim 17, wherein the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in the fourth side portion of the lower electrode.

19. A semiconductor device, comprising: a substrate; a first insulating layer on the substrate; A contact structure in the first insulating layer; A second insulating layer on the first insulating layer; A lower electrode on the second insulating layer, the lower electrode passing through the second insulating layer and contacting the contact structure, and the lower electrode having a side portion including a metal dopant; A first support pattern above the substrate; A second support pattern above the first support pattern; A dielectric layer on the lower electrode; and An upper electrode on the dielectric layer, wherein the side portion of the lower electrode includes a first side portion, a second side portion, a third side portion between the first side portion and the second side portion, and a fourth side portion below the first side portion, wherein the first support pattern contacts the first side portion of the lower electrode, wherein the second support pattern contacts the second side portion of the lower electrode, wherein the dielectric layer contacts the third side portion of the lower electrode, wherein the second insulating layer contacts the fourth side portion of the lower electrode, wherein the metal dopant includes a material different from the lower electrode, and wherein the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in at least one of the first side portion, the second side portion, and the fourth side portion of the lower electrode.

20. The semiconductor device according to claim 19, wherein: Each of the lower electrode and the upper electrode includes titanium nitride, The metal dopant includes niobium, and The dielectric layer includes hafnium oxide, aluminum oxide, and zirconium oxide.

Images