Semiconductor device

Abstract

The invention provides a semiconductor device which is applied to the technical field of semiconductors. According to the semiconductor device and the manufacturing method thereof, the semiconductor device can comprise a plurality of dummy bit lines with different widths and intervals in the horizontal direction, so that the purposes of providing a new structure and improving the reliability and the performance of the semiconductor device are achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device. Background Art

[0002] Dynamic random access memory (DRAM) is a volatile memory, which includes an array area composed of multiple memory cells and a peripheral area composed of control circuits. Each memory cell includes a transistor electrically connected to a capacitor, and the transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can locate to each memory cell to control its data access through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. Summary of the Invention

[0003] The purpose of the present invention is to provide a semiconductor device to improve the reliability and performance of the semiconductor device.

[0004] To solve the above technical problems, a semiconductor device is provided in the first embodiment of the present invention, including: a substrate;

[0005] Multiple shallow trench isolations are disposed in the substrate separately from each other, and the shallow trench isolations define multiple active regions, including multiple first active regions with a first width and at least one second active region with a second width. The at least one second active region is disposed outside all the first active regions, and the first width is less than the second width;

[0006] An insulating layer is located on the substrate and the shallow trench isolations;

[0007] Multiple bit lines are disposed on the substrate separately from each other in the horizontal direction;

[0008] Multiple dummy bit lines are located outside the multiple bit lines. The multiple dummy bit lines at least include a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other in the horizontal direction and arranged in sequence, and the bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer;

[0009] Among them, the first dummy bit line is located on the second active region, the second dummy bit line and the third dummy bit line are located on the first active region, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

[0010] Optionally, the width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction.

[0011] Optionally, the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

[0012] Optionally, the first interval between the first dummy bit line and the second dummy bit line is less than the second interval between the second dummy bit line and the third dummy bit line.

[0013] Optionally, the semiconductor device may further include:

[0014] A plurality of contact structures, between adjacent bit lines, and the bottommost surface of the contact structure is lower than the substrate.

[0015] Optionally, the contact structure may also be located between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line.

[0016] Optionally, the semiconductor device may further include:

[0017] At least one insulating structure, between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line, and the bottommost surface of the insulating structure is in direct contact with the insulating layer.

[0018] Optionally, the semiconductor device may further include:

[0019] A plurality of connection pad structures, located on the contact structure or the insulating structure.

[0020] Optionally, the semiconductor device may further include:

[0021] A plurality of bit line sidewall structures, located on both sidewalls of the plurality of bit lines, the second dummy bit line, and the third dummy bit line and on the sidewall of the first dummy bit line close to the bit line, and the bit line sidewall structure has a first thickness.

[0022] Optionally, the semiconductor device may further include:

[0023] A gate structure, located on the substrate;

[0024] The gate spacer is located on the top surface and the sidewalls of the gate structure and has a second thickness, and the first thickness is less than the second thickness.

[0025] Optionally, the gate spacer may further extend to cover the sidewall of the first dummy bit line away from the bit line.

[0026] Optionally, the semiconductor device may further include:

[0027] A plurality of isolation structures are located between the connection pad structures, and the depth of the isolation structure in contact with the contact structure is greater than the depth of the isolation structure in contact with the insulating structure.

[0028] To solve the above technical problems, a semiconductor device is provided in the second embodiment of the present invention, including: a substrate;

[0029] A plurality of shallow trench isolations are disposed in the substrate separately from each other, and the shallow trench isolations define a plurality of active regions;

[0030] An insulating layer is located on the substrate and the shallow trench isolations;

[0031] A plurality of bit lines are disposed on the substrate separately from each other in the horizontal direction;

[0032] A plurality of dummy bit lines are located outside the plurality of bit lines. The plurality of dummy bit lines at least include a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other and arranged in sequence along the horizontal direction. The first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, the third dummy bit line is directly adjacent to the bit line, and the first dummy bit line spans at least two of the active regions;

[0033] A bit line sidewall structure is located on the two sidewalls of the plurality of bit lines, the second dummy bit line, and the third dummy bit line, and on the sidewall of the first dummy bit line close to the bit line. The bottom of the part of the bit line sidewall structure on the sidewall of the dummy bit line is higher than the top of the substrate and is located on the insulating layer.

[0034] Optionally, the width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction.

[0035] Optionally, the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

[0036] Optionally, the bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer.

[0037] Optionally, a first spacing between the first dummy bit line and the second dummy bit line is less than a second spacing between the second dummy bit line and the third dummy bit line.

[0038] To solve the above technical problems, a semiconductor device is provided in a third embodiment of the present invention, including: a substrate;

[0039] An insulating layer;

[0040] A bit line group including a plurality of first bit lines and second bit lines arranged alternately, bottoms of the plurality of first bit lines being lower than the substrate, and bottoms of the plurality of second bit lines being higher than the substrate and contacting the insulating layer;

[0041] A plurality of dummy bit lines located outside the bit line group, the plurality of dummy bit lines at least including a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other in the horizontal direction and arranged in sequence, and bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line being in direct contact with the insulating layer;

[0042] Wherein, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

[0043] Optionally, a width of the first dummy bit line in the horizontal direction is greater than a width of the second dummy bit line in the horizontal direction, and a width of the second dummy bit line in the horizontal direction is greater than a width of the third dummy bit line in the horizontal direction.

[0044] Optionally, a first spacing between the first dummy bit line and the second dummy bit line is less than a second spacing between the second dummy bit line and the third dummy bit line.

[0045] In the present invention, a semiconductor device includes a plurality of bit lines and a plurality of dummy bit lines, wherein the plurality of dummy bit lines are located outside the plurality of bit lines, and the first dummy bit line, the second dummy bit line, and the third dummy bit line have different widths and spacings in the horizontal direction, so as to provide a new structure of the semiconductor device and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figures 1 to 9 It is a schematic structural diagram during the manufacturing process of a manufacturing method of a semiconductor device provided in an embodiment of the present invention; wherein,

[0047] Figure 5 It is a schematic structural diagram of a semiconductor device provided in a first embodiment of the present invention;

[0048] Figure 6 Schematic structural diagram of the semiconductor device provided in the second embodiment of the present invention;

[0049] Figure 7 Schematic structural diagram of the semiconductor device provided in the third embodiment of the present invention;

[0050] Figure 8 is Figure 9 Partial cross-sectional view of the semiconductor device corresponding to the tangent line BB' in

[0051] Figure 9 is Figure 5 Top view of the semiconductor device shown in

[0052] Among them, the reference numerals are:

[0053] 100 - Substrate, 100A - Storage area, 100B - Peripheral area, 101 - Shallow trench isolation, AR - Active region, AR1 - First active region, AR2 - Second active region, D1 - First width, D2 - Second width, 110 - Insulating layer, 120 - Bit line material layer, 121 - Semiconductor layer, 122 - Barrier layer, 123 - Metal layer, 124 - Capping layer, 121a - Bit line contact, 251 - Gate structure, 131 - Gate spacer, 140 - Barrier layer, 151 - Third mask layer, 152 - First mask layer, 153 - Second mask layer, 153a~153f - Mask patterns, 160 - Photoresist layer, H1 - First interval, H2 - Second interval, H3 - Third interval, H4 - Fourth interval, H5 - Fifth interval, BL1 - Bit line, BL2 - dummy bit line, BL2a - First dummy bit line, BL2b - Second dummy bit line, BL2c - Third dummy bit line, W1 - Width of the first dummy bit line in the horizontal direction, W2 - Width of the second dummy bit line in the horizontal direction, W3 - Width of the third dummy bit line in the horizontal direction, 170 - Bit line sidewall structure, 180 - Contact structure, 190 - Silicide layer, 201 - Connection pad structure, 202 - Insulating structure, 210 - Isolation structure, WL - Word line structure. Detailed implementation manners

[0054] The semiconductor device proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. Many specific details are set forth in the following description in order to provide a thorough understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, so the present invention is not limited by the specific embodiments disclosed below.

[0055] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead of..." in the present invention should be interpreted in the broadest manner, so that "on..." not only means "on" something without any intermediate features or layers (i.e., directly on something), but also includes the meaning of having intermediate features or layers on something. In the embodiments of the present invention, terms such as "first", "second", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence. Moreover, the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0056] Please refer to Figure 5 and in combination with Figure 8 and Figure 9 , where Figure 9 is Figure 5 the top view of the semiconductor device shown, Figure 8 is the partial cross-sectional view of the semiconductor device corresponding to the tangent line BB' in Figure 9 of the first embodiment of the present invention, Figure 5 is the partial cross-sectional view of the semiconductor device corresponding to the tangent line AA' in Figure 9 of the first embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture a dynamic random access memory (DRAM). Without departing from the spirit of the present invention, the present invention can also be applied to other types of memories.

[0057] As Figure 5 shown, the semiconductor device in the first embodiment of the present invention includes a substrate 100, a plurality of bit lines BL1, and a plurality of dummy bit lines BL2. Specifically, the substrate 100 may include a storage area 100A and a peripheral area 100B. The storage area 100A is, for example, a storage area (cell region) including semiconductor devices with relatively high component integration density, and the peripheral area 100B is, for example, a peripheral area (periphery region) including semiconductor devices with relatively low component integration density. The storage area 100A and the peripheral area 100B are, for example, arranged adjacent to each other. However, in order to clearly show the structures of the corresponding components in different areas (the storage area 100A and the peripheral area 100B) in the embodiments of the present invention, in the embodiments of the present invention Figures 1 to 7The storage area 100A and the peripheral area 100B and their corresponding structures are respectively drawn, and due to their tangent positions, the word line structure WL cannot be shown. Moreover, a plurality of shallow trench isolations (STIs) 110 are provided in the storage area 100A and the peripheral area 100B of the substrate 100 to define a plurality of active areas AR (active areas, AAs) in the substrate 100. Among them, the active area AR can be specifically divided into a plurality of first active areas AR1 and at least one second active area AR2 based on the width in the direction parallel to the surface of the substrate 100 (hereinafter simply referred to as the horizontal direction), and the second active area AR2 can be arranged outside all the first active areas AR1. For example Figure 5 the plurality of first active areas AR1 and a second active area AR2 shown can be arranged in sequence from left to right; if the width of the first active area AR1 in the horizontal direction is defined as the first width D1 and the width of the second active area AR2 in the horizontal direction is defined as the second width D2, then the first width D1 of the first active area AR1 can be less than the second width D2 of the second active area AR2 (D1 < D2), but this is not limiting

[0058] In one embodiment, the substrate 100 is any suitable substrate material known in the art. For example, it can be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator substrate, or a substrate made of other suitable materials, but not limited thereto. The trench isolation 101 may include a single layer or multiple layers of dielectric materials. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silica glass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or a combination of the above materials, but not limited thereto. Exemplarily, the trench isolation 101 in this embodiment may be strip-shaped and the long axis extends along a direction perpendicular to the surface of the substrate 100 (hereinafter simply referred to as the vertical direction). In addition, an insulating layer 110 is provided on the surface of the substrate 100, and the thickness of the insulating layer 110 in the vertical direction may be different on the storage area 100A and the peripheral area 100B of the substrate 100. For example, the thickness of the insulating layer 110 in the peripheral area 100B is less than the thickness of the insulating layer 110 in the storage area 100A. Specifically, the insulating layer 110 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but not limited thereto.

[0059] Combined with Figure 4 As shown, a plurality of bit lines BL1 in the first embodiment of the present invention may be arranged on the substrate 100 horizontally and separated from each other from left to right, and some of the bit lines BL1 have bit line plugs 121a located below the bit lines BL1 and extending vertically into the substrate 100; and a plurality of dummy bit lines BL2 may be horizontally separated from each other on one side of the plurality of bit lines BL1, for example, located on the right side of the plurality of bit lines BL1 as shown in Figure 4 or Figure 5 As shown; Exemplarily, the plurality of dummy bit lines BL2 may be divided into at least one first dummy bit line BL2a, at least one second dummy bit line BL2b, and at least one third dummy bit line BL2c, where the first dummy bit line BL2a is directly adjacent to the second dummy bit line BL2b, the second dummy bit line BL2b is directly adjacent to the third dummy bit line BL2c, and the third dummy bit line BL2c is directly adjacent to the bit line BL1 to form as shown in Figure 4A plurality of dummy bit lines BL2 arranged in sequence from right to left in the horizontal direction as shown. It should be specifically noted that in the first embodiment of the present invention, the plurality of dummy bit lines BL2 are all located on the insulating layer 110, that is, the bottom of the plurality of dummy bit lines BL2 is in direct contact with the top surface of the insulating layer 110. Specifically, the first dummy bit line BL2a is specifically located on the insulating layer 110 above the second active region AR2, while the second dummy bit line BL2b and the third dummy bit line BL2c are specifically located on the insulating layer 110 above the first active region AR1. Moreover, the widths of the plurality of dummy bit lines BL2 in the horizontal direction and the intervals between adjacent ones can all be different. For example, the width W1 of the first dummy bit line BL2a in the horizontal direction is greater than the widths (W2, W3) of the second dummy bit line BL2b or the third dummy bit line BL2c in the horizontal direction, and the width W2 of the second dummy bit line BL2b in the horizontal direction is greater than the width W3 of the third dummy bit line BL2c in the horizontal direction. The first interval H1 between the first dummy bit line BL2a and the second dummy bit line BL2b is less than the second interval H2 between the second dummy bit line BL2b and the third dummy bit line BL2c, but the second interval H2 between the second dummy bit line BL2b and the third dummy bit line BL2c is equal to the third interval H3 between the third dummy bit line BL2c and the bit line BL1 adjacent to it (the bit line BL1 located on the left side of the third dummy bit line BL2c), that is, 0 < H1 < H2 = H3, but not limited thereto.

[0060] It should be understood that in other embodiments, the bit line BL1 can also be named as a bit line group based on whether a bit line plug 121a is formed below the bit line BL1 or the positional relationship between the bottom surface of the bit line and the substrate 100. And the bit line BL1 with a bottom surface lower than the substrate 100 or with a bit line plug 121a provided below it is named as the first bit line, and the bit line BL1 with a bottom surface higher than the substrate 100 and in contact with the insulating layer 110 or without a bit line plug 121a provided below it is named as the second bit line. For the sake of simplified description, the two will be combined and explained below. For example, a plurality of bit lines BL1 (bit line groups), and the bit line BL1 (bit line group) is simply referred to as the bit line BL1, but not limited thereto.

[0061] In one embodiment, the multiple bit lines BL1 and the multiple dummy bit lines BL2 may have the same multi-layer bit line material layer 120, such as a semiconductor layer 121, a barrier layer 122, a metal layer 123, and a capping layer 124 stacked in sequence from bottom to top. Among them, the material of the semiconductor layer 121 may include crystalline silicon, poly silicon, amorphous silicon, doped silicon, SiGe, or other suitable semiconductor materials, but not limited thereto. The material of the barrier layer 122 may include metals, metal silicides, or metal nitrides, such as Ti, TiN, WSi, CoSi, WN, but not limited thereto. The material of the metal layer 123 may include W, Cu, Al, Ti, Ta, or compounds, alloys, and / or composite layers of the foregoing metal materials, but not limited thereto. The capping layer 124 may include dielectric materials, such as SiO2, SiN, SiON, SiCN, or combinations of the above materials, but not limited thereto. Exemplarily, the material of the semiconductor layer 121 is poly silicon, the material of the barrier layer 122 is CoSi, the material of the metal layer 123 is W, and the material of the capping layer 124 is SiN.

[0062] It should be understood that during the process of forming the multiple bit lines BL1 and the multiple dummy bit lines BL2, at least one gate structure 251 is correspondingly formed on the peripheral region 100B of the substrate 100 synchronously. And since the thickness of the insulating layer 110 in the peripheral region 100B may be less than the thickness of the insulating layer 110 in the storage region 100A, the top surface of the gate structure 251 may also be lower than the top surfaces of the multiple bit lines BL1 and the multiple dummy bit lines BL2 in the storage region 100A, but not limited thereto.

[0063] Continue to refer to Figure 5, sidewall structures can be provided on the sidewalls of the multiple bit lines BL1 and the multiple dummy bit lines BL2 in the first embodiment of the present invention. For the sake of easy distinction, the sidewall structures formed on the two sidewalls of the multiple bit lines BL1, the third dummy bit line BL2c, and the second dummy bit line BL2b, as well as on one sidewall of the first dummy bit line BL2a in the present invention are referred to as bit line sidewall structures 170, while the sidewall structures located on the other sidewall of the first dummy bit line BL2a and on the two sidewalls of the gate structure 251 in the peripheral region 100B are referred to as gate spacer walls 131; in one embodiment, both the bit line sidewall structures 170 and the gate spacer walls 131 can include single-layer or multi-layer insulating materials, such as silicon oxide, silicon nitride, silicon carbonitride, or a combination of the above materials. The thicknesses of the bit line sidewall structures 170 and the gate spacer walls 131 in the horizontal direction can be different. For example, the thickness of the bit line sidewall structures 170 in the horizontal direction is less than the thickness of the gate spacer walls 131 in the horizontal direction, but this is not limiting.

[0064] Furthermore, on the top surfaces of the multiple bit lines BL1 and the multiple dummy bit lines BL2 in the first embodiment of the present invention, on the top surface of the gate structure 251, on the outer surfaces of its gate spacer walls 131, and on the exposed insulating layer 110 on both sides, a barrier layer 140 can also be provided. On the barrier layer 140 (the material is, for example, an oxide) on the top surfaces of the multiple bit lines BL1 and the multiple dummy bit lines BL2, a first mask layer 152 (the material is, for example, a nitride) is further formed. And since the top surface of the gate structure 251 in the peripheral region 100B is lower than the top surfaces of the multiple bit lines BL1 and the multiple dummy bit lines BL2 in the storage region 100A, therefore, the top surfaces of the barrier layer 140 and the first mask layer 152 in the peripheral region 100B are respectively lower than the top surfaces of the barrier layer 140 and the first mask layer 152 in the storage region 100A, but this is not limiting.

[0065] Continue to refer to Figure 5, the semiconductor device in the first embodiment of the present invention further includes a plurality of contact structures 180, wherein the plurality of contact structures 180 can be respectively disposed in the intervals between adjacent bit lines BL1 (the first and second bit lines in the bit line group), between adjacent bit lines BL1 and dummy bit line BL2, and between adjacent dummy bit lines BL2. However, based on the different widths of the different intervals, the widths of the plurality of contact structures 180 in the horizontal direction can be different. For example, the widths of the contact structures 180 between adjacent bit lines BL1 in the horizontal direction can be the same, but the width of the contact structure 180 between adjacent bit line BL1 and the third dummy bit line BL2c in the horizontal direction can be greater than the width of the contact structure 180 between adjacent second dummy bit lines BL2b and the first dummy bit line BL2a in the horizontal direction, and the width of the contact structure 180 between the third dummy bit line BL2c and the second dummy bit line BL2b in the horizontal direction can be equal to the width of the contact structure 180 between adjacent bit line BL1 and the third dummy bit line BL2c in the horizontal direction, but not limited thereto. In one embodiment, both sides of the contact structure 180 are separated from the bit line BL1 and the dummy bit line BL2 by the bit line sidewall structure 170 and do not directly contact, and vertically extend in the substrate 100 between the adjacent bit lines BL1 and the dummy bit line BL2 in a direction perpendicular to the surface of the substrate 100 to be electrically connected to the substrate 100. In one embodiment, the material of the contact structure 180 may include crystalline silicon, poly silicon, amorphous silicon, doped silicon, SiGe, or other suitable silicon-containing semiconductor materials, but not limited thereto. Exemplarily, the material of the contact structure 180 is phosphorus-doped silicon (SiP).

[0066] Further, a silicide layer 190 and a connection pad structure 201 that conformally covers the silicide layer 190, the bit line sidewall structure 170, and the first mask layer 152, and an isolation structure 210 between adjacent connection pad structures 201 can further be provided on the contact structure 180 in this embodiment. In one embodiment, the connection pad structure 201 can be a single-layer structure, for example Figure 5As shown, the material thereof may be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys of the foregoing materials, and / or composite layers at this time, and preferably tungsten (W). It may also be a multi-layer composite structure (not shown). At this time, the material may be a conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) (preferably titanium nitride) and a stacked structure of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys of the foregoing materials, and / or composite layers (preferably tungsten W), but is not limited thereto. The material of the isolation structure 210 may include nitrides, such as silicon nitride, and may also include oxides, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0067] It should be understood that the shapes of some of the plurality of isolation structures 210 in this embodiment may be different. For example, the isolation structure 210 in the connection pad structure 201 between the second dummy bit line BL2b and the first dummy bit line BL2a has a bottom surface higher than that of the isolation structure 210 in the connection pad structure 201 between the adjacent bit lines BL1 or higher than that of the isolation structure 210 in the connection pad structure 201 between several other dummy bit lines BL2 because the width of the gap between the second dummy bit line BL2b and the first dummy bit line BL2a in the horizontal direction is small, but is not limited thereto.

[0068] It should be understood that "conformal" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and relevance in morphology between two or more shapes.

[0069] Those of ordinary skill in the art to which the present invention pertains should easily understand that, on the premise of meeting the requirements of actual products, the semiconductor devices of the present invention may also have other aspects and are not limited to the foregoing. Other embodiments or variations of the semiconductor devices of the present invention will be further described below. And for the sake of simplicity in description, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0070] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of a semiconductor device in the second embodiment of the present invention. As Figure 6As shown, the structure of the semiconductor device in the second embodiment of the present invention is substantially the same as that of the semiconductor device in the foregoing first embodiment. For example, the semiconductor device also includes a substrate 100, a plurality of first active regions AR1, at least one second active region AR2, a plurality of bit lines BL1 (bit line groups), a plurality of dummy bit lines BL2, a bit line sidewall structure 170, a gate structure 251, a gate spacer 131, a barrier layer 140, etc. The same parts will not be described herein again. The main difference between the semiconductor device in the second embodiment of the present invention and the foregoing first embodiment is that: the semiconductor device further includes a plurality of insulating structures 202, and the insulating structures 202 are specifically located in the gaps between the third dummy bit line BL2c and the second dummy bit line BL2b, and between the second dummy bit line BL2b and the first dummy bit line BL2a. That is, the plurality of contact structures 180 in the second embodiment of the present invention are specifically located between the plurality of bit lines BL1 (bit line groups), and between the bit line BL1 and the third dummy bit line BL2c, while there are no contact structures 180 and silicide layers 190 in the gaps between the third dummy bit line BL2c and the second dummy bit line BL2b, and between the second dummy bit line BL2b and the first dummy bit line BL2a. Moreover, part of the isolation structure 210 in the second embodiment of the present invention is also different from the part of the isolation structure 210 in the foregoing first embodiment. For example, in this embodiment, the bottom surfaces of the isolation structures 210 in the gap insulating structures 202 between the third dummy bit line BL2c and the second dummy bit line BL2b, and between the second dummy bit line BL2b and the first dummy bit line BL2a are all higher than the bottom surfaces of the isolation structures 210 in the connection pad structures 201 between the adjacent bit lines BL1. In one embodiment, the material of the insulating structure 202 can be an oxide or a nitride, such as silicon dioxide or silicon nitride, but not limited thereto.

[0071] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of the semiconductor device in the third embodiment of the present invention. As Figure 7As shown, the structure of the semiconductor device in the third embodiment of the present invention is substantially the same as that of the semiconductor device in the foregoing second embodiment. For example, the semiconductor device also includes a substrate 100, the substrate 100 includes a plurality of first active regions AR1 and at least one second active region AR2, a plurality of bit lines BL1 (bit line groups), a plurality of dummy bit lines BL2, a bit line sidewall structure 170, a gate structure 251, a gate spacer 131, a barrier layer 140, a plurality of contact structures 180, a plurality of insulating structures 202, a plurality of isolation structures 210, etc. Among them, no contact structures 180 and silicide layers 190 are provided in the gaps between the third dummy bit line BL2c and the second dummy bit line BL2b, and between the second dummy bit line BL2b and the first dummy bit line BL2a. Instead, insulating structures 202 are provided. The same parts will not be described again here. The main difference between the semiconductor device in the third embodiment of the present invention and the foregoing second embodiment is that the first dummy bit line BL2a among the plurality of dummy bit lines BL2 is specifically located on the insulating layer 110 on the first active region AR1 and the second active region AR2, that is, the first dummy bit line BL2a straddles two active regions.

[0072] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor device in the embodiments of the present invention, the present invention also provides a method for manufacturing a semiconductor device. The following will further describe the method for manufacturing the semiconductor device proposed by the present invention in conjunction with the schematic diagrams of each structure during the manufacturing process.

[0073] Among them, Figures 1 to 5 is a schematic diagram of the structure during the manufacturing process of the method for manufacturing a semiconductor device provided in the first embodiment of the present invention.

[0074] Please refer to Figure 1 and in conjunction with Figure 5 , first provide a substrate 100 (the material is, for example, a silicon substrate). The substrate 100 includes a storage area 100A and a peripheral area 100B. Then, use an etching method to form a plurality of trenches (not shown) in both the storage area 100A and the peripheral area 100B of the substrate 100. Then, fill an insulating material (the material is, for example, silicon oxide or silicon oxynitride, etc.) in the trenches to form a plurality of trench isolations 101 and a plurality of active regions AR defined by the trench isolations 101 in the substrate 100. Exemplarily, the trench isolations 101 can be in the form of long strips extending in the vertical direction, and the plurality of trench isolations 101 can divide the active regions AR into a plurality of first active regions AR1 and at least one second active region AR2; among them, the second active region AR2 can be provided outside all the first active regions AR1, and the first width D1 of the first active region AR1 can be smaller than the second width D2 of the second active region AR2 (D1 < D2), but this is not limited thereto.

[0075] Thereafter, at least one of deposition processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. can be used to form an insulating layer 110 on the surface of the substrate 100. Then, a plurality of bit line plug holes (not shown) are formed in the insulating layer 110 and the substrate 100. The bit line plug holes are the corresponding positions in the substrate 100 where the bit line plugs 121a are formed subsequently. Then, a material layer (the material is, for example, polysilicon) of the bit line plugs 121a can be formed in the bit line plug holes by using the above deposition process. Then, a bit line material layer 120 composed of a semiconductor layer 121 (the material is, for example, polysilicon), a barrier layer 122 (the material is, for example, titanium nitride), a metal layer 123 (the material is, for example, tungsten metal), and a capping layer 124 (the material is, for example, silicon nitride) stacked in sequence from bottom to top is formed on most of the area of the substrate 100 and the material layer of the bit line plugs 121a. A gate spacer 131 (the material is, for example, silicon nitride) is formed on the sidewall of the bit line material layer 120 near the exposed surface of the substrate 100, and a barrier layer 140 (the material is, for example, silicon dioxide) that conformally covers the bit line material layer 120, the gate spacer 131, and the exposed surface of the substrate 100 is formed. It should be understood that the gate structure 251 in the peripheral region 100B of the semiconductor device is formed prior to the plurality of bit lines BL1 (bit line groups) and dummy bit lines BL2 in the storage region 100A. Therefore, Figure 1 the shown gate structure 251 is a discrete structure.

[0076] Please refer to Figure 2 , and in combination with Figure 5, using a deposition process such as chemical vapor deposition, a third mask layer 151 and a first mask layer 152 are sequentially formed on the barrier layer 140 in both the storage area 100A and the peripheral area 100B of the substrate 100. At this time, the top surfaces of the third mask layer 151 and the first mask layer 152 in the peripheral area 100B and the storage area 100A are respectively flush (at the same horizontal height); then, a second mask layer 153 is formed on the first mask layer 152 in the storage area 100A; wherein, the second mask layer 153 includes mask patterns arranged at intervals in the horizontal direction, for example, the first mask pattern 153a to the seventh mask pattern 153g arranged in sequence from right to left in the figure; wherein, the gaps between some adjacent mask patterns in the second mask layer 153 can be the same, for example, the gap between the seventh mask pattern 153g and the sixth mask pattern 153f is the same as the gap between the sixth mask pattern 153f and the fifth mask pattern 153e, while the gaps between some adjacent mask patterns can be different, for example, the gap between the fourth mask pattern 153d and the third mask pattern 153c is different, so as to prepare for forming a plurality of bit lines BL1 (bit line groups) and a plurality of dummy bit lines BL2. In another embodiment (not shown in the figure), the gaps between the first mask pattern 153a to the seventh mask pattern 153g are all the same, but not limited thereto. Exemplarily, if the gap between the fourth mask pattern 153d and the third mask pattern 153c is the sixth gap H6, the gap between the third mask pattern 153c and the second mask pattern 153b is the fifth gap H5, and the gap between the second mask pattern 153b and the adjacent photoresist layer 160 is the fourth gap H4, then H6 > H5 > H4.

[0077] Please refer to Figure 3 , and in combination with Figure 5 , then a photoresist layer 160 is formed on both the peripheral area 100B and the storage area 100A of the substrate 100. Specifically, the photoresist layer 160 covers the top surfaces of the third mask layer 151 in the peripheral area 100B, a part of the first mask layer 152 and a part of the second mask layer 153 in the storage area 100A, and exposes a part of the second mask layer 152 and the third mask layer 151. That is, for the storage area 100A of the substrate 100, the photoresist layer 160 shields the first mask pattern 153a arranged at the rightmost in the horizontal direction and the part of the gap between it and the second mask pattern 153b and the first mask layer 152 on the right side of the first mask pattern 153a in the second mask layer 153, thereby realizing the method of adjusting the gap between the first mask pattern 153a and the second mask pattern 153b through the photoresist layer 160, so as to form the first dummy bit line BL2a, the second dummy bit line BL2b and the third dummy bit line BL2c with different gaps and widths from each other.

[0078] Please refer to Figure 4 , and in combination withFigure 5 Then, taking the multiple mask patterns in the second mask layer 153 as masks, part of the blocking layer 140, part of the bit line material layer 120, part of the insulating layer 110, and part of the substrate 100 are etched away vertically downward to form a plurality of bit lines BL1 (bit line groups) and a plurality of dummy bit lines BL2 that are horizontally separated from each other on the substrate 100. Among them, the plurality of dummy bit lines BL2 can be divided into at least one first dummy bit line BL2a, at least one second dummy bit line BL2b, and at least one third dummy bit line BL2c. The first dummy bit line BL2a is directly adjacent to the second dummy bit line BL2b, the second dummy bit line BL2b is directly adjacent to the third dummy bit line BL2c, and the third dummy bit line BL2c is directly adjacent to the bit line BL1 (the first bit line). It should be understood that during the formation of the plurality of bit lines BL1 (bit line groups) and the plurality of dummy bit lines BL2, at least one gate structure 251 is correspondingly formed on the peripheral region 100B of the substrate 100. Since the thickness of the insulating layer 110 in the peripheral region 100B can be less than the thickness of the insulating layer 110 in the storage region 100A, the top surface of the gate structure 251 is also lower than the top surfaces of the plurality of bit lines BL1 and the plurality of dummy bit lines BL2 in the storage region 100A, but this is not limiting.

[0079] Please refer to Figure 5 Then, using a deposition process, sidewall structures are respectively formed corresponding to the sidewalls of the plurality of bit lines BL1 (bit line groups) and the plurality of dummy bit lines BL2. For example, bit line sidewall structures 170 (the material is, for example, silicon dioxide) are formed on both sidewalls of the plurality of bit lines BL1, the third dummy bit line BL2c, the second dummy bit line BL2b, and on one sidewall of the first dummy bit line BL2a, and gate spacer walls 131 (the material is, for example, silicon dioxide) are formed on one sidewall of the first dummy bit line BL2a and on both sidewalls of the gate structure 251 in the peripheral region 100B; in one embodiment, the thicknesses of the bit line sidewall structures 170 and the gate spacer walls 131 in the horizontal direction can be different. For example, the thickness of the bit line sidewall structures 170 in the horizontal direction is less than the thickness of the gate spacer walls 131 in the horizontal direction, but this is not limiting. Then, further using deposition processes, photolithography, and etching processes, contact structures 180 (the material is, for example, phosphorus-doped silicon), silicide layers 190, connection pad structures 201 (the material is, for example, metal, copper), and isolation structures 210 (the material is, for example, insulating material, silicon nitride) are sequentially formed in the intervals between adjacent bit lines BL1 (the first and second bit lines in the bit line group), between the adjacent bit line BL1 (the first bit line) and the dummy bit line BL2, and between the adjacent dummy bit lines BL2.

[0080] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor devices in the second or third embodiments of the present invention, the present invention also provides a method for manufacturing a semiconductor device. Below, in conjunction with the schematic diagrams of various structures in the manufacturing process of the semiconductor device manufacturing method, the manufacturing method of the semiconductor device proposed by the present invention will be further described.

[0081] Among them, Figures 1 to 4 and Figure 5 or Figure 6 are schematic diagrams of the structures in the manufacturing process of the method for manufacturing a semiconductor device provided in the second or third embodiments of the present invention. Since the semiconductor devices in the second or third embodiments of the present invention are substantially the same as the foregoing first embodiment, the manufacturing methods of their corresponding components and / or devices are also the same. The parts of the manufacturing methods of the second or third embodiments of the present invention that are the same as the foregoing first embodiment will not be described in detail below, and only the different manufacturing processes will be explained.

[0082] Specifically, as Figure 6 shown, in forming the semiconductor device in the second embodiment of the present invention, before forming the contact structure 180, the silicide layer 190, and the connection pad structure 201 in the gaps between adjacent bit lines BL1 and between the bit line BL1 and the third dummy bit line BL2c, an insulating structure 202 made of a material such as silicon dioxide or silicon nitride can be further formed in the gaps between the third dummy bit line BL2c and the second dummy bit line BL2b, and in the gaps between the second dummy bit line BL2b and the first dummy bit line BL2a by a deposition process. In forming the semiconductor device in the third embodiment of the present invention, the step of forming a plurality of trench isolations 101 in the substrate 100 is different from the foregoing first embodiment. Specifically, one more trench isolation 101 can be formed in the substrate 100 so that the subsequently formed first dummy bit line BL2a can straddle two active regions, namely a first active region AR1 and a second active region AR2.

[0083] In summary, the semiconductor device in the present invention includes a plurality of bit lines and a plurality of dummy bit lines, wherein the plurality of dummy bit lines are located outside the plurality of bit lines and have a first dummy bit line, a second dummy bit line, and a third dummy bit line with different widths and intervals in the horizontal direction, so as to propose a new structure of the semiconductor device and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of shallow trench isolations are disposed in the substrate in a mutually separated manner, wherein the shallow trench isolations define a plurality of active regions, including a plurality of first active regions having a first width and at least one second active region having a second width, wherein the at least one second active region is disposed outside all of the first active regions, and the first width is smaller than the second width; an insulating layer, located on the substrate and the shallow trench isolation; A plurality of bit lines are arranged on the substrate and spaced apart from each other in a horizontal direction; A plurality of dummy bit lines, located outside the plurality of bit lines, the plurality of dummy bit lines at least comprising a first dummy bit line, a second dummy bit line and a third dummy bit line, which are separated from each other and arranged in sequence along the horizontal direction, and the bottoms of the first dummy bit line, the second dummy bit line and the third dummy bit line are directly in contact with the insulating layer; Among them, the first dummy bit line is located on the second active area, the second dummy bit line and the third dummy bit line are located on the first active area, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

2. The semiconductor device according to claim 1, wherein A width of the first dummy bit line in the horizontal direction is greater than a width of the second dummy bit line in the horizontal direction.

3. The semiconductor device according to claim 1, wherein A width of the second dummy bit line in the horizontal direction is greater than a width of the third dummy bit line in the horizontal direction.

4. The semiconductor device according to claim 1, wherein A first interval between the first dummy bit line and the second dummy bit line is smaller than a second interval between the second dummy bit line and the third dummy bit line.

5. The semiconductor device according to claim 1, wherein: Also includes: A plurality of contact structures are disposed between adjacent bit lines, and the bottom surfaces of the contact structures are lower than the substrate.

6. The semiconductor device according to claim 5, characterized in that The contact structure is also located between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line.

7. The semiconductor device according to claim 1, wherein: Also includes: At least one insulating structure is disposed between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line, and the bottommost surface of the insulating structure is in direct contact with the insulating layer.

8. The semiconductor device according to claim 7, wherein: Also includes: A plurality of connection pad structures are located on the contact structure or the insulating structure.

9. The semiconductor device according to claim 1, wherein: Also includes: A plurality of bit line sidewall structures are located on both sidewalls of the plurality of bit lines, the second dummy bit line and the third dummy bit line and on a sidewall of the first dummy bit line close to the bit line, and the bit line sidewall structures have a first thickness.

10. The semiconductor device according to claim 1, wherein Also includes: A gate structure, located on the substrate; The gate spacer is located on the top surface and the side wall of the gate structure and has a second thickness, and the first thickness is less than the second thickness.

11. The semiconductor device according to claim 10, wherein: The gate spacer further extends to cover a side wall of the first dummy bit line away from the bit line.

12. The semiconductor device according to claim 8, wherein Also includes: A plurality of isolation structures are located between the connection pad structures, wherein the depth of the isolation structure in contact with the contact structure is greater than the depth of the isolation structure in contact with the insulation structure.

13. A semiconductor device, characterized in that: include: substrate; A plurality of shallow trench isolations are disposed in the substrate in a mutually separated manner, and the shallow trench isolations define a plurality of active areas; an insulating layer, located on the substrate and the shallow trench isolation; A plurality of bit lines are arranged on the substrate and spaced apart from each other in a horizontal direction; a plurality of dummy bit lines, located outside the plurality of bit lines, the plurality of dummy bit lines at least comprising a first dummy bit line, a second dummy bit line and a third dummy bit line which are separated from each other and arranged in sequence along the horizontal direction, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, the third dummy bit line is directly adjacent to the bit line, and the first dummy bit line crosses at least two of the active regions; The bit line sidewall structure is located on both side walls of the plurality of bit lines, the second dummy bit line and the third dummy bit line and on the side wall of the first dummy bit line close to the bit line, and the bottom of the bit line sidewall structure located on the side wall of the dummy bit line is higher than the top of the substrate and is located on the insulating layer.

14. The semiconductor device according to claim 13, wherein: A width of the first dummy bit line in the horizontal direction is greater than a width of the second dummy bit line in the horizontal direction.

15. The semiconductor device according to claim 13, wherein: A width of the second dummy bit line in the horizontal direction is greater than a width of the third dummy bit line in the horizontal direction.

16. The semiconductor device according to claim 13, wherein: Bottom portions of the first dummy bit line, the second dummy bit line, and the third dummy bit line are in direct contact with the insulating layer.

17. The semiconductor device according to claim 13, wherein: A first interval between the first dummy bit line and the second dummy bit line is smaller than a second interval between the second dummy bit line and the third dummy bit line.

18. A semiconductor device, characterized in that: include: substrate; Insulation layer; A bit line group, comprising a plurality of first bit lines and a plurality of second bit lines alternately arranged, wherein the bottom surfaces of the plurality of first bit lines are lower than the substrate, and the bottom surfaces of the plurality of second bit lines are higher than the substrate and contact the insulating layer; A plurality of dummy bit lines are located outside the bit line group, the plurality of dummy bit lines at least comprising a first dummy bit line, a second dummy bit line and a third dummy bit line which are separated from each other and arranged in sequence along the horizontal direction, and the bottoms of the first dummy bit line, the second dummy bit line and the third dummy bit line are directly in contact with the insulating layer; The first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

19. The semiconductor device according to claim 18, wherein: The width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction, and the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

20. The semiconductor device according to claim 18, wherein A first interval between the first dummy bit line and the second dummy bit line is smaller than a second interval between the second dummy bit line and the third dummy bit line.

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