A semiconductor device

Abstract

The application provides a semiconductor device, and belongs to the technical field of semiconductor technology. In the application, the semiconductor device can include a plurality of dummy bit lines with different widths and intervals in a horizontal direction, so as to achieve the purposes of providing a new structure and improving the reliability and performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory that comprises an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell includes a transistor electrically connected to a capacitor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuitry, through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell, can locate each memory cell to control its data access. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device to improve the reliability and performance of semiconductor devices.

[0004] To address the aforementioned technical problems, a semiconductor device is provided in the first embodiment of the present invention, comprising: a substrate;

[0005] Multiple shallow trench isolations are disposed in the substrate in a mutually spaced manner. The shallow trench isolations define multiple active regions, including multiple first active regions having a first width and at least one second active region having a second width. The at least one second active region is disposed outside all the first active regions, and the first width is smaller than the second width.

[0006] An insulating layer is located on the substrate and the shallow trench isolation;

[0007] Multiple bit lines are arranged on the substrate, spaced apart from each other in a horizontal direction;

[0008] Multiple dummy bit lines are located outside the multiple bit lines. The multiple dummy bit lines include at least a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other and arranged sequentially along the horizontal direction. The bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer.

[0009] Wherein, the first dummy bit line is located on the second active region, the second dummy bit line and the third dummy bit line are located on the first active region, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

[0010] Optionally, the width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction.

[0011] Optionally, the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

[0012] Optionally, the first interval between the first dummy bit line and the second dummy bit line is smaller than the second interval between the second dummy bit line and the third dummy bit line.

[0013] Optionally, the semiconductor device may further include:

[0014] Multiple contact structures are located between adjacent bit lines, with the bottom surface of the contact structures being lower than the substrate.

[0015] Optionally, the contact structure may also be located between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line.

[0016] Optionally, the semiconductor device may further include:

[0017] At least one insulating structure is located between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line, with the bottom surface of the insulating structure in direct contact with the insulating layer.

[0018] Optionally, the semiconductor device may further include:

[0019] Multiple connecting pad structures are located on the contact structure or the insulating structure.

[0020] Optionally, the semiconductor device may further include:

[0021] Multiple bitline sidewall structures are located on the sidewalls of the multiple bitlines, the second dummy bitline, and the third dummy bitline, as well as on the sidewall of the first dummy bitline near the bitline, and the bitline sidewall structures have a first thickness.

[0022] Optionally, the semiconductor device may further include:

[0023] A gate structure is located on the substrate;

[0024] The gate spacer wall, located on the top surface and sidewall of the gate structure, has a second thickness, wherein the first thickness is less than the second thickness.

[0025] Optionally, the gate gap wall may also extend to cover the sidewall of the first dummy bit line that is away from the bit line.

[0026] Optionally, the semiconductor device may further include:

[0027] Multiple isolation structures are located between the connecting pad structures, wherein the depth of the isolation structure in contact with the contact structure is greater than the depth of the isolation structure in contact with the insulating structure.

[0028] To address the aforementioned technical problems, a second embodiment of the present invention provides a semiconductor device, comprising: a substrate;

[0029] Multiple shallow trench isolations are disposed in the substrate in a mutually spaced manner, and the shallow trench isolations define multiple active regions;

[0030] An insulating layer is located on the substrate and the shallow trench isolation;

[0031] Multiple bit lines are arranged on the substrate, spaced apart from each other in a horizontal direction;

[0032] Multiple dummy bit lines are located outside the multiple bit lines. The multiple dummy bit lines include at least a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other and arranged sequentially along the horizontal direction. The first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line. The first dummy bit line spans at least two of the active regions.

[0033] Bit line sidewall structures are located on the sidewalls of the plurality of bit lines, the second dummy bit line and the third dummy bit line, and on the sidewall of the first dummy bit line near the bit line, wherein the bottom of the bit line sidewall structure located on the dummy bit line sidewall is higher than the top of the substrate and is located on the insulating layer.

[0034] Optionally, the width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction.

[0035] Optionally, the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

[0036] Optionally, the bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer.

[0037] Optionally, the first interval between the first dummy bit line and the second dummy bit line is smaller than the second interval between the second dummy bit line and the third dummy bit line.

[0038] To address the aforementioned technical problems, a third embodiment of the present invention provides a semiconductor device, comprising: a substrate;

[0039] Insulating layer;

[0040] Bit line group, including multiple first bit lines and second bit lines arranged alternately, the bottom surface of the multiple first bit lines is lower than the substrate, and the bottom surface of the multiple second bit lines is higher than the substrate and contacts the insulating layer;

[0041] Multiple dummy bit lines are located outside the bit line group. The multiple dummy bit lines include at least a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other and arranged sequentially along the horizontal direction. The bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are in direct contact with the insulating layer.

[0042] Wherein, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

[0043] Optionally, the width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction, and the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

[0044] Optionally, the first interval between the first dummy bit line and the second dummy bit line is smaller than the second interval between the second dummy bit line and the third dummy bit line.

[0045] In this invention, the semiconductor device includes a plurality of bit lines and a plurality of dummy bit lines, wherein the plurality of dummy bit lines are located outside the plurality of bit lines and have a first dummy bit line, a second dummy bit line and a third dummy bit line with different widths and spacings in the horizontal direction, so as to propose a new structure for the semiconductor device and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device. Attached Figure Description

[0046] Figures 1-9 This is a schematic diagram of the structure during the fabrication process of a semiconductor device manufacturing method according to an embodiment of the present invention; wherein,

[0047] Figure 5 This is a schematic diagram of the structure of the semiconductor device provided in the first embodiment of the present invention;

[0048] Figure 6 This is a schematic diagram of the structure of the semiconductor device provided in the second embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of the structure of the semiconductor device provided in the third embodiment of the present invention;

[0050] Figure 8 for Figure 9 A partial cross-sectional view of the semiconductor device corresponding to the tangent BB' along the middle;

[0051] Figure 9 for Figure 5 The diagram shows a top view of the semiconductor device.

[0052] The attached figures are labeled as follows:

[0053] 100 - Substrate, 100A - Storage region, 100B - Peripheral region, 101 - Shallow trench isolation, AR - Active region, AR1 - First active region, AR2 - Second active region, D1 - First width, D2 - Second width, 110 - Insulating layer, 120 - Bit line material layer, 121 - Semiconductor layer, 122 - Barrier layer, 123 - Metal layer, 124 - Cap layer, 121a - Bit line contact, 251 - Gate structure, 131 - Gate spacer, 140 - Barrier layer, 151 - Third mask layer, 152 - First mask layer, 153 - Second mask layer, 153a-153f - Mask patterns, 160 - Optical... Resistive layer, H1-first gap, H2-second gap, H3-third gap, H4-fourth gap, H5-fifth gap, BL1-bit line, BL2-dummy bit line, BL2a-first dummy bit line, BL2b-second dummy bit line, BL2c-third dummy bit line, W1-width of the first dummy bit line in the horizontal direction, W2-width of the second dummy bit line in the horizontal direction, W3-width of the third dummy bit line in the horizontal direction, 170-bit line sidewall structure, 180-contact structure, 190-silicide layer, 201-connecting pad structure, 202-insulating structure, 210-isolation structure, WL-word line structure. Detailed Implementation

[0054] The semiconductor device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0055] It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, only used to facilitate and clearly illustrate the purpose of the embodiments of the present invention. It is understood that the meanings of "on," "above," and "over" in this invention should be interpreted in the broadest sense, so that "on" not only means "on" something without any intervening features or layers (i.e., directly on something), but also includes "on" something with intervening features or layers. In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0056] Please refer to Figure 5 and combined Figure 8 and Figure 9 ,in, Figure 9 for Figure 5 The top view of the semiconductor device shown. Figure 8 This is the first embodiment of the present invention. Figure 9 A partial cross-sectional view of the semiconductor device corresponding to the tangent line BB' in the middle. Figure 5 This is the first embodiment of the present invention. Figure 9 A partial cross-sectional view of the semiconductor device corresponding to the tangent line AA'. The semiconductor device of this invention can be used to manufacture dynamic random access memory (DRAM), and without departing from the spirit of this invention, it can also be applied to other types of memory.

[0057] like Figure 5 As shown, the semiconductor device in the first embodiment of the present invention includes a substrate 100, a plurality of bit lines BL1, and a plurality of dummy bit lines BL2. Specifically, the substrate 100 may include a memory region 100A and a peripheral region 100B, wherein the memory region 100A is, for example, a cell region comprising a semiconductor device with a relatively high component density, and the peripheral region 100B is, for example, a peripheral region comprising a semiconductor device with a relatively low component density. The memory region 100A and the peripheral region 100B are, for example, arranged adjacent to each other. However, to clearly illustrate the structure of the corresponding components on different regions (memory region 100A and peripheral region 100B) in the embodiment of the present invention, the structure of the components on different regions (memory region 100A and peripheral region 100B) in the embodiment of the present invention is shown in the figure. Figures 1 to 7Both the memory region 100A and the peripheral region 100B and their corresponding structures are drawn respectively, and the word line structure WL is not reflected due to the tangent position. Moreover, a plurality of shallow trench isolations 110 (shallow trench isolation, STI) are arranged in the memory region 100A and the peripheral region 100B of the substrate 100, so as to define a plurality of active regions AR (active area, AA) on the substrate 100. Wherein, the active regions AR can be specifically divided into a plurality of first active regions AR1 and at least one second active region AR2 based on the width in a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction), and the second active region AR2 can be arranged outside all the first active regions AR1, for example Figure 5 The plurality of first active regions AR1 and one second active region AR2 shown can be arranged sequentially from left to right; if it is set that the width of the first active region AR1 in the horizontal direction is a first width D1, and the width of the second active region AR2 in the horizontal direction is a second width D2, then the first width D1 of the first active region AR1 can be smaller than the second width D2 of the second active region AR2 (D1<D2), but this is not a limitation.

[0058] In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator substrate, or a substrate made of other suitable materials, but not limited thereto. The trench isolation 101 may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorinated silicon glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but not limited thereto. Exemplarily, the trench isolation 101 in this embodiment may be elongated with its long axis extending along a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction). Furthermore, an insulating layer 110 is disposed on the surface of the substrate 100. The insulating layer 110 may have different thicknesses in the vertical direction on the storage region 100A and the peripheral region 100B of the substrate 100. For example, the thickness of the insulating layer 110 on the peripheral region 100B is less than the thickness of the insulating layer 110 on the storage region 100A. Specifically, the insulating layer 110 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or it may be a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but it is not limited thereto.

[0059] Combination Figure 4 As shown, in the first embodiment of the present invention, a plurality of bit lines BL1 are disposed on the substrate 100 in a horizontally spaced manner from left to right, and some bit lines BL1 have bit line plugs 121a located below the bit lines BL1 and extending vertically into the substrate 100; while a plurality of dummy bit lines BL2 are disposed on one side of the plurality of bit lines BL1 in a horizontally spaced manner, for example, located on... Figure 4 or Figure 5 The right side of the plurality of bit lines BL1 shown; exemplarily, the plurality of dummy bit lines BL2 can be divided into at least one first dummy bit line BL2a, at least one second dummy bit line BL2b, and at least one third dummy bit line BL2c, wherein the first dummy bit line BL2a is directly adjacent to the second dummy bit line BL2b, the second dummy bit line BL2b is directly adjacent to the third dummy bit line BL2c, and the third dummy bit line BL2c is directly adjacent to the bit line BL1, to form as shown Figure 4The diagram shows multiple dummy bit lines BL2 arranged horizontally from right to left. It should be noted that in the first embodiment of the present invention, all the dummy bit lines BL2 are located on the insulating layer 110, meaning that the bottom of the multiple dummy bit lines BL2 is in direct contact with the top surface of the insulating layer 110. Specifically, the first dummy bit line BL2a is located on the insulating layer 110 on the second active region AR2, while the second dummy bit line BL2b and the third dummy bit line BL2c are specifically located on the insulating layer 110 on the first active region AR1. Furthermore, the widths of multiple dummy bit lines BL2 in the horizontal direction and the intervals between adjacent lines can be different. For example, the width W1 of the first dummy bit line BL2a in the horizontal direction is greater than the widths (W2, W3) of the second dummy bit line BL2b or the third dummy bit line BL2c in the horizontal direction, while the width W2 of the second dummy bit line BL2b in the horizontal direction is greater than the width W3 of the third dummy bit line BL2c in the horizontal direction. The first interval H1 between the first dummy bit line BL2a and the second dummy bit line BL2b is less than the second interval H2 between the second dummy bit line BL2b and the third dummy bit line BL2c. However, the second interval H2 between the second dummy bit line BL2b and the third dummy bit line BL2c is equal to the third interval H3 between the third dummy bit line BL2c and its adjacent bit line BL1 (the bit line BL1 located to the left of the third dummy bit line BL2c), i.e., 0.

[0060] It should be understood that in other embodiments, the bit line BL1 may be named a bit line group based on whether a bit line plug 121a is formed below the bit line BL1 or the positional relationship between the bottom surface of the bit line and the substrate 100. The bit line BL1 with its bottom surface lower than the substrate 100 or with a bit line plug 121a below it may be named the first bit line, and the bit line BL1 with its bottom surface higher than the substrate 100 and in contact with the insulating layer 110 or without a bit line plug 121a below it may be named the second bit line. For the sake of simplicity, the two will be explained together below. For example, there may be multiple bit lines BL1 (bit line group), and the bit line BL1 (bit line group) may be simply referred to as bit line BL1, but this is not a limitation.

[0061] ​In one embodiment, the plurality of bit lines BL1 and the plurality of dummy bit lines BL2 may have the same multilayer bit line material layer 120, such as a semiconductor layer 121, a barrier layer 122, a metal layer 123, and a capping layer 124 stacked from bottom to top. The semiconductor layer 121 may be made of crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The barrier layer 122 may be made of metal, metal silicide, or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The metal layer 123 may be made of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The capping layer 124 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. For example, the semiconductor layer 121 is made of polycrystalline silicon, the barrier layer 122 is made of cobalt silicide (CoSi), the metal layer 123 is made of tungsten (W), and the capping layer 124 is made of silicon nitride (SiN).

[0062] It should be understood that during the formation of multiple bit lines BL1 and multiple dummy bit lines BL2, at least one gate structure 251 is simultaneously formed on the peripheral region 100B of the substrate 100. Since the thickness of the insulating layer 110 in the peripheral region 100B can be less than the thickness of the insulating layer 110 in the memory region 100A, the top surface of the gate structure 251 can also be lower than the top surface of the multiple bit lines BL1 and multiple dummy bit lines BL2 in the memory region 100A, but this is not a limitation.

[0063] Continue to refer to Figure 5In the first embodiment of the present invention, sidewall structures can also be provided on the sidewalls of the plurality of bit lines BL1 and the plurality of dummy bit lines BL2. For ease of distinction, the sidewall structures formed on both sidewalls of the plurality of bit lines BL1, the third dummy bit line BL2c, the second dummy bit line BL2b, and one sidewall of the first dummy bit line BL2a are referred to as bit line sidewall structures 170, while the sidewall structures located on the other sidewall of the first dummy bit line BL2a and on both sidewalls of the gate structure 251 on the peripheral region 100B are referred to as gate spacers 131. In one embodiment, both the bit line sidewall structures 170 and the gate spacers 131 may include single or multiple layers of insulating material, such as silicon oxide, silicon nitride, silicon carbonitride, or combinations thereof. The thicknesses of the bit line sidewall structures 170 and the gate spacers 131 in the horizontal direction may be different. For example, the thickness of the bit line sidewall structures 170 in the horizontal direction may be less than the thickness of the gate spacers 131 in the horizontal direction, but this is not a limitation.

[0064] Furthermore, in the first embodiment of the present invention, a barrier layer 140 may be provided on the top surface of the plurality of bit lines BL1 and the plurality of dummy bit lines BL2, as well as on the top surface of the gate structure 251 and the outer surface of its gate gap wall 131 and on the exposed insulating layer 110 on both sides. A first mask layer 152 (material for example, nitride) is further formed on the barrier layer 140 (material is, for example, oxide) on the top surface of the plurality of bit lines BL1 and the plurality of dummy bit lines BL2. Since the top surface of the gate structure 251 in the peripheral region 100B is lower than the top surface of the plurality of bit lines BL1 and the plurality of dummy bit lines BL2 in the memory region 100A, the top surfaces of the barrier layer 140 and the first mask layer 152 in the peripheral region 100B are also lower than the top surfaces of the barrier layer 140 and the first mask layer 152 in the memory region 100A, but this is not a limitation.

[0065] Continue to refer to Figure 5The semiconductor device in the first embodiment of the present invention further includes a plurality of contact structures 180, wherein the plurality of contact structures 180 may be respectively disposed in the intervals between adjacent bit lines BL1 (the first bit line and the second bit line in the bit line group), between adjacent bit lines BL1 and dummy bit lines BL2, and between adjacent dummy bit lines BL2. However, based on the different widths of the different intervals, the widths of the plurality of contact structures 180 in the horizontal direction may be different. For example, the widths of the contact structures 180 between adjacent bit lines BL1 may be the same in the horizontal direction, but the width of the contact structure 180 between adjacent bit lines BL1 and the third dummy bit line BL2c in the horizontal direction may be greater than the width of the contact structure 180 between adjacent second dummy bit lines BL2b and the first dummy bit line BL2a in the horizontal direction. The width of the contact structure 180 between the third dummy bit line BL2c and the second dummy bit line BL2b in the horizontal direction may be equal to the width of the contact structure 180 between adjacent bit lines BL1 and the third dummy bit line BL2c in the horizontal direction, but is not limited thereto. In one embodiment, the contact structure 180 is separated from the bit line BL1 and the dummy bit line BL2 by the bit line sidewall structure 170, and does not directly contact them. It extends vertically within the substrate 100 between adjacent bit lines BL1 and dummy bit lines BL2 in a direction perpendicular to the surface of the substrate 100, for electrical connection with the substrate 100. In one embodiment, the material of the contact structure 180 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. For example, the material of the contact structure 180 is phosphorus-doped silicon (SiP).

[0066] Furthermore, in this embodiment, the contact structure 180 may further be provided with a silicide layer 190 and a conformally covered connection pad structure 201 on the silicide layer 190, the bit line sidewall structure 170, and the first mask layer 152, and an isolation structure 210 between adjacent connection pad structures 201. In one embodiment, the connection pad structure 201 may be a single-layer structure, for example... Figure 5As shown, the material can be tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, preferably tungsten (W). It can also be a multilayer composite structure (not shown), in which case the material can be a stacked structure of titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials (preferably titanium nitride) and tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials (preferably tungsten W), but is not limited thereto. The material of the isolation structure 210 may include nitrides, such as silicon nitride, or oxides, such as silicon oxide, preferably silicon nitride, but is not limited thereto.

[0067] It should be understood that the shapes of some of the multiple isolation structures 210 in this embodiment may be different. For example, the isolation structure 210 located in the connecting pad structure 201 between the second dummy bit line BL2b and the first dummy bit line BL2a may have a lower bottom surface than the bottom surface of the isolation structure 210 located in the connecting pad structure 201 between adjacent bit lines BL1, or higher than the bottom surface of the isolation structure 210 in the connecting pad structure 201 between other dummy bit lines BL2, but this is not a limitation.

[0068] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0069] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For the sake of simplicity, identical components in the various embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0070] Please see Figure 6 , Figure 6 This is a schematic diagram of the semiconductor device structure in the second embodiment of the present invention. Figure 6As shown, the structure of the semiconductor device in the second embodiment of the present invention is largely the same as that of the semiconductor device in the first embodiment. For example, the semiconductor device also includes a substrate 100, a plurality of first active regions AR1, at least one second active region AR2, a plurality of bit lines BL1 (bit line group), a plurality of dummy bit lines BL2, a bit line sidewall structure 170, a gate structure 251, a gate spacer 131, a barrier layer 140, etc. The similarities will not be described again here. The main difference between the semiconductor device in the second embodiment of the present invention and the aforementioned first embodiment is that the semiconductor device further includes multiple insulating structures 202, and the insulating structures 202 are specifically located in the gap between the third dummy bit line BL2c and the second dummy bit line BL2b, and in the gap between the second dummy bit line BL2b and the first dummy bit line BL2a. That is, the multiple contact structures 180 in the second embodiment of the present invention are specifically located between multiple bit lines BL1 (bit line groups) and between bit lines BL1 and the third dummy bit line BL2c. The gap between the third dummy bit line BL2c and the second dummy bit line BL2b, and in the gap between the second dummy bit line BL2b and the first dummy bit line BL2a, is not provided with contact structures 180 and silicide layers 190. Furthermore, some of the isolation structures 210 in the second embodiment of the present invention differ from some of the isolation structures 210 in the first embodiment. For example, in this embodiment, the bottom surface of the isolation structures 210 located in the gap insulation structure 202 between the third dummy bit line BL2c and the second dummy bit line BL2b, and between the second dummy bit line BL2b and the first dummy bit line BL2a, is higher than the bottom surface of the isolation structures 210 located in the connecting pad structure 201 between adjacent bit lines BL1. In one embodiment, the material of the insulation structure 202 may be an oxide or a nitride, such as silicon dioxide or silicon nitride, but is not limited thereto.

[0071] Please see Figure 7 , Figure 7 This is a schematic diagram of the semiconductor device in the third embodiment of the present invention. Figure 7As shown in the figure, the structure of the semiconductor device in the third embodiment of the present invention is substantially the same as that of the semiconductor device in the foregoing second embodiment. For example, the semiconductor device also comprises a substrate 100, the substrate 100 comprises a plurality of first active regions AR1, at least one second active region AR2, a plurality of bit lines BL1 (bit line groups), a plurality of dummy bit lines BL2, bit line sidewall structures 170, gate structures 251, gate spacers 131, barrier layers 140, a plurality of contact structures 180, a plurality of insulating structures 202, a plurality of isolation structures 210, etc. Wherein, neither the contact structure 180 nor the silicide layer 190 is disposed in the gap between the third dummy bit line BL2c and the second dummy bit line BL2b, and in the gap between the second dummy bit line BL2b and the first dummy bit line BL2a, instead, the insulating structures 202 are disposed therein, and the similarities will not be repeated here. The main difference between the semiconductor device in the third embodiment of the present invention and the foregoing second embodiment lies in that: the first dummy bit line BL2a among the plurality of dummy bit lines BL2 is specifically located on the insulating layer 110 over the first active region AR1 and the second active region AR2, that is, the first dummy bit line BL2a spans two active regions.

[0072] In order that those skilled in the art to which the present invention pertains can readily understand the semiconductor device in the embodiments of the present invention, the present invention further provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device proposed by the present invention will be further described below with reference to respective structural schematic diagrams during the manufacturing process of the method for manufacturing a semiconductor device.

[0073] Wherein, Figures 1-5 are structural schematic diagrams in the manufacturing process of the method for manufacturing a semiconductor device provided in the first embodiment of the present invention.

[0074] Please refer to Figure 1 and in combination with Figure 5 , firstly, a substrate 100 is provided (the material is, for example, a silicon substrate), the substrate 100 comprises a memory region 100A and a peripheral region 100B, then a plurality of trenches (not shown) are formed in both the memory region 100A and the peripheral region 100B of the substrate 100 by etching, then an insulating material (the material is, for example, silicon oxide or silicon oxynitride, etc.) is filled into the trenches, so as to form a plurality of shallow trench isolations 101 and a plurality of active regions AR defined by the trench isolations 101 in the substrate 100. Illustratively, the trench isolations 101 may be in the shape of long strips extending in a vertical direction, and the plurality of trench isolations 101 may divide the active regions AR into a plurality of first active regions AR1 and at least one second active region AR2; wherein, the second active region AR2 may be disposed outside all the first active regions AR1, and a first width D1 of the first active region AR1 may be smaller than a second width D2 of the second active region AR2 (D1<D2), but the present invention is not limited thereto.

[0075] Then, an insulating layer 110 can be formed on the surface of the substrate 100 using at least one of the deposition processes such as physical vapor deposition, chemical vapor deposition, and atomic layer deposition. Then, a plurality of bit line plug holes (not shown) are formed in the insulating layer 110 and the substrate 100. The bit line plug holes are the corresponding positions of the bit line plugs 121a formed later in the substrate 100. Next, a material layer (material, for example, polysilicon) for bit line plug 121a can be formed in the bit line plug hole using the above deposition process. Then, a bit line material layer 120 consisting of a semiconductor layer 121 (material, for example, polysilicon), a barrier layer 122 (material, for example, titanium nitride), a metal layer 123 (material, for example, tungsten), and a capping layer 124 (material, for example, silicon nitride) stacked sequentially from bottom to top is formed on most of the substrate 100 and on the material layer for bit line plug 121a. A gate spacer 131 (material, for example, silicon nitride) and a barrier layer 140 (material, for example, silicon dioxide) are formed on the sidewall of the bit line material layer 120 near the exposed surface of the substrate 100. It should be understood that the gate structure 251 in the peripheral region 100B of the semiconductor device is formed before the plurality of bit lines BL1 (bit line group) and dummy bit lines BL2 in the memory region 100A. Therefore, Figure 1 The gate structure 251 shown is a discrete structure.

[0076] Please see Figure 2 and combined Figure 5A third mask layer 151 and a first mask layer 152 are sequentially formed on the barrier layer 140 of the storage region 100A and the peripheral region 100B of the substrate 100 using a deposition process such as chemical vapor deposition. At this time, the top surfaces of the third mask layer 151 and the first mask layer 152 in the peripheral region 100B and the storage region 100A are respectively flush (located at the same horizontal height). Then, a second mask layer 153 is formed on the first mask layer 152 of the storage region 100A. The second mask layer 153 includes mask patterns that are spaced apart from each other in the horizontal direction, for example, from right to left in the figure. The first to seventh mask patterns 153a to 153g are arranged in a sequential manner. In the second mask layer 153, the gaps between some adjacent mask patterns may be the same; for example, the gap between the seventh mask pattern 153g and the sixth mask pattern 153f is the same as the gap between the sixth mask pattern 153f and the fifth mask pattern 153e. However, the gaps between some adjacent mask patterns may be different; for example, the gap between the fourth mask pattern 153d and the third mask pattern 153c is different, in preparation for forming multiple bit lines BL1 (bit line groups) and multiple dummy bit lines BL2. In another embodiment (not shown), the gaps between the first to seventh mask patterns 153g are all the same, but this is not a limitation. For example, if the gap between the fourth mask pattern 153d and the third mask pattern 153c is the sixth gap H6, the gap between the third mask pattern 153c and the second mask pattern 153b is the fifth gap H5, and the gap between the second mask pattern 153b and the photoresist layer 160 adjacent to it is the fourth gap H4, then H6>H5>H4.

[0077] Please see Figure 3 and combined Figure 5 Then, photoresist layers 160 are formed on both the peripheral region 100B and the storage region 100A of the substrate 100. Specifically, the photoresist layer 160 covers the top surface of the third mask layer 151 in the peripheral region 100B and a portion of the first mask layer 152 and a portion of the second mask layer 153 in the storage region 100A, and exposes a portion of the second mask layer 152 and the third mask layer 151. That is, for the storage region 100A of the substrate 100, the photoresist layer 160 masks a portion of the gap between the first mask pattern 153a and the second mask pattern 153b located on the rightmost side of the second mask layer 153 along the horizontal direction, as well as the first mask layer 152 located to the right of the first mask pattern 153a. This allows the photoresist layer 160 to adjust the gap between the first mask pattern 153a and the second mask pattern 153b, thereby forming a first dummy bit line BL2a, a second dummy bit line BL2b, and a third dummy bit line BL2c with different gaps and widths.

[0078] Please see Figure 4 and combined Figure 5 Next, using the multiple mask patterns in the second mask layer 153 as masks, a portion of the barrier layer 140, a portion of the bit line material layer 120, a portion of the insulating layer 110, and a portion of the substrate 100 are etched downwards in the vertical direction to form a plurality of bit lines BL1 (bit line groups) and a plurality of dummy bit lines BL2 arranged horizontally and mutually separated on the substrate 100. The plurality of dummy bit lines BL2 can be divided into at least one first dummy bit line BL2a, at least one second dummy bit line BL2b, and at least one third dummy bit line BL2c. The first dummy bit line BL2a is directly adjacent to the second dummy bit line BL2b, the second dummy bit line BL2b is directly adjacent to the third dummy bit line BL2c, and the third dummy bit line BL2c is directly adjacent to the bit line BL1 (the first bit line). It should be understood that during the formation of multiple bit lines BL1 (bit line groups) and multiple dummy bit lines BL2, at least one gate structure 251 is simultaneously formed on the peripheral region 100B of the substrate 100. Since the thickness of the insulating layer 110 in the peripheral region 100B can be less than the thickness of the insulating layer 110 in the memory region 100A, the top surface of the gate structure 251 is also lower than the top surface of the multiple bit lines BL1 and multiple dummy bit lines BL2 in the memory region 100A, but this is not a limitation.

[0079] Please see Figure 5 Next, a deposition process can be used to form corresponding sidewall structures on the sidewalls of multiple bit lines BL1 (bit line groups) and multiple dummy bit lines BL2, respectively. For example, bit line sidewall structures 170 (material, for example, silicon dioxide) are formed on both sidewalls of multiple bit lines BL1, the third dummy bit line BL2c, the second dummy bit line BL2b, and one sidewall of the first dummy bit line BL2a. Gate gap walls 131 (material, for example, silicon dioxide) are formed on one sidewall of the first dummy bit line BL2a and on both sidewalls of the gate structure 251 on the peripheral region 100B. In one embodiment, the thicknesses of the bit line sidewall structures 170 and the gate gap walls 131 in the horizontal direction may be different. For example, the thickness of the bit line sidewall structures 170 in the horizontal direction may be less than the thickness of the gate gap walls 131 in the horizontal direction, but this is not a limitation. Then, by further using deposition, photolithography and etching processes, contact structures 180 (material such as phosphorus-doped silicon), silicide layers 190, connection pad structures 201 (material such as metal, copper) and isolation structures 210 (material such as insulating material, silicon nitride) between adjacent bit lines BL1 (the first bit line and the second bit line in the bit line group) are sequentially formed in the intervals between adjacent bit lines BL1 (the first bit line) and dummy bit lines BL2, and between adjacent dummy bit lines BL2.

[0080] In order to enable those skilled in the art to easily understand the semiconductor device in the second or third embodiment of the present invention, the present invention also provides a method for preparing the semiconductor device. The following will further explain the method for preparing the semiconductor device proposed in the present invention with reference to the various structural schematic diagrams in the preparation process of the semiconductor device.

[0081] in, Figures 1-4 as well as Figure 5 or Figure 6 This is a schematic diagram illustrating the fabrication process of the semiconductor device provided in the second or third embodiment of the present invention. Since the semiconductor device of the second or third embodiment of the present invention is substantially the same as that of the first embodiment described above, the fabrication methods of its corresponding components and / or devices are also the same. Therefore, the parts of the fabrication methods of the second or third embodiment of the present invention that are the same as those of the first embodiment will not be described again below; only the different fabrication processes will be explained.

[0082] Specifically, such as Figure 6 As shown, in forming the semiconductor device in the second embodiment of the present invention, before forming the contact structure 180, silicide layer 190, and connection pad structure 201 in the gaps between adjacent bit lines BL1 and between bit line BL1 and the third dummy bit line BL2c, an insulating structure 202 made of materials such as silicon dioxide or silicon nitride can be further formed in the gaps between the third dummy bit line BL2c and the second dummy bit line BL2b, and in the gaps between the second dummy bit line BL2b and the first dummy bit line BL2a using a deposition process. In forming the semiconductor device in the third embodiment of the present invention, the step of forming multiple trench isolations 101 in the substrate 100 differs from that in the first embodiment. Specifically, an additional trench isolation 101 can be formed in the substrate 100 so that the subsequently formed first dummy bit line BL2a can span two active regions, namely a first active region AR1 and a second active region AR2.

[0083] In summary, the semiconductor device of the present invention includes multiple bit lines and multiple dummy bit lines, wherein the multiple dummy bit lines are located outside the multiple bit lines and have a first dummy bit line, a second dummy bit line, and a third dummy bit line with different widths and spacings in the horizontal direction, so as to propose a new structure for the semiconductor device and simultaneously achieve the purpose of improving the performance and reliability of the semiconductor device.

[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple shallow trench isolations are disposed in the substrate in a mutually spaced manner. The shallow trench isolations define multiple active regions, including multiple first active regions having a first width and at least one second active region having a second width. The at least one second active region is disposed outside all the first active regions, and the first width is smaller than the second width. An insulating layer is located on the substrate and the shallow trench isolation; Multiple bit lines are arranged on the substrate, spaced apart from each other in a horizontal direction; Multiple dummy bit lines are located outside the multiple bit lines. The multiple dummy bit lines include at least a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other and arranged sequentially along the horizontal direction. The bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer. Multiple bit line sidewall structures are located on the sidewalls of the multiple bit lines, the second dummy bit line, and the third dummy bit line, as well as on the sidewall of the first dummy bit line near the bit line, and the bit line sidewall structures have a first thickness; A gate structure is located on the substrate; A gate spacer wall, located on the top surface and sidewalls of the gate structure, has a second thickness, wherein the first thickness is less than the second thickness; Wherein, the first dummy bit line is located on the second active region, the second dummy bit line and the third dummy bit line are located on the first active region, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

2. The semiconductor device as claimed in claim 1, characterized in that, The width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction.

3. The semiconductor device as described in claim 1, characterized in that, The width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

4. The semiconductor device as claimed in claim 1, characterized in that, The first interval between the first dummy bit line and the second dummy bit line is smaller than the second interval between the second dummy bit line and the third dummy bit line.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Multiple contact structures are located between adjacent bit lines, with the bottom surface of the contact structures being lower than the substrate.

6. The semiconductor device as claimed in claim 5, characterized in that, The contact structure is also located between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line.

7. The semiconductor device as claimed in claim 5, characterized in that, Also includes: At least one insulating structure is located between the first dummy bit line and the second dummy bit line and / or between the second dummy bit line and the third dummy bit line, with the bottom surface of the insulating structure in direct contact with the insulating layer.

8. The semiconductor device as claimed in claim 7, characterized in that, Also includes: Multiple connecting pad structures are located on the contact structure or the insulating structure.

9. The semiconductor device as claimed in claim 1, characterized in that, The gate gap wall also extends to cover the sidewall of the first dummy bit line that is away from the bit line.

10. The semiconductor device as claimed in claim 8, characterized in that, Also includes: Multiple isolation structures are located between the connecting pad structures, wherein the depth of the isolation structure in contact with the contact structure is greater than the depth of the isolation structure in contact with the insulating structure.

11. A semiconductor device, characterized in that, include: Substrate; Multiple shallow trench isolations are disposed in the substrate in a mutually spaced manner, and the shallow trench isolations define multiple active regions; An insulating layer is located on the substrate and the shallow trench isolation; Multiple bit lines are arranged on the substrate, spaced apart from each other in a horizontal direction; Multiple dummy bit lines are located outside the multiple bit lines. The multiple dummy bit lines include at least a first dummy bit line, a second dummy bit line, and a third dummy bit line that are separated from each other and arranged sequentially along the horizontal direction. The first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line. The first dummy bit line spans at least two of the active regions. Bit line sidewall structures are located on the sidewalls of the plurality of bit lines, the second dummy bit line and the third dummy bit line, and on the sidewall of the first dummy bit line near the bit line, wherein the bottom of the bit line sidewall structure located on the dummy bit line sidewall is higher than the top of the substrate and is located on the insulating layer.

12. The semiconductor device as claimed in claim 11, characterized in that, The width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction.

13. The semiconductor device as claimed in claim 12, characterized in that, The width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

14. The semiconductor device as claimed in claim 13, characterized in that, The bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer.

15. The semiconductor device as claimed in claim 11, characterized in that, The first interval between the first dummy bit line and the second dummy bit line is smaller than the second interval between the second dummy bit line and the third dummy bit line.

16. A semiconductor device, characterized in that, include: Substrate; Insulating layer; Bit line group, including multiple first bit lines and multiple second bit lines arranged alternately, the bottom surface of the multiple first bit lines is lower than the substrate, and the bottom surface of the multiple second bit lines is higher than the substrate and contacts the insulating layer; Multiple dummy bit lines are located outside the bit line group. The multiple dummy bit lines include at least a first dummy bit line, a second dummy bit line, and a third dummy bit line that are horizontally separated from each other and arranged in sequence. The bottoms of the first dummy bit line, the second dummy bit line, and the third dummy bit line are all in direct contact with the insulating layer. Wherein, the first dummy bit line is directly adjacent to the second dummy bit line, the second dummy bit line is directly adjacent to the third dummy bit line, and the third dummy bit line is directly adjacent to the bit line.

17. The semiconductor device as claimed in claim 16, characterized in that, The width of the first dummy bit line in the horizontal direction is greater than the width of the second dummy bit line in the horizontal direction, and the width of the second dummy bit line in the horizontal direction is greater than the width of the third dummy bit line in the horizontal direction.

18. The semiconductor device as claimed in claim 16, characterized in that, The first interval between the first dummy bit line and the second dummy bit line is smaller than the second interval between the second dummy bit line and the third dummy bit line.

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