Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a storage system and a manufacturing method of the semiconductor device. The semiconductor device comprises a stacking structure, the stacking structure comprises a first stacking structure and a second stacking structure in the stacking direction, the first stacking structure comprises a first step, the second stacking structure comprises a second step, and the first step and the second step comprise a first dielectric layer and a material layer which are stacked mutually; the material layer comprises a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction; the first contact structure extends from the surface, far away from the second stacking structure, of the first stacking structure, penetrates through the second dielectric layer of the first step and is connected with the gate layer of the first step; and the second contact structure extends from the surface, far away from the first stacking structure, of the second stacking structure, penetrates through the second dielectric layer of the second step, and is connected with the gate layer of the second step.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a storage system, and a method for manufacturing a semiconductor device. Background Art

[0002] As the number of stacked layers of three-dimensional memories (e.g., 3D NAND memories) increases, the area occupied by the stepped region in the three-dimensional memory increases, which results in a decrease in the area occupied by the storage region in the three-dimensional memory, thereby reducing the storage density of the three-dimensional memory. Summary of the Invention

[0003] The present application provides a semiconductor device, a storage system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems existing in the related art or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a stacked structure including a first stacked structure and a second stacked structure in its stacking direction, the first stacked structure including a first step, the second stacked structure including a second step, the first step and the second step including a first dielectric layer and a material layer stacked with each other, the material layer including a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction; a first contact structure extending from a surface of the first stacked structure away from the second stacked structure and penetrating the second dielectric layer of the first step to connect to the gate layer of the first step; and a second contact structure extending from a surface of the second stacked structure away from the first stacked structure and penetrating the second dielectric layer of the second step to connect to the gate layer of the second step.

[0005] In some embodiments, the first contact structure includes a first connection portion and a first conductive pillar, the first connection portion penetrating the second dielectric layer of the first step to connect to the gate layer of the first step, the first conductive pillar extending from a surface of the first stacked structure away from the second stacked structure to the first connection portion and connecting to the first connection portion; the second contact structure includes a second connection portion and a second conductive pillar, the second connection portion penetrating the second dielectric layer of the second step to connect to the gate layer of the second step, the second conductive pillar extending from a surface of the second stacked structure away from the first stacked structure to the second connection portion and connecting to the second connection portion.

[0006] In some embodiments, in the stacking direction, the size of the first connection portion or the second connection portion is greater than the size of the second dielectric layer.

[0007] In some embodiments, in the stacking direction, the size of the first connection portion or the second connection portion is less than the sum of the sizes of the second dielectric layer and the first dielectric layer.

[0008] In some embodiments, in the stacking direction, the first contact structure and the second contact structure are at least partially aligned.

[0009] In some embodiments, the surface of the first stacking structure close to the second stacking structure is the first surface; in the stacking direction, the size of the first conductive pillar at a first distance from the first surface is smaller than the size of the first conductive pillar at a second distance from the first surface, and the first distance is greater than the second distance; in the stacking direction, the size of the second conductive pillar at a third distance from the first surface is greater than the size of the second conductive pillar at a fourth distance from the first surface, and the third distance is less than the fourth distance.

[0010] In some embodiments, the semiconductor device further includes: a first gate line slot structure that penetrates the stacking structure and extends in a second direction, and the second direction intersects the first direction and the stacking direction; wherein, the gate layer is located on opposite sides of the first gate line slot structure in the first direction.

[0011] In some embodiments, in the first direction, two sides of the first contact structure are respectively connected to the gate layers located at the sides of two adjacent first gate line slot structures.

[0012] In some embodiments, both the first step and the second step each have at least two partitions in the first direction, and the first step or the second step in two adjacent partitions differ by at least one stack pair, and the stack pair is a structure composed of a first dielectric layer and a material layer.

[0013] In some embodiments, the semiconductor device further includes: a second gate line slot structure that penetrates the stacking structure and extends in the second direction, and is used to divide the first step and the second step into at least two partitions, and the second gate line slot structure is located between two adjacent first gate line slot structures; wherein, the gate layer is also located on opposite sides of the second gate line slot structure in the first direction.

[0014] In some embodiments, in the first direction, one side of the first contact structure or the second contact structure is connected to the gate layer located at the side of the first gate line slot structure, and the other side of the first contact structure or the second contact structure is connected to the gate layer located at the side of the second gate line slot structure.

[0015] In some embodiments, a portion of the gate layer for connecting to the first contact structure or the second contact structure includes a first part and a second part. The second part extends along the stacking direction from one side of the first part in the stacking direction and is connected to the first dielectric layer. The size of the first part in the first direction is smaller than the size of the second part in the first direction. The second part is connected to the first gate line gap structure or the second gate line gap structure. Wherein, the semiconductor device further includes: an oxide layer located between the first part and the first gate line gap structure, or between the first part and the second gate line gap structure; and the sum of the sizes of the oxide layer and the first part in the first direction is equal to the size of the second part in the first direction.

[0016] In some embodiments, the stacking structure has a stepped area and a core area in the second direction. The first step and the second step are both located in the stepped area. The first dielectric layer and the gate layer extend to the core area. The first gate line gap structure extends to the core area. Wherein, the semiconductor device further includes: a plurality of channel structures respectively penetrating through the portions of the first dielectric layer and the gate layer located in the core area.

[0017] In some embodiments, the stacking structure has a peripheral area in the second direction. The semiconductor device further includes: a first peripheral circuit located on a side of the first stacking structure away from the second stacking structure; a second peripheral circuit located on a side of the second stacking structure away from the first stacking structure; and a through-silicon contact structure penetrating through the peripheral area of the stacking structure along the stacking direction and connected to the first peripheral circuit and the second peripheral circuit respectively.

[0018] In a second aspect, some embodiments of the present application provide a storage system. The storage system includes: a semiconductor device as described in any embodiment of the first aspect; and a controller coupled to the semiconductor device.

[0019] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a stacking structure, the stacking structure includes a first stacking structure and a second stacking structure in its stacking direction. The first stacking structure includes a first step, and the second stacking structure includes a second step. The first step and the second step include a first dielectric layer and a material layer stacked with each other. The material layer includes a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction; forming a first contact structure, the first contact structure extends from the surface of the first stacking structure away from the second stacking structure and penetrates through the second dielectric layer of the first step to be connected to the gate layer of the first step; and forming a second contact structure, the second contact structure extends from the surface of the second stacking structure away from the first stacking structure and penetrates through the second dielectric layer of the second step to be connected to the gate layer of the second step.

[0020] In some embodiments, a stacked structure is formed, including: forming an initial stacked structure that includes, in its stacking direction, a first initial stacked structure and a second initial stacked structure, the first initial stacked structure including a first initial step, the second initial stacked structure including a second initial step, the first initial step and the second initial step including a first dielectric layer and a second dielectric layer that are stacked with each other, a first guiding layer being formed on the surface of the first initial step, and a second guiding layer being formed on the surface of the second initial step; removing a part of the second dielectric layer to form a void between the first initial step and the second initial step; and filling the void and forming a gate layer within the void.

[0021] In some embodiments, removing a part of the second dielectric layer to form a void between the first initial step and the second initial step includes: forming a first gate line slit that penetrates the initial stacked structure and extends in a second direction, where the second direction intersects a first direction and the stacking direction; via the first gate line slit, removing the first guiding layer and the second guiding layer; and removing an edge part of the second dielectric layer close to the first gate line slit and parts of the second dielectric layer covered by the first guiding layer and the second guiding layer respectively to form a void.

[0022] In some embodiments, removing a part of the second dielectric layer to form a void between the first initial step and the second initial step includes: forming a first gate line slit that penetrates the initial stacked structure and extends in a second direction, side walls of the first guiding layer and the second guiding layer exposed to the first gate line slit having oxide layers, where the second direction intersects a first direction and the stacking direction; via the first gate line slit, removing a first part of an edge part of the second dielectric layer close to the first gate line slit and exposing the first guiding layer and the second guiding layer, the first part having a dimension in the first direction greater than a dimension of the oxide layer in the first direction; removing the first guiding layer and the second guiding layer; and removing a second part of the edge part of the second dielectric layer close to the first gate line slit and parts of the second dielectric layer covered by the first guiding layer and the second guiding layer respectively to form a void.

[0023] In some embodiments, the void includes a first void and a second void, the first void corresponding to the edge part of the second dielectric layer close to the first gate line slit, and the second void corresponding to parts of the non-edge part of the second dielectric layer covered by the first guiding layer and the second guiding layer respectively; wherein, forming a first contact structure includes: forming a first conductive pillar that extends from a surface of the first stacked structure away from the second stacked structure to a first connection part of the first step, the first connection part being a gate layer filled in the second void of the first step; and wherein, forming a second contact structure includes: forming a second conductive pillar that extends from a surface of the second stacked structure away from the first stacked structure to a second connection part of the second step, the second connection part being a gate layer filled in the second void of the second step.

[0024] In some embodiments, both the first initial step and the second initial step each have at least two partitions in a first direction; the method further includes: forming, between two adjacent partitions, a second gate line gap that penetrates the initial stack structure and extends in a second direction, where the second direction intersects the first direction and the stacking direction; and using the second gate line gap to replace the first guiding layer, the second guiding layer, an edge portion of the second dielectric layer adjacent to the second gate line gap, and portions of the second dielectric layer covered by the first guiding layer and the second guiding layer with a gate layer.

[0025] According to at least one embodiment of the present application, the semiconductor device, storage system, and method for manufacturing a semiconductor device provided by the present application connect the gate layer of the first stack structure from one side in the stacking direction through a first contact structure, and connect the gate layer of the second stack structure from the other side in the stacking direction through a second contact structure, and can use the two contact structures to lead out the gate layers in the two stack structures from opposite sides in the stacking direction respectively, reducing the occupied area of the steps, which is beneficial to reducing the manufacturing cost and improving the economic efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects, and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Among them:

[0027] Figure 1A is a top view schematic diagram of the semiconductor device provided by the embodiment of the present application;

[0028] Figure 1B is along Figure 1A a cross-sectional schematic diagram taken along the line A-A' shown;

[0029] Figure 1C is along Figure 1A a cross-sectional schematic diagram taken along the line B-B' shown;

[0030] Figure 1D and Figure 1E are respectively Figure 1C cross-sectional schematic diagrams taken along the lines D-D' and E-E' shown;

[0031] Figure 1F is a cross-sectional schematic diagram of the core area of the embodiment of the present application taken along the line D-D' and / or E-E';

[0032] Figure 1G is along Figure 1A a cross-sectional schematic diagram taken along the line C-C' shown;

[0033] Figure 1H is Figure 1B an enlarged schematic diagram of region I of

[0034] Figure 2A is a schematic top view of a semiconductor device provided by another embodiment of the present application;

[0035] Figure 2B It is along Figure 2A A schematic cross-sectional view taken along line AA' is shown;

[0036] Figure 2C It is along Figure 2A A schematic cross-sectional view taken along line BB' is shown;

[0037] Figure 2D and Figure 2E Along the Figure 2C Schematic cross-sectional views taken along lines D-D' and EE' are shown;

[0038] Figure 3 is a schematic top view of a semiconductor device provided by another embodiment of the present application;

[0039] Figure 4 is a system block diagram of a storage system provided by an embodiment of the present application;

[0040] Figure 5A and Figure 5B is a schematic diagram of a memory system provided by an embodiment of the present application;

[0041] Figure 6 is a flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application; and

[0042] Figures 7A to 13B It is a schematic diagram of the structure of a semiconductor device during the manufacturing process provided by an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first stacking structure discussed in this application may also be referred to as the second stacking structure, and vice versa.

[0045] In the accompanying drawings, for the sake of clarity, the thickness, dimensions, and shapes of the components have been slightly adjusted. The accompanying drawings are for illustrative purposes only and are not drawn to an exact scale. As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0046] It should also be understood that expressions such as "comprises," "comprising," "has," "including," and / or "including having" are open-ended and not closed-ended expressions in this specification, which means that there are the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application." And the term "exemplary" is intended to refer to an example or illustration.

[0047] Unless otherwise defined, all terms used herein (including engineering and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0048] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments may be combined with each other. In addition, unless clearly defined or in conflict with the context, the specific steps included in the methods described in this application do not have to be limited to the described order, but may be executed in any order or executed in parallel.

[0049] In addition, when using "connected" or "coupled" in this application, it may mean direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0050] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0051] An embodiment of the present application provides a semiconductor device. Figures 1A to 1H is a schematic structural diagram of the semiconductor device provided by the embodiment of the present application. Among them, Figure 1A is a top view schematic diagram of the semiconductor device provided by the embodiment of the present application. Figure 1B is along Figure 1A The cross-sectional schematic diagram taken along the line A-A' shown. Figure 1Cis a schematic cross-sectional view taken along Figure 1A the line B-B’ shown. Figure 1D and Figure 1E are respectively schematic cross-sectional views taken along Figure 1C the lines D-D’ and E-E’ shown. Figure 1F is a schematic cross-sectional view taken along the lines D-D’ and E-E’ of the core area of the embodiment of the present application. Figure 1G is a schematic cross-sectional view taken along Figure 1A the line C-C’ shown. Figure 1H is Figure 1B an enlarged schematic view of region I of. The semiconductor device may be a three-dimensional memory or a part of a three-dimensional memory. For example, the three-dimensional memory may be a 3D NAND memory.

[0052] It should be noted that hereinafter, the first direction is simply referred to as the D1 direction, the second direction is simply referred to as the D2 direction, and the stacking direction is simply referred to as the D3 direction. The D1 direction, D2 direction, and D3 direction in each drawing show the spatial relationship of the components in the semiconductor device. For example, the D3 direction is the stacking direction of the stacking structure, and the D1 direction and D2 direction are two directions that intersect (for example, are perpendicular) to each other on a plane that intersects (for example, is perpendicular) to the stacking direction. In addition, the D1 direction, D2 direction, and D3 direction in each drawing include not only the directions indicated by the arrows, but also the directions away from the arrows. In other words, the arrows in the D1 direction, D2 direction, and D3 direction do not have a limiting meaning. The same concept will be used throughout the present application to describe the spatial relationship of the components in the semiconductor device.

[0053] As Figures 1A to 1CAs shown, the semiconductor device 100 includes a stacked structure 110, and the stacked structure 110 includes a first stacked structure 111 and a second stacked structure 112 in the stacking direction. Both the first stacked structure 111 and the second stacked structure 112 include a plurality of steps (e.g., 121, 122), and each step includes a first dielectric layer (e.g., 1131, 1132) and a material layer (e.g., 1141, 1142) stacked on each other. For example, the first stacked structure 111 may include a plurality of first steps 121, and each first step 121 may include a first dielectric layer 1131 and a material layer 1141 stacked on each other. The second stacked structure 112 may include a plurality of second steps 122, and each second step 122 may include a first dielectric layer 1132 and a material layer 1142 stacked on each other. In the D1 direction, the material layer (e.g., 1141, 1142) may include a second dielectric layer (e.g., 1151, 1152) and a gate layer (e.g., 1161, 1162). For example, the material layer 1141 in the first step 121 may include a second dielectric layer 1151 and a gate layer 1161. The material layer 1142 in the second step 122 may include a second dielectric layer 1152 and a gate layer 1162.

[0054] The material of the first dielectric layer (e.g., 1131, 1132) may include, but is not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials. The material of the second dielectric layer (e.g., 1151, 1152) in the material layer (e.g., 1141, 1142) may include, but is not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials, and is different from the material of the first dielectric layer (e.g., 1131, 1132). For example, the material of the first dielectric layer (e.g., 1131, 1132) may be silicon oxide (SiO 2 ), and the material of the second dielectric layer (e.g., 1151, 1152) may be silicon nitride (Si 3 N 4)。In addition, the material of the gate layer (e.g., 1161, 1162) in the material layer (e.g., 1141, 1142) may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. For example, the material of the gate layer (e.g., 1161, 1162) may be tungsten (W).

[0055] The semiconductor device 100 may further include a plurality of first contact structures 117 and a plurality of second contact structures 118. The first contact structure 117 extends from the surface of the first stacked structure 111 away from the second stacked structure 112 and penetrates the second dielectric layer 1151 of a first step 121, and is connected (e.g., in contact) to the gate layer 1161 of the first step 121. The second contact structure 118 extends from the surface of the second stacked structure 112 away from the first stacked structure 111 and penetrates the second dielectric layer 1152 of a second step 122, and is connected (e.g., in contact) to the gate layer 1162 of the second step 122. The number of the first contact structures 117 is the same as the number of the first steps 121, and the number of the second contact structures 118 is the same as the number of the second steps 122. The materials of the first contact structure 117 and the second contact structure 118 may include, but are not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material.

[0056] According to the semiconductor device provided in the above embodiments of the present application, by connecting the gate layer of the first stacked structure from one side in the vertical direction through the first contact structure, and connecting the gate layer of the second stacked structure from the other side in the vertical direction through the second contact structure, it is possible to lead out the gate layers of the two stacked structures arranged in the vertical direction from the upper and lower directions respectively by using the two contact structures, reduce the occupied area of the steps in the semiconductor device, thereby increasing the occupied area of the storage area of the semiconductor device, which is beneficial to increasing the storage density of the semiconductor device.

[0057] To further illustrate the spatial relationship of the components in the semiconductor device 100, the following will be combined with Figures 1A to 1H to give an example of the semiconductor device 100.

[0058] In some embodiments, such as Figure 1AAs shown, the semiconductor device 100 may include a stepped region 101, a core region 102, and a peripheral region 103. Viewed from the D3 direction, the semiconductor device 100 is divided into a core region 102, a stepped region 101, and a peripheral region 103 along the D2 direction, where the stepped region 101 may be located between the core region 102 and the peripheral region 103. It should be noted that the present application does not specifically limit the specific arrangement form of the core region 102, the stepped region 101, and the peripheral region 103.

[0059] In some embodiments, as Figures 1A to 1C shown, the first stacked structure 111 and the second stacked structure 112 may be located in the stepped region 101. In other words, the first stacked structure 111 and the second stacked structure 112 may extend laterally (e.g., along the D1 direction and / or the D2 direction) within the stepped region 101.

[0060] In some embodiments, as Figure 1C shown, the first stacked structure 111 may have a plurality of first steps 121. In the first stacked structure 111, a first dielectric layer 1131 and a material layer 1141 may form a stacked pair, and the first dielectric layer 1131 and the material layer 1141 in the stacked pair may have the same lateral extension dimension.

[0061] The surface of the first stacked structure 111 close to the second stacked structure 112 is the first surface 1101. For two adjacent stacked pairs, the lateral extension dimension of the upper stacked pair (e.g., the one farther from the first surface 1101 among the two) may be smaller than that of the lower stacked pair (e.g., the one closer to the first surface 1101 among the two). More specifically, for two adjacent stacked pairs, their extension dimensions in the D1 direction are the same, while the extension dimension of the upper stacked pair in the D2 direction is smaller than that of the lower stacked pair in the D2 direction. The two horizontally extending surfaces of two adjacent stacked pairs and the vertically extending surface of the upper stacked pair may form the first step 121, that is, each first step 121 may include a stacked pair.

[0062] The second stacked structure 112 may have a plurality of second steps 122. The structure of the second steps 122 is similar to that of the first steps 121 and will not be described in detail here. The top layers of the first steps 121 and the second steps 122 are both material layers (e.g., 1141 and 1142). In other words, the top surfaces of the first steps 121 and the second steps 122 are the surfaces of the material layers (e.g., 1141 and 1142).

[0063] It should be noted that the present application does not specifically limit the sizes and quantities of the first dielectric layers (e.g., 1131, 1132) and the material layers (e.g., 1141, 1142). For example, each of the first dielectric layers (e.g., 1131, 1132) may have the same or different sizes, and each of the material layers (e.g., 1141, 1142) may also have the same or different sizes. Also, for example, the quantities of the first dielectric layer 1131 and the material layer 1141 included in the first stacked structure 111, and the quantities of the first dielectric layer 1132 and the material layer 1142 included in the second stacked structure 112 can be designed according to actual storage requirements. Generally speaking, the more the quantities of the first dielectric layers (e.g., 1131, 1132) and the material layers (e.g., 1141, 1142), the higher the integration degree and the higher the storage density. In addition, the first step 121 and the second step 122 can correspond one by one. The quantity of the first step 121 is the same as that of the second step 122, and when viewed from the D3 direction, the top surface of the first step 121 and the top surface of the second step 122 are at least partially aligned.

[0064] In some embodiments, as Figure 1C shown, the first stacked structure 111 may further include a first insulating structure 123 covering the top sides of the plurality of first steps 121. The second stacked structure 112 may further include a second insulating structure 124 covering the top sides of the plurality of second steps 122. The material of the first insulating structure 123 and / or the second insulating structure 124 may include, but is not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), tetraethyl orthosilicate (TEOS), or one or more of any other suitable insulating materials.

[0065] In some embodiments, as Figure 1A and Figure 1B shown, the semiconductor device 100 may further include a first gate line gap structure 125. The first gate line gap structure 125 may penetrate the stacked structure 110 (e.g., the first stacked structure 111 and the second stacked structure 112) and extend along the D2 direction (e.g., continuously extend). For example, the first gate line gap structure 125 may extend within the core region 102, the step region 101, and the peripheral region 103. The first gate line gap structure 125 may be composed of a single material or a composite material. The material of the first gate line gap structure 125 may include, but is not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y) one or more of polysilicon (poly-Si) or any other suitable material. The stacked structure 110 (e.g., the first stacked structure 111 and the second stacked structure 112) can be located between two adjacent first gate line slot structures 125. Two adjacent first gate line slot structures 125 in the D1 direction can be used to define a region and provide electrical isolation between two adjacent regions.

[0066] As described above, the material layers (e.g., 1141, 1142) can include second dielectric layers (e.g., 1151, 1152) and gate layers (e.g., 1161, 1162). Here, the material layer 1141 in the first stacked structure 111 is taken as an example for illustration. Since the first step 121 is composed of a stack pair, the material layer 1141 of each stack pair is the top layer of the first step 121.

[0067] As Figure 1D and Figure 1E shown, in the material layer 1141, the gate layer 1161 extends from the second dielectric layer 1151 along both sides in the D1 direction and is respectively in contact with the first gate line slot structure 125. In other words, the gate layer 1161 is located on the opposite sides of the first gate line slot structure 125 in the D1 direction. It should be noted that compared with Figure 1D the upper material layer 1141 shown, Figure 1E the second dielectric layer 1151 in the lower material layer 1141 shown has a larger extension dimension in the D2 direction. In addition, the structure of the material layer 1142 is similar to that of the material layer 1141, and will not be elaborated here.

[0068] In some embodiments, as Figures 1C to 1E shown, the first contact structure 117 and the second contact structure 118 can include connecting portions (e.g., 1171, 1181) and conductive posts (e.g., 1172, 1182). For example, the first contact structure 117 can include a first connecting portion 1171 and a first conductive post 1172. The first connecting portion 1171 penetrates the second dielectric layer 1151 of the first step 121 in the D3 direction and is located on one side (e.g., the side away from the core region 102) of the non-penetrated second dielectric layer 1151 in the D2 direction. In the D1 direction, both sides of the first connecting portion 1171 are respectively connected to the gate layer 1161 located on the sides of two adjacent first gate line slot structures 125 ( Figure 1D and Figure 1E)。The first conductive pillar 1172 extends from the surface of the first stacked structure 111 away from the second stacked structure 112 in the D3 direction to the first connection portion 1171 and is connected (e.g., in contact) to the first connection portion 1171. The first connection portion 1171 is exposed on the first step 121, the first insulating structure 123 covers the first connection portion 1171, and the first conductive pillar 1172 extends from the surface of the first insulating structure 123 away from the second stacked structure 112 in the D3 direction to the first connection portion 1171. The dimension of the first connection portion 1171 in the D3 direction may be greater than the dimension of the second dielectric layer 1151 in the D3 direction. Further, the dimension of the first connection portion 1171 in the D3 direction may be less than the sum of the dimensions of the second dielectric layer 1151 and the first dielectric layer 1131 in the D3 direction. It should be noted that a part of the second dielectric layer 1151 close to the first connection portion 1171 may be exposed on the first step 121 so that there is a spacing distance between the first connection portion 1171 on the lower first step 121 and the side surface of the upper first step 121. Viewed from the D3 direction, in two adjacent first steps 121, the projection of the first connection portion 1171 corresponding to the upper first step 121 is located within the projection of the second dielectric layer 1151 corresponding to the lower first step 121.

[0069] Similarly, the second contact structure 118 may include a second connection portion 1181 and a second conductive pillar 1182. The second connection portion 1181 penetrates the second dielectric layer 1152 of the second step 122 in the D3 direction and is located on one side (e.g., the side away from the core region 102) of the non-penetrated second dielectric layer 1152 in the D2 direction. In the D1 direction, both sides of the second connection portion 1181 are connected to the gate layer 1162 located at the sides of two adjacent first gate line gap structures 125. The second conductive pillar 1182 extends from the surface of the second stacked structure 112 away from the first stacked structure 111 in the D3 direction to the second connection portion 1181 and is connected (e.g., in contact) to the second connection portion 1181. The second conductive pillar 1182 is also connected (e.g., in contact) to the second dielectric layer 1152 of the material layer below the second step 122 penetrated by the second connection portion 1181. The second connection portion 1181 may be exposed on the second step 122. The dimension of the second connection portion 1181 in the D3 direction may be greater than the dimension of the second dielectric layer 1152 in the D3 direction. Further, the dimension of the second connection portion 1181 in the D3 direction may be less than the sum of the dimensions of the second dielectric layer 1152 and the first dielectric layer 1132 in the D3 direction. It should be noted that a part of the second dielectric layer 1152 close to the second connection portion 1181 is exposed on the second step 122 so that there is a spacing distance between the second connection portion 1181 on the lower second step 122 and the side surface of the upper second step 122.

[0070] In this embodiment, by allowing the first contact structure and the second contact structure to pass through the first step and the second step from the upper and lower directions respectively, the total size of the first contact structure and the second contact structure in the D3 direction can be reduced, the formation difficulty of the first contact structure and the second contact structure can be lowered, and at the same time, the occupied area of the steps in the semiconductor device can also be reduced.

[0071] In some embodiments, as Figure 1C shown, the surface of the first stacked structure 111 close to the second stacked structure 112 is the first surface 1101. In the D3 direction, the size of the first conductive pillar 1172 at a first distance from the first surface 1101 is smaller than the size of the first conductive pillar 1172 at a second distance from the first surface 1101, and the first distance is greater than the second distance. In other words, the size of the first conductive pillar 1172 in the D3 direction decreases as the stacking height increases. In the D3 direction, the size of the second conductive pillar 1182 at a third distance from the first surface 1101 is greater than the size of the second conductive pillar 1182 at a fourth distance from the first surface 1101, and the third distance is less than the fourth distance. In other words, the size of the second conductive pillar 1182 in the D3 direction increases as the stacking height increases. The first conductive pillar 1172 and the second conductive pillar 1182 can be generally cylindrical. Additionally, from the D3 direction, the first contact structure 117 and the second contact structure 118 are at least partially aligned.

[0072] In some embodiments, as Figure 1C shown, the first contact structure 117 and the second contact structure 118 may further include insulating layers (e.g., 1173, 1183). For example, the first contact structure 117 may include an insulating layer 1173, and the insulating layer 1173 is sleeved around the first conductive pillar 1172 to provide electrical isolation. The second contact structure 118 may include an insulating layer 1183, and the insulating layer 1183 is sleeved around the second conductive pillar 1182 to provide electrical isolation.

[0073] In some embodiments, as Figure 1H shown, for each step (e.g., 121, 122), the part of the gate layer (e.g., 1161, 1162) for connecting to the first contact structure 117 or the second contact structure 118 may include a first portion 1163 and a second portion 1164. The first portion 1163 is connected to the first insulating structure 123 or the second contact structure 124 at one side in the D3 direction. The second portion 1164 extends along the D3 direction from one side of the first portion 1163 in the D3 direction and is connected to the first dielectric layer (e.g., 1131, 1132). The extension dimension of the first portion 1163 in the D1 direction may be smaller than the extension dimension of the second portion 1164 in the D1 direction. In the D1 direction, the second portion 1164 is connected to the first gate line gap structure 125.

[0074] The semiconductor device 100 may further include an oxide layer 155 located between the first part 1163 and the first gate line gap structure 125. The material of the oxide layer 155 may be silicon oxide (SiO 2 ). The two side portions of the oxide layer 155 in the D1 direction are respectively in contact with the first part 1163 and the first gate line gap structure 125. One side portion of the oxide layer 155 in the D3 direction is in contact with the first insulating structure 123 or the second contact structure 124, and the other side portion of the oxide layer 155 in the D3 direction is in contact with the second part 1164. The sum of the extension dimensions of the oxide layer 155 and the first part 1163 in the D1 direction may be equal to the extension dimension of the second part 1164 in the D1 direction. The extension dimension of the oxide layer 155 in the D3 direction may be equal to the extension dimension of the first part 1163 in the D3 direction. In other examples, the semiconductor device 100 may not include the above-mentioned oxide layer 155, that is, the first part 1163 is in contact with the first gate line gap structure 125 in the D1 direction.

[0075] In some embodiments, as Figure 1A 、 Figure 1F and Figure 1G shown, in addition to being located in the step region 101, the first stacked structure 111 and the second stacked structure 112 may also extend to the core region 102. Among them, the first dielectric layer (for example, 1131, 1132) and the gate layer (for example, 1161, 1162) can both extend to the core region 102. The part of the gate layers 1161, 1162 located in the core region 102 may be composed of a composite material (for example, tungsten (W) on the inner side and titanium nitride (TiN) on the outer side).

[0076] In some embodiments, as Figure 1A 、 Figure 1F 、 Figure 1G shown, the semiconductor device 100 may further include a plurality of channel structures 126. The plurality of channel structures 126 may be arranged in an array within the core region 102. For one channel structure 126, it may penetrate through the portions of the first stacked structure 111 and the second stacked structure 112 located in the core region 102, that is, penetrate through the portions of the first dielectric layer (for example, 1131, 1132) and the gate layer (for example, 1161, 1162) located in the core region 102. The channel structure 126 may include a blocking layer, a charge trapping layer, a tunneling layer, and a channel layer arranged in sequence from outside to inside. Among them, the blocking layer, the charge trapping layer, and the tunneling layer may be referred to as functional layers. The materials of the blocking layer, the charge trapping layer, and the tunneling layer may sequentially include silicon oxide (SiO 2 ), silicon nitride (Si 3 O 4 ), and silicon oxide (SiO 2)。The material of the channel layer may include amorphous silicon (α-Si), polycrystalline silicon (poly-Si), or any other suitable semiconductor material.

[0077] The portion of the channel structure 126 surrounded by a gate layer (e.g., 1161, 1162) and a part of the gate layer (e.g., 1161, 1162) constitute a memory cell MC. A plurality of memory cells MC are arranged in series along the extending direction of the channel structure 126 (e.g., D3 direction) to form a memory string and share the channel layer. The remaining part of the gate layer (e.g., 1161, 1162) can serve as a word line connecting a plurality of memory cells MC at the same height in different memory strings. By applying a voltage to the gate layer (e.g., 1161, 1162), the charge in the channel layer can enter the charge trapping layer in the memory cell MC, or the charge in the charge trapping layer can return to the channel layer, so that the memory cell MC is in a programmed state or an erased state (unprogrammed state).

[0078] In some embodiments, as Figure 1A and Figure 1G shown, the semiconductor device 100 may further include a plurality of virtual channel structures 127. For a virtual channel structure 127, it can penetrate the first stacked structure 111 and the second stacked structure 112 in the D3 direction. A part of the virtual channel structures 127 can be disposed on the side of the channel structure 126 close to the first contact structure 117, and another part of the virtual channel structures 127 can be disposed between the first gate line gap structure 125 and the first contact structure 117. The above virtual channel structures 127 do not actually function as memory cells, but play a role in supporting the stacked structure, for example.

[0079] In some embodiments, as Figure 1A and Figure 1C shown, the first insulating structure 123 and the second insulating structure 124 may further extend to the peripheral region 103. The semiconductor device 100 may further include a first peripheral circuit 130, a second peripheral circuit 140, and a through-silicon contact structure 119. The first peripheral circuit 130 may be located on the side of the first stacked structure 111 away from the second stacked structure 112. The second peripheral circuit 140 may be located on the side of the second stacked structure 112 away from the first stacked structure 111. The through-silicon contact structure 119 penetrates the peripheral region 103 of the stacked structure 110 in the D3 direction (e.g., penetrates the portions of the first insulating structure 123 and the second insulating structure 124 located in the peripheral region 103) and is respectively connected to the first peripheral circuit 130 and the second peripheral circuit 140.

[0080] Figures 2A to 2E is a schematic structural diagram of a semiconductor device provided by another embodiment of the present application. Among them, Figure 2AIt is a top view schematic diagram of a semiconductor device provided by another embodiment of the present application. Figure 2B is a cross-sectional schematic diagram taken along Figure 2A the line A-A' shown. Figure 2C is a cross-sectional schematic diagram taken along Figure 2A the line B-B' shown. Figure 2D and Figure 2E are cross-sectional schematic diagrams taken along Figure 2C the lines D-D' and E-E' shown respectively. For the purpose of concise description, the same content as in the previous embodiment will not be elaborated in this embodiment.

[0081] As Figures 2A to 2C shown, the first stacked structure 211 and the second stacked structure 212 have at least two partitions in the D1 direction. Hereinafter, an example is given in which the first stacked structure 211 and the second stacked structure 212 have two partitions 204a and 204b in the D1 direction. It can be understood that the first stacked structure 211 and the second stacked structure 212 may have other numbers of partitions in the D1 direction, and the present application does not make specific limitations thereto. For example, Figure 3 shown, the first stacked structure 211 and the second stacked structure 212 in the semiconductor device shown have three partitions (for example, 204a, 204b, and 204c) in the D1 direction.

[0082] In some embodiments, as Figure 2B and Figure 2C shown, in the first stacked structure 211, a first dielectric layer 2131 and a material layer 2141 can form a stack pair. The first step 221 can include two stack pairs (hereinafter referred to as a group of stack pairs), and the first dielectric layer 2131 and the material layer 2141 in the two stack pairs can have the same extension dimension in the D2 direction.

[0083] The surface of the first stacked structure 211 close to the second stacked structure 212 is the first surface 2101. For two adjacent groups of stack pairs, the extension dimension of the upper group of stack pairs (for example, the group farther from the first surface 2101 among the two) in the D2 direction can be smaller than the extension dimension of the lower group of stack pairs (for example, the group closer to the first surface 2101 among the two) in the D2 direction. The two horizontally extending surfaces and the vertically extending surface in the upper group of stack pairs among the two adjacent groups of stack pairs can form the first step 221. The difference in the number of stack pairs between adjacent first steps 221 is 2, and is equal to the number of partitions.

[0084] Similarly, the second stacked structure 212 may have a plurality of second steps 222. The number of stacked pairs between adjacent second steps 222 is 2, which is equal to the number of partitions. Among them, the top layers of the first step 221 and the second step 222 are both material layers (e.g., 2141 and 2142). In other words, the top surfaces of the first step 221 and the second step 222 are the surfaces of the material layers (e.g., 2141 and 2142).

[0085] Continuing to refer to Figure 2B and Figure 2C , the first steps 221 located in adjacent partitions (e.g., 204a and 204b) differ by one stacked pair. The second steps 222 located in adjacent partitions (e.g., 204a and 204b) also differ by one stacked pair. While the first stacked structure 211 has a plurality of first steps 221 with a gradient descent in the D2 direction (refer to Figure 2C ), the first steps 221 also have a gradient descent in the D1 direction (refer to Figure 2B ). Similarly, the second stacked structure 212 also has a similar structure in different partitions. It should be noted that the first steps 221 and the second steps 222 correspond one by one. The number of the first steps 221 is the same as the number of the second steps 222, and from the D3 direction, the top surface of the first step 221 at least partially overlaps with the top surface of the second step 222.

[0086] In some embodiments, as shown in Figure 2A and Figure 2B , the semiconductor device 200 may further include a second gate line slot structure 228. The second gate line slot structure 228 may penetrate the stacked structure 210 (e.g., the second stacked structure 212 and the first stacked structure 211) and extend in the D2 direction (e.g., continuously extend). The second gate line slot structure 228 may extend within the step region 201. The second gate line slot structure 228 may be used to divide the first steps 221 and the second steps 222 into partitions 204a and 204b in the D1 direction. The second gate line slot structure 228 may be composed of a single material or a composite material. The material of the second gate line slot structure 228 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), polysilicon (poly-Si) or any other suitable material. The second gate line slot structure 228 is located between two adjacent first gate line slot structures 225 to divide the first steps 221 and the second steps 222 between the two adjacent first gate line slot structures 225 into different partitions.

[0087] Taking the material layer 2141 in the first stacking structure 211 as an example, the following is an illustration. The first step 221 is composed of two stacked pairs, and there is a difference of one stacked pair between adjacent partitions (for example, 204a and 204b).

[0088] For the two stacked pairs in the first step 221, the upper material layer 2141 is only located within partition 204a, and it can serve as the top material layer within partition 204a. The gate layer 2161 extends from both sides of the second dielectric layer 2151 along the D1 direction, and one side of the gate layer 2161 is in contact with the first gate line slot structure 225, and the other side is in contact with the second gate line slot structure 228. In other words, the gate layer 2161 is located not only on the opposite sides of the first gate line slot structure 225 in the D1 direction but also on the opposite sides of the second gate line slot structure 228 in the D1 direction.

[0089] The material layer 2141 in the lower stacked pair is located in both partitions 204a and 204b simultaneously. It can serve as the top material layer within partition 204b and as a non-top material layer within partition 204a. In other words, the material layer 2141 in the lower stacked pair can include the material layer 2141a located in partition 204a and the material layer 2141b located in partition 204b. Among them, the material layer 2141a is a non-top material layer within partition 204a, and the material layer 2141b is the top material layer within partition 204b.

[0090] As Figure 2D and Figure 2E shown, in the material layer (for example, 2141a, 2141b), the gate layer (for example, 2161a, 2161b) extends from both sides of the second dielectric layer (for example, 2151a, 2151b) along the D1 direction, and one side of the gate layer (for example, 2161a, 2161b) is in contact with the first gate line slot structure 225, and the other side is in contact with the second gate line slot structure 228. In other words, the gate layer (for example, 2161a, 2161b) is located not only on the opposite sides of the first gate line slot structure 225 in the D1 direction but also on the opposite sides of the second gate line slot structure 228 in the D1 direction. For example, in the material layer 2141a, the gate layer 2161a extends from both sides of the second dielectric layer 2151a along the D1 direction, and one side of the gate layer 2161a is in contact with the first gate line slot structure 225, and the other side is in contact with the second gate line slot structure 228. In the material layer 2141b, the gate layer 2161b extends from both sides of the second dielectric layer 2151b along the D1 direction, and one side of the gate layer 2161b is in contact with the first gate line slot structure 225, and the other side is in contact with the second gate line slot structure 228.

[0091] It should be noted that within the same partition, compared with Figure 2DThe material layers (e.g., 2141a, 2141b) in the upper stack pair shown Figure 2E The second dielectric layer (e.g., 2151a, 2151b) of the material layer (e.g., 2141a, 2141b) in the lower stack pair shown has a greater extension dimension in the D2 direction. And, for the lower material layer 2141 in a stack pair, the second dielectric layer 2151a in partition 204a has a greater extension dimension in the D2 direction than the second dielectric layer 2151b in partition 204b.

[0092] In some embodiments, as Figures 2C to 2E shown, the first contact structure (e.g., 217a, 217b) and the second contact structure (e.g., 218a, 218b) may include connection portions (e.g., 2171a, 2171b, 2181a, 2181b) and conductive posts (e.g., 2172a, 2172b, 2182a, 2182b). For example, the first contact structure 217a may include a first connection portion 2171a and a first conductive post 2172a. The first connection portion 2171a penetrates the upper second dielectric layer 2151 of the first step 221 in the D3 direction and is located on one side of the non-penetrated upper second dielectric layer 2151 along the D2 direction (e.g., the side away from the core area 202). In the D1 direction, one side of the first connection portion 2171a is connected to the gate layer 2161 on the side of the first gate line gap structure 225, and the other side is connected to the gate layer 2161 on the side of the second gate line gap structure 228. The first conductive post 2172a extends from the surface of the first stack structure 211 away from the second stack structure 212 in the D3 direction to the first connection portion 2171a and is connected (e.g., in contact) with the first connection portion 2171a.

[0093] The first contact structure 217b may include a first connection portion 2171b and a first conductive post 2172b. The first connection portion 2171b penetrates the lower second dielectric layer 2151b of the first step 221 in the D3 direction and is located on one side of the non-penetrated lower second dielectric layer 2151b along the D2 direction (e.g., the side away from the core area 202). In the D1 direction, one side of the first connection portion 2171b is connected to the gate layer 2161b on the side of the first gate line gap structure 225, and the other side is connected to the gate layer 2161b on the side of the second gate line gap structure 228. The first conductive post 2172b extends from the surface of the first stack structure 211 away from the second stack structure 212 in the D3 direction to the first connection portion 2171b and is connected (e.g., in contact) with the first connection portion 2171b.

[0094] It should be noted that for the two stacked pairs in the first step 221, within the partition 204a, the upper material layer 2141 serves as the top material layer, while the lower material layer 2141 serves as the non-top material layer. Then, the first connection portion 2171a is only located in the upper material layer 2141 and will not be located in the lower material layer 2141. Therefore, the extension dimension of the second dielectric layer 2151a of the lower material layer 2141a in the D2 direction is greater than the extension dimension of the second dielectric layer 2151b in the D2 direction. Additionally, the extension dimension of the first conductive column 2172a in the D3 direction is less than the extension dimension of the first conductive column 2172b in the D3 direction.

[0095] Similarly, the second contact structure 218a may include a second connection portion 2181a and a second conductive column 2182a. The second connection portion 2181a penetrates the upper second dielectric layer 2152 of the second step 222 in the D3 direction and is located on one side of the non-penetrated upper second dielectric layer 2152 along the D2 direction (e.g., the side away from the core area 202). In the D1 direction, one side of the second connection portion 2181a is connected to the gate layer 2162 on the side of the first gate line slot structure 225, and the other side is connected to the gate layer 2162 on the side of the second gate line slot structure 228. The second conductive column 2182a extends from the surface of the second stacked structure 212 away from the first stacked structure 211 in the D3 direction to the second connection portion 2181a and is connected to (e.g., contacts) the second connection portion 2181a. The second conductive column 2182a is also connected to (e.g., contacts) the second dielectric layer 2152 of the material layer below the second step 222 penetrated by the second connection portion 2181a.

[0096] The second contact structure 218b may include a second connection portion 2181b and a second conductive column 2182b. The second connection portion 2181b penetrates the lower second dielectric layer 2152b of the second step 222 in the D3 direction and is located on one side of the non-penetrated lower second dielectric layer 2152b along the D2 direction (e.g., the side away from the core area 202). In the D1 direction, one side of the second connection portion 2181b is connected to the gate layer 2162b on the side of the first gate line slot structure 225, and the other side is connected to the gate layer 2162b on the side of the second gate line slot structure 228. The second conductive column 2182b extends from the surface of the second stacked structure 212 away from the first stacked structure 211 in the D3 direction to the second connection portion 2181b and is connected to (e.g., contacts) the second connection portion 2181b. The second conductive column 2182b is also connected to (e.g., contacts) the second dielectric layer 2152b of the material layer below the second step 222 penetrated by the second connection portion 2181b.

[0097] It should be noted that for the two stacked pairs in the second step 222, within the partition 204a, the upper material layer 2142 serves as the top material layer, while the lower material layer 2142 serves as the non-top material layer. Then, the second connecting portion 2181a is only located in the upper material layer 2142 and will not be located in the lower material layer 2142. Therefore, the extension dimension of the second dielectric layer 2152a of the lower material layer 2142a in the D2 direction is greater than the extension dimension of the second dielectric layer 2152b in the D2 direction. Additionally, the extension dimension of the second conductive pillar 2182a in the D3 direction is greater than the extension dimension of the second conductive pillar 2182b in the D3 direction.

[0098] In this embodiment, by providing steps in both the D1 direction and the D2 direction for the first stacked structure and the second stacked structure, when the number of stacked layers is the same, the occupied area of the steps in the semiconductor device can be reduced, thereby increasing the storage density of the semiconductor device.

[0099] In some embodiments, for each step (e.g., 221, 222), the part of the gate layer (e.g., 2161, 2162) for connecting to the first contact structure 217 or the second contact structure 218 may include a first part and a second part. The first part is connected to the first insulating structure 223 or the second contact structure 224 at one side in the D3 direction. The second part extends along the D3 direction from one side of the first part in the D3 direction and is connected to the first dielectric layer (e.g., 2131, 2132). The extension dimension of the first part in the D1 direction is smaller than the extension dimension of the second part in the D1 direction. In the D1 direction, the second part is connected to the first gate line gap structure 225 or the second gate line gap structure 228.

[0100] The oxide layer is located between the first part and the first gate line gap structure 225, and between the first part and the second gate line gap structure 228. The material of the oxide layer may be silicon oxide (SiO 2 ). The oxide layer contacts the first part at one side in the D1 direction, and contacts the first gate line gap structure 225 or the second gate line gap structure 228 at the other side in the D1 direction. The oxide layer contacts the first insulating structure 223 or the second contact structure 224 at one side in the D3 direction, and contacts the second part at the other side in the D3 direction. The sum of the extension dimensions of the oxide layer and the first part in the D1 direction is equal to the extension dimension of the second part in the D1 direction. The extension dimension of the oxide layer in the D3 direction is equal to the extension dimension of the first part in the D3 direction. In other examples, the semiconductor device 200 may not include the above-mentioned oxide layer, that is, the first part contacts the first gate line gap structure 225 or the second gate line gap structure 228 in the D1 direction. It should be noted that the structure and positional relationship of the oxide layer in this embodiment can refer to Figure 1H the structure and positional relationship of the oxide layer 155 shown.

[0101] It should be noted that although the above examples illustrate the first stacking structure and the second stacking structure as having a plurality of first steps and a plurality of second steps respectively. However, in some other embodiments, the first stacking structure and the second stacking structure may not have steps, and the present application does not make specific limitations.

[0102] An embodiment of the present application also provides a storage system. Figure 4 FIG. is a system block diagram of a system having a storage system provided by an embodiment of the present application. Figure 5A and Figure 5B FIG. is a schematic diagram of the storage system provided by an embodiment of the present application.

[0103] As Figure 4 shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having a storage system 12 therein). As Figure 4 shown, the system 11 may include a host 18 and a storage system 12, and the storage system 12 has one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of the electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memory 14.

[0104] The three-dimensional memory 14 may include the semiconductor devices described in any embodiment of the present application. For example, Figures 1A to 1H the semiconductor device 100 shown in Figures 2A to 2E or Figure 3The semiconductor device 200 shown. According to some embodiments, the controller 16 is coupled to the 3D memory 14 and the host 18, and is configured to control the 3D memory 14. The controller 16 can manage the data stored in the 3D memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an Embedded Multi-Media-Card (eMMC) used as a data storage device for mobile devices, and enterprise storage arrays, where the mobile devices are such as smart phones, tablets, laptop computers, etc. The controller 16 can be configured to control the operations of the 3D memory 14, such as read, erase, and program operations. The controller 16 can also be configured to manage various functions related to the data stored in or to be stored in the 3D memory 14, and the various functions include but are not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process an Error Correction Code (ECC) related to the data read from or written to the 3D memory 14. Any other suitable functions can also be performed by the controller 16, for example, formatting the 3D memory 14. The controller 16 can communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a High-Speed PCI (PCI-Express, PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0105] The controller 16 and one or more 3D memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the storage system 12 can be implemented and packaged into different types of final electronic products. In as Figure 5AIn one example shown, the controller 16 and the single three-dimensional memory 14 can be integrated into the memory card 22. The memory card 22 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 22 can further include a memory card connector 24 that couples the memory card 22 to a host (e.g., the host 18 in Figure 4 ). In another example shown in Figure 5B , the controller 16 and multiple three-dimensional memories 14 can be integrated into the SSD 26. The SSD 26 can further include an SSD connector 28 that couples the SSD 26 to a host (e.g., the host 18 in Figure 4 ). In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0106] The embodiments of the present application also provide a method for manufacturing a semiconductor device. Figure 6 FIG. is a flowchart of the method for manufacturing a semiconductor device provided by the embodiments of the present application. As shown in Figure 6 , the method 300 for manufacturing a semiconductor device (hereinafter simply referred to as the manufacturing method 300) includes the following steps.

[0107] S310, forming a stacked structure. The stacked structure includes a first stacked structure and a second stacked structure in its stacking direction. The first stacked structure includes a first step, and the second stacked structure includes a second step. The first step and the second step include a first dielectric layer and a material layer that are stacked with each other. The material layer includes a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction.

[0108] S320, forming a first contact structure. The first contact structure extends from the surface of the first stacked structure away from the second stacked structure and penetrates through the second dielectric layer of the first step to connect to the gate layer of the first step.

[0109] S330, forming a second contact structure. The second contact structure extends from the surface of the second stacked structure away from the first stacked structure and penetrates through the second dielectric layer of the second step to connect to the gate layer of the second step.

[0110] According to the manufacturing method 300 of the semiconductor device provided by the embodiments of the present application, the gate layer of the first stacked structure is connected from one side in the vertical direction through the first contact structure, and the gate layer of the second stacked structure is connected from the other side in the vertical direction through the second contact structure. It is possible to lead out the gate layers of the two vertically arranged stacked structures from the upper and lower directions respectively by using the two contact structures, reduce the occupied area of the steps in the semiconductor device, thereby increasing the occupied area of the storage area of the semiconductor device, which is beneficial to increasing the storage density of the semiconductor device.

[0111] Figures 7A to 13B is a schematic structural diagram of the semiconductor device provided by the embodiments of the present application during the manufacturing process. For example, Figures 7A to 13B may be an intermediate structure formed according to Figure 6 the manufacturing method 300 shown, and is used to form a semiconductor device 100 as shown in Figures 1A to 1H the following. The following will be further described in conjunction with Figures 7A to 13B the Figure 6 manufacturing method 300 shown.

[0112] S310, form a stacked structure, the stacked structure includes a first stacked structure and a second stacked structure in its stacking direction, the first stacked structure includes a first step, the second stacked structure includes a second step, the first step and the second step include a first dielectric layer and a material layer stacked with each other, and the material layer includes a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction.

[0113] Specifically, step S310 may include the following steps:

[0114] S311, forming an initial stacked structure, the initial stacked structure includes a first initial stacked structure and a second initial stacked structure in its stacking direction, the first initial stacked structure includes a first initial step, the second initial stacked structure includes a second initial step, the first initial step and the second initial step include a first dielectric layer and a second dielectric layer stacked on each other, a first guiding layer is formed on the surface of the first initial step, and a second guiding layer is formed on the surface of the second initial step.

[0115] S312, removing part of the second dielectric layer to form a void between the first initial step and the second initial step.

[0116] S313, filling the void and forming a gate layer in the void.

[0117] Figure 7A and Figure 7B show a cross-sectional schematic diagram of the intermediate structure 400a after forming the initial stacked structure, the first guiding layer and the second guiding layer. Specifically, Figure 7A is a cross-sectional schematic diagram of the intermediate structure 400a intercepted along the D2 direction in the step area (refer to Figure 1A ). Figure 7B is a cross-sectional schematic diagram of the intermediate structure 400a intercepted along the D1 direction in the step area (refer to Figure 1A ).

[0118] In step S311, as shown in Figure 7A and Figure 7B , a second initial stack structure 412 is formed on one side of the substrate 450. The second initial stack structure 412 includes a first dielectric layer 4132 and a second dielectric layer 4152 stacked opposite to each other. For example, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to alternately form the first dielectric layer 4132 and the second dielectric layer 4152. The material of the first dielectric layer 4132 and the material of the second dielectric layer 4152 may be different from each other, so that the two have different etching selectivity ratios with respect to the same etching material. The material of the first dielectric layer 4132 may include silicon oxide (SiO 2 ), and the material of the second dielectric layer 4152 may include silicon nitride (Si 3 N 4 ). The substrate 450 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP), or the semiconductor substrate may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate, etc. It should be noted that the first dielectric layer 4132 and the second dielectric layer 4152 may extend laterally into the core region (refer to Figure 1A ).

[0119] In some embodiments, a "trim-etch" process is used to etch the second initial stack structure 412 to form a plurality of second initial steps 422. Adjacent second initial steps 422 differ by one first dielectric layer 4132 and one second dielectric layer 4152, and the top layer of the second initial step 422 is the second dielectric layer 4152. Next, a second guiding layer 4221 covering at least a part of the top surface of the plurality of second initial steps 422 is formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the second guiding layer 4221 may include polycrystalline silicon (poly-Si). The thickness of the second guiding layer 4221 may be less than the thickness of the first dielectric layer 4132 located above it.

[0120] In some embodiments, a second insulating structure 424 covering the top sides of the plurality of second steps 422 is formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The surface of the second insulating structure 424 away from the substrate 450 may be substantially flush (for example, the error is within ±10%).

[0121] In some embodiments, a first initial stack structure 411 is formed on a side of the second initial stack structure 412 away from the substrate 450. The first initial stack structure 411 includes a first dielectric layer 4131 and a second dielectric layer 4151 stacked relative to each other. For example, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof is used to alternately form the first dielectric layer 4131 and the second dielectric layer 4151. The first dielectric layers 4131, 4132 may be, for example, of the same material, and the second dielectric layers 4151, 4152 may be, for example, of the same material. It should be noted that the first dielectric layer 4131 and the second dielectric layer 4151 may extend laterally into the core region (refer to Figure 1A ).

[0122] In some embodiments, a "trim-etch" process is used to etch the first initial stack structure 411 to form a plurality of first initial steps 421. Adjacent first initial steps 421 differ by one first dielectric layer 4131 and one second dielectric layer 4151, and the top layer of the first initial step 421 is the second dielectric layer 4151. Next, a first guiding layer 4211 covering at least a part of the top surfaces of the plurality of first initial steps 421 is formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the first guiding layer 4211 may include polycrystalline silicon (poly-Si). The thickness of the first guiding layer 4211 may be less than the thickness of the first dielectric layer 4131 located above it. Additionally, the first initial steps 421 and the second initial steps 422 may correspond one by one. The number of the first initial steps 421 may be the same as the number of the second initial steps 422, and from the D3 direction, at least a part of the top surfaces of the first initial steps 421 and the second initial steps 422 are aligned.

[0123] In some embodiments, a first insulating structure 423 covering the top sides of the plurality of first initial steps 421 is formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The surface of the first insulating structure 423 away from the substrate 450 may be substantially flush (for example, the error is within ±10%).

[0124] Figure 8 The cross-sectional schematic view of the intermediate structure 400b after forming the first gate line gap is shown taken along the D1 direction in the step region (refer to Figure 1A ). Figures 9A to 9D The cross-sectional schematic view of the intermediate structure 400c after forming voids between the first initial steps and the second initial steps is shown. Specifically, Figure 9A it is the cross-sectional schematic view of the intermediate structure 400c taken along the D2 direction in the step region (refer to Figure 1A ). Figure 9B It is Figure 9A the cross-sectional schematic view taken along the line D-D'.

[0125] Figure 9C is Figure 9A A schematic cross-sectional view taken along line E-E' along the line. Figure 9D is for the stepped area (refer to Figure 1A ) A schematic cross-sectional view of the intermediate structure 400c taken along the D1 direction within. Figure 9E is Figure 8 A partial enlarged schematic view of region II of Figures 9F to 9K A schematic view of the structure of region II during the process of forming the void.

[0126] In step S312, as Figure 8 shown, an etching process (e.g., dry etching and / or wet etching) is used to form a first gate line gap 451 that penetrates the initial stack structure and extends in the D2 direction. Specifically, the first gate line gap 451 penetrates the first guiding layer 4211, the first initial stack structure 411, the second guiding layer 4221, and the second initial stack structure 412. The first gate line gap 451 extends into the substrate 450 in the D3 direction and extends into the core region in the D2 direction.

[0127] In some embodiments, as Figures 9A to 9D shown, using the first gate line gap 451, the edge portions of the first guiding layer 4211, the second guiding layer 4221, the second dielectric layer (e.g., 4151, 4152) close to the first gate line gap 451, and the portions of the second dielectric layer (e.g., 4151, 4152) covered by the first guiding layer 4211 and the second guiding layer 4221 respectively are removed to form voids (e.g., 4521, 4522). Specifically, a wet etching process is used, and for example, a high etching selectivity with respect to polysilicon (poly-Si) is selected, while with respect to silicon oxide (SiO 2 ) and silicon nitride (Si 3 N 4)An etchant with a low etching selectivity is used to remove the first guiding layer 4211 and the second guiding layer 4221. Then, a wet etching process is adopted to remove the edge portions of the second dielectric layer (e.g., 4151, 4152) near the first gate line gap 451 and the portions of the second dielectric layer (e.g., 4151, 4152) covered by the first guiding layer 4211 and the second guiding layer 4221 respectively. When removing the edge portions of the second dielectric layer (e.g., 4151, 4152) near the first gate line gap 451, since the first guiding layer 4211 and the second guiding layer 4221 have been removed, the etching solution will fill the regions where the first guiding layer 4211 and the second guiding layer 4221 were originally located, so that the second dielectric layer (e.g., 4151, 4152) originally covered by the first guiding layer 4211 and the second guiding layer 4221 is in contact with the etching solution on both sides and the top surface in the D1 direction, thus having a larger reaction area. Therefore, under the same etching parameters, the portions of the second dielectric layer (e.g., 4151, 4152) covered by the first guiding layer 4211 and the second guiding layer 4221 are both removed.

[0128] In some embodiments, as Figure 9E shown, after the first gate line gap 451 is formed, an oxide layer 455 is formed on the sidewall of the first guiding layer 4211 exposed to the first gate line gap 451. The oxide layer 455 can extend along the D2 direction and has the same extension dimension as the first guiding layer 4211. When the material of the first guiding layer 4211 is polysilicon (poly-Si), the material of the oxide layer 455 can be silicon oxide (SiO 2 ). When the sidewall of the first guiding layer 4211 exposed to the first gate line gap 451 has the oxide layer 455, it is difficult to remove the first guiding layer 4211. Similarly, an oxide layer 455 is also formed on the sidewall of the second guiding layer 4221 exposed to the first gate line gap 451, and it is also difficult to remove the second guiding layer 4221. The edge portion 4153 of the second dielectric layer (e.g., 4151, 4152) near the first gate line gap 451 can include a first portion 4154 and a second portion 4155. The above problems can be solved by the following embodiments of the present application.

[0129] In one example, first, as Figure 9FAs shown, through the first gate line gap 451, using a wet etching process, and by controlling the etching parameters (e.g., etching time and / or etching rate), the first part 4154 of the edge portion of the second dielectric layer 4151 close to the first gate line gap 451 is removed to expose the first guiding layer 4211. The size of the first part 4154 in the D1 direction can be greater than the size of the oxide layer 455 in the D1 direction, so that the bottom surface of the first guiding layer 4211 in the D3 direction is exposed. Similarly, the same method is used to remove the first part 4154 of the edge portion of the second dielectric layer 4152 close to the first gate line gap 451 to expose the second guiding layer 4221.

[0130] Then, as Figure 9G shown, using a wet etching process, the first guiding layer 4211 is removed. When the material of the first guiding layer 4211 is polysilicon (poly-Si), an etchant with a high etching selectivity relative to polysilicon (poly-Si) and a low etching selectivity relative to silicon oxide (SiO 2 ) and silicon nitride (Si 3 N 4 ) can be selected to remove the first guiding layer 4211. Similarly, the same method is used to remove the second guiding layer 4221.

[0131] Finally, as Figure 9H shown, using a wet etching process, the second part 4155 of the edge portion of the second dielectric layer 4151 close to the first gate line gap 451 and the portion of the second dielectric layer 4151 covered by the first guiding layer 4211 are removed to form a void. When removing the second part 4155 of the edge portion of the second dielectric layer 4151 close to the first gate line gap 451, since the first guiding layer 4211 has been removed, the etching solution will fill the original area where the first guiding layer 4211 is located, so that the two sides and the top surface of the second dielectric layer 4151 originally covered by the first guiding layer 4211 are in contact with the etching solution, thus having a larger reaction area. Therefore, under the same etching parameters, the portion of the second dielectric layer 4151 covered by the first guiding layer 4211 is removed. Similarly, the same method is used to remove the second part 4155 of the edge portion of the second dielectric layer 4152 close to the first gate line gap 451 and the portion of the second dielectric layer 4152 covered by the second guiding layer 4221 to form a void.

[0132] In another example, first, as Figure 9I shown, using a wet etching process, the oxide layer 455 at the sidewall of the first guiding layer 4211 is removed. Specifically, when the material of the first guiding layer 4211 is polysilicon (poly-Si), an etchant with a high etching selectivity relative to silicon oxide (SiO 2) having a high etching selectivity and a low etching selectivity with respect to silicon nitride (Si 3 N 4 ) to remove the oxide layer 455 by controlling etching parameters (e.g., etching time and / or etching rate). It should be noted that when the material of the first dielectric layer 4131 is silicon oxide, during the removal of the oxide layer 455, the edge portion of the first dielectric layer 4131 near the first gate line gap 451 will also be removed, and the size of the removed edge portion of the first dielectric layer 4131 near the first gate line gap 451 in the D1 direction is substantially the same as the size of the oxide layer 455 in the D1 direction. Similarly, the same method is used to remove the oxide layer 455 at the sidewall of the second guiding layer 4221.

[0133] Then, as Figure 9J shown, a wet etching process is used to remove the first guiding layer 4211. When the material of the first guiding layer 4211 is polysilicon (poly-Si), an etchant having a high etching selectivity with respect to polysilicon (poly-Si) and a low etching selectivity with respect to silicon oxide (SiO 2 ) and silicon nitride (Si 3 N 4 ) can be selected to remove the first guiding layer 4211. Similarly, the same method is used to remove the second guiding layer 4221.

[0134] Finally, as Figure 9K shown, a wet etching process is used to remove the edge portion 4153 of the second dielectric layer 4151 near the first gate line gap 451 and the portion of the second dielectric layer 4151 covered by the first guiding layer 4211 to form a void. When removing the edge portion 4153 of the second dielectric layer 4151 near the first gate line gap 451, since the first guiding layer 4211 has been removed, the etching solution will fill the region where the first guiding layer 4211 was originally located, making the two sides and the top surface of the second dielectric layer 4151 originally covered by the first guiding layer 4211 in contact with the etching solution, thus having a larger reaction area. Therefore, under the same etching parameters, the portion of the second dielectric layer 4151 covered by the first guiding layer 4211 is removed. Similarly, the same method is used to remove the edge portion 4153 of the second dielectric layer 4152 near the first gate line gap 451 and the portion of the second dielectric layer 4152 covered by the second guiding layer 4221 to form a void.

[0135] In some embodiments, as Figures 9B to 9D 、 Figure 9H and Figure 9KAs shown, the voids (e.g., 4521, 4522) may include a first void and a second void. The first void corresponds to the edge portion of the second dielectric layer (e.g., 4151, 4152) close to the first gate line gap 451, and the second void corresponds to the portion of the non-edge portion of the second dielectric layer (e.g., 4151, 4152) covered by the first guiding layer 4211 and the second guiding layer 4221 respectively. For example, the void 4521 may include a first void 45211 and a second void 45212. The first void 45211 is located at the edge portion of the second dielectric layer 4151 close to the first gate line gap 451, and the second void 45212 is located at the portion of the non-edge portion of the second dielectric layer 4151 covered by the first guiding layer 4211.

[0136] Figure 10A and Figure 10B FIG. shows a cross-sectional schematic diagram of the intermediate structure 400d after forming the gate layer in the void. Specifically, Figure 10A is a cross-sectional schematic diagram of the intermediate structure 400d taken along the D2 direction in the step region (refer to Figure 1A ). Figure 10B is a cross-sectional schematic diagram of the intermediate structure 400d taken along the D1 direction in the step region (refer to Figure 1A ). Figure 10C is a schematic diagram of the structure of region II after forming the gate layer in the void.

[0137] In step S313, as shown in Figure 10A and Figure 10B , a gate layer (e.g., 4161, 4162) is formed in the voids (e.g., 4521, 4522) by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. Specifically, a gate layer (e.g., 4161, 4162) is formed in the first void 45211, and a connection portion (e.g., 4171, 4181) of the subsequent contact structure (e.g., 417, 418) is formed in the second void 45212. In other words, the connection portion (e.g., 4171, 4181) can be formed synchronously with the gate layer (e.g., 4161, 4162), and the two materials can be the same. The material of the gate layer (e.g., 4161, 4162) may include but is not limited to one or more of tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si) or any other suitable conductive material. Among them, the distribution and positional relationship of the gate layer (e.g., 4161, 4162) and the connection portion (e.g., 4171, 4181) have been described in detail above, and will not be elaborated herein. After this step, the first initial stacked structure 411 can be converted into the first stacked structure, and the second initial stacked structure 412 can be converted into the second stacked structure.

[0138] In some embodiments, the manufacturing method 300 may further include a step of forming a first gate line gap structure 425. Specifically, using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, fill the first gate line gap 451 with at least one of materials such as silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), polysilicon (poly-Si), or any other suitable material to form the first gate line gap structure 425. In one example, after forming the first gate line gap structure 425, the two side portions of the oxide layer 455 in the D1 direction are in contact with the first portion 4163 of the gate layer (e.g., 4161, 4162) and the first gate line gap structure 425 respectively ( Figure 10C ). In another example, since the oxide layer 455 has been removed, after forming the first gate line gap structure 425, the first portion 4163 of the gate layer (e.g., 4161, 4162) and the first gate line gap structure 425 are in contact.

[0139] S320, form a first contact structure, the first contact structure extends from the surface of the first stacked structure away from the second stacked structure and penetrates the second dielectric layer of the first step to connect with the gate layer of the first step.

[0140] Figure 11A and Figure 11B show a cross-sectional schematic diagram of the intermediate structure 400e after forming the first contact hole. Specifically, Figure 11A is a cross-sectional schematic diagram of the intermediate structure 400e taken along the D2 direction within the step region (refer to Figure 1A ). Figure 11B is a cross-sectional schematic diagram of the intermediate structure 400e taken along the D1 direction within the step region (refer to Figure 1A ). Figure 12A and Figure 12B show a cross-sectional schematic diagram of the intermediate structure 400f after forming the first conductive pillar within the first contact hole. Specifically, Figure 12A is a cross-sectional schematic diagram of the intermediate structure 400f taken along the D2 direction within the step region (refer to Figure 1A ). Figure 12B is a cross-sectional schematic diagram of the intermediate structure 400f taken along the D1 direction within the step region (refer to Figure 1A ).

[0141] In step S320, as shown in Figure 11A and Figure 11BAs shown, a first contact hole 452 is formed by an etching process method to extend a first connection portion 4171 from a surface of the first stacked structure 411 away from the second stacked structure 412. The first contact hole 452 penetrates through the first insulating structure 423 and can expose the first connection portion 4171. As Figure 12A and Figure 12B shown, after the first contact hole 452 is formed, a first conductive pillar 4172 is formed in the first contact hole 452 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The first conductive pillar 4172 extends from a surface of the first stacked structure 411 away from the second stacked structure 412 to the first connection portion 4171. The material of the first conductive pillar 4172 may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. Among them, the distribution and positional relationship of the first conductive pillar 4172 and the first connection portion 4171 have been described in detail above, and will not be elaborated herein. After this step, a first contact structure 417 is formed. The first contact structure 417 may include a first connection portion 4171 and a first conductive pillar 4172. In addition, the first contact structure 417 may further include an insulating layer 4173 sleeved around the periphery of the first conductive pillar 4172.

[0142] In some embodiments, the first initial stacked structure 411 and the first insulating structure 423 may further extend to the peripheral region, which may be located on a side of the step region away from the core region. The lowermost first dielectric layer 4131 of the first initial stacked structure 411 extends to the peripheral region, and a first guiding layer 4211 is covered on the top surface of the first dielectric layer 4131. The first insulating structure 423 covers the first dielectric layer 4131 and the first guiding layer 4211 in the peripheral region. In the peripheral region, a first through hole 4531 is formed by an etching process method to extend the first guiding layer 4211 from a surface of the first initial insulating structure 423 away from the second stacked structure 412. Further, a first through-silicon contact structure 4191 is formed in the first through hole 4531 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0143] S330, form a second contact structure, the second contact structure extends from the surface of the second stacked structure away from the first stacked structure and penetrates the second dielectric layer of the second step to connect with the gate layer of the second step.

[0144] Figure 13A and Figure 13B shows a cross-sectional schematic diagram of the intermediate structure 400g after the second contact hole is formed. Specifically, Figure 13A is a cross-sectional schematic diagram of the intermediate structure 400g taken along the D2 direction in the step region (refer to Figure 1A ). Figure 13B is a cross-sectional schematic diagram of the intermediate structure 400g taken along the D2 direction in the step region (refer toFigure 1A ) Schematic cross-sectional view of the intermediate structure 400g taken along the D1 direction therein.

[0145] In step S330, as Figure 13A and Figure 13B shown, a second contact hole 454 is formed by an etching process method to extend the second connection portion 4181 from the surface of the second stacked structure 412 away from the first stacked structure 411. The second contact hole 454 can expose the second connection portion 4181. Further, a second conductive pillar (not shown) is formed in the second contact hole 454 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The second conductive pillar extends the second connection portion 4181 from the surface of the second stacked structure 412 away from the first stacked structure 411. The material of the second conductive pillar can include but is not limited to one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si) or any other suitable conductive material. Among them, the distribution and positional relationship of the second connection portion 4181 and the second conductive pillar have been described in detail above, and will not be elaborated herein. After this step, a second contact structure 418 is formed. The second contact structure 418 can include a second connection portion and a second conductive pillar. In addition, the second contact structure 418 can further include an insulating layer sleeved around the second conductive pillar. It should be noted that the substrate 450 can be doped to form an insulating structure.

[0146] In some embodiments, the second initial stacked structure 412 and the second insulating structure 424 can also extend to the peripheral region. The first dielectric layer 4132 of the second initial stacked structure 412 that is farthest from the first initial stacked structure 411 extends to the peripheral region, and the top surface of the first dielectric layer 4132 is covered with a second guiding layer 4221. The second insulating structure 424 covers the first dielectric layer 4132 and the second guiding layer 4221 in the peripheral region. In the peripheral region, a second through hole 4532 is formed by an etching process method to extend from the surface of the second stacked structure 412 away from the first initial stacked structure 411 to the first guiding layer 4211. Further, a second through-silicon contact structure is formed in the second through hole 4532 by a thin film deposition process such as CVD, PVD, ALD or any combination thereof. The second through-silicon contact structure and the first through-silicon contact structure together form a through-silicon contact structure. A first peripheral circuit 430 is connected to one side of the through-silicon contact structure close to the first stacked structure 411, and a second peripheral circuit is connected to one side of the through-silicon contact structure close to the second stacked structure 412.

[0147] In some embodiments, the manufacturing method 300 may further include the steps of forming a channel hole (not shown) that penetrates the first initial stack structure and the second initial stack structure in the core region, and forming a channel structure using the channel hole. For example, the channel hole may be formed respectively in the etching processes for forming the first contact hole and the second contact hole.

[0148] In some embodiments, the manufacturing method 300 may further include the steps of forming a dummy channel hole (not shown) that penetrates the first initial stack structure and the second initial stack structure, and forming a dummy channel structure using the dummy channel hole.

[0149] In another embodiment, a "trim-etch" process is used to form a plurality of first initial steps and a plurality of second initial steps having partitions (e.g., 204a, 204b) in the D1 direction (refer to Figure 2A ). Subsequently, between two adjacent partitions (e.g., 204a, 204b), an etching process (e.g., dry etching and / or wet etching) is used to form a second gate line gap (not shown) that penetrates the initial stack structure and extends in the D2 direction. The second gate line gap penetrates the first guiding layer 4211, the first initial stack structure 411, the second guiding layer 4221, and the second initial stack structure 412. For example, the second gate line gap may correspond to Figure 2A and Figure 2B the outer contour of the second gate line gap structure shown. The second gate line gap may extend in the D2 direction and divide the first initial steps and the second initial steps into at least two partitions in the D1 direction. Further, during the execution of steps S312 and S313, the second gate line gap may be utilized, and for example, the method described above is used to replace the edge portions of the first guiding layer 4211, the second guiding layer 4221, the second dielectric layer close to the second gate line gap, and the portions of the second dielectric layer covered by the first guiding layer 4211 and the second guiding layer 4221 with a gate layer, thereby forming a material layer as shown in Figures 2B to 2E .

[0150] The above description is only for the embodiments of the present application and the illustration of the technical principles applied. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, comprising: a stacked structure including a first stacked structure and a second stacked structure in its stacking direction, the first stacked structure including a first step, the second stacked structure including a second step, the first step and the second step including a first dielectric layer and a material layer stacked with each other, the material layer including a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction; a first contact structure extending from a surface of the first stacked structure away from the second stacked structure and penetrating through the second dielectric layer of the first step to connect with the gate layer of the first step; and a second contact structure extending from a surface of the second stacked structure away from the first stacked structure and penetrating through the second dielectric layer of the second step to connect with the gate layer of the second step.

2. The semiconductor device according to claim 1, wherein, the first contact structure includes a first connection portion and a first conductive pillar, the first connection portion penetrating through the second dielectric layer of the first step and connecting with the gate layer of the first step, the first conductive pillar extending from a surface of the first stacked structure away from the second stacked structure to the first connection portion and connecting with the first connection portion; the second contact structure includes a second connection portion and a second conductive pillar, the second connection portion penetrating through the second dielectric layer of the second step and connecting with the gate layer of the second step; the second conductive pillar extending from a surface of the second stacked structure away from the first stacked structure to the second connection portion and connecting with the second connection portion.

3. The semiconductor device according to claim 2, wherein, in the stacking direction, the size of the first connection portion or the second connection portion is greater than the size of the second dielectric layer.

4. The semiconductor device according to claim 2, wherein, in the stacking direction, the size of the first connection portion or the second connection portion is less than the sum of the sizes of the second dielectric layer and the first dielectric layer.

5. The semiconductor device according to claim 1, wherein, in the stacking direction, the first contact structure and the second contact structure are at least partially aligned.

6. The semiconductor device according to claim 2, wherein, a surface of the first stacked structure close to the second stacked structure is a first surface; in the stacking direction, the size of the first conductive pillar at a first distance from the first surface is less than the size of the first conductive pillar at a second distance from the first surface, the first distance being greater than the second distance; in the stacking direction, the size of the second conductive pillar at a third distance from the first surface is greater than the size of the second conductive pillar at a fourth distance from the first surface, the third distance being less than the fourth distance.

7. The semiconductor device according to claim 1, wherein, further comprising: a first gate line gap structure penetrating through the stacked structure and extending in a second direction, the second direction intersecting the first direction and the stacking direction; Wherein, the gate layer is located on opposite sides of the first gate line gap structure along the first direction.

8. The semiconductor device according to claim 7, wherein, In the first direction, two sides of the first contact structure are respectively connected to the gate layer located at the sides of two adjacent first gate line gap structures.

9. The semiconductor device according to claim 7, wherein, Both the first step and the second step each have at least two partitions in the first direction, and the first step or the second step in two adjacent partitions differ by at least one stack pair, and the stack pair is a structure composed of the first dielectric layer and the material layer.

10. The semiconductor device according to claim 9, wherein, further comprising: A second gate line gap structure, penetrating the stacked structure and extending along the second direction, for dividing the first step and the second step into the at least two partitions, and the second gate line gap structure is located between two adjacent first gate line gap structures; Wherein, the gate layer is also located on opposite sides of the second gate line gap structure along the first direction.

11. The semiconductor device according to claim 10, wherein, In the first direction, one side of the first contact structure or the second contact structure is connected to the gate layer located at the side of the first gate line gap structure, and the other side of the first contact structure or the second contact structure is connected to the gate layer located at the side of the second gate line gap structure.

12. The semiconductor device according to claim 7 or 10, wherein, The portion of the gate layer for connecting to the first contact structure or the second contact structure includes a first part and a second part, the second part extends along the stacking direction from one side of the first part in the stacking direction and is connected to the first dielectric layer, the size of the first part in the first direction is smaller than the size of the second part in the first direction, and the second part is connected to the first gate line gap structure or the second gate line gap structure; Wherein, the semiconductor device further comprises: An oxide layer, located between the first part and the first gate line gap structure, or located between the first part and the second gate line gap structure; the sum of the sizes of the oxide layer and the first part in the first direction is equal to the size of the second part in the first direction.

13. The semiconductor device according to claim 7, wherein, The stacked structure has a stepped area and a core area in the second direction, both the first step and the second step are located in the stepped area, the first dielectric layer and the gate layer extend to the core area, and the first gate line gap structure extends to the core area; Wherein, the semiconductor device further comprises: A plurality of channel structures, respectively penetrating through the portions of the first dielectric layer and the gate layer located in the core area.

14. The semiconductor device according to claim 13, wherein, The stacked structure has a peripheral area in the second direction; the semiconductor device further comprises: A first peripheral circuit, located on a side of the first stacked structure away from the second stacked structure; A second peripheral circuit, located on a side of the second stacked structure away from the first stacked structure; and A through-silicon contact structure, penetrating through the peripheral region of the stacked structure along the stacking direction and connected to the first peripheral circuit and the second peripheral circuit respectively.

15. A storage system, Characterized in that, It includes: The semiconductor device according to any one of claims 1 to 14; And A controller, coupled to the semiconductor device.

16. A method for manufacturing a semiconductor device, Characterized in that, It includes: Forming a stacked structure, the stacked structure including a first stacked structure and a second stacked structure in its stacking direction, the first stacked structure including a first step, the second stacked structure including a second step, the first step and the second step including a first dielectric layer and a material layer stacked with each other, the material layer including a gate layer and a second dielectric layer in a first direction perpendicular to the stacking direction; Forming a first contact structure, the first contact structure extending from a surface of the first stacked structure away from the second stacked structure and penetrating through the second dielectric layer of the first step to be connected to the gate layer of the first step; And Forming a second contact structure, the second contact structure extending from a surface of the second stacked structure away from the first stacked structure and penetrating through the second dielectric layer of the second step to be connected to the gate layer of the second step.

17. The manufacturing method according to claim 16, Wherein, Forming a stacked structure includes: Forming an initial stacked structure, the initial stacked structure including a first initial stacked structure and a second initial stacked structure in its stacking direction, the first initial stacked structure including a first initial step, the second initial stacked structure including a second initial step, the first initial step and the second initial step including the first dielectric layer and the second dielectric layer stacked with each other, a first guiding layer being formed on a surface of the first initial step, and a second guiding layer being formed on a surface of the second initial step; Removing a part of the second dielectric layer to form voids in the first initial step and the second initial step; and Filling the voids and forming the gate layer in the voids.

18. The manufacturing method according to claim 17, Wherein, Removing a part of the second dielectric layer to form voids in the first initial step and the second initial step includes: Forming a first gate line gap penetrating through the initial stacked structure and extending in a second direction, wherein the second direction intersects the first direction and the stacking direction; Via the first gate line gap, removing the first guiding layer and the second guiding layer; Removing edge portions of the second dielectric layer close to the first gate line gap and portions of the second dielectric layer covered by the first guiding layer and the second guiding layer respectively to form the voids.

19. The manufacturing method according to claim 17, Wherein, Removing a part of the second dielectric layer to form a void between the first initial step and the second initial step, including: Forming a first gate line gap that penetrates the initial stacked structure and extends in a second direction, wherein sidewalls of the first guiding layer and the second guiding layer exposed to the first gate line gap have oxide layers, and wherein the second direction intersects the first direction and the stacking direction; Via the first gate line gap, removing a first part of an edge portion of the second dielectric layer adjacent to the first gate line gap and exposing the first guiding layer and the second guiding layer, wherein the size of the first part in the first direction is greater than the size of the oxide layer in the first direction; Removing the first guiding layer and the second guiding layer; and Removing a second part of the edge portion of the second dielectric layer adjacent to the first gate line gap and portions of the second dielectric layer covered by the first guiding layer and the second guiding layer respectively to form the void.

20. The manufacturing method according to claim 18 or 19, wherein, the void includes a first void and a second void, the first void corresponding to the edge portion of the second dielectric layer adjacent to the first gate line gap, and the second void corresponding to portions of the non-edge portion of the second dielectric layer covered by the first guiding layer and the second guiding layer respectively; wherein forming a first contact structure includes: Forming a first conductive pillar that extends from a surface of the first stacked structure away from the second stacked structure to a first connection portion of the first step, the first connection portion being the gate layer filled in the second void of the first step; wherein forming a second contact structure includes: Forming a second conductive pillar that extends from a surface of the second stacked structure away from the first stacked structure to a second connection portion of the second step, the second connection portion being the gate layer filled in the second void of the second step.

21. The manufacturing method according to claim 17, wherein, both the first initial step and the second initial step have at least two partitions in the first direction; the manufacturing method further includes: Forming a second gate line gap that penetrates the initial stacked structure and extends in a second direction between two adjacent partitions, wherein the second direction intersects the first direction and the stacking direction; and Utilizing the second gate line gap to replace the first guiding layer, the second guiding layer, an edge portion of the second dielectric layer adjacent to the second gate line gap, and portions of the second dielectric layer covered by the first guiding layer or the second guiding layer respectively with the gate layer.

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