Memory device and forming method thereof

Abstract

The invention discloses a memory device and a forming method thereof, and the memory device comprises a substrate which is internally provided with a P-type well region; a control gate layer located on the P-type well region; the charge trapping layer is positioned on the P-type well region; the high-K dielectric layer is positioned on the charge trapping layer; the storage grid layer is positioned on the high-K dielectric layer; the source doping layer is positioned in the P-type well region; and the drain doping layer is positioned in the P-type well region. The introduction of the high-K dielectric layer can optimize the energy band structure of the tunneling oxide layer and improve the tunneling efficiency of electrons, thereby improving the writing and erasing speed of the memory device. The band gap gradient can be formed by adjusting the combination of the nitride, the oxide and the high-K dielectric layer in the charge trapping layer, so that the data retention capability of the memory is improved. The large band gap of the high-K dielectric layer can also increase the barrier height of thermal injection, so that channel electrons are more difficult to inject into the charge trapping layer, electron tunneling and injection effects in the memory device are reduced, and the performance of the memory device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a storage device and a method for forming the same. Background Art

[0002] Charge-trapping split-gate cells can be applied not only to general-purpose MCUs, but also to fields such as industrial and automotive application MCUs that require both high-speed random read characteristics, extremely low defect rates, and demanding high-temperature durability.

[0003] The storage medium layer of a traditional flash memory is a polysilicon floating gate, while the charge-trapping type stores charges with a silicon nitride material. For a polysilicon floating-gate type cell, the storage area is a conductor. When there is a conductive defect in the oxide film around the polysilicon floating gate, all stored charges will eventually be lost through the defect. In contrast, for a charge-trapping memory, the storage area is charge traps in a thin insulating silicon nitride film. Multiple traps are distributed separately, and only the charges near the defect are lost. That is to say, it is inherently more reliable. This structure realizes the storage operation and erasure operation of charges, enabling the memory to have different threshold voltages in the storage state and the erased state, and then differentiating the logically "0" and "1" states by reading the leakage currents (of different orders of magnitude) in these two states. Nitride film storage is highly compatible with logic CMOS. Low-power programming can be achieved by using source-side injection channel hot electrons (SSI-CHE). In addition, there is no high voltage (HV) in the low-voltage word-line drive and read path, enabling high-speed random read of >100 MHz, lower-power read operations, and smaller flash cell sizes.

[0004] However, there are still many problems in existing storage devices. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a storage device and a method for forming the same to improve the performance of the storage device.

[0006] To solve the above problems, the technical solution of the present invention provides a storage device, including: a substrate having a P-type well region therein, and the top surface of the P-type well region is exposed on the substrate; a control gate layer located on the P-type well region, the control gate layer including opposite first and second sidewalls; a charge-trapping layer located on the P-type well region; a high-K dielectric layer located on the charge-trapping layer; a storage gate layer located on the high-K dielectric layer, the storage gate layer including opposite third and fourth sidewalls, and the second sidewall of the control gate layer is adjacent to the third sidewall of the storage gate layer; a source doping layer located in the P-type well region; a drain doping layer located in the P-type well region, and the control gate layer and the storage gate layer are located between the source doping layer and the drain doping layer.

[0007] Optionally, the structure of the charge trapping layer is an ONO structure.

[0008] Optionally, the structure of the charge trapping layer is an ONONO structure.

[0009] Optionally, the high-K dielectric layer is a single-layer structure or a multi-layer structure.

[0010] Optionally, the material of the high-K dielectric layer includes: Al 2 O 3 、HfO 2 、La 2 O 3 、ZrO 2 、and TiO 2 or one or more of them.

[0011] Optionally, the charge trapping layer and the high-K dielectric layer are also located between the second sidewall of the control gate layer and the third sidewall of the storage gate layer; wherein, the charge trapping layer is close to the control gate layer, and the high-K dielectric layer is close to the storage gate layer.

[0012] Optionally, it further includes: a gate dielectric layer located on the substrate, and the control gate layer is located on the gate dielectric layer.

[0013] Optionally, it further includes: sidewalls located on the first sidewall of the control gate layer and the fourth sidewall of the storage gate layer.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a storage device, including: providing a substrate, having a P-type well region therein, and the substrate exposes the top surface of the P-type well region; forming a control gate layer on the P-type well region, the control gate layer includes opposite first and second sidewalls; forming a charge trapping layer, a high-K dielectric layer and a storage gate layer on the P-type well region, the high-K dielectric layer is located on the charge trapping layer, the storage gate layer is located on the high-K dielectric layer, the storage gate layer includes opposite third and fourth sidewalls, and the second sidewall of the control gate layer is adjacent to the third sidewall of the storage gate layer; forming a source doping layer and a drain doping layer in the P-type well region, and the control gate layer and the storage gate layer are located between the source doping layer and the drain doping layer.

[0015] Optionally, the structure of the charge trapping layer is an ONO structure.

[0016] Optionally, the structure of the charge trapping layer is an ONONO structure.

[0017] Optionally, the high-K dielectric layer is a single-layer structure or a multi-layer structure.

[0018] Optionally, the material of the high-k dielectric layer includes: Al 2 O 3 , HfO 2 , La 2 O 3 , ZrO 2 and TiO 2 or one or more of them.

[0019] Optionally, the charge trapping layer and the high-k dielectric layer are also located between the second sidewall of the control gate layer and the third sidewall of the storage gate layer; wherein, the charge trapping layer is close to the control gate layer, and the high-k dielectric layer is close to the storage gate layer.

[0020] Optionally, the forming methods of the charge trapping layer, the high-k dielectric layer and the storage gate layer include: forming a charge trapping material layer and a high-k dielectric material layer stacked in sequence on the substrate, the charge trapping material layer and the high-k dielectric material layer covering the surface of the control gate layer; forming a storage gate material layer on the high-k dielectric material layer; performing a patterning etching process on the charge trapping material layer, the high-k dielectric material layer and the storage gate material layer to form the charge trapping layer, the high-k dielectric layer and the storage gate layer.

[0021] Optionally, the forming method of the control gate layer includes: forming a control gate material layer on the substrate; performing a patterning etching process on the control gate material layer to form the control gate layer.

[0022] Optionally, before forming the control gate layer, it further includes: forming a gate dielectric layer on the substrate, and the control gate layer is located on the gate dielectric layer.

[0023] Optionally, before forming the source doping layer and the drain doping layer, it further includes: forming sidewalls on the first sidewall of the control gate layer and the fourth sidewall of the storage gate layer.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the storage device of the technical solution of the present invention, holes are provided in the P-type well region. By adding the high-K dielectric layer on the charge trapping layer, the introduction of the high-K dielectric layer can optimize the energy band structure of the tunneling oxide layer in the charge trapping layer to improve the tunneling efficiency of electrons, allowing sufficient electric field strength to be achieved at a lower voltage, accelerating the charge tunneling process, thereby improving the write and erase speeds of the storage device. By adjusting the combination of nitride, oxide in the charge trapping layer and the high-K dielectric layer, a bandgap gradient can be formed to balance the charge injection efficiency and reduce the thermal excitation leakage to improve the data retention ability of the memory. In addition, the larger bandgap of the high-K dielectric layer can also increase the barrier height of thermal injection. Channel electrons need to cross the barrier to be injected into the storage medium. Therefore, the increased barrier will reduce the channel electron tunneling and injection effects, making it more difficult for channel electrons to be injected into the charge trapping layer, and thus reducing the electron tunneling and injection effects in the storage device, thereby improving the performance of the storage device.

[0026] Furthermore, the structure of the charge trapping layer is an ONONO structure. The ONONO structure can more evenly distribute charges in the multi-layer structure by adding additional nitride and oxide layers, reducing local electric field concentration, thereby improving the charge retention ability. The multi-layer structure of the ONONO structure provides more tunneling paths and a more uniform electric field distribution, thereby improving the tunneling efficiency of electrons and reducing the write and erase voltages. In addition, the multi-layer structure of the ONONO structure also disperses the pressure of charge injection and extraction, reducing the damage of a single interface, thereby significantly improving the durability of the device.

[0027] Furthermore, the charge trapping layer and the high-K dielectric layer are also located between the second sidewall of the control gate layer and the third sidewall of the storage gate layer; wherein, the charge trapping layer is close to the control gate layer, and the high-K dielectric layer is close to the storage gate layer. By retaining the charge trapping layer and the high-K dielectric layer between the control gate layer and the storage gate layer, the patterning etching process can be simplified and the process difficulty can be reduced. In addition, the charge trapping layer and the high-K dielectric layer located between the control gate layer and the storage gate layer can also increase the isolation voltage between the control gate layer and the storage gate layer, enabling the control gate layer and the storage gate layer to have higher operating voltages.

[0028] In the method for forming a storage device according to the technical solution of the present invention, hole carriers are provided in the P-type well region. By forming the high-K dielectric layer on the charge trapping layer, the introduction of the high-K dielectric layer can optimize the energy band structure of the tunneling oxide layer in the charge trapping layer to improve the tunneling efficiency of electrons, allowing sufficient electric field strength to be achieved at a lower voltage, accelerating the charge tunneling process, and thus enhancing the write and erase speeds of the storage device. By adjusting the combination of nitride, oxide in the charge trapping layer and the high-K dielectric layer, a bandgap gradient can be formed to balance the charge injection efficiency and reduce thermally activated leakage to improve the data retention ability of the memory. In addition, the relatively large bandgap of the high-K dielectric layer can also increase the barrier height of thermal injection. Channel electrons need to cross the barrier to be injected into the storage medium. Therefore, the increased barrier will reduce the channel electron tunneling and injection effects, making it more difficult for channel electrons to be injected into the charge trapping layer, and thus reducing the electron tunneling and injection effects in the storage device, thereby enhancing the performance of the storage device.

[0029] Furthermore, the structure of the charge trapping layer is an ONONO structure. The ONONO structure can more evenly distribute charges in the multi-layer structure by adding additional nitride and oxide layers, reducing local electric field concentration, thereby improving the charge retention ability. The multi-layer structure of the ONONO structure provides more tunneling paths and a more uniform electric field distribution, thus improving the tunneling efficiency of electrons and reducing the write and erase voltages. In addition, the multi-layer structure of the ONONO structure also disperses the pressure of charge injection and extraction, reducing the damage to a single interface, thereby significantly improving the durability of the device.

[0030] Furthermore, the charge trapping layer and the high-K dielectric layer are also located between the second sidewall of the control gate layer and the third sidewall of the storage gate layer; wherein, the charge trapping layer is close to the control gate layer, and the high-K dielectric layer is close to the storage gate layer. By retaining the charge trapping layer and the high-K dielectric layer between the control gate layer and the storage gate layer, the patterning etching process can be simplified and the process difficulty can be reduced. In addition, the charge trapping layer and the high-K dielectric layer located between the control gate layer and the storage gate layer can also increase the isolation voltage between the control gate layer and the storage gate layer, enabling the control gate layer and the storage gate layer to have higher operating voltages. Description of the Drawings

[0031] Figure 1 is a schematic structural diagram of a storage device;

[0032] Figures 2 to 5 is a schematic structural diagram of each step in the method for forming a storage device according to an embodiment of the present invention. Detailed Embodiments

[0033] As described in the background art, there are still many problems in the existing storage devices. The following will be specifically described with reference to the drawings.

[0034] Please refer to Figure 1 , a storage device, comprising: a substrate 100; a control gate layer 101 located on the substrate 100, the control gate layer 101 including opposite first sidewalls 101a and second sidewalls 101b; a charge trapping layer 102 located on the substrate 100; a storage gate layer 103 located on the charge trapping layer 102, the storage gate layer 103 including opposite third sidewalls 103a and fourth sidewalls 103b, the second sidewall 101b of the control gate layer 101 being adjacent to the third sidewall 103a of the storage gate layer 103; a source doping layer 104 located in the substrate 100; a drain doping layer 105 located in the substrate 100, the control gate layer 101 and the storage gate layer 103 being located between the source doping layer 104 and the drain doping layer 105.

[0035] In this embodiment, the charge trapping layer 102 is a structure composed of an oxide-nitride-oxide (Oxide-Nitride-Oxide, abbreviated as ONO). In SONOS storage devices and ONO transistors, the ONO structure plays a key role. In SONOS storage devices, the ONO structure injects charges into the nitride layer through the bottom oxide layer, and the charges are trapped by the traps in the nitride layer, thereby realizing data storage. However, it is difficult to obtain faster write and erase speeds and good data retention performance in current storage devices.

[0036] On this basis, the present invention provides a storage device and a method for forming the same. The P-type well region provides hole carriers. By adding the high-K dielectric layer on the charge trapping layer, the introduction of the high-K dielectric layer can optimize the energy band structure of the tunneling oxide layer in the charge trapping layer to improve the tunneling efficiency of electrons, allowing sufficient electric field strength to be achieved at a lower voltage, accelerating the charge tunneling process, and thus improving the write and erase speeds of the storage device. By adjusting the combination of the nitride, oxide, and the high-K dielectric layer in the charge trapping layer, a bandgap gradient can be formed to balance the charge injection efficiency and reduce the thermal excitation leakage to improve the data retention ability of the memory. In addition, the larger bandgap of the high-K dielectric layer can also increase the barrier height of thermal injection. Channel electrons need to cross the barrier to be injected into the storage medium. Therefore, the increased barrier will reduce the channel electron tunneling and injection effects, making it more difficult for channel electrons to be injected into the charge trapping layer, and thus reducing the electron tunneling and injection effects in the storage device, thereby improving the performance of the storage device.

[0037] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0038] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "upper", "lower", "top surface", "bottom surface", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated position or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not require or imply any actual relationship, order, or relative importance between these entities or operations.

[0039] Figures 2 to 5 It is a schematic structural diagram of each step of the method for forming a storage device according to an embodiment of the present invention.

[0040] Please refer to Figure 2 , provide a substrate 200, the substrate 200 has a P-type well region therein, and the substrate 200 exposes the top surface of the P-type well region 201.

[0041] In this embodiment, the method for forming the P-type well region 201 includes: performing an implantation process of P-type ions on the substrate 200 to form the P-type well region 201 in the substrate 200.

[0042] In this embodiment, the material of the substrate 200 is silicon.

[0043] In other embodiments, the material of the substrate may further include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0044] Please continue to refer to Figure 2 , in this embodiment, before forming the P-type well region 201, several isolation structures 202 are formed in the substrate 200.

[0045] In this embodiment, the isolation structure 202 is used to electrically isolate each adjacent memory cell formed subsequently, and the material of the isolation structure 202 is an insulating material, specifically, silicon oxide can be used.

[0046] In this embodiment, the method for forming the isolation structure 202 includes: forming an isolation trench (not labeled) in the substrate 200, and filling the isolation structure 202 in the isolation trench.

[0047] Please refer to Figure 3 , a control gate layer 203 is formed on the P-type well region 201, and the control gate layer 203 includes opposite first sidewalls 203a and second sidewalls 203b.

[0048] In this embodiment, before forming the control gate layer 203, a gate dielectric layer 204 is formed on the substrate 200, and the control gate layer 203 is located on the gate dielectric layer 204.

[0049] In this embodiment, the method for forming the control gate layer 203 and the gate dielectric layer 204 includes: forming a control gate material layer and a gate dielectric material layer (not shown) on the substrate 200; performing a patterning etching process on the control gate material layer and the gate dielectric material layer to form the control gate layer 203 and the gate dielectric layer 204.

[0050] In this embodiment, the control gate structure is jointly constituted by the gate dielectric layer 204 and the control gate layer 203. Among them, the material of the gate dielectric layer 204 is silicon oxide, and the material of the control gate layer 203 is polysilicon.

[0051] Please refer to Figure 4 , after forming the control gate layer 203, a charge trapping layer 205, a high-K dielectric layer 206, and a storage gate layer 207 are formed on the P-type well region 201. The high-K dielectric layer 206 is located on the charge trapping layer 205, the storage gate layer 207 is located on the high-K dielectric layer 206, the storage gate layer 207 includes opposite third sidewalls 207a and fourth sidewalls 207b, and the second sidewall 203b of the control gate layer 203 is adjacent to the third sidewall 207a of the storage gate layer 207.

[0052] The P-type well region 201 provides hole carriers. By adding the high-K dielectric layer 206 on the charge trapping layer 205, the introduction of the high-K dielectric layer 206 can optimize the energy band structure of the tunneling oxide layer in the charge trapping layer 205 to improve the tunneling efficiency of electrons, allowing sufficient electric field strength to be achieved at a lower voltage, accelerating the charge tunneling process, and thus enhancing the write and erase speeds of the memory device. By adjusting the combination of nitride, oxide in the charge trapping layer 205 and the high-K dielectric layer 206, a bandgap gradient can be formed to balance the charge injection efficiency and reduce the thermally activated leakage to improve the data retention ability of the memory. In addition, the larger bandgap of the high-K dielectric layer 206 can also increase the barrier height of thermal injection. Channel electrons need to cross the barrier to be injected into the storage medium. Therefore, the increased barrier will reduce the channel electron tunneling and injection effects, making it more difficult for channel electrons to be injected into the charge trapping layer 205, and thus reducing the electron tunneling and injection effects in the memory device, thereby enhancing the performance of the memory device.

[0053] In this embodiment, the structure of the charge trapping layer 205 is an ONONO structure, that is, the charge trapping layer 205 includes a silicon oxide layer - a silicon nitride layer - a silicon oxide layer - a silicon nitride layer - a silicon oxide layer (Oxide-Nitride-Oxide-Nitride-Oxide, abbreviated as ONONO). Through the ONONO structure with additional nitride and oxide layers, charges can be more evenly distributed in the multi-layer structure, reducing the local electric field concentration, thereby improving the charge retention ability. The multi-layer structure of the ONONO structure provides more tunneling paths and a more uniform electric field distribution, thus improving the tunneling efficiency of electrons and reducing the write and erase voltages. In addition, the multi-layer structure of the ONONO structure also disperses the pressure of charge injection and extraction, reducing the damage of a single interface, thereby significantly improving the durability of the device.

[0054] In other embodiments, the structure of the charge trapping layer can also be an ONO structure, that is, the charge trapping layer includes a silicon oxide layer - a silicon nitride layer - a silicon oxide layer (Oxide-Nitride-Oxide, abbreviated as ONO).

[0055] In this embodiment, the thicknesses of the respective film layers in the ONONO structure can be 13 Å / 20 Å / 25 Å / 60 Å / 60 Å in sequence.

[0056] The high-K dielectric layer 206 is a single-layer structure or a multi-layer structure. The materials of the high-K dielectric layer 206 include: Al 2 O 3 、HfO 2 、La 2 O 3 、ZrO 2 and TiO 2One or more of them.

[0057] In a specific embodiment, HAONONO (i.e., HfO 2 / Al 2 O 3 / SiO 2 / SiN / SiO 2 / SiN / SiO 2 , hafnium oxide / aluminum oxide / silicon oxide / silicon nitride / silicon oxide / silicon nitride / silicon oxide), in the structure, the material of the high-K dielectric layer 206 can adopt a bilayer structure of Al 2 O 3 and HfO 2 , where the film layer of Al 2 O 3 is in contact with the charge trapping layer 205, the film layer of HfO 2 is located on the film layer of Al 2 O 3 , and the film layer thickness of HfO 2 is less than 50 angstroms.

[0058] In this embodiment, the material of the storage gate layer 207 is polysilicon.

[0059] In this embodiment, the charge trapping layer 205 and the high-K dielectric layer 206 are also located between the second sidewall 203b of the control gate layer 203 and the third sidewall 207a of the storage gate layer 207; wherein, the charge trapping layer 205 is close to the control gate layer 203, and the high-K dielectric layer 206 is close to the storage gate layer 207.

[0060] In this embodiment, the formation methods of the charge trapping layer 205, the high-K dielectric layer 206 and the storage gate layer 207 include: forming a charge trapping material layer and a high-K dielectric material layer stacked in sequence on the substrate 200, and the charge trapping material layer and the high-K dielectric material layer cover the surface of the control gate layer 203; forming a storage gate material layer on the high-K dielectric material layer; performing a patterning etching process on the charge trapping material layer, the high-K dielectric material layer and the storage gate material layer to form the charge trapping layer 205, the high-K dielectric layer 206 and the storage gate layer 207.

[0061] By retaining the charge trapping layer 205 and the high-k dielectric layer 206 between the control gate layer 203 and the storage gate layer 207, the patterning etching process can be simplified and the process difficulty can be reduced. In addition, the charge trapping layer 205 and the high-k dielectric layer 206 located between the control gate layer 203 and the storage gate layer 207 can also increase the isolation voltage between the control gate layer 203 and the storage gate layer 207, enabling the control gate layer 203 and the storage gate layer 207 to have a higher operating voltage.

[0062] In other embodiments, there may be no charge trapping layer and high-k dielectric layer between the second sidewall of the control gate layer and the third sidewall of the storage gate layer.

[0063] Please refer to Figure 5 , after forming the charge trapping layer 205, the high-k dielectric layer 206, and the storage gate layer 207, a source doping layer 208 and a drain doping layer 209 are formed in the P-type well region 201, and the control gate layer 203 and the storage gate layer 207 are located between the source doping layer 208 and the drain doping layer 209.

[0064] In this embodiment, the writing mechanism of the storage device: A positive high voltage is applied to the source doping layer 208 and the storage gate layer 207, and a positive bias voltage higher than the threshold voltage is applied to the control gate layer 203 to open the channel. Electrons are accelerated towards the source doping layer 208 under the action of the horizontal electric field. Due to the positive high voltage applied to the storage gate layer 207, electrons are injected into the charge trapping layer 205 (specifically, the silicon nitride layer in the charge trapping layer 205) under the action of the vertical electric field, completing the writing process.

[0065] The erasing mechanism of the storage device: A positive high voltage is applied to the source doping layer 208, and a negative high voltage is applied to the storage gate layer 207. Due to the band-to-band tunneling effect, electron-hole pairs are generated near the source doping layer 208, and holes are injected into the charge trapping layer 205 under the action of the vertical electric field to neutralize the electrons originally in the charge trapping layer 205, completing the erasing process.

[0066] The reading process of the storage device: An operating voltage Vdd is applied to the drain doping layer 209 (i.e., the bit line) and the control gate layer 203, and the state of the memory cell is determined by reading the current on the drain doping layer 209. If the current of the bit line is large, it means that the electron trapping layer in the memory cell captures holes or electrons are released, and the threshold voltage decreases, which is the erased state ("1"); if the current of the bit line is small, it means that the electron trapping layer in the memory cell captures electrons, and the threshold voltage increases, which is the stored state ("0").

[0067] In this embodiment, before forming the source doping layer 208 and the drain doping layer 209, it further includes: forming sidewalls 210 on the first sidewall 203a of the control gate layer 203 and the fourth sidewall 207b of the storage gate layer 207.

[0068] In this embodiment, the method for forming the source doping layer 208 and the drain doping layer 209 includes: using the control gate layer 203, the storage gate layer 207, and the sidewalls 210 as masks, injecting source / drain ions into the P-type well region 201 to form the source doping layer 208 and the drain doping layer 209 in the P-type well region 201.

[0069] Correspondingly, an embodiment of the present invention further provides a storage device. Please continue to refer to Figure 5 , which includes: a substrate 200 having a P-type well region 201 therein, and the substrate 200 exposes the top surface of the P-type well region 201; a control gate layer 203 located on the P-type well region 201, and the control gate layer 203 includes opposite first sidewall 203a and second sidewall 203b; a charge trapping layer 205 located on the P-type well region 201; a high-K dielectric layer 206 located on the charge trapping layer 205; a storage gate layer 207 located on the high-K dielectric layer 206, and the storage gate layer 207 includes opposite third sidewall 207a and fourth sidewall 207b, and the second sidewall 203b of the control gate layer 203 is adjacent to the third sidewall 207a of the storage gate layer 207; a source doping layer 208 located in the P-type well region 201; a drain doping layer 209 located in the P-type well region 201, and the control gate layer 203 and the storage gate layer 207 are located between the source doping layer 208 and the drain doping layer 209.

[0070] The P-type well region 201 provides hole carriers. By adding the high-k dielectric layer 206 on the charge trapping layer 205, the introduction of the high-k dielectric layer 206 can optimize the energy band structure of the tunneling oxide layer in the charge trapping layer 205 to improve the tunneling efficiency of electrons, allowing sufficient electric field strength to be achieved at a lower voltage, accelerating the charge tunneling process, and thus enhancing the write and erase speeds of the memory device. By adjusting the combination of nitride, oxide in the charge trapping layer 205, and the high-k dielectric layer 206, a bandgap gradient can be formed to balance the charge injection efficiency and reduce the thermally activated leakage to enhance the data retention ability of the memory. In addition, the larger bandgap of the high-k dielectric layer 206 can also increase the barrier height of thermal injection. Channel electrons need to cross the barrier to be injected into the storage medium. Therefore, the increased barrier will reduce the channel electron tunneling and injection effects, making it more difficult for channel electrons to be injected into the charge trapping layer 205, and thus reducing the electron tunneling and injection effects in the memory device, thereby enhancing the performance of the memory device.

[0071] In this embodiment, the material of the substrate 200 is silicon.

[0072] In other embodiments, the material of the substrate may also include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0073] In this embodiment, the memory device further includes a plurality of isolation structures 202 located in the substrate 200. The isolation structures 202 are used to electrically isolate adjacent memory cells, and the material of the isolation structures 202 is an insulating material, specifically silicon oxide can be used.

[0074] In this embodiment, the structure of the charge trapping layer 205 is an ONONO structure, that is, the charge trapping layer 205 includes a silicon oxide layer - a silicon nitride layer - a silicon oxide layer - a silicon nitride layer - a silicon oxide layer (Oxide-Nitride-Oxide-Nitride-Oxide, abbreviated as ONONO). Through the ONONO structure, by adding additional nitride and oxide layers, charges can be more evenly distributed in the multi-layer structure, reducing local electric field concentration, thereby improving the charge retention ability. The multi-layer structure of the ONONO structure provides more tunneling paths and a more uniform electric field distribution, thus improving the tunneling efficiency of electrons and reducing the write and erase voltages. In addition, the multi-layer structure of the ONONO structure also disperses the pressure of charge injection and extraction, reducing the damage to a single interface, thereby significantly improving the durability of the device.

[0075] In other embodiments, the structure of the charge trapping layer may also be an ONO structure, that is, the charge trapping layer includes a silicon oxide layer - silicon nitride layer - silicon oxide layer (Oxide - Nitride - Oxide, abbreviated as ONO).

[0076] In this embodiment, the thicknesses of the respective film layers in the ONONO structure may be 13 Å / 20 Å / 25 Å / 60 Å / 60 Å in sequence.

[0077] In this embodiment, the memory device further includes: a gate dielectric layer 204 located on the substrate 200, and the control gate layer 203 is located on the gate dielectric layer 204, and the gate dielectric layer 204 and the control gate layer 203 constitute a control gate structure.

[0078] The high - K dielectric layer 206 is a single - layer structure or a multi - layer structure. The materials of the high - K dielectric layer 206 include: Al 2 O 3 、HfO 2 、La 2 O 3 、ZrO 2 and TiO 2 or one or more of them.

[0079] In a specific embodiment, in the HAONONO (that is, HfO 2 / Al 2 O 3 / SiO 2 / SiN / SiO 2 / SiN / SiO 2 , hafnium oxide / aluminum oxide / silicon oxide / silicon nitride / silicon oxide / silicon nitride / silicon oxide) structure, the material of the high - K dielectric layer 206 may adopt a bilayer structure of Al 2 O 3 and HfO 2 , wherein the film layer of Al 2 O 3 contacts the charge trapping layer 205, the film layer of HfO 2 is located on the film layer of Al 2 O 3 , and the film layer thickness of HfO 2 is less than 50 Å.

[0080] In this embodiment, the material of the storage gate layer 207 is polysilicon.

[0081] In this embodiment, the charge trapping layer 205 and the high-k dielectric layer 206 are also located between the second sidewall 203b of the control gate layer 203 and the third sidewall 207a of the storage gate layer 207; wherein, the charge trapping layer 205 is close to the control gate layer 203, and the high-k dielectric layer 206 is close to the storage gate layer 207.

[0082] By retaining the charge trapping layer 205 and the high-k dielectric layer 206 between the control gate layer 203 and the storage gate layer 207, the patterning etching process can be simplified and the process difficulty can be reduced. In addition, the charge trapping layer 205 and the high-k dielectric layer 206 located between the control gate layer 203 and the storage gate layer 207 can also increase the isolation voltage between the control gate layer 203 and the storage gate layer 207, so that the control gate layer 203 and the storage gate layer 207 can have a higher operating voltage.

[0083] In other embodiments, the charge trapping layer and the high-k dielectric layer may not be provided between the second sidewall of the control gate layer and the third sidewall of the storage gate layer.

[0084] In this embodiment, the storage device further includes: sidewalls 210 located on the first sidewall 203a of the control gate layer 203 and the fourth sidewall 207b of the storage gate layer 207.

[0085] In this embodiment, the writing mechanism of the storage device: A positive high voltage is applied to the source doping layer 208 and the storage gate layer 207, and a positive bias voltage higher than the threshold voltage is applied to the control gate layer 203 to open the channel. Electrons are accelerated and move towards the source doping layer 208 under the action of the horizontal electric field. Since a positive high voltage is applied to the storage gate layer 207, electrons are injected into the charge trapping layer 205 (specifically, the silicon nitride layer in the charge trapping layer 205) under the action of the vertical electric field, completing the writing process.

[0086] The erasing mechanism of the storage device: A positive high voltage is applied to the source doping layer 208, and a negative high voltage is applied to the storage gate layer 207. Due to the band-to-band tunneling effect, electron-hole pairs are generated near the source doping layer 208, and holes are injected into the charge trapping layer 205 under the action of the vertical electric field to neutralize the electrons originally in the charge trapping layer 205, completing the erasing process.

[0087] Reading process of the memory device: An operating voltage Vdd is applied to the drain doping layer 209 (i.e., the bit line) and the control gate layer 203, and the state of the memory cell is determined by reading the current on the drain doping layer 209. If the current of the bit line is large, it means that the electron trapping layer in the memory cell captures holes or electrons are released, and the threshold voltage decreases, which is the erased state ("1"); if the current of the bit line is small, it means that the electron trapping layer in the memory cell captures electrons, and the threshold voltage increases, which is the stored state ("0").

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A storage device, characterized in that: include: A substrate having a P-type well region therein, wherein the substrate exposes a top surface of the P-type well region; A control gate layer located on the P-type well region, the control gate layer comprising a first sidewall and a second sidewall opposite to each other; a charge trapping layer located on the P-type well region; a high-K dielectric layer located on the charge trapping layer; a storage gate layer located on the high-K dielectric layer, the storage gate layer comprising a third sidewall and a fourth sidewall opposite to each other, the second sidewall of the control gate layer being adjacent to the third sidewall of the storage gate layer; a source doping layer located in the P-type well region; The drain doping layer is located in the P-type well region, and the control gate layer and the storage gate layer are located between the source doping layer and the drain doping layer.

2. The memory device according to claim 1, wherein: The structure of the charge trapping layer is an ONO structure.

3. The memory device according to claim 1, wherein: The structure of the charge trapping layer is an ONONO structure.

4. The memory device according to claim 1, wherein: The high-K dielectric layer is a single-layer structure or a multi-layer structure.

5. The memory device according to claim 4, wherein: The material of the high-K dielectric layer includes one or more of Al2O3, HfO2, La2O3, ZrO2 and TiO2.

6. The memory device according to claim 1, wherein: The charge trapping layer and the high-K dielectric layer are also located between the second side wall of the control gate layer and the third side wall of the storage gate layer; wherein the charge trapping layer is close to the control gate layer, and the high-K dielectric layer is close to the storage gate layer.

7. The memory device according to claim 1, wherein: Also includes: A gate dielectric layer is located on the substrate, and the control gate layer is located on the gate dielectric layer.

8. The memory device according to claim 1, wherein: Also includes: A sidewall is located on the first sidewall of the control gate layer and the fourth sidewall of the storage gate layer.

9. A method for forming a memory device, characterized in that: include: Providing a substrate, wherein the substrate has a P-type well region, and the substrate exposes a top surface of the P-type well region; forming a control gate layer on the P-type well region, wherein the control gate layer comprises a first sidewall and a second sidewall opposite to each other; forming a charge trapping layer, a high-K dielectric layer and a storage gate layer on the P-type well region, wherein the high-K dielectric layer is located on the charge trapping layer, the storage gate layer is located on the high-K dielectric layer, the storage gate layer comprises a third sidewall and a fourth sidewall opposite to each other, and the second sidewall of the control gate layer is adjacent to the third sidewall of the storage gate layer; A source doping layer and a drain doping layer are formed in the P-type well region, and the control gate layer and the storage gate layer are located between the source doping layer and the drain doping layer.

10. The method for forming a memory device according to claim 9, wherein: The structure of the charge trapping layer is an ONO structure.

11. The method for forming a memory device according to claim 9, wherein: The structure of the charge trapping layer is an ONONO structure.

12. The method for forming a memory device according to claim 9, wherein: The high-K dielectric layer is a single-layer structure or a multi-layer structure.

13. The method for forming a memory device according to claim 12, wherein: The material of the high-K dielectric layer includes one or more of Al2O3, HfO2, La2O3, ZrO2 and TiO2.

14. The method for forming a memory device according to claim 9, wherein: The charge trapping layer and the high-K dielectric layer are also located between the second side wall of the control gate layer and the third side wall of the storage gate layer; wherein the charge trapping layer is close to the control gate layer, and the high-K dielectric layer is close to the storage gate layer.

15. The method for forming a memory device according to claim 14, wherein: The method for forming the charge trapping layer, the high-K dielectric layer and the storage gate layer comprises: forming a charge trapping material layer and a high-K dielectric material layer stacked in sequence on the substrate, wherein the charge trapping material layer and the high-K dielectric material layer cover the surface of the control gate layer; forming a storage gate material layer on the high-K dielectric material layer; and performing a patterned etching process on the charge trapping material layer, the high-K dielectric material layer and the storage gate material layer to form the charge trapping layer, the high-K dielectric layer and the storage gate layer.

16. The method for forming a memory device according to claim 9, wherein: The method for forming the control gate layer comprises: forming a control gate material layer on the substrate; and performing a patterning etching process on the control gate material layer to form the control gate layer.

17. The method for forming a memory device according to claim 9, wherein: Before forming the control gate layer, the method further includes: forming a gate dielectric layer on the substrate, wherein the control gate layer is located on the gate dielectric layer.

18. The method for forming a memory device according to claim 9, wherein: Before forming the source doping layer and the drain doping layer, the method further includes: forming a sidewall on the first sidewall of the control gate layer and the fourth sidewall of the storage gate layer.

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