Memory and forming method thereof

Abstract

The invention discloses a memory and a forming method thereof, and the memory comprises a first wafer which comprises a plurality of bit line layers; the second wafer is bonded on the first wafer, the second wafer comprises a plurality of transistor structures, and source ends of the transistor structures are interconnected with the bit line layer; and the third wafer is bonded on the second wafer, the third wafer comprises a plurality of storage capacitors, two polar plates of the storage capacitors are respectively connected with a capacitor plate line and a capacitor bit line, and the capacitor bit line is interconnected with the drain end of the transistor structure. According to the invention, the storage density can be increased, and higher frequency and higher response speed of the memory can be realized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a memory and a method for forming the same. Background Art

[0002] In pursuit of the ultimate chip area utilization, major memory (for example, Dynamic Random Access Memory (DRAM)) manufacturers use advanced semiconductor processes to reduce the area of ​​a single array transistor as much as possible. As the size of transistors continues to shrink, a series of new challenges have been brought to the chip process and design.

[0003] In the field of complementary metal oxide semiconductor image sensor (CMOS Image Sensor, CIS) and 3D NAND flash memory, there is already a mature wafer stacking process. For example, in the 3D NAND flash memory currently on the market, complementary metal oxide semiconductor (CMOS) and array wafer are processed separately, and then the CMOS and array wafer are bonded together through a bonding process to achieve interconnection of functional areas. This method greatly shortens the product production cycle, improves the storage density of the chip, and reduces the impact of the storage array process on the CMOS.

[0004] Compared with DRAM, especially ferroelectric memory, there are currently no products on the market that use the technical solution of stacking multiple chips. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a memory and a method for forming the same, which are beneficial to increase storage density and achieve a higher frequency and a faster response speed of the memory.

[0006] To solve the above problems, an embodiment of the present invention provides a memory, including: a first wafer, including multiple bit line layers; a second wafer, bonded to the first wafer, the second wafer including multiple transistor structures, and the source end of the transistor structure is interconnected with the bit line layer; a third wafer, bonded to the second wafer, the third wafer including multiple storage capacitors, two plates of the storage capacitor are respectively connected to the capacitor plate line and the capacitor bit line, and the capacitor bit line is interconnected with the drain end of the transistor structure.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a memory, including: forming a first wafer, the first wafer including a plurality of bit line layers; forming a second wafer and bonding the second wafer to the first wafer, the second wafer including a plurality of transistor structures, the source ends of the transistor structures being interconnected with the bit line layers; forming a third wafer and bonding the third wafer to the second wafer, the third wafer including a plurality of storage capacitors, the two electrodes of the storage capacitors being respectively connected to a capacitor plate line and a capacitor bit line, and the capacitor bit line being interconnected with the drain end of the transistor structure.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: In the memory provided by the embodiment of the present invention, the first wafer includes a plurality of bit line layers, the second wafer is bonded to the first wafer, the second wafer includes a plurality of transistor structures, the source ends of the transistor structures are interconnected with the bit line layers, the third wafer is bonded to the second wafer, the third wafer includes a plurality of storage capacitors, and the capacitor bit lines of the storage capacitors are interconnected with the drain ends of the transistor structures; in the embodiment of the present invention, the first wafer, the second wafer, and the third wafer are bonded to each other to form a memory. The method of forming a memory by stacking multiple wafers is beneficial to increasing the storage density, and distributing the bit line layers, transistor structures, and storage capacitors of the memory on different wafers is beneficial to preventing the structural layout on each wafer from being too dense, beneficial to reducing the manufacturing process difficulty of each wafer, and while achieving an increase in storage density, beneficial to avoiding the reduction of the critical dimensions of various devices in the memory. At the same time, by performing the manufacturing processes of the bit line layers, transistor structures, and storage capacitors on multiple wafers respectively, the segmented manufacturing process is beneficial to reducing the influence of heat treatment (Thermal) on the devices, especially effectively avoiding the cumulative heat influence suffered by the transistor structures during the manufacturing process of the storage capacitors, reducing the influence of the manufacturing process of the storage capacitors on the thermal budget of the transistor structures, thereby reducing the probability of performance degradation (such as impurity diffusion, lattice structure change, etc.) of the transistor structures due to excessive thermal budget. Moreover, since the transistor structures are independently designed on the second wafer, a better transistor density can be provided, enabling a single second wafer to control multiple array wafers simultaneously, which is beneficial to achieving a lower word line delay, and thus beneficial to achieving a higher frequency and a faster response speed of the memory. In addition, by performing the manufacturing processes of the bit line layers, transistor structures, and storage capacitors on multiple wafers respectively, the manufacturing processes of the bit line layers, transistor structures, and storage capacitors can be carried out simultaneously on different wafers, which is beneficial to improving the memory formation efficiency and thus accelerating the product delivery speed.

[0009] In the forming method provided by the embodiment of the present invention, a first wafer is formed. The first wafer includes multiple bit line layers. A second wafer is formed and bonded to the first wafer. The second wafer includes multiple transistor structures. The source end of the transistor structure is interconnected with the bit line layer. A third wafer is formed and bonded to the second wafer. The third wafer includes multiple storage capacitors. The capacitance bit line of the storage capacitor is interconnected with the drain end of the transistor structure. In the embodiment of the present invention, the first wafer, the second wafer, and the third wafer are bonded to each other to form a memory. The method of forming a memory by stacking multiple wafers is beneficial to increasing the storage density. And distributing the bit line layer, the transistor structure, and the storage capacitor of the memory on different wafers is beneficial to preventing the structural layout on each wafer from being too dense, beneficial to reducing the manufacturing process difficulty of each wafer. And while achieving an increase in storage density, it is beneficial to avoid reducing the critical dimensions of various devices in the memory. At the same time, by performing the manufacturing processes of the bit line layer, the transistor structure, and the storage capacitor on multiple wafers respectively, the segmented manufacturing process is beneficial to reducing the influence of heat treatment (Thermal) on the devices. Especially, it effectively avoids the cumulative heat influence on the transistor structure during the manufacturing process of the storage capacitor, reduces the influence of the thermal budget of the storage capacitor manufacturing process on the transistor structure, thereby reducing the probability of performance degradation (such as impurity diffusion, lattice structure change, etc.) of the transistor structure due to excessive thermal budget. And since the transistor structure is independently designed on the second wafer, it can provide a better transistor density, realizing that one second wafer controls multiple array wafers simultaneously, which is beneficial to achieving a lower word line delay, and further beneficial to achieving a higher frequency and a faster response speed of the memory. In addition, by performing the manufacturing processes of the bit line layer, the transistor structure, and the storage capacitor on multiple wafers respectively, the manufacturing processes of the bit line layer, the transistor structure, and the storage capacitor can be carried out simultaneously on different wafers, which is beneficial to improving the forming efficiency of the memory, thereby accelerating the product delivery speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic structural diagram corresponding to an embodiment of the memory of the present invention; Figures 2 to 47 is a schematic structural diagram corresponding to each step in an embodiment of the forming method of the memory of the present invention; Wherein, Figure 2 is a schematic structural diagram corresponding to the step of providing a first substrate; Figure 3 is a schematic structural diagram corresponding to the step of patterning a first mask layer; Figure 4 is a schematic structural diagram corresponding to the step of patterning a bit line material layer and a part of the thickness of the first substrate; Figure 5It is a schematic structural diagram corresponding to the step of removing the first mask layer; Figure 6 It is a schematic structural diagram corresponding to the step of forming the first repair layer; Figure 7 It is a schematic structural diagram corresponding to the step of forming the first dielectric layer covering the bit line layer; Figure 8 It is a schematic structural diagram corresponding to the step of forming the first via hole penetrating the first dielectric layer on the bit line layer; Figure 9 It is a schematic structural diagram corresponding to the step of enlarging the opening size of the first via hole; Figure 10 It is a schematic structural diagram corresponding to the step of forming the first interconnect structure; Figure 11 It is a schematic structural diagram corresponding to the step of providing the second substrate and patterning the second mask layer; Figure 12 It is a schematic structural diagram corresponding to the step of patterning a part of the thickness of the second substrate; Figure 13 It is a schematic structural diagram corresponding to the step of removing the second mask layer and forming the second repair layer; Figure 14 It is a schematic structural diagram corresponding to the step of forming the second protective material layer filling the second trench; Figure 15 It is a schematic structural diagram corresponding to the step of removing a part of the thickness of the second protective material layer to expose the source end; Figure 16 It is a schematic structural diagram corresponding to the step of forming the first protective material layer covering the top and side walls of the exposed second protrusion structure and the top of the remaining thickness of the second protective material layer; Figure 17 It is a schematic structural diagram corresponding to the step of removing the first protective material layer on the top of the second protective material layer; Figure 18 It is a schematic structural diagram corresponding to the step of removing a part of the thickness of the second protective material layer to expose the channel layer; Figure 19 It is a schematic structural diagram corresponding to the step of forming the gate oxide layer covering the channel layer; Figure 20 It is a schematic structural diagram corresponding to the step of forming the gate material layer covering the first protective layer, the gate oxide layer, and the top of the second protective layer; Figure 21 It is a schematic structural diagram corresponding to the step of patterning the gate material layer and retaining the gate material layer covering the gate oxide layer as the gate layer; Figure 22 It is a schematic structural diagram corresponding to the step of forming the second dielectric layer filling the second trench and covering the source end; Figure 23 It is a schematic structural diagram corresponding to the step of forming a second through hole exposing the source end surface; Figure 24 It is a schematic structural diagram corresponding to the step of enlarging the opening size of the second through hole; Figure 25 It is a schematic structural diagram corresponding to the step of forming a second interconnect structure; Figure 26 It is a schematic structural diagram corresponding to the step of bringing the second interconnect structure into contact with the first interconnect structure to achieve bonding; Figure 27 It is a schematic structural diagram corresponding to the step of removing the remaining part of the second substrate thickness to expose the drain end; Figure 28 It is a schematic structural diagram corresponding to the step of forming a third dielectric layer covering the drain end and forming a third through hole exposing the drain end surface; Figure 29 It is a schematic structural diagram corresponding to the step of enlarging the opening size of the third through hole; Figure 30 It is a schematic structural diagram corresponding to the step of forming a third interconnect structure; Figure 31 It is a schematic structural diagram corresponding to the step of providing a third substrate and forming an alternately arranged first isolation layer and sacrificial layer; Figure 32 It is a schematic structural diagram corresponding to the step of forming a fifth through hole penetrating the first isolation layer and the sacrificial layer; Figure 33 It is a schematic structural diagram corresponding to the step of removing the fourth mask layer; Figure 34 It is a schematic structural diagram corresponding to the step of forming a second isolation layer covering the surface of the third substrate exposed by the fifth through hole; Figure 35 It is a schematic structural diagram corresponding to the step of forming a capacitive bit line material layer filling the fifth through hole; Figure 36 It is a schematic structural diagram corresponding to the step of planarizing the capacitive bit line material layer and retaining the capacitive bit line material layer located in the fifth through hole as a capacitive bit line; Figure 37 It is a schematic structural diagram corresponding to the step of forming a third trench penetrating the first isolation layer and the sacrificial layer; Figure 38 It is a schematic structural diagram corresponding to the step of removing the fifth mask layer; Figure 39 It is a schematic structural diagram corresponding to the step of removing the sacrificial layer along the third trench; Figure 40 It is a schematic structural diagram corresponding to the step of forming a storage material layer covering each surface of the through groove; Figure 41 It is a schematic structural diagram corresponding to the step of filling the through groove to form the capacitor plate line; Figure 42 It is a schematic structural diagram corresponding to the step of planarizing the filling material; Figure 43 It is a schematic structural diagram corresponding to the step of removing the interconnecting wall; Figure 44 It is a schematic structural diagram corresponding to the step of forming a fourth dielectric layer through the top of the capacitor bit line and exposing a fourth through hole on the surface of the capacitor bit line; Figure 45 It is a schematic structural diagram corresponding to the step of enlarging the opening size of the fourth through hole; Figure 46 It is a schematic structural diagram corresponding to the step of forming a fourth interconnect structure; Figure 47 It is a schematic structural diagram corresponding to the step of bringing the fourth interconnect structure into contact with the third interconnect structure to achieve bonding. Detailed implementation manners

[0011] As can be seen from the background art, in the fields of CIS and 3D NAND flash memories, the existing wafer stacking process is to process the CMOS and the Array Wafer separately, and then through the bonding process, bond the CMOS and the Array Wafer together to achieve the interconnection of the functional areas, so as to reduce the production cycle of the product, improve the storage density of the chip, and reduce the influence of the storage array process on the CMOS. In contrast to DRAM, especially ferroelectric memories, there is currently no product on the market using a multi-chip stacking technical solution.

[0012] To solve the above technical problems, an embodiment of the present invention provides a memory, including: a first wafer including a plurality of bit line layers; a second wafer bonded to the first wafer, the second wafer including a plurality of transistor structures, and the source ends of the transistor structures are interconnected with the bit line layers; a third wafer bonded to the second wafer, the third wafer including a plurality of storage capacitors, and two electrodes of the storage capacitors are respectively connected to a capacitor plate line and a capacitor bit line, and the capacitor bit line is interconnected with the drain end of the transistor structure.

[0013] In the embodiments of the present invention, the first wafer, the second wafer, and the third wafer are bonded to each other to form a memory. The method of stacking multiple wafers to form a memory is beneficial to increasing the storage density. Moreover, distributing the bit line layer, transistor structure, and storage capacitor of the memory on different wafers is beneficial to preventing the structural layout on each wafer from being too dense, which is beneficial to reducing the manufacturing process difficulty of each wafer. At the same time, while achieving an increase in storage density, it is beneficial to avoid reducing the critical dimensions of various devices in the memory. Meanwhile, by separately performing the manufacturing processes of the bit line layer, transistor structure, and storage capacitor on multiple wafers, the segmented manufacturing process is beneficial to reducing the impact of heat treatment (Thermal) on the devices. And, since the transistor structure is independently designed on the second wafer, it can provide a better transistor density, enabling a single second wafer to control multiple array wafers simultaneously, which is beneficial to achieving a lower word line delay, and further beneficial to achieving a higher frequency and faster response speed of the memory. In addition, by separately performing the manufacturing processes of the bit line layer, transistor structure, and storage capacitor on multiple wafers, the manufacturing processes of the bit line layer, transistor structure, and storage capacitor can be simultaneously carried out on different wafers, which is beneficial to improving the memory formation efficiency, thereby accelerating the product shipment speed.

[0014] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0015] Figure 1 It is a schematic structural diagram corresponding to an embodiment of the memory of the present invention.

[0016] Refer to Figure 1 , the memory includes: a first wafer 100a, including a plurality of bit line layers 140; a second wafer 200a, bonded to the first wafer 100a, the second wafer 200a including a plurality of transistor structures, and the source terminal 251 of the transistor structure is interconnected with the bit line layer 140; a third wafer 300a, bonded to the second wafer 200a, the third wafer 300a including a plurality of storage capacitors, and two plates of the storage capacitor are respectively connected to the capacitor plate line 370 and the capacitor bit line 351, and the capacitor bit line 351 is interconnected with the drain terminal 253 of the transistor structure.

[0017] The first wafer 100a is used to form the structure of the bit line (Bit Line, BL) in the memory.

[0018] Specifically, in this embodiment, the bit line layer 140 of the memory is independently formed only in the first wafer 100a.

[0019] The bit line layer 140 is used as the bit line of the memory, which is a key signal line for realizing the data reading and writing functions of the memory, and is responsible for transmitting and detecting the charge change in the storage unit, thereby realizing the storage and reading of data.

[0020] Specifically, in a read operation, the bit line is used to detect changes in the charge in the memory cell. When the voltage of the Plate Line (PL) changes, the charge in the memory cell can be released through the capacitive bit line 351. When the transistor structure is turned on, a voltage change can be generated on the bit line. By comparing the change in the bit line voltage, it can be determined whether the data stored in the memory cell is "0" or "1". In a write operation, the bit line is used to apply a specific voltage to the memory cell to write "0" or "1" data. For example, when writing the data "0", the bit line is set to a low level and the plate line is set to a high level. When writing the data "1", the bit line is set to a high level and the plate line is set to a low level.

[0021] In this embodiment, the material of the bit line layer 140 includes conductive materials such as tungsten, copper, and / or titanium nitride.

[0022] In this embodiment, in the first wafer 100a, a first interconnect structure 180 electrically connected to the bit line layer 140 is formed on the bit line layer 140.

[0023] The first interconnect structure 180 is used to achieve the electrical connection between the bit line layer 140 and the outside.

[0024] In this embodiment, the material of the first interconnect structure 180 includes tungsten, copper, or aluminum.

[0025] In this embodiment, in the first wafer 100a, multiple bit line layers 140 extend in the same direction and are arranged in parallel, and multiple first interconnect structures 180 arranged along the extension direction of the bit line layer 140 are formed on each bit line layer 140.

[0026] Multiple first interconnect structures 180 arranged along the extension direction of the bit line layer 140 are formed on each bit line layer 140, so that each bit line layer 140 can control multiple storage capacitors (i.e., memory cells) arranged in the direction parallel to the extension direction of the bit line layer 140.

[0027] In a memory, memory cells are usually arranged in a matrix form on a plane. The bit line and the Word Line (WL) are respectively used to control the columns and rows of the memory cells through the transistor structure. The bit line is connected to all the memory cells in the same column, and the word line is connected to the memory cells in the same row. Therefore, one bit line layer 140 can control multiple memory cells. However, each time an operation is performed, the specific memory cell to be operated is determined by the selection of the word line, thus improving the storage density while ensuring the flexibility and efficiency of data access.

[0028] In one embodiment of the present application, the memory is a 1TnC ferroelectric memory, and each bit line layer 140 can control a plurality of capacitor bit lines 351 arranged parallel to the extending direction of the bit line layer 140 and connected to the corresponding bit line layer 140 through a transistor, thereby controlling a plurality of memory cell strings. The capacitor bit lines 351 are arranged in an array on a plane parallel to the first wafer 100a and extend in a direction perpendicular to the first wafer 100a, the capacitor plate lines 370 extend on a plane parallel to the first wafer 100a, and are stacked in a direction perpendicular to the first wafer 100a, and a memory cell string includes a plurality of storage capacitors arranged perpendicular to the first wafer 100a, and the capacitor dielectric of the storage capacitor is a ferroelectric material.

[0029] In this embodiment, the first wafer 100a further includes: a first substrate 100. The first substrate 100 is used to provide a process operation basis for forming the first wafer 100a.

[0030] As an example, in this embodiment, the material of the first substrate 100 is silicon. However, it is not limited thereto. In some embodiments, the first substrate 100 is a substrate with at least one surface being insulated, such as a silicon substrate with an insulating layer formed on the surface, or an insulating substrate, depending on the specific situation.

[0031] In this embodiment, protruding first protruding structures 160 are formed on the first substrate 100 , and adjacent first protruding structures 160 surround a first trench 101 .

[0032] The first protruding structures 160 are used to support the spaced bit line layers 140 . Accordingly, adjacent first protruding structures 160 surround a first trench 101 to separate adjacent bit line layers 140 .

[0033] In this embodiment, the bit line layer 140 is located on the first substrate 100 .

[0034] Specifically, in this embodiment, the bit line layer 140 is located on the first protruding structure 160 .

[0035] In this embodiment, the first wafer 100 a further includes: a first dielectric layer 170 covering the bit line layer 140 and the first substrate 100 .

[0036] The first dielectric layer 170 is used to achieve electrical isolation between adjacent bit line layers 140 .

[0037] In this embodiment, the material of the first dielectric layer 170 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0038] Correspondingly, in this embodiment, the first dielectric layer 170 also fills the first trench 101 .

[0039] The first dielectric layer 170 also fills the first trench 101 to obtain a process platform with better flatness.

[0040] In this embodiment, an air gap is formed in the first dielectric layer 170 in the first trench 101.

[0041] The first dielectric layer 170 is generally formed by filling the first trench 101 using a chemical vapor deposition (CVD) process. Since voids are likely to be formed during the operation process, an air gap is formed in the first dielectric layer 170 in the first trench 101, which helps reduce the parasitic capacitance between adjacent bit line layers 140.

[0042] Correspondingly, in this embodiment, the first interconnect structure 180 penetrates the first dielectric layer 170 on the bit line layer 140 and contacts the bit line layer 140.

[0043] The first interconnect structure 180 penetrates the first dielectric layer 170 to electrically connect one end to the bit line layer 140 and the other end to the outside of the first wafer 100a.

[0044] The second wafer 200a is used to form the transistor structure in the memory.

[0045] Specifically, in this embodiment, the transistor structure of the memory is independently formed only in the second wafer 200a.

[0046] The transistor structure is used to connect the word line (WL) of the memory to control the access to the memory cell or memory cell string. Among them, the gate layer in the transistor structure is connected to the word line or formed integrally with the word line. The source end 251 in the transistor structure is connected to the bit line layer 140, and the drain end 253 in the transistor structure is connected to the storage capacitor via the capacitive bit line 351.

[0047] Specifically, the word line can control the on and off states of the transistor structure. By cross-selecting the word line and the bit line, a specific memory cell or memory cell string can be selected for read and write operations.

[0048] In this embodiment, in the second wafer 200a, a second interconnect structure 291 electrically connected to the source end 251 of the transistor structure is formed on the source end 251 of the transistor structure, and a third interconnect structure 293 electrically connected to the drain end 253 of the transistor structure is formed on the drain end 253 of the transistor structure. The second interconnect structure 291 contacts the first interconnect structure 180 for electrical connection.

[0049] The second interconnect structure 291 is used to electrically connect to the first interconnect structure 180 to realize the electrical connection between the source end 251 and the bit line layer 140. The third interconnect structure 293 is used to realize the electrical connection between the drain end 253 and the outside.

[0050] In this embodiment, the material of the second interconnect structure 291 includes tungsten, copper or aluminum; the material of the third interconnect structure 293 includes tungsten, copper or aluminum.

[0051] In this embodiment, in the second wafer 200a, the source end 251 and the drain end 253 of the transistor structure are longitudinally opposite to each other. The source end 251 of the transistor structure faces the first wafer 100a, and the drain end 253 of the transistor structure faces the third wafer 300a. That is, the source end 251 to the drain end 253 of the transistor extends vertically. The transistor structure is a vertical transistor.

[0052] The source end 251 and the drain end 253 of the transistor structure are longitudinally opposite to each other, which makes it easy to realize the electrical connection between the source end 251 and the drain end 253 and the outside of the second wafer 200a longitudinally. Therefore, the circuit structure of the longitudinal stacking of the second wafer 200a with the first wafer 100a and the third wafer 300a is relatively simple and easy to realize. Specifically, the source end 251 of the transistor structure faces the first wafer 100a, making the electrical connection route between the source end 251 and the bit line layer 140 in the first wafer 100a simple and easy to realize. The drain end 253 of the transistor structure faces the third wafer 300a, making the electrical connection route between the drain end 253 and the storage capacitor in the third wafer 300a simple and easy to realize.

[0053] In this embodiment, in the second wafer 200a, the transistor structure further includes: a channel layer 252 located between the source end 251 and the drain end 253; a gate oxide layer 270 covering the channel layer 252; and a gate layer 281 covering the gate oxide layer 270.

[0054] The channel layer 252, the source end 251 and the drain end 253 at both ends of the channel layer 252, the gate oxide layer 270 covering the channel layer 252, and the gate layer 281 covering the gate oxide layer 270 constitute the basic functions of the transistor structure, and the transistor is a field effect transistor.

[0055] In this embodiment, the transistor structures are arrayed in a plane parallel to the first wafer 100a. The source end 251, the channel layer 252, and the drain end 253 are formed as a single body, and the orthographic projection on the plane parallel to the first wafer 100a is circular or polygonal.

[0056] In this embodiment, the second wafer 200a further includes: an isolation dielectric layer 274 covering the source end 251, the gate layer 281, and the drain end 253 of the transistor structure.

[0057] The isolation dielectric layer 274 is used to achieve electrical isolation between adjacent transistor structures.

[0058] In this embodiment, the material of the isolation dielectric layer 274 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, and silicon carbon nitride oxynitride.

[0059] Correspondingly, in this embodiment, the second interconnect structure 291 penetrates through the isolation dielectric layer 274 on the source end 251 and contacts the source end 251.

[0060] The second interconnect structure 291 penetrates through the isolation dielectric layer 274 on the source end 251 to electrically connect one end to the source end 251 and the other end to the outside of the second wafer 200a.

[0061] Correspondingly, in this embodiment, the third interconnect structure 293 penetrates through the isolation dielectric layer 274 on the drain end 253 and contacts the drain end 253.

[0062] The third interconnect structure 293 penetrates through the isolation dielectric layer 274 on the drain end 253 to electrically connect one end to the drain end 253 and the other end to the outside of the second wafer 200a.

[0063] In this embodiment, the second wafer 200a further includes: a protective layer 261 covering the sidewalls and the top of the source end 251.

[0064] In the process of manufacturing the second wafer 200a, the protective layer 261 covers the sidewalls and the top of the source end 251, the isolation dielectric layer 274 covers the sidewalls and the top of the drain end 253, and the channel layer 252 is exposed, so that the gate oxide layer 270 and the gate layer 281 are only formed at the position of the channel layer 252, and the source end 251 and the drain end 253 are well protected during the manufacturing process.

[0065] In the process of manufacturing the second wafer 200a, after forming the protective layer 261, a complete transistor structure is formed, and then the surface of the process platform of the second wafer 200a is filled with a dielectric material to obtain the isolation dielectric layer 274 as an integrated film layer. Therefore, in this embodiment, the isolation dielectric layer 274 covers the protective layer 261.

[0066] Correspondingly, in this embodiment, the second interconnect structure 291 also penetrates through the protective layer 261 to contact the source end 251.

[0067] The third wafer 300a is used to form a storage capacitor (Capacitor, CAP) structure in the memory.

[0068] Specifically, in this embodiment, the storage capacitor of the memory is independently formed only in the third wafer 300a.

[0069] The storage capacitor is used to form the storage unit of the memory and is the core component of the storage unit. Specifically, the storage capacitor includes two layers of electrode plates respectively connected to the capacitor plate line 370 and the capacitor bit line 351, and a storage material layer 360 located between the two layers of electrode plates. The capacitor plate line 370 is equivalent to the capacitor word line in the storage capacitor. The capacitor plate line 370 is used to apply a voltage to control the state of the storage material layer. The capacitor bit line 351 is used to transmit data signals, such as the data read and written. The storage material layer 360 is used as the storage medium. Optionally, the two layers of electrode plates respectively connected to the capacitor plate line 370 and the capacitor bit line 351 are integrally formed with the capacitor plate line 370 and the capacitor bit line 351.

[0070] Specifically, in this embodiment, the write operation includes: setting the capacitor bit line 351 to a low level and the capacitor plate line 370 to a high level to write the data "0"; setting the capacitor bit line 351 to a high level and the capacitor plate line 370 to a low level to write the data "1". The read operation includes: setting the capacitor bit line 351 to a low level, and the capacitor plate line 370 changing from a low level to a high level. The charge stored in the storage capacitor is released through the capacitor bit line 351, generating a voltage change. The change in the voltage of the capacitor bit line 351 is detected by a sense amplifier to determine whether the data in the storage unit is "0" or "1".

[0071] In this embodiment, the first wafer 100a, the second wafer 200a, and the third wafer 300a are bonded to each other to form a memory. The method of forming a memory by stacking multiple wafers is beneficial to increasing the storage density. Moreover, distributing the bit line layer 140, the transistor structure, and the storage capacitor of the memory on different wafers is beneficial to preventing the structural layout on each wafer from being too dense, beneficial to reducing the manufacturing difficulty of each wafer, and while achieving an increase in storage density, beneficial to avoiding the reduction of the critical dimensions of various devices in the memory. At the same time, by performing the manufacturing processes of the bit line layer 140, the transistor structure, and the storage capacitor on multiple wafers respectively, the segmented manufacturing process is beneficial to reducing the impact of heat treatment (Thermal) on the devices. In particular, it effectively avoids the cumulative heat impact on the transistor structure during the manufacturing process of the storage capacitor, reduces the impact of the thermal budget of the storage capacitor manufacturing process on the transistor structure, thereby reducing the probability of performance degradation (such as impurity diffusion, lattice structure change, etc.) of the transistor structure due to excessive thermal budget. And, since the transistor structure is independently designed on the second wafer 200a, a better transistor density can be provided, enabling a single second wafer 200a to control multiple array wafers simultaneously, which is beneficial to achieving a lower word line delay, and further beneficial to achieving a higher frequency and a faster response speed of the memory. In addition, by performing the manufacturing processes of the bit line layer 140, the transistor structure, and the storage capacitor on multiple wafers respectively, the manufacturing processes of the bit line layer 140, the transistor structure, and the storage capacitor can be carried out on different wafers simultaneously, which is beneficial to improving the memory formation efficiency, thereby accelerating the product shipment speed.

[0072] In this embodiment, in the third wafer 300a, a fourth interconnect structure 390 is formed on the capacitive bit line 351 of the storage capacitor and is in electrical connection therewith. The fourth interconnect structure 390 contacts the third interconnect structure 293 for electrical connection.

[0073] The fourth interconnect structure 390 is used to realize the electrical connection between the capacitive bit line 351 and the outside.

[0074] In this embodiment, the material of the fourth interconnect structure 390 includes tungsten, copper, or aluminum.

[0075] In an embodiment of the present application, in the third wafer 300a, the capacitor plate lines 370 extend horizontally and are arranged in parallel at intervals in the longitudinal direction. The capacitor plate lines 370 horizontally surround the capacitive bit line 351. The capacitive bit line 351 extends longitudinally through multiple capacitor plate lines 370. A storage material layer 360 is formed between the capacitive bit line 351 and the capacitor plate lines 370. The storage material layer 360 serves as the capacitive dielectric layer of the storage capacitor.

[0076] That is, a portion near the intersection of the capacitor plate line 370 and the capacitor bit line 351 and the storage material layer 360 located therebetween form a storage unit, and the storage units are distributed in a three-dimensional array on the third wafer 300a.

[0077] In this embodiment, the materials of the capacitor plate line 370 and the capacitor bit line 351 are metal materials. As an example, in this embodiment, the materials of the capacitor plate line 370 and the capacitor bit line 351 are tungsten.

[0078] It should be noted that in this embodiment, by etching a stepped structure on the side of the third wafer 300a, the capacitor plate line 370 of each layer is exposed, and the signal lines of the capacitor plate line 370 of each layer are respectively led out to achieve independent control of the capacitor plate line 370 of each layer. The stepped structure is adopted in this embodiment to lead out the signal lines, which can reduce the length and complexity of the signal lines and improve the integration density.

[0079] In this embodiment, the material of the storage material layer 360 includes ferroelectric materials.

[0080] Correspondingly, in this embodiment, the storage capacitor is a ferroelectric capacitor (Ferroelectric Capacitor, FECAP), and the formed memory is a ferroelectric random access memory (Ferroelectric Random Access Memory, FeRAM). FeRAM uses a ferroelectric material (such as lead zirconate titanate PZT) as the storage medium. The ferroelectric material has the characteristic of spontaneous polarization, that is, under the action of an external electric field, the atoms or ions inside the material will displace to form a polarized state, and the polarized state can still be maintained even if the external electric field is removed. This characteristic enables FeRAM to have non-volatility. FeRAM realizes non-volatile storage by utilizing the polarization characteristic of the ferroelectric material, and has advantages such as high-speed reading and writing, high durability, and low power consumption, and is suitable for application scenarios with various high-performance storage requirements.

[0081] In this embodiment, the third wafer further includes: a third substrate 300.

[0082] The third substrate 300 is used to provide a process operation basis for forming the third wafer 30a.

[0083] As an example, in this embodiment, the material of the third substrate 300 is silicon, but it is not limited thereto. In some embodiments, the material of the third substrate is an insulating substrate.

[0084] Correspondingly, in this embodiment, the capacitor bit line 351 is located on the third substrate 300.

[0085] In this embodiment, the capacitor bit line 351 also extends into a part of the thickness of the third substrate 300.

[0086] The capacitive bit line 351 also extends in the third substrate 300 with a partial thickness, which is beneficial to ensuring that the capacitive bit line 351 completely passes through the capacitor plate line 370.

[0087] In this embodiment, a first isolation layer 310 is located between longitudinally adjacent capacitor plate lines 370.

[0088] The first isolation layer 310 is used to achieve electrical isolation between longitudinally adjacent capacitor plate lines 370.

[0089] In this embodiment, the material of the first isolation layer 310 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. As an example, in this embodiment, the material of the first isolation layer 310 is silicon oxide.

[0090] Correspondingly, in this embodiment, the storage material layer 360 is also located between the first isolation layer 310 and the capacitor plate line 370.

[0091] In this embodiment, a second isolation layer 340 is also formed between the capacitive bit line 351 and the third substrate 300.

[0092] The second isolation layer 340 is used to achieve electrical isolation between the capacitive bit line 351 and the third substrate 300.

[0093] In this embodiment, the material of the second isolation layer 340 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. As an example, in this embodiment, the material of the second isolation layer 340 is silicon oxide.

[0094] In this embodiment, the third wafer 300a further includes: a fourth dielectric layer 380 covering the first isolation layer 310 and the capacitive bit line 351.

[0095] The fourth dielectric layer 380 is used to achieve electrical isolation between adjacent fourth interconnect structures 390.

[0096] In this embodiment, the material of the fourth dielectric layer 380 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride.

[0097] Correspondingly, in this embodiment, the fourth interconnect structure 390 penetrates the fourth dielectric layer 380 on the capacitive bit line 351 and contacts the capacitive bit line 351 to be electrically connected to the capacitive bit line 351.

[0098] Figures 2 to 47 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the memory of the present invention.

[0099] With reference to Figures 2 to 10, wherein, Figure 10 (a) is Figure 10 the top view of (b), forming the first wafer 100a, and the first wafer 100a includes a plurality of bit line layers 140.

[0100] The first wafer 100a is used to form the structure of the bit line (BL) in the memory.

[0101] Specifically, in this embodiment, the bit line layer 140 of the memory is independently formed only in the first wafer 100a.

[0102] The bit line layer 140 is used as the bit line of the memory, which is the key signal line for realizing the data read and write functions of the memory, and is responsible for transmitting and detecting the charge change in the storage unit, so as to realize the storage and reading of data.

[0103] Specifically, in the read operation, the bit line is used to detect the charge change in the storage unit. When the voltage of the plate line (PL) changes, the charge in the storage unit can be released through the subsequently formed capacitive bit line. When the transistor structure is turned on, a voltage change can be generated on the bit line. By comparing the change in the bit line voltage, it can be determined whether the data stored in the storage unit is "0" or "1"; in the write operation, the bit line is used to apply a specific voltage to the storage unit to write "0" or "1" data. For example, when writing data "0", the bit line is set to a low level and the plate line is set to a high level. When writing data "1", the bit line is set to a high level and the plate line is set to a low level.

[0104] In this embodiment, the material of the bit line layer 140 includes conductive materials such as tungsten, copper, and / or titanium nitride.

[0105] In this embodiment, in the step of forming the first wafer 100a, a first interconnect structure 180 electrically connected to the bit line layer 140 is formed on the bit line layer 140.

[0106] The first interconnect structure 180 is used to realize the electrical connection between the bit line layer 140 and the outside.

[0107] In this embodiment, the material of the first interconnect structure 180 includes tungsten, copper, or aluminum.

[0108] In this embodiment, in the step of forming the first wafer 100a, a plurality of bit line layers 140 extend in the same direction and are arranged in parallel, and a plurality of first interconnect structures 180 arranged along the extension direction of the bit line layer 140 are formed on each bit line layer 140.

[0109] Specifically, as Figure 10As shown in (a), a plurality of first interconnect structures 180 arranged along the extending direction of the bit line layer 140 are formed on each bit line layer 140. Then, each bit line layer 140 can control a plurality of storage capacitors (i.e., storage units) arranged in the direction parallel to the extending direction of the bit line layer 140.

[0110] In a memory, storage units are usually arranged in a matrix form on a plane. Bit lines and word lines (WL) are respectively used to control the columns and rows of storage units through transistor structures. Bit lines connect all storage units in the same column, while word lines connect storage units in the same row. Therefore, one bit line layer 140 can control a plurality of storage units. However, during each operation, the specific storage unit to be operated is determined by the selection of the word line, thereby improving the storage density while ensuring the flexibility and efficiency of data access.

[0111] In an embodiment of the present application, the memory is a 1TnC ferroelectric memory. Each bit line layer 140 can control a plurality of subsequently formed capacitive bit lines arranged in the direction parallel to the extending direction of the bit line layer 140 and connected to the corresponding bit line layer 140 through transistors, and further control a plurality of storage cell strings. The capacitive bit lines are arrayed in the plane parallel to the first wafer 100a and extend in the direction perpendicular to the first wafer 100a. The subsequently formed capacitor plate lines extend in the plane parallel to the first wafer 100a and are stacked in the direction perpendicular to the first wafer 100a. A storage cell string includes a plurality of storage capacitors arranged in the direction perpendicular to the first wafer 100a, and the capacitance dielectric of the storage capacitor is a ferroelectric material.

[0112] Specifically, referring to Figure 2 , the step of forming the first wafer 100a includes: providing a first substrate 100. The first substrate 100 is used to provide a process operation basis for forming the first wafer 100a.

[0113] As an example, in this embodiment, the material of the first substrate 100 is silicon. However, it is not limited thereto. In some embodiments, the first substrate 100 is a substrate that is at least surface-insulated, such as a silicon substrate with an insulating layer formed on its surface, or an insulating substrate, depending on the specific situation.

[0114] Referring to Figures 2 to 4 , a plurality of spaced-apart bit line layers 140 are formed on the first substrate 100.

[0115] Specifically, referring to Figure 2 , the step of forming a plurality of spaced-apart bit line layers 140 on the first substrate 100 includes: forming a bit line material layer 110 covering the first substrate 100.

[0116] The bit line material layer 110 is used to form the bit line layer 140.

[0117] In this embodiment, a first mask layer 130 and a first dielectric anti-reflection layer 120 located between the first mask layer 130 and the bit line material layer 110 are further formed on the bit line material layer 110 .

[0118] The first mask layer 130 is used as an etching mask for patterning the bit line material layer 110 , and the first dielectric anti-reflection layer 120 is used to reduce light reflection and improve photolithography accuracy.

[0119] In this embodiment, the first mask layer 130 includes an advanced patterning film (APF), a hard mask layer located on the advanced patterning film (for example, a silicon oxynitride layer, a spin-on hard mask (SOH) located on the silicon oxynitride layer, and a silicon oxynitride layer located on the spin-on hard mask), and a photoresist layer (PR) located on the hard mask layer.

[0120] As an example, in this embodiment, the material of the first dielectric anti-reflection layer 120 is silicon oxynitride.

[0121] Combined with reference Figure 3 and Figure 4 , patterning the bit line material layer 110 and the first substrate 100 of a partial thickness, forming a first protruding structure 160 protruding from the first substrate 100 of the remaining thickness, and a plurality of bit line layers 140 spaced apart from each other on the first protruding structure 160, and adjacent first protruding structures 160 enclosing a first groove 101.

[0122] The first protruding structures 160 are used to support the spaced bit line layers 140 . Accordingly, adjacent first protruding structures 160 surround a first trench 101 to separate adjacent bit line layers 140 .

[0123] Specifically, in this embodiment, the step of patterning the bit line material layer 110 and the first substrate 100 of a partial thickness includes: referring to Figure 3 , patterning the first mask layer 130; referring to Figure 4 , the bit line material layer 110 and the partial thickness of the first substrate 100 are patterned along the patterned first mask layer 130 to form a first protruding structure 160 protruding from the remaining thickness of the first substrate 100, and a plurality of bit line layers 140 spaced apart from each other on the first protruding structure 160.

[0124] Accordingly, in this embodiment, in the step of patterning a partial thickness of the first substrate 100 , the first dielectric anti-reflection layer 120 is also patterned.

[0125] refer to Figure 5, after forming the bit line material layer 110 covering the first substrate 100, it further includes: removing the first mask layer 130 to prepare for subsequent processes.

[0126] Reference Figure 6 , before forming the first dielectric layer covering the plurality of bit line layers 140 subsequently, it further includes: forming a first repair layer 150 covering each surface of the first trench 101.

[0127] The first repair layer 150 is used to repair the surface defects of the first trench 101. Especially for the hole defects at the bottom corner of the first trench 101, it can play a good repair role.

[0128] In this embodiment, the first repair layer 150 covering each surface of the first trench 101 is formed by atomic layer deposition (ALD) process.

[0129] The first repair layer 150 formed by atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the first repair layer 150 can conformally cover the bottom and side walls of the first trench 101 well, and is beneficial to forming a first repair layer 150 with better film layer quality, which is beneficial to improving the repair effect of the first repair layer 150.

[0130] As an example, in this embodiment, the material of the first repair layer 150 includes silicon oxide.

[0131] Reference Figure 7 , forming a first dielectric layer 170 covering the plurality of bit line layers 140.

[0132] The first dielectric layer 170 is used to provide a process operation platform for the subsequent formation of the first interconnect structure 180.

[0133] In this embodiment, the material of the first dielectric layer 170 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon nitride silicon and carbon oxynitride silicon. As an example, the material of the first dielectric layer 170 is silicon oxide. Correspondingly, in this embodiment, the first dielectric layer 170 and the first repair layer 150 are an integral structure.

[0134] In this embodiment, the first dielectric layer 170 covering the plurality of bit line layers 140 is formed by chemical vapor deposition (CVD) process.

[0135] The chemical vapor deposition process is simple to operate and has low cost.

[0136] In this embodiment, in the step of forming the first dielectric layer 170 covering multiple bit line layers 140, the first dielectric layer 170 also fills the first trench 101.

[0137] The first dielectric layer 170 also fills the first trench 101 to obtain a process platform with better flatness and simultaneously achieve electrical isolation between adjacent bit line layers 140.

[0138] In this embodiment, in the step of forming the first dielectric layer 170 covering multiple bit line layers 140, an air gap is formed in the first dielectric layer 170 in the first trench 101.

[0139] The first dielectric layer 170 is formed by filling the first trench 101 using chemical vapor deposition (CVD) process. Since holes are easily formed during the operation process, an air gap is formed in the first dielectric layer 170 in the first trench 101, which is beneficial to reducing the parasitic capacitance between adjacent bit line layers 140.

[0140] With reference to Figures 8 to 10 , a first interconnect structure 180 is formed that penetrates the first dielectric layer 170 on the bit line layer 140 and contacts the bit line layer 140.

[0141] The first interconnect structure 180 penetrates the first dielectric layer 170 to electrically connect one end to the bit line layer 140 and the other end to the outside of the first wafer 100a.

[0142] Specifically, with reference to Figure 8 , the step of forming the first interconnect structure 180 that penetrates the first dielectric layer 170 on the bit line layer 140 and contacts the bit line layer 140 includes: forming a first via hole 102 that penetrates the first dielectric layer 170 on the bit line layer 140 and exposes the surface of the bit line layer 140.

[0143] The first via hole 102 is used to provide a spatial position for the formation of the first interconnect structure 180.

[0144] With reference to Figure 9 , before filling the first via hole 102 subsequently, it further includes: removing a part of the width of the first dielectric layer 170 at the opening position of the first via hole 102 to enlarge the opening size of the first via hole 102.

[0145] Removing a part of the width of the first dielectric layer 170 at the opening position of the first via hole 102 to enlarge the opening size of the first via hole 102 is beneficial to increasing the process window and making it easier to fill the first via hole 102 better subsequently.

[0146] With reference to Figure 10 , fill the first via hole 102 to form the first interconnect structure 180.

[0147] Combined reference Figures 11 to 30 to form a second wafer 200a, and bond the second wafer 200a to the first wafer 100a. The second wafer 200a includes a plurality of transistor structures, and the source end 251 of the transistor structure is interconnected with the bit line layer 140.

[0148] The second wafer 200a is used to form the transistor structures in the memory.

[0149] Specifically, in this embodiment, the transistor structures of the memory are independently formed only in the second wafer 200a.

[0150] The transistor structure is used to connect the word line (Word Line, WL) of the memory, and is used to control the access to the memory cell or the memory cell string. Among them, the gate layer in the transistor structure is connected to the word line or formed integrally with the word line. The source end 251 in the transistor structure is connected to the bit line layer 140, and the drain end 253 in the transistor structure is connected to the memory capacitor via the capacitive bit line.

[0151] Specifically, the word line can control the on and off of the transistor structure, and specific memory cells or memory cell strings can be selected for read and write operations by the cross selection of the word line and the bit line.

[0152] In this embodiment, in the step of forming the second wafer 200a and bonding the second wafer 200a to the first wafer 100a, a second interconnect structure 291 electrically connected thereto is formed on the source end 251 of the transistor structure, and a third interconnect structure 293 electrically connected thereto is formed on the drain end 253 of the transistor structure. The second interconnect structure 291 contacts the first interconnect structure 180 for electrical connection.

[0153] The second interconnect structure 291 is used to electrically connect to the first interconnect structure 180 to realize the electrical connection between the source end 251 and the bit line layer 140. The third interconnect structure 293 is used to realize the electrical connection between the drain end 253 and the outside.

[0154] In this embodiment, the material of the second interconnect structure 291 includes tungsten, copper or aluminum; the material of the third interconnect structure 293 includes tungsten, copper or aluminum.

[0155] In this embodiment, in the step of forming the second wafer 200a and bonding the second wafer 200a to the first wafer 100a, the source end 251 and the drain end 253 of the transistor structure are longitudinally opposite to each other. The source end 251 of the transistor structure faces the first wafer 100a. Correspondingly, the drain end 253 of the transistor structure faces away from the first wafer 100a, that is, the source end 251 to the drain end 253 of the transistor extends vertically and is distributed, and the transistor structure is a vertical transistor.

[0156] The source end 251 and the drain end 253 of the transistor structure face away from each other longitudinally, making it easy to achieve electrical connections of the source end 251 and the drain end 253 with the outside of the second wafer 200a longitudinally. As a result, the circuit structure of the longitudinal stacking of the second wafer 200a with the first wafer 100a and the third wafer is relatively simple and easy to implement. Specifically, the source end 251 of the transistor structure faces the first wafer 100a, making the electrical connection route between the source end 251 and the bit line layer 140 in the first wafer 100a simple and easy to implement. The drain end 253 of the transistor structure faces away from the second wafer 200a, that is, the subsequent drain end 253 faces the third wafer, making the electrical connection route between the drain end 253 and the storage capacitor in the third wafer simple and easy to implement.

[0157] Reference Figure 11 , the steps of forming the second wafer 200a include: providing a second substrate 200.

[0158] The second substrate 200 is used to provide a process operation basis for forming the second wafer 200a.

[0159] As an example, in this embodiment, the material of the second substrate 200 is silicon.

[0160] In this embodiment, a second mask layer 220 and a second dielectric antireflection layer 210 located between the second mask layer 220 and the second substrate 200 are further formed on the second substrate 200.

[0161] The second mask layer 220 is used as an etching mask for patterning the second substrate 200, and the second dielectric antireflection layer 210 is used to reduce light reflection and improve lithography accuracy.

[0162] In this embodiment, the second mask layer 220 includes an advanced film, a hard mask layer on the advanced film (for example, a silicon oxynitride layer, a spin-on mask on the silicon oxynitride layer, and a silicon oxynitride layer on the spin-on mask), and a photoresist layer on the hard mask layer.

[0163] As an example, in this embodiment, the material of the second dielectric antireflection layer 210 is silicon oxynitride.

[0164] Combined with reference Figures 11 to 12 , pattern a part of the thickness of the second substrate 200 to form a second protrusion structure 250 protruding from the remaining thickness of the second substrate 200. Adjacent second protrusion structures 250 enclose a second trench 201. The second protrusion structure 250 includes a source end 251, a channel layer 252, and a drain end 253 in sequence from the top to the bottom.

[0165] The second protrusion structure 250 is used as the basis for forming the transistor structure, the second trench 201 is used to separate adjacent transistor structures, the channel layer 252, the source end 251 and the drain end 253 at both ends of the channel layer 252 are the basic functional components of the transistor structure, and the transistor is a field effect transistor.

[0166] In this embodiment, the transistor structures are distributed in an array on a plane parallel to the first wafer 100a. The source end 251, the channel layer 252, and the drain end 253 are formed integrally, and their orthographic projections on a plane parallel to the first wafer 100a are circular or polygonal.

[0167] Specifically, in this embodiment, the steps of patterning the second substrate 200 with a partial thickness include: referring to Figure 11 , patterning the second mask layer 220; referring to Figure 12 , patterning the second substrate 200 with a partial thickness along the patterned second mask layer 220 to form the second protrusion structure 250 protruding from the second substrate 200 with the remaining thickness.

[0168] Exemplarily, the pattern of the second mask layer 220 includes circular or polygonal shapes distributed in an array, the second protrusion structure 250 is in a corresponding columnar shape, and the transistor structure is a vertical transistor.

[0169] Correspondingly, in this embodiment, in the steps of patterning the second substrate 200 with a partial thickness, the second dielectric antireflection layer 210 is also patterned.

[0170] Referring to Figure 13 , after patterning the second substrate 200 with a partial thickness, it further includes: removing the second mask layer 220 to prepare for subsequent processes.

[0171] Continuing to refer to Figure 13 , before subsequently forming the second protective material layer that fills the second trench 201 and covers the second protrusion structure 250, it further includes: forming a second repair layer 230 that covers each surface of the second trench 201.

[0172] The second repair layer 230 is used to repair the surface defects of the second trench 201. Especially for the hole defects at the bottom corners of the second trench 201, it can play a good repair role.

[0173] In this embodiment, the second repair layer 230 covering each surface of the second trench 201 is formed by an atomic layer deposition process.

[0174] The second repair layer 230 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, enabling the second repair layer 230 to conformally cover the bottom and side walls of the second trench 201 well, facilitating the formation of the second repair layer 230 with better film quality, and being conducive to improving the repair effect of the second repair layer 230.

[0175] In other embodiments, it is also possible to form a second repair layer covering each surface of the second trench by an oxidation process.

[0176] As an example, in this embodiment, the material of the second repair layer 230 includes silicon oxide.

[0177] With reference to Figures 14 to 18 , before forming the gate oxide layer covering the side walls of the second protrusion structure 250 at the position of the channel layer 252 subsequently, it further includes: forming a first protection layer 261 covering the side walls of the second protrusion structure 250 at the position of the source end 251, and a second protection layer 240 covering the side walls of the second protrusion structure 250 at the position of the drain end 253.

[0178] The first protection layer 261 is used to protect the side walls of the second protrusion structure 250 at the position of the source end 251, the second protection layer 240 is used to protect the side walls of the second protrusion structure 250 at the position of the drain end 253, and the first protection layer 261 and the second protection layer 240 expose the side walls of the second protrusion structure 250 at the position of the channel layer 252, leaving a space position for the subsequent formation of the gate oxide layer and the gate electrode layer.

[0179] In this embodiment, the first protection layer 261 and the second protection layer 240 are insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon nitride silicon, and carbon oxynitride silicon. As an example, in this embodiment, the material of the first protection layer 261 is silicon nitride, and the material of the second protection layer 240 is silicon oxide.

[0180] Specifically, with reference to Figure 14 , the steps of forming a first protection layer 261 covering the side walls of the second protrusion structure 250 at the position of the source end 251 and a second protection layer 240 covering the side walls of the second protrusion structure 250 at the position of the drain end 253 include: forming a second protection material layer 241 that fills the second trench 201 and covers the second protrusion structure 250.

[0181] The second protection material layer 241 is used to form the second protection layer 240.

[0182] Correspondingly, in this embodiment, the material of the second protection material layer 241 is silicon oxide. Correspondingly, in this embodiment, the second protection material layer 241 and the second repair layer 230 are of an integral structure.

[0183] With reference toFigure 15 , a second protective material layer 241 with a partial thickness removed, exposing a second protrusion structure 250 at the position of the source end 251.

[0184] Removing a second protective material layer 241 with a partial thickness to expose a second protrusion structure 250 at the position of the source end 251 prepares for the formation of the second protective layer 240.

[0185] In this embodiment, in the step of removing a second protective material layer 241 with a partial thickness, a partial second protective material layer 241 on the top of the second protrusion structure 250 is retained to protect the top of the second protrusion structure 250.

[0186] Reference Figure 16 , a first protective material layer 260 is formed to cover the top and side walls of the exposed second protrusion structure 250 and the top of the second protective material layer 241 with the remaining thickness.

[0187] The first protective material layer 260 is used to form the first protective layer 261.

[0188] Correspondingly, in this embodiment, the material of the first protective material layer 260 is silicon nitride.

[0189] Reference Figure 17 , the first protective material layer 260 on the top of the second protective material layer 241 with the remaining thickness is removed, and the remaining first protective material layer 260 is retained as the first protective layer 261.

[0190] Removing the first protective material layer 260 on the top of the second protective material layer 241 with the remaining thickness prepares for the subsequent removal of a second protective material layer 241 with a partial thickness.

[0191] In this embodiment, a dry etching process is used to remove the first protective material layer 260 on the top of the second protective material layer 241 with the remaining thickness.

[0192] The dry etching process is an anisotropic etching process with the characteristics of anisotropic etching. Its longitudinal etching rate is much greater than the lateral etching rate, and it can obtain a quite accurate pattern conversion, forming a first protective layer 261 with better morphology quality and dimensional accuracy.

[0193] In this embodiment, the step of removing the first protective material layer 260 on the top of the second protective material layer 241 with the remaining thickness includes: forming a third mask layer 221 on the first protective material layer 260 on the top of the second protrusion structure 250, and the third mask layer 221 exposes the first protective material layer 260 on the side wall of the second protrusion structure 250; patterning the first protective material layer 260 along the third mask layer 221 to remove the first protective material layer 260 on the top of the second protective material layer 241 with the remaining thickness.

[0194] It should be noted that in this embodiment, an anisotropic dry etching process is used to pattern the first protective material layer 260 along the pattern of the third mask layer 221. Its longitudinal etching rate is much greater than the lateral etching rate. Therefore, while removing the first protective material layer 260 on the top of the remaining thickness of the second protective material layer 241, the first protective material layer 260 on the sidewalls of the second protrusion structure 250 can be retained.

[0195] Reference Figure 18 , a part of the thickness of the second protective material layer 241 is removed to expose the sidewalls of the second protrusion structure 250 at the position of the channel layer 252, and the remaining second protective material layer 241 is retained as the second protective layer 240.

[0196] A part of the thickness of the second protective material layer 241 is removed to expose the sidewalls of the second protrusion structure 250 at the position of the channel layer 252, preparing for the subsequent formation of the gate oxide layer.

[0197] In this embodiment, a dry etching process is used to remove a part of the thickness of the second protective material layer 241.

[0198] The dry etching process has the characteristics of anisotropic etching, which is beneficial to reducing the damage to the sidewalls of the second protrusion structure 250 while removing a part of the thickness of the second protective material layer 241. Moreover, the dry etching process can better control the process parameters, has a high process controllability, and is easy to accurately control the thickness of the removed second protective material layer 241.

[0199] In this embodiment, a part of the thickness of the second protective material layer 241 is removed along the third mask layer 221.

[0200] Continue to refer to Figure 18 , after removing a part of the thickness of the second protective material layer 241, it further includes: removing the third mask layer 221 to prepare for the subsequent manufacturing process.

[0201] Reference Figure 19 , a gate oxide layer 270 covering the sidewalls of the second protrusion structure 250 at the position of the channel layer 252 is formed.

[0202] The gate oxide layer 270 is a basic functional component of the transistor structure.

[0203] In this embodiment, an oxidation process is used to form the gate oxide layer 270 covering the sidewalls of the second protrusion structure 250 at the position of the channel layer 252.

[0204] The oxidation process can selectively form the gate oxide layer 270 on the sidewalls of the second protrusion structure 250 at the position of the channel layer 252. The formed film layer has good quality, and there is no need for additional etching steps. The process flow is simple and the process efficiency is high.

[0205] Combined with referenceFigure 20 and Figure 21 , a gate layer 281 covering the gate oxide layer 270 is formed.

[0206] The gate layer 281 is a basic functional component of the transistor structure.

[0207] Specifically, referring to Figure 20 , the steps of forming the gate layer 281 covering the gate oxide layer 270 include: forming a first protective layer 261 covering the top and sidewalls of the second protrusion structure 250, a gate oxide layer 270, and a gate material layer 280 covering the top of the second protective layer 240.

[0208] The gate material layer 280 is used to form the gate layer 281.

[0209] Referring to Figure 21 , the first protective layer 261 covering the top and sidewalls of the second protrusion structure 250 and the gate material layer 280 covering the top of the second protective layer 240 are removed, and the gate material layer 280 covering the gate oxide layer 270 is retained as the gate layer 281.

[0210] In this embodiment, a dry etching process is used to remove the first protective layer 261 covering the top and sidewalls of the second protrusion structure 250 and the gate material layer 280 covering the top of the second protective layer 240.

[0211] The dry etching process is an anisotropic etching process with the characteristics of anisotropic etching. Its longitudinal etching rate is much greater than the lateral etching rate, so that the gate material layer 280 covering the top of the second protrusion structure 250 and the top of the second protective layer 240 can be removed in a maskless manner. At the same time, the first protective layer 261 on the sidewalls of the second protrusion structure 250 is moderately over-etched to be removed, and the gate material layer 280 covering the gate oxide layer 270 is retained as the gate layer 281.

[0212] Referring to Figure 22 , a second dielectric layer 290 filling the second trench 201 and covering the source end 251 is formed.

[0213] The second dielectric layer 290 is used to provide a process operation platform for the subsequent formation of the second interconnect structure 291.

[0214] In this embodiment, the material of the second dielectric layer 290 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride. As an example, the material of the second dielectric layer 290 is silicon oxide. Correspondingly, in this embodiment, the second dielectric layer 290 and the second protective layer 240 are an integral structure.

[0215] Correspondingly, in this embodiment, in the step of forming the second dielectric layer 290 that fills the second trench 201 and covers the source end 251, the second dielectric layer 290 covers the first protective layer 261 and the second protective layer 240.

[0216] In this embodiment, a third dielectric antireflection layer is further formed on the second dielectric layer 290.

[0217] The third dielectric antireflection layer is used to reduce the reflection of light, improve the lithography accuracy, and is also used as a bonding interface subsequently.

[0218] As an example, in this embodiment, the material of the third dielectric antireflection layer is silicon nitride. Using silicon nitride as the bonding surface is beneficial to making the bonding force relatively strong, and using silicon nitride can also inhibit the metal diffusion at the interface to ensure the device performance.

[0219] With reference to Figures 23 to 25 , a second interconnect structure 291 is formed that penetrates the top of the second protrusion structure 250 and contacts the source end 251 through the second dielectric layer 290.

[0220] The second interconnect structure 291 penetrates the second dielectric layer 290 to electrically connect one end to the source end 251 and the other end to the outside of the second wafer 200a.

[0221] Correspondingly, in this embodiment, in the step of forming the second interconnect structure 291 that penetrates the top of the second protrusion structure 250 and contacts the source end 251 through the second dielectric layer 290, the second interconnect structure 291 also penetrates the first protective layer 261 on the top of the second protrusion structure 250.

[0222] Specifically, with reference to Figure 23 , the step of forming the second interconnect structure 291 that penetrates the top of the second protrusion structure 250 and contacts the source end 251 through the second dielectric layer 290 includes: forming a second via 202 that penetrates the top of the second protrusion structure 250 and exposes the surface of the source end 251 through the second dielectric layer 290.

[0223] The second via 202 is used to provide a spatial position for the formation of the second interconnect structure 291.

[0224] Correspondingly, in this embodiment, in the step of forming the second via 202 that penetrates the top of the second protrusion structure 250 and exposes the surface of the source end 251 through the second dielectric layer 290, the third dielectric antireflection layer is also patterned to form the second via 202 that penetrates the third dielectric antireflection layer.

[0225] With reference to Figure 24 , before filling the second via 202 subsequently, it further includes: removing a part of the width of the second dielectric layer 290 at the opening position of the second via 202 to expand the opening size of the second via 202.

[0226] Remove the second dielectric layer 290 at a partial width at the opening position of the second through hole 202 to expand the opening size of the second through hole 202, which is beneficial to increasing the process window and making it easier to fill the second through hole 202 better subsequently.

[0227] Reference Figure 25 , fill the second through hole 202 to form the second interconnect structure 291.

[0228] Reference Figure 26 , before removing the remaining thickness of the second substrate 200 to expose the drain end 253, contact the second interconnect structure 291 with the first interconnect structure 180 to achieve bonding, and expose the bottom of the second substrate 200.

[0229] Contact the second interconnect structure 291 with the first interconnect structure 180 to achieve bonding, which is used to use the first wafer 100a as a process support for forming the second wafer 200a, and expose the bottom of the second substrate 200 to use the bottom of the second substrate 200 as a process operation platform.

[0230] Reference Figure 27 , remove the remaining thickness of the second substrate 200 to expose the drain end 253.

[0231] Remove the remaining thickness of the second substrate 200 to expose the drain end 253, preparing for the subsequent formation of the third interconnect structure 293.

[0232] Correspondingly, in this embodiment, in the step of removing the remaining thickness of the second substrate 200 to expose the drain end 253, part of the thickness of the second protective layer 240 is also removed to obtain a process platform with better flatness.

[0233] Reference Figure 28 , form a third dielectric layer 292 covering the drain end 263.

[0234] The third dielectric layer 292 is used to provide a process platform for the formation of the third interconnect structure 293.

[0235] Correspondingly, in this embodiment, in the step of forming the third dielectric layer 292 covering the drain end 253, the third dielectric layer 292 also covers the remaining thickness of the second protective layer 240.

[0236] In this embodiment, the material of the third dielectric layer 292 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, and carbon oxynitride. As an example, the material of the third dielectric layer 292 is silicon oxide. Correspondingly, in this embodiment, the third dielectric layer 292 and the second dielectric layer 290 are of an integral structure.

[0237] Combined with referenceFigures 28 to 30 A third interconnect structure 293 is formed to penetrate through the third dielectric layer 292 on the drain end 253 and be in contact with the drain end 253.

[0238] The third interconnect structure 293 penetrates through the third dielectric layer 292 to electrically connect one end to the drain end 253 and the other end to the outside of the second wafer 200a.

[0239] Specifically, referring to Figure 28 The steps of forming the third interconnect structure 293 that penetrates through the third dielectric layer 292 on the drain end 253 and is in contact with the drain end 253 include: forming a third dielectric layer 292 that penetrates through the top of the drain end 253 and exposing a third via hole 203 on the surface of the drain end 253.

[0240] The third via hole 203 is used to provide a spatial position for the formation of the third interconnect structure 293.

[0241] Referring to Figure 29 Before filling the third via hole 203 subsequently, it further includes: removing a part of the width of the third dielectric layer 292 at the opening position of the third via hole 203 to enlarge the opening size of the third via hole 203.

[0242] Removing a part of the width of the third dielectric layer 292 at the opening position of the third via hole 203 to enlarge the opening size of the third via hole 203 is beneficial to increasing the process window and making it easier to fill the third via hole 203 well subsequently.

[0243] Referring to Figure 30 Fill the third via hole 203 to form the third interconnect structure 293.

[0244] Combined with referring to Figures 31 to 47 A third wafer 300a is formed and bonded to the second wafer 200a. The third wafer 300a includes a plurality of storage capacitors. Two plates of the storage capacitor are respectively connected to a capacitor plate line 370 and a capacitor bit line 351, and the capacitor bit line 351 is interconnected with the drain end 253 of the transistor structure.

[0245] The third wafer 300a is used to form a storage capacitor (Capacitor, CAP) structure in the memory.

[0246] Specifically, in this embodiment, the storage capacitor of the memory is independently formed only in the third wafer 300a.

[0247] The storage capacitor is used to form the storage unit of the memory and is the core component of the storage unit. Specifically, the storage capacitor includes a capacitance plate line 370 and a capacitance bit line 351 that are respectively connected as two-layer electrode plates, and a storage material layer 360 located between the two-layer electrode plates. The capacitance plate line 370 is equivalent to the capacitance word line in the storage capacitor. The capacitance plate line 370 is used to apply a voltage to control the state of the storage material layer. The capacitance bit line 351 is used to transmit data signals, such as the data read and written. The storage material layer 360 is used as the storage medium. Optionally, the two-layer electrode plates respectively connected to the capacitance plate line 370 and the capacitance bit line 351 are integrally formed with the capacitance plate line 370 and the capacitance bit line 351.

[0248] Specifically, in this embodiment, the write operation includes: setting the capacitance bit line 351 to a low level and the capacitance plate line 370 to a high level to write the data "0"; setting the capacitance bit line 351 to a high level and the capacitance plate line 370 to a low level to write the data "1". The read operation includes: setting the capacitance bit line 351 to a low level, and the capacitance plate line 370 changes from a low level to a high level. The charge stored in the storage capacitor is released through the capacitance bit line 351, generating a voltage change. The change in the voltage of the capacitance bit line 351 is detected by a sense amplifier to determine whether the data in the storage unit is "0" or "1".

[0249] In this embodiment, the first wafer 100a, the second wafer 200a, and the third wafer 300a are bonded to each other to form a memory. The method of forming a memory by stacking multiple wafers is beneficial to increasing the storage density. Moreover, distributing the bit line layer 140, the transistor structure, and the storage capacitor of the memory on different wafers is beneficial to preventing the structural layout on each wafer from being too compact, beneficial to reducing the manufacturing difficulty of each wafer, and beneficial to avoiding the reduction of the critical dimensions of various devices in the memory while achieving an increase in storage density. At the same time, by performing the manufacturing processes of the bit line layer 140, the transistor structure, and the storage capacitor on multiple wafers respectively, the segmented manufacturing process is beneficial to reducing the impact of heat treatment (Thermal) on the devices. In particular, it effectively avoids the cumulative heat impact on the transistor structure during the manufacturing process of the storage capacitor, reduces the impact of the thermal budget of the storage capacitor manufacturing process on the transistor structure, thereby reducing the probability of performance degradation (such as impurity diffusion, lattice structure change, etc.) of the transistor structure due to excessive thermal budget. And, since the transistor structure is independently designed on the second wafer 200a, a better transistor density can be provided, enabling a single second wafer 200a to control multiple array wafers (Array Wafer) simultaneously, which is beneficial to achieving a lower word line delay, and further beneficial to achieving a higher frequency and faster response speed of the memory. In addition, by performing the manufacturing processes of the bit line layer 140, the transistor structure, and the storage capacitor on multiple wafers respectively, the manufacturing processes of the bit line layer 140, the transistor structure, and the storage capacitor can be carried out simultaneously on different wafers, which is beneficial to improving the memory formation efficiency, thereby accelerating the product delivery speed.

[0250] In this embodiment, in the step of forming the third wafer 300a and bonding the third wafer 300a to the second wafer 200a, a fourth interconnect structure 390 is formed on the capacitive bit line 351 of the storage capacitor, and the fourth interconnect structure 390 is in contact with the third interconnect structure 293 for electrical connection.

[0251] The fourth interconnect structure 390 is used to realize the electrical connection between the capacitive bit line 351 and the outside.

[0252] In this embodiment, the material of the fourth interconnect structure 390 includes tungsten, copper, or aluminum.

[0253] In this embodiment, in the step of forming the third wafer 300a and bonding the third wafer 300a to the second wafer 200a, the drain end 253 of the transistor structure faces the third wafer 300a.

[0254] The drain end 253 of the transistor structure faces the third wafer 300a, making the electrical connection route between the drain end 253 and the storage capacitor in the third wafer 300a simple and easy to implement.

[0255] In an embodiment of the present application, in the step of forming the third wafer 300a and bonding the third wafer 300a to the second wafer 200a, the capacitor plate lines 370 extend horizontally and are arranged in parallel at intervals in the longitudinal direction. The capacitor plate lines 370 surround the capacitor bit lines 351 horizontally. The capacitor bit lines 351 extend longitudinally through a plurality of capacitor plate lines 370. A storage material layer 360 is formed between the capacitor bit lines 351 and the capacitor plate lines 370. The storage material layer 360 serves as the capacitive dielectric layer of the storage capacitor.

[0256] That is, the part near the intersection of the capacitor plate lines 370 and the capacitor bit lines 351 and the storage material layer 360 located therebetween constitute storage units, and the storage units are distributed in a three-dimensional array on the third wafer 300a.

[0257] In this embodiment, the materials of the capacitor plate lines 370 and the capacitor bit lines 351 are metal materials. As an example, in this embodiment, the materials of the capacitor plate lines 370 and the capacitor bit lines 351 are tungsten.

[0258] It should be noted that in this embodiment, by etching a stepped structure on the side of the third wafer 300a to expose the capacitor plate lines 370 of each layer and respectively leading out the signal lines of each layer of capacitor plate lines 370, independent control of each layer of capacitor plate lines 370 is achieved. The stepped structure is adopted in this embodiment to lead out the signal lines, which can reduce the length and complexity of the signal lines and improve the integration density.

[0259] In this embodiment, the material of the storage material layer 360 includes ferroelectric materials.

[0260] Correspondingly, in this embodiment, the storage capacitor is a ferroelectric capacitor (Ferroelectric Capacitor, FECAP), and the formed memory is a ferroelectric random access memory (Ferroelectric Random Access Memory, FeRAM). FeRAM uses a ferroelectric material (such as lead zirconate titanate PZT) as the storage medium. The ferroelectric material has the characteristic of spontaneous polarization, that is, under the action of an external electric field, the atoms or ions inside the material will displace to form a polarized state, and even if the external electric field is removed, the polarized state can still be maintained. This characteristic enables FeRAM to have non-volatility. FeRAM realizes non-volatile storage by utilizing the polarization characteristic of the ferroelectric material, and has advantages such as high-speed reading and writing, high durability, and low power consumption, and is suitable for application scenarios with various high-performance storage requirements.

[0261] Specifically, referring to Figure 31 , the step of forming the third wafer 300a includes: providing a third substrate 300.

[0262] The third substrate 300 is used to provide a process operation basis for forming the third wafer 300a.

[0263] As an example, in this embodiment, the material of the third substrate 300 is silicon.

[0264] Continue to refer to Figure 31 , and an alternating arrangement of a first isolation layer 310 and a sacrificial layer 320 is formed on the third substrate 300.

[0265] The sacrificial layer 320 is used to occupy the spatial position for the subsequent formation of the capacitor plate line 370, and the first isolation layer 310 is used to electrically isolate the longitudinally adjacent capacitor plate lines 370 subsequently.

[0266] In this embodiment, in the step of forming the alternating arrangement of the first isolation layer 310 and the sacrificial layer 320 on the third substrate 300, the first isolation layer 310 and the sacrificial layer 320 have an etching selectivity, so as to reduce the damage to the first isolation layer 310 during the subsequent removal of the sacrificial layer 320.

[0267] As an example, in this embodiment, the material of the first isolation layer 310 is silicon oxide, and the material of the sacrificial layer 320 is silicon nitride. Silicon oxide and silicon nitride can form a relatively large etching selectivity, which is beneficial to reducing the damage to the first isolation layer 310 during the subsequent removal of the sacrificial layer 320.

[0268] In this embodiment, with the alternating arrangement of the first isolation layer 310 and the sacrificial layer 320 as a stacked structure, a fourth mask layer 330 and a top dielectric layer 381 located between the fourth mask layer 330 and the stacked structure are further formed on the stacked structure.

[0269] The fourth mask layer 330 is used as an etching mask for patterning the third substrate 300 and the stacked structure, and the top dielectric layer 381 is used to isolate the fourth mask layer 330 from the stacked structure to protect the stacked structure.

[0270] In this embodiment, the fourth mask layer 330 includes an advanced pattern film, a hard mask layer (for example, a silicon oxynitride layer) located on the advanced pattern film, and a photoresist layer located on the hard mask layer.

[0271] As an example, in this embodiment, the material of the top dielectric layer 381 is silicon oxynitride.

[0272] Combined with reference to Figures 32 to 36 , a capacitor bit line 351 penetrating the first isolation layer 310 and the sacrificial layer 320 is formed.

[0273] The capacitor bit line 351 penetrates the first isolation layer 310 and the sacrificial layer 320, and plays a supporting role for the first isolation layer 310 when the sacrificial layer 320 is removed subsequently.

[0274] Specifically, refer to Figure 32The steps of forming the capacitive bit line 351 that penetrates the first isolation layer 310 and the sacrificial layer 320 include: patterning the first isolation layer 310, the sacrificial layer 320, and a part of the thickness of the third substrate 300 to form a fifth via 301 that penetrates the first isolation layer 310 and the sacrificial layer 320 and extends into the part of the thickness of the third substrate 300.

[0275] The fifth via 301 is used to provide a spatial position for the subsequent formation of the capacitive bit line 351.

[0276] In this embodiment, the fifth via 301 extends into the part of the thickness of the third substrate 300, which is beneficial to ensuring that the fifth via 301 completely penetrates the stacked structure.

[0277] Specifically, in this embodiment, the steps of patterning the first isolation layer 310, the sacrificial layer 320, and a part of the thickness of the third substrate 300 include: patterning the fourth mask layer 330; patterning the first isolation layer 310, the sacrificial layer 320, and a part of the thickness of the third substrate 300 along the patterned fourth mask layer 330 to form a fifth via 301 that penetrates the first isolation layer 310 and the sacrificial layer 320 and extends into the part of the thickness of the third substrate 300.

[0278] Correspondingly, in this embodiment, in the steps of patterning the first isolation layer 310 and the sacrificial layer 320, the top dielectric layer 381 is also patterned.

[0279] Reference Figure 33 After patterning the first isolation layer 310, the sacrificial layer 320, and a part of the thickness of the third substrate 300, it further includes: removing the fourth mask layer 330 to prepare for subsequent processes.

[0280] Reference Figure 34 A second isolation layer 340 is formed to cover the surface of the third substrate 300 exposed by the fifth via 301.

[0281] The second isolation layer 340 is used to isolate the capacitive bit line 351 from the third substrate 300 in the subsequent process. The second isolation layer 340 is also used to repair the surface defects of the fifth via 301. Especially for the hole defects at the bottom corner of the fifth via 301, it can play a good role in repair.

[0282] In this embodiment, the second isolation layer 340 covering the surface of the third substrate 300 exposed by the fifth via 301 is formed by an oxidation process.

[0283] The oxidation process can selectively form the second isolation layer 340 on the surface of the third substrate 300 exposed by the fifth via 301. The formed film layer has good quality, and no additional etching steps are required. The process flow is simple and the process efficiency is high.

[0284] In other embodiments, an atomic layer deposition process may also be used to form a second isolation layer covering the surface of the third substrate exposed by the fifth through hole.

[0285] As an example, in this embodiment, the material of the second isolation layer 340 includes silicon oxide.

[0286] With reference to Figure 35 and Figure 36 , the fifth through hole 301 is filled to form a capacitor bit line 351, and the capacitor bit line 351 covers the second isolation layer 340.

[0287] Specifically, in this embodiment, the steps of filling the fifth through hole 301 to form the capacitor bit line 351 include: with reference to Figure 35 , a capacitor bit line material layer 350 is formed to fill the fifth through hole 301 and cover the top of the top dielectric layer 381; with reference to Figure 36 , the capacitor bit line material layer 350 is planarized, and the capacitor bit line material layer 350 on the top of the top dielectric layer 381 is removed, and the capacitor bit line material layer 350 located in the fifth through hole 301 is retained as the capacitor bit line 351 to obtain a process platform with better flatness.

[0288] Correspondingly, in this embodiment, the capacitor bit line 351 also extends into the third substrate 300 with a partial thickness.

[0289] With reference to Figures 37 to 39 , the sacrificial layer 320 is removed to form a through groove 303 surrounded by the longitudinally adjacent first isolation layers 310.

[0290] The through groove 303 provides a spatial position for the subsequent formation of the capacitor plate line 370.

[0291] It should be noted that Figures 37 to 46 the cross-sectional view direction of Figures 31 to 36 is perpendicular to the cross-sectional view direction of

[0292] Specifically, with reference to Figure 37 , the steps of removing the sacrificial layer 320 to form the through groove 303 surrounded by the longitudinally adjacent first isolation layers 310 include: forming a third trench 302 penetrating the first isolation layer 310 and the sacrificial layer 320.

[0293] The third trench 302 exposes the sacrificial layer 320 so that the sacrificial layer 320 can be removed through the third trench 302 subsequently.

[0294] In this embodiment, in the step of forming the third trench 302 penetrating the first isolation layer 310 and the sacrificial layer 320, a part of the thickness of the third substrate 300 is also removed so that the third trench 302 extends into the third substrate 300 with a partial thickness.

[0295] In this embodiment, the steps of forming the third trench 302 that penetrates through the first isolation layer 310 and the sacrificial layer 320 include: forming a fifth mask layer 331 that covers the top dielectric layer 381; patterning the fifth mask layer 331; along the patterned fifth mask layer 331, patterning the first isolation layer 310, the sacrificial layer 320, and a part of the thickness of the third substrate 300 to form the third trench 302, so as to ensure that the stacked structure of the first isolation layer 310 and the sacrificial layer 320 is completely penetrated by the third trench 302.

[0296] Reference Figure 38 , after forming the third trench 302 that penetrates through the first isolation layer 310 and the sacrificial layer 320, it further includes: removing the fifth mask layer 331 to prepare for subsequent processes.

[0297] Reference Figure 39 , removing the sacrificial layer 320 along the third trench 302.

[0298] In this embodiment, the sacrificial layer 320 is removed along the third trench 302 by using a wet etching process.

[0299] The wet etching process has relatively low cost, simple operation steps, and can also achieve a large etching selectivity ratio, which is beneficial to reducing the damage to the first isolation layer 310 during the process of removing the sacrificial layer 320.

[0300] Reference Figure 40 , forming a storage material layer 360 that covers all surfaces of the through - slot 303.

[0301] In this embodiment, in the step of forming the storage material layer 360 that covers all surfaces of the through - slot 303, the storage material layer 360 also covers all surfaces of the third trench 302.

[0302] Specifically, in this embodiment, the storage material layer 360 covers all surfaces of the first isolation layer 310 exposed in the through - slot 303, the sidewalls of the capacitor bit lines 351 exposed in the through - slot 303, and the sidewalls of the third trench 302.

[0303] In this embodiment, the storage material layer 360 that covers all surfaces of the through - slot 303 is formed by using an atomic layer deposition process.

[0304] The storage material layer 360 formed by using the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the storage material layer 360 can conformally cover all surfaces of the through - slot 303 and the third trench 302 well.

[0305] It should be noted that, in this embodiment, in the step of forming the storage material layer 360 that covers all surfaces of the through - slot 303, the storage material layer 360 also covers the top surface of the top dielectric layer 381.

[0306] Correspondingly, in this embodiment, the storage material layer 360 is a ferroelectric material layer.

[0307] Reference Figure 41 , fill the through groove 303 to form the capacitor plate line 370.

[0308] In this embodiment, in the step of filling the through groove 303 to form the capacitor plate line 370, the third trench 302 is also filled to form the interconnect wall 382.

[0309] In this embodiment, the atomic layer deposition process is used to fill the through groove 303 to form the capacitor plate line 370.

[0310] The capacitor plate line 370 formed by the atomic layer deposition process has good thickness uniformity and good step coverage ability, so that the capacitor plate line 370 can be well filled in the through groove 303.

[0311] It should be noted that in this embodiment, in the step of filling the through groove 303, the filling material also covers the top surface of the top dielectric layer 381.

[0312] Reference Figure 42 , planarize the filling material, and remove the filling material on the top surface of the top dielectric layer 381 and the storage material layer 360 to prepare for subsequent processes.

[0313] Reference Figure 43 , before forming the fourth dielectric layer covering the first isolation layer 310 and the capacitor bit line 351 subsequently, it further includes: removing the interconnect wall 382.

[0314] Remove the interconnect wall 382 to isolate the laterally adjacent and vertically adjacent capacitor plate lines 370.

[0315] Specifically, in this embodiment, the interconnect wall 382 and the storage material layer 360 on the sidewall of the interconnect wall 382 are removed to expose the third trench 302.

[0316] Continue to refer to Figure 43 , form the fourth dielectric layer 380 covering the first isolation layer 310 and the capacitor bit line 351.

[0317] The fourth dielectric layer 380 is used to provide a process platform for the formation of the fourth interconnect structure 390.

[0318] Correspondingly, in this embodiment, in the step of forming the fourth dielectric layer 380 covering the first isolation layer 310 and the capacitor bit line 351, the fourth dielectric layer 380 also fills the third trench 302.

[0319] In this embodiment, the material of the fourth dielectric layer 380 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. As an example, the material of the fourth dielectric layer 380 is silicon oxide. Correspondingly, in this embodiment, the fourth dielectric layer 380 and the top dielectric layer 381 are of an integral structure.

[0320] With reference to Figures 44 to 46 , a fourth interconnect structure 390 is formed that penetrates the fourth dielectric layer 380 on the capacitor bit line 351 and contacts the capacitor bit line 351.

[0321] The fourth interconnect structure 390 penetrates the fourth dielectric layer 380 to achieve electrical connection of one end to the capacitor bit line 351 and electrical connection of the other end to the outside of the third wafer 300a.

[0322] Specifically, with reference to Figure 44 , the steps of forming the fourth interconnect structure 390 that penetrates the fourth dielectric layer 380 on the capacitor bit line 351 and contacts the capacitor bit line 351 include: forming a fourth via 304 that penetrates the top of the capacitor bit line 351 and exposes the surface of the capacitor bit line 351 in the fourth dielectric layer 380.

[0323] The fourth via 304 is used to provide a spatial position for the formation of the fourth interconnect structure 390.

[0324] In this embodiment, before forming the fourth via 304 that penetrates the top of the capacitor bit line 351 and exposes the surface of the capacitor bit line 351, it further includes: forming a fourth dielectric antireflection layer covering the fourth dielectric layer 380.

[0325] The fourth dielectric antireflection layer is used to reduce light reflection, improve lithography accuracy, and is also used as a bonding interface subsequently.

[0326] As an example, in this embodiment, the material of the fourth dielectric antireflection layer is silicon nitride. Using silicon nitride as the bonding surface is beneficial for making the bonding force relatively strong, and using silicon nitride can also inhibit metal diffusion at the interface and ensure device performance.

[0327] Correspondingly, in this embodiment, in the steps of forming the fourth via 304 that penetrates the top of the capacitor bit line 351 and exposes the surface of the capacitor bit line 351, the fifth dielectric antireflection layer is also patterned to form the fourth via 304 that penetrates the fifth dielectric antireflection layer.

[0328] With reference to Figure 45 , before filling the fourth via 304 subsequently, it further includes: removing a part of the width of the fourth dielectric layer 380 at the opening position of the fourth via 304 to expand the opening size of the fourth via 304.

[0329] Remove part of the width of the fourth dielectric layer 380 at the opening position of the fourth through hole 304 to expand the opening size of the fourth through hole 304, which is beneficial to increasing the process window and making it easier to fill the subsequent fourth through hole 304 better.

[0330] Reference Figure 46 , fill the fourth through hole 304 to form a fourth interconnect structure 390.

[0331] Reference Figure 47 , after forming a fourth interconnect structure 390 that penetrates the fourth dielectric layer 380 on the capacitive bit line 351 and contacts the capacitive bit line 351, contact the fourth interconnect structure 390 with the third interconnect structure 293 to achieve bonding.

[0332] Contact the fourth interconnect structure 390 with the third interconnect structure 293 to achieve bonding and form a vertically stacked memory structure.

[0333] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A memory, characterized in that: include: A first wafer including a plurality of bit line layers; A second wafer bonded to the first wafer, the second wafer comprising a plurality of transistor structures, source ends of the transistor structures being interconnected with the bit line layer; A third wafer is bonded to the second wafer, and the third wafer includes a plurality of storage capacitors, wherein two plates of the storage capacitors are respectively connected to a capacitor plate line and a capacitor bit line, and the capacitor bit line is interconnected with a drain terminal of the transistor structure.

2. The memory according to claim 1, wherein: In the first wafer, a first interconnect structure electrically connected to the bit line layer is formed on the bit line layer; In the second wafer, a second interconnect structure electrically connected to the source end of the transistor structure is formed thereon, a third interconnect structure electrically connected thereto is formed at the drain end of the transistor structure, and the second interconnect structure is in contact with the first interconnect structure to be electrically connected thereto; In the third wafer, a fourth interconnection structure electrically connected to the capacitor bit line is formed on the capacitor bit line, and the fourth interconnection structure is in contact with the third interconnection structure to be electrically connected.

3. The memory according to claim 2, wherein: In the first wafer, the plurality of bit line layers extend in the same direction and are arranged in parallel, and a plurality of first interconnect structures arranged along the extending direction of the bit line layer are formed on each of the bit line layers.

4. The memory according to claim 3, wherein: The first wafer further includes: a first substrate; The bit line layer is located on the first substrate; A first dielectric layer covering the bit line layer and the first substrate; The first interconnect structure penetrates the first dielectric layer on the bit line layer and contacts the bit line layer.

5. The memory according to claim 4, wherein: A first protruding structure is formed on the first substrate, and adjacent first protruding structures form a first groove; The bit line layer is located on the first protrusion structure; The first dielectric layer also fills the first trench.

6. The memory according to claim 5, characterized in that An air gap is formed in the first dielectric layer in the first trench.

7. The memory according to claim 2, wherein: In the second wafer, the source end and the drain end of the transistor structure are vertically opposite to each other, the source end of the transistor structure faces the first wafer, and the drain end of the transistor structure faces the third wafer.

8. The memory according to claim 7, wherein: In the second wafer, the transistor structure further includes: a channel layer located between the source terminal and the drain terminal; a gate oxide layer covering the channel layer; A gate layer covering the gate oxide layer; The second wafer further includes: an isolation dielectric layer covering the source terminal, the gate layer, and the drain terminal of the transistor structure; The second interconnect structure penetrates the isolation dielectric layer on the source end and contacts the source end; The third interconnection structure penetrates the isolation dielectric layer on the drain terminal and contacts the drain terminal.

9. The memory according to claim 8, characterized in that The second wafer further includes: a protection layer covering the sidewalls and the top of the source end; The insulating medium layer covers the protective layer; The second interconnect structure also penetrates the protection layer.

10. The memory according to claim 2, wherein: In the third wafer, the capacitor plate lines extend in the transverse direction and are arranged in parallel with each other in the longitudinal direction, the capacitor plate lines transversely surround the capacitor bit lines, the capacitor bit lines extend in the longitudinal direction and penetrate multiple capacitor plate lines, a storage material layer is formed between the capacitor bit lines and the capacitor plate lines, and the storage material layer is used as a capacitor dielectric layer of the storage capacitor.

11. The memory according to claim 10, wherein: The material of the storage material layer includes ferroelectric material.

12. The memory according to claim 10, wherein: The third wafer further includes: a third substrate; The capacitor bit line is located on the third substrate; a first isolation layer disposed between longitudinally adjacent capacitor plate lines; The storage material layer is also located between the first isolation layer and the capacitor plate line; A fourth dielectric layer covering the first isolation layer and the capacitor bit line; The fourth interconnection structure penetrates the fourth dielectric layer on the capacitor bit line and contacts the capacitor bit line.

13. The memory according to claim 12, wherein: The capacitor bit line also extends into a portion of the thickness of the third substrate; A second isolation layer is formed between the capacitor bit line and the third substrate.

14. A method for forming a memory, characterized in that: include: forming a first wafer, the first wafer comprising a plurality of bit line layers; forming a second wafer and bonding the second wafer to the first wafer, wherein the second wafer comprises a plurality of transistor structures, and source ends of the transistor structures are interconnected with the bit line layer; A third wafer is formed and bonded to the second wafer, wherein the third wafer comprises a plurality of storage capacitors, two plates of the storage capacitors are respectively connected to a capacitor plate line and a capacitor bit line, and the capacitor bit line is interconnected with a drain terminal of the transistor structure.

15. The method for forming a memory according to claim 14, wherein: In the step of forming the first wafer, a first interconnect structure electrically connected to the bit line layer is formed on the bit line layer; In the step of forming a second wafer and bonding the second wafer to the first wafer, a second interconnection structure electrically connected to the source end of the transistor structure is formed on the source end of the transistor structure, a third interconnection structure electrically connected to the drain end of the transistor structure is formed on the drain end of the transistor structure, and the second interconnection structure is in contact with the first interconnection structure to be electrically connected; In the step of forming a third wafer and bonding the third wafer to the second wafer, a fourth interconnection structure electrically connected to the capacitor bit line is formed on the capacitor bit line, and the fourth interconnection structure contacts the third interconnection structure to be electrically connected.

16. The method for forming a memory according to claim 15, wherein: In the step of forming the first wafer, the plurality of bit line layers extend in the same direction and are arranged in parallel, and a plurality of first interconnect structures arranged along the extending direction of the bit line layer are formed on each of the bit line layers.

17. The method for forming a memory according to claim 16, wherein: The steps of forming the first wafer include: providing a first substrate; forming a plurality of spaced-apart bit line layers on the first substrate; forming a first dielectric layer covering the plurality of bit line layers; A first interconnect structure is formed which penetrates the first dielectric layer on the bit line layer and contacts the bit line layer.

18. The method for forming a memory according to claim 17, wherein: The step of forming a plurality of spaced-apart bit line layers on the first substrate includes: forming a bit line material layer covering the first substrate; Patterning the bit line material layer and a portion of the thickness of the first substrate to form a first protruding structure protruding from the remaining thickness of the first substrate and a plurality of bit line layers spaced apart from each other on the first protruding structure, wherein adjacent first protruding structures form a first groove; In the step of forming a first dielectric layer covering the plurality of bit line layers, the first dielectric layer also fills the first trench.

19. The method for forming a memory according to claim 18, wherein: Before forming the first dielectric layer covering the plurality of bit line layers, the method further includes: forming a first repair layer covering each surface of the first trench.

20. The method for forming a memory according to claim 18, wherein: In the step of forming a first dielectric layer covering the plurality of bit line layers, an air gap is formed in the first dielectric layer in the first trench.

21. The method for forming a memory according to claim 15, wherein: In the step of forming the second wafer and bonding the second wafer to the first wafer, the source end and the drain end of the transistor structure are longitudinally opposite to each other, and the source end of the transistor structure faces the first wafer; In the step of forming a third wafer and bonding the third wafer to the second wafer, the drain end of the transistor structure faces the third wafer.

22. The method for forming a memory according to claim 21, wherein: The step of forming the second wafer includes: providing a second substrate; Patterning a portion of the thickness of the second substrate to form a second protruding structure protruding from the remaining thickness of the second substrate, adjacent second protruding structures enclosing a second groove, the second protruding structure sequentially including a source terminal, a channel layer, and a drain terminal from the top to the bottom; forming a gate oxide layer covering the sidewalls of the second protruding structure at the position of the channel layer; forming a gate layer covering the gate oxide layer; forming a second dielectric layer filling the second trench and covering the source end; forming a second interconnect structure penetrating through the second dielectric layer on the top of the second protruding structure and contacting the source end; removing a remaining portion of the thickness of the second substrate to expose the drain terminal; forming a third dielectric layer covering the drain end; A third interconnect structure is formed which penetrates the third dielectric layer on the drain terminal and contacts the drain terminal.

23. The method for forming a memory according to claim 22, wherein: Before forming the gate oxide layer covering the sidewalls of the second protruding structure at the position of the channel layer, the method further includes: forming a first protective layer covering the sidewalls of the second protruding structure at the position of the source terminal, and a second protective layer covering the sidewalls of the second protruding structure at the position of the drain terminal; In the step of forming a second dielectric layer filling the second trench and covering the source end, the second dielectric layer covers the first protective layer and the second protective layer; In the step of removing the remaining thickness of the second substrate to expose the drain terminal, a portion of the thickness of the second protective layer is also removed; In the step of forming a third dielectric layer covering the drain terminal, the third dielectric layer also covers the remaining thickness of the second protection layer.

24. The method for forming a memory according to claim 23, wherein: The steps of forming a first protective layer covering the sidewall of the second protruding structure at the source terminal position and a second protective layer covering the sidewall of the second protruding structure at the drain terminal position include: forming a second protective material layer filling the second groove and covering the second protruding structure; Removing a portion of the thickness of the second protective material layer to expose the second protruding structure at the source end position; forming a first protective material layer covering the exposed top and sidewalls of the second protruding structure and the top of the second protective material layer of remaining thickness; removing the first protective material layer on top of the second protective material layer with a remaining thickness, and retaining the remaining first protective material layer as the first protective layer; removing a portion of the thickness of the second protective material layer to expose the sidewall of the second protruding structure at the position of the channel layer, and retaining the remaining second protective material layer as the second protective layer; In the step of forming a second interconnect structure penetrating the second dielectric layer on the top of the second protruding structure and contacting the source terminal, the second interconnect structure also penetrates the first protection layer on the top of the second protruding structure.

25. The method for forming a memory according to claim 24, wherein: Before forming the second protection material layer filling the second groove and covering the second protruding structure, the method further includes: forming a second repair layer covering each surface of the second groove.

26. The method for forming a memory according to claim 22, wherein: The remaining thickness of the second substrate is removed to expose the drain terminal, and the second interconnect structure is brought into contact with the first interconnect structure to achieve bonding, thereby exposing the bottom of the second substrate.

27. The method for forming a memory according to claim 22, wherein: The step of forming a second interconnect structure penetrating the second dielectric layer on the top of the second protruding structure and contacting the source end comprises: forming a second through hole penetrating the first dielectric layer on the top of the second protruding structure and exposing the surface of the source end; The second through hole is filled to form the second interconnect structure.

28. The method for forming a memory according to claim 15, wherein: In the step of forming a third wafer and bonding the third wafer to the second wafer, the capacitor plate lines extend in a transverse direction and are arranged in parallel with each other in a longitudinal direction, the capacitor plate lines transversely surround the capacitor bit lines, the capacitor bit lines extend in a longitudinal direction and penetrate multiple capacitor plate lines, a storage material layer is formed between the capacitor bit lines and the capacitor plate lines, and the storage material layer is used as a capacitor dielectric layer of the storage capacitor.

29. The method for forming a memory according to claim 28, wherein: The material of the storage material layer includes ferroelectric material.

30. The method for forming a memory according to claim 28, wherein: The step of forming the third wafer includes: providing a third substrate; forming alternately arranged first isolation layers and sacrificial layers on the third substrate; forming a capacitor bit line penetrating the first isolation layer and the sacrificial layer; The sacrificial layer is removed to form a through groove surrounded by the first isolation layers adjacent to each other in the longitudinal direction; forming a storage material layer covering each surface of the through groove; filling the through groove to form the capacitor plate line; forming a fourth dielectric layer covering the first isolation layer and the capacitor bit line; A fourth interconnection structure is formed which penetrates the fourth dielectric layer on the capacitor bit line and contacts the capacitor bit line.

31. The method for forming a memory according to claim 30, wherein: The step of forming a capacitor bit line penetrating the first isolation layer and the sacrificial layer comprises: patterning the first isolation layer and the sacrificial layer, and the third substrate of a partial thickness, forming a fifth through hole penetrating the first isolation layer and the sacrificial layer and extending in the third substrate of a partial thickness; forming a second isolation layer covering the surface of the third substrate exposed by the fifth through hole; The fifth through hole is filled to form the capacitor bit line, and the capacitor bit line covers the second isolation layer.

Images