Embedded memory and manufacturing method thereof

Abstract

The invention provides an embedded memory and a manufacturing method thereof, and the embedded memory comprises a semiconductor substrate which is internally provided with a first lead; the insulation structure layer covers the first wire, and a groove is formed in the insulation structure layer; the first electrode penetrates through the insulating structure layer, is communicated with the first wire and partially protrudes out of the insulating structure layer; the second electrode and the storage material structure layer are transversely arranged on the insulating structure layer, the second electrode and the first electrode are oppositely arranged, and the space between the first electrode and the second electrode is filled with the storage material structure layer; and the second wire is arranged above the second electrode and is communicated with the second electrode. The embedded memory and the manufacturing method thereof provided by the invention can be better applied to different process nodes so as to optimize the process technology and ensure the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an embedded memory and a manufacturing method thereof. Background Art

[0002] The resistive random access memory (RRAM) is a non-volatile memory based on the reversible conversion between a high-resistance state and a low-resistance state of a resistive material under the action of an external electric field. Its simplified electrode structure is as Figure 1 shown. The upper electrode 14', the resistive structure layer 13', and the lower electrode 12' are sequentially stacked in the vertical direction (longitudinally) between the first interconnecting line 11' and the second interconnecting line 15' on the substrate 10', and a bottom-up conduction working mode is formed. The resistive random access memory has the advantages of simple structure, low working power consumption, good miniaturization, etc., and can be manufactured using the processes and equipment related to logic chips, has good compatibility with the existing integrated circuit manufacturing processes, and has good application prospects in the application of embedded memories.

[0003] With the development of devices with an embedded resistive memory structure and integrated circuit processes in application promotion, there is a need to introduce the above-mentioned resistive random access memory at lower process nodes. However, for the structure as Figure 1 shown, due to the limitations of its area and the thickness of each film layer, it cannot be well applied to lower-node processes (such as complex processes and / or poor devices), and it is also not conducive to the miniaturization and densification of devices. Summary of the Invention

[0004] The purpose of the present invention is to provide an embedded memory and a manufacturing method thereof, so that it can be better applied to different process nodes.

[0005] To solve the above technical problems, the embedded memory provided by the present invention includes:

[0006] A semiconductor substrate, in which a first wire is provided;

[0007] An insulating structure layer, covering the first wire;

[0008] A first electrode, passing through the insulating structure layer to connect to the first wire and partially protruding from the insulating structure layer;

[0009] A second electrode and a storage material structure layer arranged horizontally on the insulating structure layer, the second electrode is disposed opposite to the first electrode, and the storage material structure layer is filled between the first electrode and the second electrode;

[0010] A second wire, disposed above the second electrode and connected to the second electrode.

[0011] Optionally, the first electrode includes a first part located in the insulating structure layer and a second part protruding from the insulating structure layer and connected to the first part. The second part includes N side faces, and at least one of the side faces corresponds to one of the second electrodes and one of the storage material structure layers.

[0012] Optionally, the second part is rectangular in shape, the second part includes four side faces, and one side face of the second part corresponds to one of the second electrodes and one of the storage material structure layers.

[0013] Optionally, the storage material structure layer includes a resistive random access memory (RRAM) storage material structure layer or a phase change memory (PCM) storage material structure layer.

[0014] Based on another aspect of the present invention, there is also provided a method for manufacturing an embedded memory, including:

[0015] Providing a semiconductor substrate with a first wire disposed therein;

[0016] Forming an insulating structure layer to cover the semiconductor substrate;

[0017] Forming the first electrode to penetrate the insulating structure layer and communicate with the first wire, and a part of the first electrode protruding from the insulating structure layer;

[0018] Forming a storage material structure layer and a second electrode on the insulating structure layer. The storage material structure layer covers the side wall of the first electrode, the second electrode covers the side wall of the storage material structure layer, and the second electrode is disposed opposite to the first electrode;

[0019] Forming a second wire above the second electrode and connecting it to the second electrode.

[0020] Optionally, the step of forming the first electrode includes:

[0021] Forming a through hole in the insulating structure layer to expose the first wire;

[0022] Forming a first electrode material layer to cover the surface of the insulating structure layer and filling the through hole to be above the surface of the insulating structure layer;

[0023] Performing a planarization process on the first electrode material layer on the surface of the insulating structure layer;

[0024] Performing a patterning process on the first electrode material layer, and using the remaining first electrode material layer as the first electrode. The first electrode includes a first part located in the insulating structure layer and a second part protruding from the insulating structure layer and connected to the first part.

[0025] Optionally, the step of forming the storage material structure layer includes:

[0026] Form a first storage material layer to cover the surface of the insulating structure layer and the outer wall of the first electrode;

[0027] Remove the top wall of the first electrode and the first storage material on the insulating structure layer, and use the first storage material on the side wall of the first electrode as the first storage material layer;

[0028] Similarly, form a second storage material layer on the side wall of the first storage material layer, and use the first storage material layer and the second storage material layer as the storage material structure layer.

[0029] Optionally, the step of forming the second electrode includes:

[0030] Form a second electrode material layer to cover the surface of the insulating structure layer up to above the first electrode;

[0031] Use the first electrode as a polishing stop layer, perform a polishing process to expose the surface of the first electrode, and retain the second electrode material layer on the surface of the insulating structure layer;

[0032] Form a patterned mask layer on the surfaces of the first electrode, the storage material structure layer, and the second electrode material layer;

[0033] Use the patterned mask layer to etch the first electrode, the storage material structure layer, and the second electrode material layer, and use the remaining second electrode material layer as the second electrode.

[0034] Optionally, after forming the second electrode, continue to etch a part of the thickness of the insulating structure layer and retain the remaining thickness of the insulating structure layer.

[0035] Optionally, the second part is rectangular, and the patterned mask layer is cross-shaped or strip-shaped.

[0036] In summary, the present invention forms a first electrode on an insulating structure layer on a first wire and is connected to the first wire, and a portion of the first electrode protrudes from the insulating structure layer, the second electrode is arranged on the insulating structure layer and is arranged opposite to the portion of the first electrode protruding from the insulating structure layer, and the storage material structure layer is arranged on the insulating structure layer between the first electrode and the second electrode, thereby forming an embedded storage structure on the insulating structure layer in which the first electrode, the storage structure material layer, and the second electrode are arranged in a horizontal direction, the horizontal width of the embedded storage structure is the sum of the widths of the three, and the vertical height of the embedded storage structure is the height of the area directly facing the three (the height of any one of the three). It is particularly noted that when the transversely arranged storage structure of this embodiment is embedded in a device of a lower process node, the thickness of the storage structure originally stacked in the longitudinal direction and thicker can be converted into a width arranged in the transverse direction, and the side of the storage structure facing the three film layers is used as the height, thereby breaking through the limitation that the storage structure cannot be directly embedded between two adjacent interconnection layers of a device of a lower process node due to the overall thickness. The embedded storage structure provided by this embodiment can be better compatible with the original (conventional CMOS process) interconnection process of the device and ensure the performance of the device (including the embedded storage structure). In addition, the embedded storage structure of this embodiment can also be used in devices of higher process nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0038] Figure 1 is a schematic diagram of an embedded storage structure in the related art;

[0039] Figure 2 is a flow chart of a method for manufacturing an embedded memory provided in Embodiment 1;

[0040] Figures 3a to 3m A schematic structural diagram corresponding to corresponding steps of the method for manufacturing an embedded memory provided in the first embodiment;

[0041] Figures 4a to 4d This is a partial structural diagram of a method for manufacturing another embedded memory provided in Example 2.

[0042] Figure 1 Middle: 10'-substrate; 11'-first interconnection line; 12'-lower electrode; 13'-resistive switching structure layer; 14'-upper electrode; 15'-second interconnection line.

[0043] Figures 3a to 4dIn the figure: 10 - semiconductor substrate; 11 - first wire; 21 - insulating structure layer; 21a - first insulating layer; 21b - second insulating layer; 21c - third insulating layer; 22 - via hole; 23 - first electrode material layer; 24 - first electrode; 24a - first part; 24b - second part; 25a - first storage material; 25 - first storage material layer; 26 - second storage material layer; 27 - storage material structure layer; 28a - second electrode material layer; 28 - second electrode; 29 - patterned mask layer; 31 - insulating structure repair layer; 32 - isolation material layer; 33 - interlayer dielectric layer; 34 - second wire. Detailed implementation manners

[0044] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and are not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphasis to be shown in each of the accompanying drawings is different, and sometimes different scales are used.

[0045] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features, unless the content clearly indicates otherwise.

[0046] Embodiment 1

[0047] Embodiment 1 provides a method for manufacturing an embedded memory.

[0048] Figure 2 It is a flowchart of the method for manufacturing the embedded memory provided for Embodiment 1.

[0049] As Figure 2 shown, the method for manufacturing the embedded memory provided in this embodiment includes:

[0050] S01: Provide a semiconductor substrate, in which a first wire is provided;

[0051] S02: Form an insulating structure layer to cover the semiconductor substrate;

[0052] S03: Form the first electrode to penetrate through the insulating structure layer to connect to the first wire, and part of the first electrode protrudes from the insulating structure layer;

[0053] S04: Form a storage material structure layer and a second electrode on the insulating structure layer. The storage material structure layer covers the sidewall of the first electrode, the second electrode covers the sidewall of the storage material structure layer, and the second electrode is disposed opposite to the first electrode;

[0054] S05: Form a second wire above the second electrode and connect it to the second electrode.

[0055] Figures 3a to 3m It is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of the embedded memory provided in Embodiment 1. Next, the manufacturing method of the embedded memory will be described in detail in conjunction with Figures 3a to 3m .

[0056] First, please refer to Figure 3a , and execute step S01 to provide a semiconductor substrate 10 with a first wire 11 disposed therein.

[0057] The material of the semiconductor substrate 10 may include any suitable substrate material well-known to those skilled in the art. For example, it may be at least one of the materials mentioned below: silicon, glass, quartz, plastic, etc.

[0058] A semiconductor device layer and an interconnect layer (or a part of the interconnect layer) connected to the semiconductor device layer may be sequentially formed in the semiconductor substrate 10. Among them, the semiconductor device layer may include any suitable semiconductor device, such as a logic device, and the interconnect layer may include a contact layer (also called the zero-th metal layer) for leading out the semiconductor device layer and the N-th metal layer, where N is an integer greater than or equal to 1.

[0059] In this embodiment, the semiconductor device may include a transistor formed in the semiconductor substrate 10. A plurality of first wires 11 are exposed on the surface of the semiconductor substrate 10, and at least part of each first wire 11 is connected to a transistor in the semiconductor substrate 10. The first wire 11 may be an interconnect line in the zero-th metal layer or the N-th metal layer.

[0060] Next, please refer to Figure 3b , and execute step S02 to form an insulating structure layer 21 to cover the semiconductor substrate 10.

[0061] Among them, the insulating structure layer 21 may include one or more layers of insulating materials, and the materials of two adjacent insulating materials in the multi-layer insulating materials are different. In a preferred example, the insulating structure layer 21 may include a first insulating layer 21a, a second insulating layer 21b, and a third insulating layer 21c formed in sequence from bottom to top. The first insulating layer 21a and the second insulating layer 21b may serve as the isolation layers of the first wire 11 (the thickness is, for example, 300 Å to 400 Å), and the third insulating layer 21c may serve as the isolation layer of the embedded storage structure (the thickness is, for example, 100 Å to 200 Å), which has a better isolation effect on the oxygen source to prevent the storage material from oxidizing and deteriorating. The material of the third insulating layer 21c may, for example, include silicon carbonitride.

[0062] Next, step S03 is executed to form a first electrode 24 passing through the insulating structure layer 21 to communicate with the first wire 11 and a part of the first electrode 24 protruding from the insulating structure layer 21.

[0063] Specifically, please refer to Figure 3c , a through hole 22 is formed in the insulating structure layer 21 to expose the first wire 11. The through hole 22 is located above the first wire 11, and the opening width thereof may, for example, be 70 nm to 100 nm.

[0064] Please refer to Figure 3d , a first electrode material layer 23 is formed to cover the surface of the insulating structure layer 21 and fill the through hole 22 above the surface of the insulating structure layer 21. The material of the first electrode material layer 23 may, for example, include titanium nitride or tantalum nitride. The first electrode material layer 23 has a depression above the through hole 22, and the height of the lowest point of the depression from the surface of the insulating structure layer 21 should be greater than the height of the subsequent first electrode on the insulating structure layer 21 to provide necessary space for the subsequent manufacture of the embedded storage structure. In this embodiment, the height of the lowest point of the above-mentioned depression from the surface of the insulating structure layer 21 may be greater than 500 Å.

[0065] Please refer to Figure 3e , a planarization process is performed on the first electrode material layer 23 on the surface of the insulating structure layer 21, and then a patterning process is performed on the first electrode material layer 23 to retain the first electrode material layer 23 in and around the through hole 22, which serves as the first electrode 24. The first electrode 24 includes a first part 24a located in the insulating structure layer 21 and a second part 24b protruding from the insulating structure layer 21 and connected to the first part 24a. The width of the second part 24b may be greater than or equal to the width of the through hole 22. In this embodiment, the second part 24b may be rectangular, the X-direction width (longer side) of the second part 24b may be 100 nm to 250 nm, the Y-direction width (shorter side) thereof is between the X-direction width and the width of the through hole 22, and the thickness of the second part 24b may be 400 Å to 500 Å.

[0066] Next, step S04 is performed to form a storage material structure layer 27 and a second electrode 28 on the insulating structure layer 21. The storage material structure layer 27 covers the sidewalls of the first electrode 24, and the second electrode 28 covers the sidewalls of the storage material structure layer 27, and the second electrode 28 is disposed opposite to the first electrode 24.

[0067] Among them, the storage material structure layer 27 can be any suitable type of storage material layer, which can include a single layer of storage material or a stack composed of at least two layers of storage materials. In this embodiment, the type of the embedded storage structure can be a resistive random access memory (RRAM) structure, that is, the material of the storage material structure layer 27 is a resistive random access memory material.

[0068] In this embodiment, the storage material structure layer 27 can include two layers of resistive materials. The specific formation process can include: Please refer to Figure 3f , to form a first storage material 25a covering the surface of the insulating structure layer 21 and the outer wall of the first electrode 24. The material of the first storage material 25a can include, for example, hafnium oxide, titanium, titanium oxide, tantalum oxide, etc. The film thickness of the first storage material 25a covering the sidewalls of the first electrode 24 can be 20 Å to 150 Å to serve as the width (in the lateral direction) of the subsequent first storage material layer 25.

[0069] Please refer to Figure 3g , to remove the top wall of the first electrode 24 and the first storage material 25a on the insulating structure layer 21, and use the first storage material 25a on the sidewalls of the first electrode 24 as the first storage material layer 25. Among them, maskless dry etching can be used and over-etching can be appropriately performed to ensure that the first storage material 25a on the insulating structure layer 21 is completely removed.

[0070] Please refer to Figure 3h , similarly, a second storage material layer 26 is formed on the sidewalls of the first storage material layer 25, and the first storage material layer 25 and the second storage material layer 26 are used as the storage material structure layer 27.

[0071] Please refer to Figure 3i, a second electrode material layer 28a is formed to cover the surface of the insulating structure layer 21 above the first electrode 24. Using the first electrode 24 as a polishing stop layer, a polishing process is performed to expose the surface of the first electrode 24 and retain the second electrode material layer 28a on the surface of the insulating structure layer 21. Among them, the material of the second electrode material layer 28a can refer to the material of the first electrode 24, such as titanium nitride or tantalum nitride. Preferably, when the first electrode 24 is used as a polishing stop layer to perform a polishing process (such as chemical mechanical polishing), the first electrode 24, the storage material structure layer 27, and the second electrode 28 material layer can also be continuously polished to a preset height from the surface of the insulating structure layer 21 to control the embedded storage structure at an appropriate height, such as within 350 angstroms. In addition, a surface oxidation process is also used to insulate the above surface to prevent leakage between the first electrode 24 and the second electrode material layer 28a and increase the reliability of the device.

[0072] It should be noted that after the first storage material 25a is formed, a masked dry etching can also be used, that is, a mask pattern is formed to cover the first electrode 24 and the first storage material 25a on its sidewalls, and then the first storage material 25a on the insulating structure layer 21 is removed, and the first storage material 25a on the first electrode 24 and its sidewalls is retained. Similarly, a second storage material is formed to cover the surface and sidewalls of the remaining first storage material 25a, and after the second electrode material layer 28a is formed, a polishing process is performed to remove the second electrode material layer 28a, the second storage material, and the first storage material 25a on the first electrode 24 to form a storage material structure layer 27.

[0073] Please refer to Figure 3j_1 and Figure 3j_2 , a patterned mask layer 29 is formed on the surfaces of the first electrode 24, the storage material structure layer 27, and the second electrode material layer 28a. Among them, Figure 3j_1 is a cross-sectional schematic diagram, Figure 3j_2 is a top view schematic diagram. In this embodiment, taking the formation of 1T2R (one transistor corresponding to two resistive memory structures) as an example, the patterned mask layer 29 can be strip-shaped, and it extends from the center of the first electrode 24 to both ends along the width direction of the first electrode 24 (such as the X direction) (across the storage material structure layer 27) to the second electrode material layer 28a to define the shape of the embedded storage structure. The width (such as the X direction) and length (such as the Y direction) of the patterned mask layer 29 can be set as needed, but the length (such as the Y direction) of the patterned mask layer 29 should be between the size of the first part 24a (via 22) and the shorter side of the second part 24b (that is, its length is greater than or equal to the size of the via 22 and less than or equal to the size of the second part 24b in the Y direction). The part of the patterned mask layer 29 covering the second electrode material layer 28a is the second electrode.

[0074] Please refer toFigure 3k_1 and Figure 3k_2 , using the patterned mask layer 29, the first electrode 24, the storage material structure layer 27 and the second electrode material layer 28a are etched, and the remaining second electrode material layer 28a is used as the second electrode 28, and a 1T2R embedded storage structure consisting of one first electrode 24 (corresponding to one transistor), two storage material structure layers 27 and two second electrodes 28 is formed.

[0075] In addition, after removing the first electrode 24, the storage material structure layer 27 and the second electrode material layer 28a on the insulating structure layer 21 to expose the surface of the insulating structure layer 21, the insulating structure layer 21 of a part of the thickness is further etched (overetched), and the insulating structure layer 21 of the remaining thickness is retained to ensure that no electrode material or storage material remains to affect the device performance. Taking the insulating structure layer 21 in this embodiment including the first to third insulating layers 21c as an example, the second insulating layer 21b and the third insulating layer 21c can be etched away, and the first insulating layer 21a with a thickness of 50 angstroms to 100 angstroms is retained to prevent the first conductive line 11 from being affected.

[0076] Thus, an embedded storage structure is formed on the insulating structure layer 21, which is composed of the first electrode 24, the storage structure material layer, and the second electrode 28 arranged in the horizontal direction. The width of the embedded storage structure in the horizontal direction is the sum of the widths of the three, and the height of the embedded storage structure in the vertical direction is the height of the area directly facing the three (the height of any one of the three). Therefore, when the storage structure arranged in the horizontal direction of this embodiment is embedded in a device of a lower process node, the thickness of the storage structure originally stacked in the vertical direction and thicker can be converted into the width arranged in the horizontal direction, and the side directly facing the three film layers in the storage structure is used as the height, thereby breaking through the limitation that the storage structure cannot be directly embedded between two adjacent interconnection layers of a device of a lower process node due to the overall thickness. Of course, the embedded storage structure of this embodiment can also be applied to devices of higher process nodes.

[0077] Please refer to Figure 3l , forming an isolation material layer 32 to cover the remaining insulation structure layer 21 and the outer wall of the embedded storage structure. In one example, before forming the isolation material layer 32, an insulation structure repair layer 31 may be formed to cover the remaining insulation structure layer 21 and the outer wall of the embedded storage structure, and then the isolation material layer 32 is formed, and the material of the insulation structure repair layer 31 may have a better oxygen source isolation effect. Preferably, the material of the insulation structure repair layer 31 may be preferably the same as the material of the third insulation layer 21c, and the thickness of the film layer on the first wire 11 is substantially the same as that before the storage structure is not embedded, so that the capacitance, inductance and electrical signal of the device after being embedded in the storage structure are not changed as much as possible.

[0078] Next, please refer to Figure 3m, perform step S05 to form a second wire 34 above the second electrode 28 and connect it to the second electrode 28.

[0079] Specifically, an interlayer dielectric layer 33 can be formed on the isolation material layer 32, and then a (N + 1)-th interconnect layer is formed in the interlayer dielectric layer 33, which includes a second wire 34 connected to the second electrode 28. The material of the interlayer dielectric layer 33 can, for example, include silicon oxide doped with carbon and hydrogen (silicon oxycarbide). Since the height of the embedded memory structure in this embodiment is relatively low, the parameters (such as thickness) and processes before embedding can be referred to for forming the interlayer dielectric layer 33. Taking a device with a relatively low process node (such as 28 nm and below) as an example, the distance between the insulation structure layer 21 on the first wire 11 and the second wire 34 can be 500 angstroms or less (such as 400 angstroms to 500 angstroms), and the height of the embedded memory structure in this embodiment can be 350 angstroms to 400 angstroms.

[0080] Embodiment 2

[0081] Embodiment 2 provides a method for manufacturing an embedded memory.

[0082] Figure 2 It is a flowchart of the method for manufacturing the embedded memory provided by Embodiment 2.

[0083] As Figure 2 shown, the method for manufacturing the embedded memory provided by this embodiment includes:

[0084] S01: Provide a semiconductor substrate with a first wire disposed therein;

[0085] S02: Form an insulation structure layer to cover the semiconductor substrate;

[0086] S03: Form the first electrode to penetrate through the insulation structure layer to connect to the first wire and part of the first electrode protrudes from the insulation structure layer;

[0087] S04: Form a storage material structure layer and a second electrode on the insulation structure layer, the storage material structure layer covers the sidewall of the first electrode, the second electrode covers the sidewall of the storage material structure layer, and the second electrode is disposed opposite to the first electrode;

[0088] S05: Form a second wire above the second electrode and connect it to the second electrode.

[0089] The method for manufacturing the embedded memory provided by Embodiment 2 is basically the same as the manufacturing method provided by Embodiment 1, and the difference is only that other 1TnR embedded memory structures except 1T2R are formed.

[0090] In one example, as Figure 4aThe top view shown (refer to Figure 3j_1 and Figure 3j_2 ), the patterned mask layer 29 formed on the surfaces of the first electrode 24, the storage material structure layer 27, and the second electrode material layer 28a is cross-shaped, that is, the patterned mask layer 29 extends from the center of the first electrode 24 to all four sides onto the second electrode material layer 28a. In a preferred embodiment, the cross-section (top view) of the second part 24b of the first electrode 24 can be square-shaped. After performing the etching process using the above-mentioned patterned mask layer 29, as Figure 4b shown in the top view, an embedded memory structure composed of 1 first electrode 24 (corresponding to one transistor), 4 storage material structure layers 27, and 4 second electrodes 28 (1T4R) can be formed.

[0091] In another example, as Figure 4c shown in the top view, the patterned mask layer 29 formed on the surfaces of the first electrode 24, the storage material structure layer 27, and the second electrode material layer 28a is strip-shaped, that is, the patterned mask layer 29 extends from the center of the first electrode 24 to one side onto the second electrode material layer 28a. After performing the etching process using the above-mentioned patterned mask layer 29, as Figure 4d shown in the top view, an embedded memory structure composed of 1 first electrode 24 (corresponding to one transistor), 1 storage material structure layer 27, and 1 second electrode 28 (1T1R) can be formed.

[0092] Embodiment 3

[0093] Embodiment 3 provides an embedded memory.

[0094] Figure 3m is a schematic diagram of an embedded memory provided for Embodiment 3.

[0095] As Figure 3m shown, the embedded memory provided in this embodiment includes a semiconductor substrate 10, an insulating structure layer 21, a first electrode 24, a storage material structure layer 27, a second electrode 28, and a second wire 34. A plurality of first wires 11 arranged at intervals are provided in the semiconductor substrate 10, and the surfaces of the first wires 11 are exposed on the surface of the semiconductor substrate 10. The insulating structure layer 21 covers the surfaces of the semiconductor substrate 10 and the first wires 11. The first electrode 24 penetrates through the insulating structure layer 21 to connect to the first wire 11 and partially protrudes from the insulating structure layer 21. The second electrode 28 and the storage material structure layer 27 arranged horizontally on the insulating structure layer 21, the second electrode 28 is disposed opposite to the first electrode 24, and the storage material structure layer 27 is filled between the first electrode 24 and the second electrode 28; the second wire 34 is disposed above the second electrode 28 and is connected to the second electrode 28.

[0096] A semiconductor device layer and an interconnect layer (or a part of the interconnect layer) connected to the semiconductor device layer may be sequentially formed in the semiconductor substrate 10. Among them, the semiconductor device layer may include any suitable semiconductor devices, such as logic devices. The interconnect layer may include a contact layer (also referred to as the zero-th metal layer) or the N-th metal layer that leads out the semiconductor device layer, that is, N may be an integer greater than or equal to 0. In this embodiment, the semiconductor device may include a transistor formed in the semiconductor substrate 10. A plurality of first wires 11 are exposed on the surface of the semiconductor substrate 10, and one first wire 11 (i.e., one first electrode 24) may be connected to one transistor in the semiconductor substrate 10. The first wire 11 may be an interconnect line in the N-th metal layer (N is an integer greater than or equal to zero), and the second wire 34 may be an interconnect line in the (N + 1)-th metal layer. An embedded storage structure is disposed between the first wire 11 and the second wire 34, and one second electrode 28 is connected to one second wire 34. Among them, the first electrode 24 includes a first part 24a located in the insulating structure layer 21 and a second part 24b that protrudes from the insulating structure layer 21 and is connected to the first part 24a. One or at least two second electrodes 28 may be provided on the insulating structure layer 21 and are respectively opposite to at least a part of the side walls of the second part 24b. At least one storage material structure layer 27 is located on the insulating structure layer 21 and is disposed (filled) between the second part 24b and the second electrode 28, thereby forming an embedded storage structure in which the first electrode 24 (the second part 24b), the storage material structure layer 27, and the second electrode 28 are arranged laterally along the surface of the insulating structure layer 21. And a 1TnR structure (n is an integer greater than or equal to 1) is correspondingly formed according to the number (n) of the storage material structure layers 27 and the number (n) of the second electrodes 28. For example Figure 3m the 1T2R structure shown in Figure 4b the 1T4R structure shown in or Figure 4d the 1T1R structure shown in

[0097] In summary, in the present invention, a first electrode is formed on the insulating structure layer on the first wire and connected to the first wire, and a part of the first electrode protrudes from the insulating structure layer. The second electrode is disposed on the insulating structure layer and is disposed opposite to the part of the first electrode protruding from the insulating structure layer. The storage material structure layer is disposed on the insulating structure layer between the first electrode and the second electrode, so as to form an embedded storage structure arranged horizontally on the insulating structure layer by the first electrode, the storage structure material layer, and the second electrode. The width of the embedded storage structure in the horizontal direction is the sum of the widths of the three, and the height of the embedded storage structure in the vertical direction is the height of the area where the three are directly opposite (the height of any one of the three). It should be particularly noted that when the horizontally arranged storage structure in this embodiment is embedded into a device with a lower process node, the originally thick thickness of the storage structure stacked longitudinally can be converted into a width arranged horizontally, and the side where the three film layers of the storage structure are directly opposite is used as the height, thereby breaking through the limitation that the storage structure cannot be directly embedded between two adjacent interconnect layers of a device with a lower process node due to its overall thick thickness. The embedded storage structure provided in this embodiment can preferably be compatible with the original (conventional CMOS process) interconnect process of the device and ensure the performance of the device (including the embedded storage structure). In addition, the embedded storage structure of this embodiment can also be applied to devices with a higher process node.

[0098] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An embedded memory, characterized in that, it includes: a semiconductor substrate with a first wire disposed therein; an insulating structure layer covering the first wire; a first electrode passing through the insulating structure layer to connect to the first wire and partially protruding from the insulating structure layer; a second electrode and a storage material structure layer arranged horizontally on the insulating structure layer, the second electrode being disposed opposite to the first electrode, and the storage material structure layer being filled between the first electrode and the second electrode; a second wire disposed above the second electrode and connected to the second electrode.

2. The embedded memory according to claim 1, characterized in that, the first electrode includes a first part located in the insulating structure layer and a second part protruding from the insulating structure layer and connected to the first part, the second part includes N sides, and at least one of the sides corresponds to one of the second electrodes and one of the storage material structure layers.

3. The embedded memory according to claim 2, characterized in that, the second part is rectangular, the second part includes four sides, and one side of the second part corresponds to one of the second electrodes and one of the storage material structure layers.

4. The embedded memory according to claim 1, characterized in that, the storage material structure layer includes a resistive random access memory (RRAM) storage material structure layer or a phase change memory (PCM) storage material structure layer.

5. A manufacturing method of an embedded memory, characterized in that, it includes: providing a semiconductor substrate with a first wire disposed therein; forming an insulating structure layer to cover the semiconductor substrate; forming the first electrode passing through the insulating structure layer to connect to the first wire and partially protruding from the insulating structure layer; forming a storage material structure layer and a second electrode on the insulating structure layer, the storage material structure layer covering the side wall of the first electrode, the second electrode covering the side wall of the storage material structure layer, and the second electrode being disposed opposite to the first electrode; forming a second wire above the second electrode and connecting it to the second electrode.

6. The manufacturing method of the embedded memory according to claim 5, characterized in that, the step of forming the first electrode includes: forming a through hole in the insulating structure layer to expose the first wire; forming a first electrode material layer to cover the surface of the insulating structure layer and filling the through hole above the surface of the insulating structure layer; performing a planarization process on the first electrode material layer on the surface of the insulating structure layer; performing a patterning process on the first electrode material layer, and using the remaining first electrode material layer as the first electrode, the first electrode includes a first part located in the insulating structure layer and a second part protruding from the insulating structure layer and connected to the first part.

7. The manufacturing method of the embedded memory according to claim 5 or 6, characterized in that, the step of forming the storage material structure layer includes: forming a first storage material layer to cover the surface of the insulating structure layer and the outer wall of the first electrode; Remove the first storage material on the top wall of the first electrode and the insulating structure layer, and use the first storage material on the side wall of the first electrode as the first storage material layer; Similarly, form a second storage material layer on the side wall of the first storage material layer, and use the first storage material layer and the second storage material layer as the storage material structure layer.

8. The manufacturing method of the embedded memory according to claim 6, characterized in that, The step of forming the second electrode includes: Form a second electrode material layer to cover the surface of the insulating structure layer up to above the first electrode; Using the first electrode as a polishing stop layer, perform a polishing process to expose the surface of the first electrode and retain the second electrode material layer on the surface of the insulating structure layer; Form a patterned mask layer on the surfaces of the first electrode, the storage material structure layer, and the second electrode material layer; Using the patterned mask layer, etch the first electrode, the storage material structure layer, and the second electrode material layer, and use the remaining second electrode material layer as the second electrode.

9. The manufacturing method of the embedded memory according to claim 8, characterized in that, After forming the second electrode, continue to etch a part of the thickness of the insulating structure layer and retain the remaining thickness of the insulating structure layer.

10. The manufacturing method of the embedded memory according to claim 8, characterized in that, The second part is rectangular, and the patterned mask layer is cross-shaped or strip-shaped.

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