Embedded memory and manufacturing method thereof

Abstract

The invention provides an embedded memory and a manufacturing method thereof, and the embedded memory comprises a semiconductor substrate which is internally provided with a first lead; the insulation structure layer covers the first wire, and a groove is formed in the insulation structure layer; the plug penetrates through the insulating structure layer along the side wall of the groove and is connected with the first wire; the first electrode, the storage material structure layer and the second electrode are arranged in the groove and sequentially arranged along the bottom wall of the groove, the first electrode is located on the side wall of the groove and connected with the plug, the second electrode and the first electrode are oppositely arranged, and the space between the first electrode and the second electrode is filled with the storage material structure layer; and the second wire is arranged above the second electrode and is connected with the second electrode. The embedded memory and the manufacturing method thereof provided by the invention can be better applied to different process nodes so as to optimize the process technology and ensure the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to an embedded memory and a manufacturing method thereof. Background Art

[0002] The resistive random access memory (RRAM) is a non-volatile memory based on the reversible conversion between a high-resistance state and a low-resistance state of a resistive material under an externally applied electric field. Its simplified electrode structure is as Figure 1 shown. The upper electrode 14', the resistive structure layer 13', and the lower electrode 12' are sequentially stacked in a vertical direction (longitudinally) between the first interconnect line 11' and the second interconnect line 15' on the substrate 10', and a bottom-up conduction working mode is formed. The resistive random access memory has the advantages of simple structure, low working power consumption, good miniaturization, etc., and can be manufactured using logic chip-related processes and equipment, and has good compatibility with the existing integrated circuit manufacturing process, and has good application prospects in the application of embedded memories.

[0003] With the development of devices and integrated circuit processes with an embedded resistive memory structure in application promotion, there is a need to introduce the above-mentioned resistive random access memory at a lower process node. However, for the structure as Figure 1 shown, due to the limitations of its area and the thickness of each film layer, it cannot be well applied to lower-node processes (such as complex processes and / or poor devices), and it is also not conducive to the miniaturization and densification of devices. Summary of the Invention

[0004] The purpose of the present invention is to provide an embedded memory and a manufacturing method thereof, so that it can be better applied to different process nodes.

[0005] To solve the above technical problems, the embedded memory provided by the present invention includes:

[0006] A semiconductor substrate, in which a first wire is provided;

[0007] An insulating structure layer, covering the first wire, and a groove is provided in the insulating structure layer;

[0008] A plug, penetrating the insulating structure layer along the side wall of the groove to connect the first wire;

[0009] A first electrode, a storage material structure layer, and a second electrode, which are sequentially arranged horizontally in the groove. The first electrode covers the side wall of the groove and the plug exposed in the groove. The second electrode is disposed opposite to the first electrode, and the storage material structure layer is filled between the first electrode and the second electrode;

[0010] A second wire, disposed above the second electrode and connected to the second electrode.

[0011] Optionally, the insulating structure layer includes a first insulating layer, a second insulating layer, and a third insulating layer sequentially away from the first wire, and the groove is formed in the third insulating layer.

[0012] Optionally, the inner wall of the groove is further covered with a fourth insulating layer, and the plug is partially embedded in the fourth insulating layer on the side wall of the groove and sequentially penetrates through the fourth insulating layer, the second insulating layer, and the first insulating layer to communicate with the first wire.

[0013] Optionally, the cross-sectional shape of the groove is rectangular, the first electrode covers at least two side walls of the groove, and the first electrode partially surrounds the second electrode.

[0014] Optionally, one plug is provided at each end of the groove and is respectively connected to one of the first wires, and two embedded storage structures are provided in the groove and are respectively connected to one of the plugs. Each embedded storage structure includes the first electrode, the storage material structure layer, and the second electrode.

[0015] Based on another aspect of the present invention, a method for manufacturing an embedded memory is further provided, including:

[0016] Providing a semiconductor substrate with a first wire disposed therein;

[0017] Forming an insulating structure layer to cover the semiconductor substrate, and forming a groove in the insulating structure layer above the first wire;

[0018] Forming a plug along the side wall of the groove to penetrate through the insulating structure layer and connect to the first wire;

[0019] Forming a first electrode, a storage material structure layer, and a second electrode arranged horizontally in sequence in the groove. The first electrode covers the side wall of the groove and the plug exposed in the groove, the second electrode is disposed opposite to the first electrode, and the storage material structure layer is filled between the first electrode and the second electrode;

[0020] Forming a second wire above the second electrode and connecting to the second electrode.

[0021] Optionally, the steps of forming the insulating structure layer and the groove include:

[0022] Sequentially forming the first to third insulating layers on the first wire;

[0023] Using the second insulating layer as an etching stop layer, forming the groove in the third insulating layer, and the edge projection of the groove is on the first wire.

[0024] Optionally, a fourth insulating layer is further formed to cover the inner wall of the groove.

[0025] Optionally, the step of forming the plug includes:

[0026] Forming a sacrificial material layer to cover the fourth insulating layer and fill the groove;

[0027] Performing a patterning process to form a through hole penetrating the sacrificial material layer, the fourth insulating layer, and the insulating structure layer, exposing the surface of the first wire;

[0028] Forming a plug material layer to cover the surface of the sacrificial material layer and fill the through hole;

[0029] Using the surface of the fourth insulating layer as a polishing stop layer, performing a polishing process, using the plug material layer in the through hole as the plug, and then removing the remaining sacrificial material layer.

[0030] Optionally, the steps of forming the first electrode, the storage material structure layer, and the second electrode include:

[0031] Forming a first electrode material layer to cover the surface of the fourth insulating layer and the outer wall of the plug;

[0032] Removing the first electrode material layer on the surface of the fourth insulating layer, and using the first electrode material layer on the side wall of the groove and the outer wall of the plug as the first electrode;

[0033] Forming a storage material to cover the surface of the fourth insulating layer and the outer wall of the first electrode;

[0034] Removing the storage material on the surface of the fourth insulating layer and the top wall of the first electrode, and using the storage material on the side wall of the first electrode as the storage material structure layer;

[0035] Forming a second electrode material layer to cover the surface of the fourth insulating layer, the top wall of the first electrode, and the outer wall of the storage material structure layer;

[0036] Using the insulating structure layer as a polishing stop layer, performing a polishing process, and using the remaining second electrode material layer in the groove as the second electrode.

[0037] In summary, in the present invention, a plug is formed in a groove in an insulating structure layer. The plug penetrates the insulating structure layer along the side wall of the groove and is connected to a first wire. A first electrode covers the side wall of the groove and the plug exposed in the groove to be electrically connected to the first wire. A second electrode is disposed in the groove and is disposed opposite to the first electrode. A storage material structure layer is filled between the first electrode and the second electrode. Thus, an embedded storage structure arranged horizontally by the first electrode, the storage structure material layer, and the second electrode is formed in the groove in the insulating structure layer. The width of the embedded storage structure in the horizontal direction is the sum of the widths of the three. The height of the embedded storage structure in the vertical direction is the height of the area where the three are directly opposite (the height of any one of the three). It should be specifically noted that when the horizontally arranged storage structure in this embodiment is embedded into a device with a lower process node, the originally relatively thick thickness of the storage structure stacked longitudinally can be converted into the width arranged horizontally, and the side where the three film layers of the storage structure are directly opposite is used as the height. Thus, the limitation that the storage structure cannot be directly embedded between two adjacent interconnect layers of a device with a lower process node due to its relatively thick overall thickness is broken through. The embedded storage structure provided in this embodiment can preferably be compatible with the original (conventional CMOS process) interconnect process of the device and ensure the performance of the device (including the embedded storage structure). In addition, the embedded storage structure of this embodiment can also be applied to devices with higher process nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Those of ordinary skill in the art should understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention.

[0039] Figure 1 is a schematic diagram of an embedded storage structure in the related art;

[0040] Figure 2 is a flowchart of a manufacturing method of an embedded memory provided in Embodiment 1;

[0041] Figures 3a to 3o is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of the embedded memory provided in Embodiment 1.

[0042] Figure 1 In [the figure]: 10'-substrate; 11'-first interconnecting line; 12'-lower electrode; 13'-resistive switching structure layer; 14'-upper electrode; 15'-second interconnecting line.

[0043] Figures 3a to 3oIn: 10 - semiconductor substrate; 11 - first wire; 21 - insulating structure layer; 21a - first insulating layer; 21b - second insulating layer; 21c - third insulating layer; 22 - groove; 23 - fourth insulating layer; 24 - sacrificial material layer; 25 - via; 26a - plug material layer; 26 - plug; 27a - first electrode material layer; 27 - first electrode; 28 - storage material structure layer; 28a - first storage material layer; 28b - second storage material layer; 29a - second electrode material layer; 29 - second electrode; 30 - storage structure; 31 - patterned mask; 32 - isolation material layer; 33 - interlayer dielectric layer; 34 - second wire. Detailed implementation

[0044] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are in a very simplified form and not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the emphasis to be shown in each drawing is different, and sometimes different scales are used.

[0045] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features, unless the content clearly indicates otherwise.

[0046] Embodiment 1

[0047] Embodiment 1 provides a method for manufacturing an embedded memory.

[0048] Figure 1 is a flowchart of the method for manufacturing the embedded memory provided in Embodiment 1.

[0049] As Figure 1 shown, the method for manufacturing the embedded memory provided in this embodiment includes:

[0050] S01: Provide a semiconductor substrate with a first wire disposed therein;

[0051] S02: Form an insulating structure layer to cover the semiconductor substrate, and form a groove in the insulating structure layer above the first wire;

[0052] S03: Form a plug along the side wall of the groove to penetrate through the insulating structure layer to connect the first wire.

[0053] S04: A first electrode, a storage material structure layer, and a second electrode are arranged in sequence along the bottom wall of the groove in the groove. The first electrode is located on the side wall of the groove and is connected to the plug in the groove. The second electrode is disposed opposite to the first electrode, and the storage material structure layer is filled between the first electrode and the second electrode.

[0054] S05: Form a second wire above the second electrode and connect it to the second electrode.

[0055] Figures 3a to 3o FIG. is a schematic structural diagram corresponding to the corresponding steps of the manufacturing method of the embedded memory provided in Embodiment 1. Next, the manufacturing method of the embedded memory will be described in detail with reference to Figures 3a to 3o FIG..

[0056] First, please refer to Figure 3a FIG., and perform step S01 to provide a semiconductor substrate 10 in which a first wire 11 is provided.

[0057] The material of the semiconductor substrate 10 may include any suitable substrate material well-known to those skilled in the art. For example, it may be at least one of the materials mentioned below: silicon, glass, quartz, and plastic, etc.

[0058] A semiconductor device layer and an interconnect layer (or a part of the interconnect layer) connected to the semiconductor device layer may be sequentially formed in the semiconductor substrate 10. Among them, the semiconductor device layer may include any suitable semiconductor device, such as a logic device. The interconnect layer may include a contact layer (also called a zero-th metal layer) for leading out the semiconductor device layer and an N-th metal layer, where N is an integer greater than or equal to 1.

[0059] In this embodiment, the semiconductor device may include a transistor formed in the semiconductor substrate 10. A plurality of first wires 11 are exposed on the surface of the semiconductor substrate 10, and at least part of the first wires 11 are respectively connected to a transistor in the semiconductor substrate 10. The first wire 11 may be an interconnect line in the zero-th metal layer or the N-th metal layer.

[0060] Next, please refer to Figure 3b FIG., and perform step S02 to form an insulating structure layer 21 to cover the semiconductor substrate 10 and form a groove 22 in the insulating structure layer 21 above the first wire 11.

[0061] Among them, the insulating structure layer 21 may include one or more layers of insulating materials, and the materials of two adjacent insulating materials in the multiple layers of insulating materials are different. In a preferred example, the insulating structure layer 21 may include a first insulating layer 21a, a second insulating layer 21b, and a third insulating layer 21c formed in sequence from bottom to top. The first insulating layer 21a and the second insulating layer 21b may serve as isolation layers for the first wire 11 (the thickness thereof is, for example, 300 angstroms to 400 angstroms). The third insulating layer 21c is used to provide a space to accommodate the subsequent embedded storage structure 30 and provide a corresponding process window, and its thickness may be greater than the sum of the thicknesses of the first insulating layer 21a and the second insulating layer 21b (the thickness thereof is, for example, 600 angstroms to 700 angstroms), and its material may be the same as or close to the material of the interlayer dielectric layer between the interconnect layers.

[0062] The step of forming the groove 22 in the insulating structure layer 21 may include: forming a patterned mask on the third insulating layer 21c, at least one edge of the opening of which projects onto the surface of the first wire 11 (that is, at least one edge of the opening is located above the first wire 11), and then performing an etching process with the second insulating layer 21b as an etching stop layer, and forming a groove 22 in the third insulating layer 21c to expose the surface of the second insulating layer 21b. In this embodiment, the formed groove 22 (top view) may be rectangular, and the two edges of the groove 22 respectively project onto two first wires 11 (that is, both ends of the groove 22 are respectively located above the two first wires 11), so as to form two embedded storage structures in one groove 22 at the same time.

[0063] Next, perform step S03 to form a plug 26 through the insulating structure layer 21 along the side wall of the groove 22 to connect to the first wire 11.

[0064] Specifically, please refer to Figure 3c , form a fourth insulating layer 23 to cover the surface of the insulating structure layer 21 and the inner wall of the groove 22. The fourth insulating layer 23 may preferably be a dielectric material with a better isolation effect on the oxygen source, so as to serve as an isolation layer for the embedded storage structure in the groove 22 to prevent the storage material from oxidizing and deteriorating. The material of the fourth insulating layer 23 may be, for example, silicon carbonitride. In addition, the fourth insulating layer 23 may also serve as a mask stop layer in subsequent mask processes and a hard mask layer in etching processes.

[0065] Please refer to Figure 3d, a sacrificial material layer 24 is formed to cover the fourth insulating layer 23 and fill the groove 22, and a patterning process is performed to form a through hole 25 that penetrates the sacrificial material layer 24, the fourth insulating layer 23, the second insulating layer 21b, and the first insulating layer 21a, exposing the surface of the first wire 11. A part of the through hole 25 is embedded in the fourth insulating layer 23 on the side wall of the groove 22, and another part of the through hole 25 is embedded in the sacrificial material layer 24 in the groove 22. Among them, the material of the sacrificial material layer 24 can be different from that of the fourth insulating layer 23, and it fills the groove 22 completely; when performing the patterning process, a bottom anti-reflection layer can also be used to cover the sacrificial material layer 24 to form a relatively flat surface above the groove 22, then a patterned mask is formed, and an etching process is performed to form two through holes 25 exposing the first wire 11 at two opposite edges of the groove 22. The opening width of the through hole 25 can be, for example, 70 nanometers to 100 nanometers, a part of it is embedded in the fourth insulating layer 23 on the side wall of the groove 22, and the sacrificial material layer 24 in the groove 22 is exposed. In addition, in some examples, in addition to being embedded in the fourth insulating layer 23 on the side wall of the groove 22 and the sacrificial material layer 24 in the groove 22, the through hole 25 can also be partially embedded in the third insulating layer 21c.

[0066] Please refer to Figure 3e , a plug material layer 26a is formed to cover the surface of the sacrificial material layer and fill the through hole 25. Among them, the material of the plug material layer 26a can be a conductive material suitable for forming the plug 26, for example, including tungsten metal.

[0067] Please refer to Figure 3f_1 and Figure 3f_2 , using the surface of the fourth insulating layer 23 as a polishing stop layer, a polishing process is performed, and then the remaining plug material layer 26a is removed, and the plug material layer 26a in the through hole 25 is used as the plug 26. Figure 3f_1 is a top view schematic diagram, Figure 3f_2 is a cross-sectional schematic diagram. One end of the plug 26 close to the semiconductor substrate 10 is connected to the first wire 11, and the other end away from the semiconductor substrate 10 can be flush with the fourth insulating layer 23 outside the groove 22. A part of the side wall of the plug 26 is embedded in the second insulating layer 21b, the third insulating layer 21c, and the fourth insulating layer 23, and the other part of the side wall is exposed in the groove 22.

[0068] Next, step S04 is performed to form a first electrode 27, a storage material structure layer 28, and a second electrode 29 arranged in sequence along the bottom wall in the groove 22. The first electrode 27 is located on the side wall of the groove 22 and is connected to the plug 26, the second electrode 29 is disposed opposite to the first electrode 27, and the storage material structure layer 28 is filled between the first electrode 27 and the second electrode 29.

[0069] Specifically, please refer to Figure 3g, a first electrode material layer 27a is formed to cover the surface of the fourth insulating layer 23 (including the fourth insulating layer 23 outside and inside the groove 22) and the outer wall of the plug 26. The material of the first electrode material layer 27a may include, for example, titanium nitride, titanium, tantalum nitride, or tantalum, etc. The thickness of the first electrode material layer 27a on the sidewalls of the groove 22 and the plug 26 may be 5 nanometers to 20 nanometers, that is, the width of the subsequently formed first electrode may be 5 nanometers to 20 nanometers.

[0070] Please refer to Figure 3h , the first electrode material layer 27a on the surface of the fourth insulating layer 23 outside the groove 22 and on the bottom wall of the groove 22 (on the fourth insulating layer 23 at the bottom of the groove) is removed, and the first electrode material layer 27a on the sidewalls of the groove 22 and the outer wall of the plug 26 is used as the first electrode 27. The formed first electrode 27 is disposed along the fourth insulating layer 23 on the sidewall of the groove 22 and covers the sidewall of the plug 26. Among them, maskless dry etching (perpendicular to the substrate surface) can be used, and over-etching is appropriately performed to ensure that the first electrode material layer 27a on the surface of the fourth insulating layer 23 outside the groove 22 and on the bottom wall of the groove 22 is removed completely.

[0071] Please refer to Figure 3i , a storage material structure layer 28 is formed on the sidewall of the first electrode 27. The specific steps may include: forming a storage material to cover the surface of the fourth insulating layer 23 (including the fourth insulating layer 23 outside and inside the groove 22) and the outer wall of the first electrode 27; removing the storage material on the surface of the fourth insulating layer 23 outside the groove 22, the top wall of the first electrode 27, and the bottom wall of the groove 22 (on the fourth insulating layer 23 at the bottom of the groove), and using the storage material on the sidewall of the first electrode 27 as the storage material structure layer 28. Among them, the storage material structure layer 28 may be any suitable type of storage material layer, which may include a single layer of storage material or a stack composed of at least two layers of storage materials. In this embodiment, the type of the embedded storage structure 30 may be a resistive random access memory (RRAM) structure 30, that is, the material of the storage material structure layer 28 is a resistive random access memory material.

[0072] In this embodiment, the storage material structure layer 28 may include two layers of resistive change materials. The specific formation process may include: forming a first storage material to cover the surface of the insulating structure layer 21 and the outer wall of the first electrode 27. The material of the first storage material may include, for example, hafnium oxide, titanium, titanium oxide, tantalum oxide, etc. The thickness of the first storage material attached to the side wall of the first electrode 27 may be 20 angstroms to 150 angstroms, so that the side wall width of the subsequently formed first storage material layer 28a is 20 angstroms to 150 angstroms. Then, remove the first storage material on the surface of the fourth insulating layer 23 outside the groove 22, the top wall of the first electrode 27, and the bottom wall of the groove 22, and use the first storage material on the side wall of the first electrode 27 as the first storage material layer 28a, that is, the side wall width of the first storage material layer 28a may be 20 angstroms to 150 angstroms. Similarly, form a second storage material layer 28b on the side wall of the first storage material layer 28a, and use the first storage material layer 28a and the second storage material layer 28b as the storage material structure layer 28.

[0073] Please refer to Figure 3j , form a second electrode material layer 29a to cover the fourth insulating layer 23, the first electrode 27, and the surface of the storage material structure layer 28, and fill the groove 22. The material of the second electrode material layer 29a may refer to the material of the first electrode 27, for example, titanium nitride or tantalum nitride. The thickness of the second electrode material layer 29a is preferably greater than the thickness of the first electrode material layer 27a, so that the second electrode material layer 29a fills the groove 22, thereby providing a larger process window for subsequent processes. In this embodiment, the thickness of the second electrode material layer 29a may be 400 angstroms to 500 angstroms.

[0074] Please refer to Figure 3k_1 and Figure 3k_2 , use the insulating structure layer 21 outside the groove 22 as a polishing stop layer, perform a polishing process to remove the second electrode material layer 29a and the fourth insulating layer 23 outside the groove 22, expose the surface of the insulating structure layer 21, and use the remaining second electrode material layer 29a in the groove 22 as the second electrode 29. Among them, Figure 3k_1 is a cross-sectional schematic diagram, Figure 3k_2 is a top view schematic diagram. During the polishing process (chemical mechanical polishing), the overall height of the groove 22 can also be controlled, that is, the heights of the first electrode 27, the storage material structure layer 28, and the second electrode 29 are controlled, for example, within 350 angstroms. In addition, a surface oxidation process is also used to further insulate the above surface to prevent leakage between the first electrode 27 and the second electrode 29 and increase the reliability of the device.

[0075] Please refer to Figure 3l_1 and Figure 3l_2, a patterned mask 31 is formed on the surfaces of the first electrode 27, the storage material structure layer 28, the second electrode 29, the plug 26, the fourth insulating layer 23, and the insulating structure layer 21. Among them, Figure 3l_1 is a cross-sectional schematic diagram, Figure 3l_2 is a top-down schematic diagram. In this embodiment, an example of forming an embedded resistive random access memory (RRAM) structure 30 in a groove 22 (rectangular shape) is used for illustration. Two patterned masks 31 in a rectangular shape are provided on one groove 22. Each of the two patterned masks 31 covers a plug 26 (spaced along the arrangement direction of the plug 26) and the surfaces of the first electrode 27, the storage material structure layer 28, the second electrode 29, and the insulating structure layer 21 around it. That is, the mutually remote ends of the two patterned masks 31 are disposed on the insulating structure layers 21 on both sides, and the mutually close ends of the two patterned masks 31 are on the second electrode 29 and are spaced apart. The spaced area between the two patterned masks, that is, the exposed portions of the first electrode 27, the storage material structure layer 28, the second electrode 29, and the insulating structure layer 21, can be used to truncate the above three.

[0076] Please refer to Figure 3m_1 and Figure 3m_2 , using the patterned mask 31, etch the first electrode 27, the storage material structure layer 28, and the second electrode 29 to form two embedded storage structures 30 in the groove 22. Each embedded storage structure 30 corresponds to a plug 26 (i.e., a first wire 11), a first electrode 27, a storage material structure layer 28, and a second electrode 29, that is, two IT1R embedded storage structures 30. In one of the embedded storage structures 30 in this embodiment, the second electrode 29 is in a rectangular shape, the storage material structure layer 28 covers the second electrode 29 along three side surfaces of the second electrode 29 (rectangular), the first electrode 27 on the side wall of the groove 22 covers the storage material structure layer 28 along three side surfaces of the storage material structure layer 28, and the plug 26 is partially embedded in the first electrode 27. That is to say, the first electrode 27 partially surrounds the second electrode 29, and the storage material structure layer 28 is filled between the first electrode 27 and the second electrode 29 and is in contact with both of them.

[0077] Of course, in the above etching process, it is also feasible to synchronously etch the exposed insulating structure layer 21 by a certain thickness.

[0078] Accordingly, an embedded memory structure 30 formed by a first electrode 27, a material layer of the memory structure 30, and a second electrode 29 arranged horizontally is formed in the groove 22 of the insulating structure layer 21. The width of the embedded memory structure 30 in the horizontal direction is the sum of the sidewall widths of the three, and the height of the embedded memory structure 30 in the vertical direction is the height of the facing area of the three (the height of any one of the three). Therefore, when the horizontally arranged memory structure 30 in this embodiment is embedded into a device with a lower process node, the originally thick thickness of the memory structure 30 stacked longitudinally can be converted into a width arranged horizontally, and one side where the three film layers of the memory structure 30 face each other is used as the height, thereby breaking through the limitation that the memory structure 30 cannot be directly embedded between two adjacent interconnect layers of a device with a lower process node due to its overall thick thickness. Of course, the embedded memory structure 30 in this embodiment can also be applied to devices with a higher process node.

[0079] In addition, compared with the two electrodes arranged vertically in the related art (as shown in Figure 1 ), in this embodiment, the formed first electrode 27 partially surrounds (surrounds on three sides) the second electrode 29, which can increase the facing area of the first electrode 27 and the second electrode 29 on the same substrate area, and is more conducive to miniaturizing the size of the embedded memory structure 30 and its memory performance.

[0080] Please refer to Figure 3n , an isolation material layer 32 can also be formed to cover the surface of the embedded memory structure 30 to protect the embedded memory structure 30. The material of the isolation material layer 32 can refer to the material of the fourth insulating layer 23. In addition, after forming the isolation material layer 32 to cover the surface of the embedded memory structure 30 and the insulating structure layer 21, the isolation material layer 32 on the insulating structure layer 21 can be removed by a photolithography process, so that the film thickness on the first wire 11 is basically the same as that before the memory structure 30 is embedded, so that the capacitance, inductance, and electrical signal of the device hardly change after the memory structure 30 is embedded.

[0081] Next, please refer to Figure 3o , perform step S05 to form a second wire 34 above the second electrode 29 and connect it to the second electrode 29.

[0082] Specifically, an interlayer dielectric layer 33 can be formed on the insulating structure layer 21 and the isolation material layer 32, and then a (N + 1)th interconnect layer is formed in the interlayer dielectric layer 33, which includes a second wire 34 connected to the second electrode 29. The material of the interlayer dielectric layer 33 can include, for example, silicon oxide doped with carbon and hydrogen (silicon carbon hydroxide). Since the height of the embedded memory structure 30 in this embodiment is relatively low, the interlayer dielectric layer 33 can be formed with reference to the parameters (such as thickness) and processes before embedding, so as to improve the compatibility with the existing process. Taking a device with a relatively low process node (such as 28 nm and below) as an example, the distance between the first wire 11 and the second wire 34 can be 500 angstroms or less (such as 400 angstroms to 500 angstroms), and the height of the embedded memory structure 30 in this embodiment can be 350 angstroms to 400 angstroms.

[0083] Embodiment 2

[0084] Embodiment 2 provides an embedded memory.

[0085] Figure 3o It is a schematic structural diagram of the embedded memory provided in Embodiment 2.

[0086] As Figure 3o shown, the embedded memory provided in this embodiment includes a semiconductor substrate 10, a first wire 11, an insulating structure layer 21, a plug 26, a first electrode 27, a memory material structure layer 28, a second electrode 29, and a second wire 34. The semiconductor substrate 10 has the first wire 11 disposed therein; the insulating structure layer 21 covers the first wire 11, and a groove 22 is provided in the insulating structure layer 21; the plug 26 penetrates the insulating structure layer 21 along the sidewall of the groove 22 to connect to the first wire 11; the first electrode 27, the memory material structure layer 28, and the second electrode 29 are sequentially arranged along the bottom wall of the groove 22. The first electrode 27 is located on the sidewall of the groove 22 and is connected to the plug 26 in the groove 22. The second electrode 29 is disposed opposite to the first electrode 27, and the memory material structure layer 28 is filled between the first electrode 27 and the second electrode 29; the second wire 34 is disposed above the second electrode 29 and is connected to the second electrode 29.

[0087] A semiconductor device layer and an interconnect layer (or a part of the interconnect layer) connected to the semiconductor device layer may be sequentially formed in the semiconductor substrate 10. Among them, the semiconductor device layer may include any suitable semiconductor devices, such as logic devices. The interconnect layer may include a contact layer (also referred to as the zero-th metal layer) or the N-th metal layer that leads out the semiconductor device layer, that is, N may be an integer greater than or equal to 0. Among them, the semiconductor device may include a transistor formed in the semiconductor substrate 10. A plurality of first wires 11 are exposed on the surface of the semiconductor substrate 10, and one first wire 11 (that is, one first electrode 27) may be connected to one transistor in the semiconductor substrate 10. The first wire 11 may be an interconnect line in the N-th metal layer (N is an integer greater than or equal to zero), and the second wire 34 may be an interconnect line in the (N + 1)-th metal layer. The embedded storage structure 30 is disposed between the first wire 11 and the second wire 34, and one second electrode 29 is connected to one second wire 34.

[0088] In this embodiment, the embedded memory structure 30 can be disposed in the groove 22 in the insulating structure layer 21 on the semiconductor substrate 10. The fourth insulating layer 23 covers the inner wall of the groove 22 (including the side wall and the bottom wall of the groove 22). The plug 26 penetrates through the fourth insulating layer 23 and the insulating structure layer 21 along the fourth insulating layer 23 on the side wall of the groove 22 and is connected to the first wire 11. A part of the side wall of the plug 26 is embedded in the fourth insulating layer 23, and another part of the side wall of the plug 26 is exposed in the groove 22. The side wall of the first electrode 27 is in contact with the exposed side wall of the plug 26 to achieve electrical connection. The second electrode 29 is disposed on the fourth insulating layer 23 at the bottom wall of the groove 22, and is disposed opposite to the first electrode 27 at an interval. The storage material structure layer 28 is disposed (filled) between the first electrode 27 and the second electrode 29 to form an embedded memory structure 30 arranged horizontally along the bottom wall (the fourth insulating layer 23) of the groove 22 in the groove 22. Wherein, the groove 22 can be rectangular, and an embedded memory structure 30 with a 1T1R structure is formed at each end of the groove 22. The two embedded memory structures 30 can be symmetric and independent of each other. The two first electrodes 27 cover three side walls of their corresponding parts along the side wall (the fourth insulating layer 23) of the groove 22. The two second electrodes 29 are correspondingly disposed at the middle positions on the bottom wall of the groove 22, so that the first electrode 27 surrounds the second electrode 29 on three sides, thereby increasing the facing area of the first electrode 27 and the second electrode 29 on the same substrate area, which is more conducive to miniaturizing the size of the embedded memory structure 30 and its storage performance. The storage material structure layer 28 can be any suitable type of storage material layer, which can include a single layer of storage material or a stack composed of at least two layers of storage materials. In this embodiment, the type of the embedded memory structure 30 can be a resistive change memory structure 30, that is, the material of the storage material structure layer 28 is a resistive change storage material. The storage material structure layer 28 can include a first storage material layer 28a covering the side wall of the first electrode 27 and a second storage material layer 28b covering the side wall of the first storage material layer 28a. The side wall of the second storage material layer 28b is in contact with the side wall of the second electrode 29.

[0089] In summary, in the present invention, plugs are formed in the grooves of the insulating structure layer. The plugs penetrate the insulating structure layer along the side walls of the grooves and are connected to the first wire. The first electrode covers the side walls of the grooves and the plugs exposed in the grooves to be electrically connected to the first wire. The second electrode is disposed in the grooves and is opposite to the first electrode. The storage material structure layer is filled between the first electrode and the second electrode. Thus, an embedded storage structure arranged horizontally by the first electrode, the storage structure material layer, and the second electrode is formed in the grooves of the insulating structure layer. The width of the embedded storage structure in the horizontal direction is the sum of the widths of the three. The height of the embedded storage structure in the vertical direction is the height of the area where the three are directly opposite (the height of any one of the three). It should be particularly noted that when the horizontally arranged storage structure in this embodiment is embedded in a device with a lower process node, the originally relatively thick thickness of the storage structure stacked longitudinally can be converted into the width arranged horizontally, and the side where the three film layers of the storage structure are directly opposite is used as the height. Thus, the limitation that the storage structure cannot be directly embedded between two adjacent interconnect layers of a device with a lower process node due to its relatively thick overall thickness is broken through. The embedded storage structure provided in this embodiment can preferably be compatible with the original (conventional CMOS process) interconnect process of the device and ensure the performance of the device (including the embedded storage structure). In addition, the embedded storage structure of this embodiment can also be applied to devices with a higher process node.

[0090] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. An embedded memory, characterized in that, comprising: a semiconductor substrate with a first wire disposed therein; an insulating structure layer covering the first wire, and a groove is provided in the insulating structure layer; a plug passing through the insulating structure layer along the side wall of the groove to connect the first wire; a first electrode, a storage material structure layer, and a second electrode disposed in sequence along the bottom wall of the groove, the first electrode is located on the side wall of the groove and is connected to the plug in the groove, the second electrode is disposed opposite to the first electrode, and the storage material structure layer is filled between the first electrode and the second electrode; a second wire disposed above the second electrode and connected to the second electrode.

2. The embedded memory according to claim 1, characterized in that, the insulating structure layer includes a first insulating layer, a second insulating layer, and a third insulating layer sequentially disposed in a direction away from the first wire, and the groove is formed in the third insulating layer.

3. The embedded memory according to claim 2, characterized in that, the inner wall of the groove is further covered with a fourth insulating layer, and the plug is partially embedded in the fourth insulating layer on the side wall of the groove and sequentially penetrates through the fourth insulating layer, the second insulating layer, and the first insulating layer to communicate with the first wire.

4. The embedded memory according to claim 1, characterized in that, the cross-sectional shape of the groove is rectangular, the first electrode covers the side wall of the groove, and the first electrode partially surrounds the second electrode.

5. The embedded memory according to claim 1 or 4, characterized in that, one plug is provided at each end of the groove and is respectively connected to one first wire, and two embedded storage structures are disposed in the groove and are respectively connected to one plug, and each embedded storage structure includes the first electrode, the storage material structure layer, and the second electrode.

6. A manufacturing method of an embedded memory, characterized in that, comprising: providing a semiconductor substrate with a first wire disposed therein; forming an insulating structure layer to cover the semiconductor substrate, and forming a groove in the insulating structure layer above the first wire; forming a plug along the side wall of the groove to penetrate through the insulating structure layer to connect the first wire; forming a first electrode, a storage material structure layer, and a second electrode in sequence along the bottom wall of the groove in the groove, the first electrode is located on the side wall of the groove and is connected to the plug in the groove, the second electrode is disposed opposite to the first electrode, and the storage material structure layer is filled between the first electrode and the second electrode; forming a second wire above the second electrode and connecting it to the second electrode.

7. The manufacturing method of the embedded memory according to claim 6, characterized in that, the step of forming the insulating structure layer and the groove includes: forming the first to third insulating layers in sequence on the first wire; using the second insulating layer as an etching stop layer to form the groove in the third insulating layer, and the edge projection of the groove is on the first wire.

8. The manufacturing method of the embedded memory according to claim 6, characterized in that, a fourth insulating layer is further formed to cover the inner wall of the groove.

9. The manufacturing method of the embedded memory according to claim 8, characterized in that, the step of forming the plug includes: forming a sacrificial material layer to cover the fourth insulating layer and fill the groove; performing a patterning process to form a through hole penetrating the sacrificial material layer, the fourth insulating layer, and the insulating structure layer, exposing the surface of the first wire; forming a plug material layer to cover the surface of the sacrificial material layer and fill the through hole; using the surface of the fourth insulating layer as a polishing stop layer, performing a polishing process, and using the plug material layer in the through hole as the plug.

10. The manufacturing method of the embedded memory according to claim 9, characterized in that, the steps of forming the first electrode, the storage material structure layer, and the second electrode include: forming a first electrode material layer to cover the surface of the fourth insulating layer and the outer wall of the plug; removing the first electrode material layer on the surface of the fourth insulating layer, and using the first electrode material layer on the side wall of the groove and the outer wall of the plug as the first electrode; forming a storage material to cover the surface of the fourth insulating layer and the outer wall of the first electrode; removing the storage material on the surface of the fourth insulating layer and the top wall of the first electrode, and using the storage material on the side wall of the first electrode as the storage material structure layer; forming a second electrode material layer to cover the surface of the fourth insulating layer, the top wall of the first electrode, and the outer wall of the storage material structure layer; using the insulating structure layer as a polishing stop layer, performing a polishing process, and using the remaining second electrode material layer in the groove as the second electrode.

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