Phase change memory

Abstract

The invention provides a phase change memory, the phase change memory comprises a substrate and at least one memory cell group which is located on the substrate and is stacked along a first direction, and each memory cell group comprises a first memory cell and a second memory cell which is located at one side, far away from the substrate, of the first memory cell. The first memory cell includes a first bottom electrode, a first gate layer, a first intermediate electrode, a first memory layer, and a first top electrode stacked in a first direction. The second memory cell includes a second bottom electrode, a second gate layer, a second intermediate electrode, a second memory layer, and a second top electrode stacked in the first direction, the second gate layer being different from the first gate layer. Therefore, the threshold voltage difference caused by opposite current directions of the first gating layer and the second gating layer can be made up, so that the threshold voltage difference of the first gating layer and the second gating layer is reduced until the threshold voltages of the first gating layer and the second gating layer are equivalent, and the first storage unit and the second storage unit can be operated by adopting the same electric signal.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a phase change memory. Background Art

[0002] With the development of artificial intelligence and in-memory computing technologies, higher requirements are put forward for data storage and computing capabilities. In the current von Neumann computing architecture, a large amount of data needs to be read and stored between DRAM and storage SSD. There is a huge performance gap between them, resulting in a bottleneck in the performance improvement of the current von Neumann computing system. At present, it is proposed to use Storage Class Memory (SCM) to connect DRAM and SSD to improve the current storage architecture. Among several emerging storage class memories, the most mature one is the phase change memory, and among them, the three-dimensional phase change memory is the most promising, with the advantages of large capacity, high speed, non-volatility, and good cycling performance.

[0003] The storage unit of the phase change memory includes a phase change storage layer, a selection layer (Ovonic Threshold Switching, OTS), and electrodes, etc. Among them, the role of the selection layer is to help correct addressing, reduce miswriting, misreading, and leakage current.

[0004] For a phase change memory with multiple stacked storage units, the current entering from the word line will enter the upper and lower asymmetric storage units from opposite directions respectively, that is, the current enters the upper selection layer and the lower selection layer from opposite directions respectively, resulting in a significant difference in the threshold voltages of the upper selection layer and the lower selection layer, thus complicating the design of electrical signals. Summary of the Invention

[0005] An embodiment of this application provides a phase change memory, which can reduce the difference in the threshold voltages of the first selection layer and the second selection layer and simplify the design of electrical signals.

[0006] An embodiment of this application provides a phase change memory, including: a substrate; at least one storage unit group stacked on the substrate along a first direction, each storage unit group including a first storage unit and a second storage unit, the second storage unit being located on a side of the first storage unit away from the substrate, the first direction being perpendicular to the surface of the substrate; the first storage unit including a first bottom electrode, a first selection layer, a first intermediate electrode, a first storage layer, and a first top electrode stacked along the first direction, the first storage layer being located on a side of the first selection layer away from the substrate; the second storage unit including a second bottom electrode, a second selection layer, a second intermediate electrode, a second storage layer, and a second top electrode stacked along the first direction, the second storage layer being located on a side of the second selection layer away from the substrate, and the second selection layer being different from the first selection layer.

[0007] In some embodiments, the material of the first strobing layer includes a first matrix material, the material of the second strobing layer includes a second matrix material, and the first matrix material is the same as the second matrix material; at least one of the first matrix material and the second matrix material is doped, and the doping of the first matrix material is different from that of the second matrix material.

[0008] In some embodiments, the first matrix material is doped with first doping particles, and the first doping particles include at least one of boron, carbon, and nitrogen.

[0009] In some embodiments, the second matrix material is doped with second doping particles, and the second doping particles include at least one of silicon and sulfur.

[0010] In some embodiments, at least one of the first matrix material and the second matrix material has doping particles, and the atomic percentage concentration of the doping particles is 0 at% to 10 at%.

[0011] In some embodiments, the thickness of the first strobing layer is the same as the thickness of the second strobing layer; when the first matrix material is doped, the threshold voltage of the first strobing layer is less than the threshold voltage of the first matrix material; when the second matrix material is doped, the threshold voltage of the second strobing layer is greater than the threshold voltage of the second matrix material.

[0012] In some embodiments, the thickness of the second strobing layer is greater than the thickness of the first strobing layer.

[0013] In some embodiments, the materials of the first storage layer and the second storage layer both include a first chalcogenide, and the material of the first storage layer is the same as the material of the second storage layer; the first strobing layer and the second strobing layer include the same matrix material, the matrix material includes a second chalcogenide, and the material of the first chalcogenide is different from the material of the second chalcogenide.

[0014] In some embodiments, the first strobing layer has a first threshold voltage, the second strobing layer has a second threshold voltage, and the absolute value of the difference between the first threshold voltage and the second threshold voltage is 0 V to 0.5 V.

[0015] In some embodiments, it further includes: a first conductive wire, located on a side of the first storage unit away from the second storage unit and electrically connected to the first bottom electrode; a second conductive wire, located between the first storage unit and the second storage unit and electrically connected to the first top electrode and the second bottom electrode; a third conductive wire, located on a side of the second storage unit away from the second conductive wire and electrically connected to the second top electrode.

[0016] In the phase change memory according to the embodiment of the present application, by setting the first select gate layer and the second select gate layer differently, the threshold voltage difference caused by the opposite current directions of the first select gate layer and the second select gate layer can be compensated, so as to reduce the threshold voltage difference between the first select gate layer and the second select gate layer until the threshold voltages of the two are equivalent. In this way, the same electrical signal can be used to operate the first storage unit and the second storage unit, simplifying the electrical signal design, which helps to achieve more layers of stacking, improve the storage capacity, and can also reduce the performance change difference of different layer devices during use, improving the reliability of the device.

[0017] Other features and advantages of the present application will be described in detail in the following specific implementation section. Brief Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] In order to more fully understand the present application and its beneficial effects, the following description will be made in conjunction with the drawings, where the same reference numerals represent the same parts in the following description.

[0020] Figure 1 is a schematic cross-sectional structure diagram of a phase change memory provided by an embodiment of the present application;

[0021] Figure 2 is a schematic cross-sectional structure diagram of a phase change memory provided by some embodiments of the present application;

[0022] Figure 3 is a graph of the electrical property test results of doped silicon in the second matrix material provided by some embodiments of the present application;

[0023] Figure 4 is a schematic cross-sectional structure diagram of a phase change memory provided by some embodiments of the present application;

[0024] Figure 5 is a schematic cross-sectional structure diagram of a phase change memory provided by some embodiments of the present application;

[0025] Figure 6 is a schematic three-dimensional structure diagram of a phase change memory provided by some embodiments of the present application. Detailed Description of the Embodiments

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0027] Please refer to Figure 1 , Figure 1 which is a schematic cross-sectional structure diagram of a phase change memory provided by an embodiment of the present application.

[0028] Taking a three-dimensional phase change memory with two stacked layers as an example, the same word line (WL) is shared between different layers of the phase change memory, and two bit lines are respectively located at the upper and lower ends of the stacked structure, called the top bit line (TBL) and the bottom bit line (BBL). When an electrical signal is loaded, the word line WL is loaded with a high level, and the top bit line TBL or the bottom bit line BBL is loaded with a low level. A storage cell with the current direction flowing from the word line WL to the bottom bit line BBL is defined as the first storage cell C1, and a storage cell with the current direction flowing from the word line WL to the top bit line TBL is defined as the second storage cell C2, that is to say, the two layers of storage cells share an electrical signal with a high level.

[0029] The first storage cell C1 includes a first bottom electrode B1, a first select gate layer S1, a first intermediate electrode M1, a first storage layer P1, and a first top electrode T1 stacked in sequence on the bottom bit line BBL; the second storage cell C2 includes a second bottom electrode B2, a second select gate layer S2, a second intermediate electrode M2, a second storage layer P2, and a second top electrode T2 stacked in sequence on the word line WL. The first select gate layer S1 is the same as the second select gate layer S2, and "the same" means that the element composition and element concentration are the same.

[0030] In some embodiments, electrical performance tests are respectively performed on Figure 1 the first storage cell C1 and the second storage cell C2 in, and the object of the electrical performance test is the SET state threshold voltage of the storage cell, that is, the threshold voltage of the select gate layer. The results show that there is a difference in the threshold voltage between the second storage cell C2 and the first storage cell C1, that is, there is a difference in the threshold voltage between the second select gate layer S2 and the first select gate layer S1. This results in the inability to use the same current operation for the upper and lower layers. The difference in the threshold voltage between the upper and lower layers complicates the electrical signal design and reduces the device reliability.

[0031] Therefore, an embodiment of the present application provides a phase change memory, which includes: a substrate; at least one storage cell group stacked on the substrate along a first direction, each storage cell group including a first storage cell and a second storage cell, the second storage cell being located on a side of the first storage cell away from the substrate, the first direction being perpendicular to the surface of the substrate; the first storage cell including a first bottom electrode, a first select gate layer, a first intermediate electrode, a first storage layer, and a first top electrode stacked along the first direction, the first storage layer being located on a side of the first select gate layer away from the substrate; the second storage cell including a second bottom electrode, a second select gate layer, a second intermediate electrode, a second storage layer, and a second top electrode stacked along the first direction, the second storage layer being located on a side of the second select gate layer away from the substrate, and the second select gate layer being different from the first select gate layer.

[0032] By setting the first select gate layer and the second select gate layer to be different, the threshold voltage difference caused by the opposite current directions of the first select gate layer and the second select gate layer can be compensated, so as to reduce the threshold voltage difference between the first select gate layer and the second select gate layer until the threshold voltages of the two are equivalent. In this way, the same electrical signal can be used to operate the first storage cell and the second storage cell, simplifying the electrical signal design, facilitating the realization of more layers of stacking, increasing the storage capacity, and also reducing the performance variation difference of different layer devices during use, improving the reliability of the device.

[0033] The structure of the phase change memory provided by some embodiments of the present application will be described below with reference to the accompanying drawings.

[0034] Please refer to Figure 2 , Figure 2 which is a schematic cross-sectional structure diagram of the phase change memory provided by some embodiments of the present application.

[0035] The phase change memory 100 includes a substrate 10 and at least one memory cell group 20 stacked on the substrate 10 along a first direction Z. Each memory cell group 20 includes a first memory cell 21 and a second memory cell 22. The second memory cell 22 is located on a side of the first memory cell 21 away from the substrate 10. The first direction Z is perpendicular to the surface of the substrate 10. The first memory cell 21 includes a first bottom electrode 211, a first select gate layer 212, a first intermediate electrode 213, a first memory layer 214, and a first top electrode 215 stacked along the first direction Z. The first memory layer 214 is located on a side of the first select gate layer 212 away from the substrate 10. The second memory cell 22 includes a second bottom electrode 221, a second select gate layer 222, a second intermediate electrode 223, a second memory layer 224, and a second top electrode 225 stacked along the first direction Z. The second memory layer 224 is located on a side of the second select gate layer 222 away from the substrate 10. The second select gate layer 222 is different from the first select gate layer 212.

[0036] Wherein, the first direction Z represents the direction perpendicular to the surface of the substrate 10, the second direction X and the third direction Y represent the directions parallel to the surface of the substrate 10, and the second direction X is different from the third direction Y. In some embodiments, the first direction Z, the second direction X, and the third direction Y may be perpendicular to each other.

[0037] The phase change memory 100 may further include a first conductive wire 31, a second conductive wire 32, and a third conductive wire 33. The first conductive wire 31 is located on a side of the first memory cell 21 away from the second memory cell 22 and is electrically connected to the first bottom electrode 211. The second conductive wire 32 is located between the first memory cell 21 and the second memory cell 22 and is electrically connected to the first top electrode 215 and the second bottom electrode 221. The third conductive wire 33 is located on a side of the second memory cell 22 away from the second conductive wire 32 and is electrically connected to the second top electrode 225.

[0038] In this embodiment, the first conductive wire 31 and the third conductive wire 33 are bit lines, and the second conductive wire 32 is a word line. When an electrical signal is loaded, a high level is loaded on the second conductive wire 32, and low levels are loaded on the first conductive wire 31 and the third conductive wire 33. The first memory cell 21 and the second memory cell 22 share the second conductive wire 32. And when operating, the current direction of the first memory cell 21 is from the first top electrode 215 to the first bottom electrode 211, and the current direction of the second memory cell 22 is from the second bottom electrode 221 to the second top electrode 225.

[0039] That is to say, in the embodiments of the present application, two memory cells sharing a high-level signal are used as one of the memory cell groups 20. Conversely, two memory cells sharing a low-level signal cannot be used as one memory cell group, and they should belong to two different memory cell groups 20 respectively. That is, the current directions of the first memory cell 21 and the second memory cell 22 in one memory cell group 20 are opposite, rather than relative.

[0040] The phase change memory 100 may include 1, 2, 3, 4 or more memory cell groups 20. Starting from the substrate 10, a memory cell in an odd layer (such as 1, 3, 5) and a memory cell in an even layer (such as 2, 4, 6) above it form one memory cell group 20. In other words, in each memory cell group 20, the first memory cell 21 is a memory cell in an odd layer, and the second memory cell 22 is a memory cell in an even layer.

[0041] It should be noted that each memory cell has a SET state threshold voltage and a RESET state threshold voltage; in each memory cell, the select layer has an on-state threshold voltage, and the memory layer has a low-resistance state threshold voltage and a high-resistance state threshold voltage. Taking the first memory cell 21 as an example, when a voltage signal is applied to the first conductive wire 31 and the second conductive wire 32, when the partial voltage applied to both sides (the first bottom electrode 211 and the first intermediate electrode 213) of the first select layer 212 is greater than the on-state threshold voltage, the first select layer 212 is in the on state, and at this time the first memory layer 214 is still in the low-resistance state (i.e., the SET state); when the voltage signal is increased, when the partial voltage applied to both sides (the first intermediate electrode 213 and the first top electrode 215) of the first memory layer 214 is greater than the high-resistance state threshold voltage, the first memory layer 214 is in the high-resistance state (i.e., the RESET state). Therefore, the on-state threshold voltage of the first select layer 212 is the SET state threshold voltage of the first memory cell 21, and the high-resistance state threshold voltage of the first memory layer 214 is the RESET state threshold voltage of the first memory cell 21. In other words, adjusting the threshold voltage of the select layer is to adjust the SET state threshold voltage of the memory cell, and the matching of the threshold voltage of the select layer means the matching of the SET state threshold voltage of the memory cell.

[0042] It can be understood that the function of the select layer is to assist in correct addressing, reduce miswriting, misreading and leakage current. The select layer has a threshold conversion characteristic, and is converted into a low-resistance state (i.e., the on state) when the partial voltage applied to both sides of the select layer is higher than its threshold voltage, and is converted into a high-resistance state (i.e., the off state) when the partial voltage applied to both sides of the select layer is lower than its threshold voltage, so as to realize the function of current conduction and blocking and realize the addressing function.

[0043] In some embodiments, each conductive wire may be in direct contact with the electrode to which it is electrically connected, or an adhesion layer may be provided between the conductive wire and the electrode to which it is electrically connected to improve the adhesion force.

[0044] In some embodiments, the substrate 10 may be silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI), etc.

[0045] In some embodiments, the materials of the first bottom electrode 211, the first intermediate electrode 213, the first top electrode 215, the second bottom electrode 221, the second intermediate electrode 223, and the second top electrode 225 may each include at least one of carbon, amorphous carbon, titanium nitride, tantalum nitride, tantalum carbide, or a metal. The metal may include copper, tungsten, aluminum, gold, cobalt, titanium, tantalum, etc.

[0046] In some embodiments, the materials of the first storage layer 214 and the second storage layer 224 each include a first chalcogenide compound, and the materials of the first storage layer 214 and the second storage layer 224 are the same.

[0047] For example, the first chalcogenide compound includes at least one of germanium telluride (Ge-Te) compound, antimony telluride (Sb-Te) compound, germanium antimony telluride (Ge-Sb-Te) compound, silicon antimony telluride (Si-Sb-Te) compound, titanium antimony telluride (Ti-Sb-Te) compound, aluminum antimony telluride (Al-Sb-Te) compound, germanium antimony selenide (Ge-Sb-Se); germanium selenium gallium (Ge-Sb-Ga); germanium selenium bismuth (Ge-Sb-Bi).

[0048] In some embodiments, the first gate layer 212 and the second gate layer 222 include the same matrix material. The matrix material includes a second chalcogenide compound, and the materials of the first chalcogenide compound and the second chalcogenide compound are different.

[0049] For example, the second chalcogenide compound includes at least one of AsSeGe, SeGe, AsSe, InAsSeGe, SiAsSeGe, InSiAsSeGe, Ge-Te, B-Te, Ge-Te-As, Ge-S, Ga-S, Ge-As-S.

[0050] In some embodiments, the material of the first strobing layer 212 includes a first matrix material, the material of the second strobing layer 222 includes a second matrix material, and the first matrix material is the same as the second matrix material; at least one of the first matrix material and the second matrix material is doped, and the first matrix material and the second matrix material are doped differently.

[0051] For example, the first matrix material is doped with doping particles, or the second matrix material is doped with doping particles, or the first matrix material and the second matrix material are doped with different types of doping particles, or the first matrix material and the second matrix material are doped with different concentrations of doping particles.

[0052] Through electrical tests, it is found that by doping specific doping particles in a selenium-based chalcogenide, the resistivity of the material can be changed, and then the partial voltage on both sides of the strobing layer can be changed to change the threshold voltage. Therefore, by doping specific doping particles in the first matrix material and the second matrix material, the threshold voltages of the first strobing layer 212 and the second strobing layer 222 can be changed respectively. It can be understood that the same doping particles doped in different matrix materials have different regulating effects on the threshold voltage, and different doping particles doped in the same matrix material also have different regulating effects on the threshold voltage, and the regulating effects include increasing and decreasing the threshold voltage.

[0053] In some embodiments, by changing the material, the first strobing layer 212 can have a first threshold voltage, the second strobing layer 222 can have a second threshold voltage, and the first threshold voltage is substantially the same as the second threshold voltage.

[0054] "Substantially the same" means that the difference between the first threshold voltage and the second threshold voltage is very small. For example, the absolute value of the difference between the first threshold voltage and the second threshold voltage is 0V to 0.5V, so that the same electrical signal can be used to successfully operate the first storage unit 21 and the second storage unit 22.

[0055] In some embodiments, the electrical test results show that when the materials of the first strobing layer S1 and the second strobing layer S2 are the same, the threshold voltage of the second strobing layer S2 is lower than the threshold voltage of the first strobing layer S1. Therefore, it is necessary to increase the threshold voltage of the second strobing layer S2 and / or decrease the threshold voltage of the first strobing layer S1 to make the threshold voltages of the two substantially the same.

[0056] In some embodiments, when the thickness of the first gate layer 212 is the same as that of the second gate layer 222, when the first base material is doped, the threshold voltage of the first gate layer 212 is less than the threshold voltage of the first base material. That is, doping in the first base material can reduce the threshold voltage of the material. When the second base material is doped, the threshold voltage of the second gate layer 222 is greater than the threshold voltage in the second base material. That is, doping in the first base material can increase the threshold voltage of the material. Having doping means having doping particles. Since the first base material and the second base material are the same, and the doping particles in the first base material and the doping particles in the second base material have different regulating effects on the threshold voltage, the types of doping particles in the first base material and the second base material are different.

[0057] In some embodiments, at least one of the first base material and the second base material has doping particles, and the atomic percentage concentration of the doping particles is 0 at% to 10 at%. It should be noted that one or more doping particles can be doped in the first base material, and one or more doping particles different from those in the first base material can also be doped in the second base material, and the atomic percentage concentration of a single doping particle is 0 at% to 10 at%. That is to say, "the atomic percentage concentration of the doping particles" refers to the atomic percentage concentration of a single type of doping particle.

[0058] As Figure 2 shown, the second doping particle D2 is doped in the second base material, and the second doping particle D2 includes at least one of silicon and sulfur; no additional doping particles are doped in the first base material, that is, the material of the first gate layer 212 is the same as the second base material of the second gate layer 222. The electrical test results show that doping silicon or sulfur in a selenium-based chalcogenide can increase the threshold voltage of the second gate layer 222.

[0059] Please refer to Figure 3 , Figure 3 which is a graph of the electrical test results of doping silicon in the second base material provided by some embodiments of the present application. Among them, the abscissa represents the atomic percentage concentration of silicon in the second base material, and the ordinate represents the threshold voltage of the material.

[0060] It can be Figure 3 seen from the figure that as the atomic percentage concentration of silicon in the second base material increases, the threshold voltage of the material increases, and the fitting results show that there is a linear correlation between the two within a certain range. Therefore, the concentration of silicon can be determined according to the fitting data and the difference between the two threshold voltages.

[0061] In some embodiments, the atomic percentage concentration of the second doping particle D2 is 0 at% to 10 at%.

[0062] Please refer to Figure 4 , Figure 4 which is a schematic cross-sectional structure diagram of a phase change memory provided by some embodiments of the present application. The difference between this phase change memory and the phase change memory 100 in Figure 2 lies in the materials of the first selection layer 212 and the second selection layer 222.

[0063] In this embodiment, in the first selection layer 212, the first matrix material is doped with a first doping particle D1, and the first doping particle D1 includes at least one of boron, carbon, and nitrogen; the second selection layer 222 is not doped with additional doping particles, that is, the material of the second selection layer 222 is the same as the first matrix material in the first selection layer 212.

[0064] The electrical test results show that doping boron, carbon, and nitrogen in the first matrix material can all reduce the threshold voltage of the material, that is, a first selection layer 212 with a lower threshold voltage is obtained, achieving the purpose of matching the second selection layer 222.

[0065] Please refer to Figure 5 , Figure 5 which is a schematic cross-sectional structure diagram of a phase change memory provided by some embodiments of the present application. The difference between this phase change memory and the phase change memories in Figure 2 and Figure 4 lies in the materials of the first selection layer 212 and the second selection layer 222.

[0066] In this embodiment, in the first selection layer 212, the first matrix material is doped with a first doping particle D1, and the first doping particle D1 includes at least one of boron, carbon, and nitrogen; in the second selection layer 222, the second matrix material is doped with a second doping particle D2, and the second doping particle D2 includes at least one of silicon and sulfur.

[0067] Therefore, in this embodiment, while increasing the threshold voltage of the second selection layer 222, the threshold voltage of the first selection layer 212 is reduced until the two are equivalent. And, compared with the embodiments in Figure 2 and Figure 4 , the atomic percentage concentrations of the first doping particle D1 and the second doping particle D2 can be relatively reduced. For example, Figure 5 the atomic percentage concentration of the first doping particle D1 in Figure 4 is reduced relative to the atomic percentage concentration of the first doping particle D1 in Figure 5 the atomic percentage concentration of the second doping particle D2 in Figure 4 is reduced relative to the atomic percentage concentration of the second doping particle D2 in

[0068] It is found through electrical testing that the thicknesses of the first selection layer 212 and the second selection layer 222 will affect their respective resistances, thereby affecting their threshold voltages. Among them, the "thickness" is the dimension along the first direction Z.

[0069] In some embodiments, the thickness of the second selection layer 222 is greater than the thickness of the first selection layer 212. In this way, the resistance of the second selection layer 222 can be increased to a certain extent to increase the threshold voltage. Furthermore, when the threshold voltages of the first selection layer 212 and the second selection layer 222 are basically the same, the atomic percentage concentration of the doped particles can be reduced.

[0070] For example, the thickness of the second selection layer 222 can be increased so that the thickness of the second selection layer 222 is greater than the thickness of the first selection layer; or the thickness of the first selection layer 212 can be reduced so that the thickness of the second selection layer 222 is greater than the thickness of the first selection layer; or the thickness of the first selection layer 212 can be increased and the thickness of the second selection layer 222 can be reduced simultaneously.

[0071] Please refer to Figure 6 , Figure 6 which is a schematic three-dimensional structure diagram of a phase change memory provided by some embodiments of the present application.

[0072] The phase change memory 100 includes four layers of storage units. The first layer and the second layer form a storage unit group 20, and the third layer and the fourth layer form a storage unit group 20. Each storage unit group 20 includes a first storage unit 21 located in the lower layer and a second storage unit 22 located in the upper layer.

[0073] In this embodiment, the second conductive wire 32 between the first storage unit 21 and the second storage unit 22 includes a first sub-wire 321 and a second sub-wire 322. The second sub-wire 322 is located on the side of the first sub-wire 321 away from the first conductive wire 31. During operation, the same high-level signal is loaded on the first sub-wire 321 and the second sub-wire 322, and a lower-level signal is loaded on the second conductive wire 32 and the third conductive wire 33.

[0074] Among them, both the first conductive wire 31 and the third conductive wire 33 extend along the second direction X, both the first sub-wire 321 and the second sub-wire 322 extend along the third direction Y. The first storage unit 21 is located at the intersection of the first conductive wire 31 and the first sub-wire 321, and the second storage unit 22 is located at the intersection of the second sub-wire 322 and the third conductive wire 33.

[0075] Among them, the specific structures of the first storage unit 21 and the second storage unit 22 can refer to Figure 2 , Figure 4 and Figure 5. Within each memory cell group 20, the second selection layer 222 is different from the first selection layer 212, such that the threshold voltages of the first selection layer 212 and the second selection layer 222 are substantially the same, that is, the SET state threshold voltages of the first memory cell 21 and the second memory cell 22 are substantially the same. Further, the first memory cell 21 and the second memory cell 22 within each memory cell group 20 can adopt the same electrical signal design, which simplifies the electrical signal design, helps to achieve more layers of stacking, increases the storage capacity, and can also reduce the performance variation difference between different layer devices during use, improving the reliability of the device.

[0076] Correspondingly, some embodiments of the present application further provide a method for forming the phase change memory in any of the above embodiments, and all methods capable of forming the phase change memory are within the protection scope of the present application.

[0077] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0078] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0079] The embodiments, implementation manners and related technical features of the present application can be combined and replaced with each other without conflict.

[0080] The above are only the preferred embodiments of the present application and do not impose any form of limitation on the present application. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A phase change memory, characterized in that: include: substrate; At least one storage cell group stacked along a first direction on the substrate, each of the storage cell groups comprising a first storage cell and a second storage cell, the second storage cell being located on a side of the first storage cell away from the substrate, and the first direction being perpendicular to a surface of the substrate; The first memory cell comprises a first bottom electrode, a first gating layer, a first intermediate electrode, a first memory layer and a first top electrode stacked along the first direction, wherein the first memory layer is located on a side of the first gating layer away from the substrate; The second storage unit includes a second bottom electrode, a second gating layer, a second intermediate electrode, a second storage layer and a second top electrode stacked along the first direction, the second storage layer is located on a side of the second gating layer away from the substrate, and the second gating layer is different from the first gating layer.

2. The phase change memory according to claim 1, characterized in that: The material of the first gating layer includes a first base material, the material of the second gating layer includes a second base material, and the first base material is the same as the second base material; at least one of the first base material and the second base material is doped, and the first base material and the second base material have different doping.

3. The phase change memory according to claim 2, characterized in that: The first matrix material is doped with first doping particles, and the first doping particles include at least one of boron, carbon and nitrogen.

4. The phase change memory according to claim 2 or 3, characterized in that: The second matrix material is doped with second doping particles, and the second doping particles include at least one of silicon and sulfur.

5. The phase change memory according to claim 2, characterized in that: At least one of the first matrix material and the second matrix material has doping particles, and the atomic percentage concentration of the doping particles is 0 at % to 10 at %.

6. The phase change memory according to claim 2, characterized in that: The thickness of the first gating layer is the same as the thickness of the second gating layer; when the first matrix material is doped, the threshold voltage of the first gating layer is less than the threshold voltage of the first matrix material; when the second matrix material is doped, the threshold voltage of the second gating layer is greater than the threshold voltage of the second matrix material.

7. The phase change memory according to claim 1 or 2, characterized in that: The thickness of the second gating layer is greater than the thickness of the first gating layer.

8. The phase change memory according to claim 1, characterized in that: The material of the first storage layer and the material of the second storage layer both include a first chalcogenide compound, and the material of the first storage layer is the same as the material of the second storage layer; The first gating layer and the second gating layer include the same base material, the base material includes a second chalcogenide compound, and the first chalcogenide compound and the second chalcogenide compound are made of different materials.

9. The phase change memory according to claim 1, characterized in that: The first gating layer has a first threshold voltage, the second gating layer has a second threshold voltage, and an absolute value of a difference between the first threshold voltage and the second threshold voltage is 0V to 0.5V.

10. The phase change memory according to claim 1, characterized in that: Also includes: a first conductive line, located at a side of the first memory cell away from the second memory cell and electrically connected to the first bottom electrode; a second conductive line, located between the first memory cell and the second memory cell, and electrically connected to the first top electrode and the second bottom electrode; The third conductive line is located at a side of the second storage unit away from the second conductive line and is electrically connected to the second top electrode.

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