Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a manufacturing method of the semiconductor device, which can suppress reduction of withstand voltage of a capacitor and can realize miniaturization. The semiconductor device includes: a substrate having a first main surface and a second main surface facing the first main surface; the organic barrier layer is arranged above the first main surface; the first electrode is arranged above the organic barrier layer; an insulating film provided on the first electrode; a second electrode provided on the insulating film; a first through hole penetrating the substrate and the organic barrier layer and reaching the first electrode; and a metal layer that covers the second main surface and a first inner wall surface of the first through-hole and is electrically connected to the first electrode.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] For example, in a semiconductor integrated circuit such as a monolithic microwave integrated circuit (MMIC), a metal-insulator-metal (MIM) type capacitor in which a lower electrode, an insulating film, and an upper electrode are stacked may be formed.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-006958

[0006] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2018-037497

[0007] Patent Document 3: Japanese Unexamined Patent Application Publication No. 2020-017647

[0008] For miniaturization of a semiconductor device, formation of a through hole that penetrates a substrate and reaches a lower electrode is considered, and a metal layer connected to the lower electrode through the through hole is provided on the back surface of the substrate. However, when forming the through hole, the lower electrode may be damaged, or the insulating film between the lower electrode and the upper electrode may be damaged. Damage to the lower electrode and the insulating film causes a reduction in the withstand voltage of the capacitor. By providing a thick film between the substrate and the lower electrode, damage to the lower electrode and the like can be suppressed, but in this case, etching of the thick film requires a long time, resulting in a reduction in production capacity. Summary of the Invention

[0009] An object of the present disclosure is to provide a semiconductor device and a method of manufacturing the semiconductor device that can suppress a reduction in the withstand voltage of a capacitor and can achieve miniaturization.

[0010] The semiconductor device of the present disclosure includes: a substrate having a first main surface and a second main surface opposite to the first main surface; an organic barrier layer provided above the first main surface; a first electrode provided above the organic barrier layer; an insulating film provided above the first electrode; a second electrode provided above the insulating film; a first through hole that penetrates the substrate and the organic barrier layer and reaches the first electrode; and a metal layer that covers the second main surface and a first inner wall surface of the first through hole and is electrically connected to the first electrode.

[0011] Advantageous Effects of the Invention

[0012] According to the present disclosure, it is possible to suppress a reduction in the withstand voltage of a capacitor and to achieve miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional view of a semiconductor device showing an embodiment.

[0014] Figure 2 It is a cross-sectional view (part one) of a method for manufacturing a semiconductor device showing an embodiment.

[0015] Figure 3 It is a cross-sectional view (part two) of a method for manufacturing a semiconductor device showing an embodiment.

[0016] Figure 4 It is a cross-sectional view (part three) of a method for manufacturing a semiconductor device showing an embodiment.

[0017] Figure 5 It is a cross-sectional view (part four) of a method for manufacturing a semiconductor device showing an embodiment.

[0018] Figure 6 It is a cross-sectional view (part five) of a method for manufacturing a semiconductor device showing an embodiment.

[0019] Figure 7 It is a cross-sectional view (part six) of a method for manufacturing a semiconductor device showing an embodiment.

[0020] Figure 8 It is a cross-sectional view (part seven) of a method for manufacturing a semiconductor device showing an embodiment.

[0021] Figure 9 It is a cross-sectional view (part eight) of a method for manufacturing a semiconductor device showing an embodiment.

[0022] Figure 10 It is a cross-sectional view (part nine) of a method for manufacturing a semiconductor device showing an embodiment.

[0023] REFERENCE SIGNS LIST

[0024] 11: Substrate, 11A: First main surface, 11B: Second main surface, 12: Semiconductor layer, 20: FET, 21: Insulating film, 21G: Opening, 22D: Drain electrode, 22G: Gate electrode, 22S: Source electrode, 40: MIM type capacitor, 41: Lower electrode, 42: Insulating film, 43: Upper electrode, 51: Insulating film, 52: Organic barrier layer, 53: Inorganic barrier layer, 54: Interlayer insulating film, 61C, 61D: Openings, 62C, 62D: Wiring, 71C, 71S: Through holes, 72: Back electrode, 80: Structure, 100: Semiconductor device. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] [Description of Embodiments of the Present Disclosure]

[0026] First, embodiments of the present disclosure will be listed and described.

[0027] 〔1〕A semiconductor device according to one aspect of the present disclosure includes: a substrate having a first main surface and a second main surface opposite to the first main surface; an organic stopper layer provided above the first main surface; a first electrode provided above the organic stopper layer; an insulating film provided above the first electrode; a second electrode provided above the insulating film; a first through hole that penetrates the substrate and the organic stopper layer and reaches the first electrode; and a metal layer that covers the second main surface and a first inner wall surface of the first through hole and is electrically connected to the first electrode.

[0028] An organic stopper layer is provided between the substrate and the first electrode. When the first through hole is formed in the substrate, the organic stopper layer functions as an etching stopper. Therefore, damage to the first electrode and the insulating film when the first through hole is formed in the substrate can be suppressed. Therefore, a reduction in the withstand voltage of the MIM capacitor including the first electrode, the insulating film, and the second electrode can be suppressed, and the semiconductor device can be miniaturized.

[0029] 〔2〕In 〔1〕, the semiconductor device may further include: a semiconductor layer provided above the first main surface; a third electrode provided above the semiconductor layer; and a second through hole that penetrates the substrate and the semiconductor layer and reaches the third electrode. The organic stopper layer is provided above the semiconductor layer, the first through hole penetrates the semiconductor layer, and the metal layer covers a second inner wall surface of the second through hole and is electrically connected to the third electrode. In this case, an MMIC including a semiconductor element such as a transistor and a MIM capacitor can be formed, where the transistor includes the semiconductor layer and the third electrode.

[0030] 〔3〕In 〔1〕 or 〔2〕, the organic stopper layer may contain polyimide or benzocyclobutene. In this case, it is easy to obtain a desired thickness for the organic stopper layer.

[0031] 〔4〕In any one of 〔1〕 to 〔3〕, the thickness of the organic stopper layer may be 1 μm or more and 10 μm or less. In this case, the time required for etching the organic stopper layer can be suppressed to be short, and it is easy for the organic stopper layer to function as an etching stopper during processing of the substrate or the like.

[0032] 〔5〕In any one of 〔1〕 to 〔4〕, it may also be that the semiconductor device has an inorganic barrier layer provided between the organic barrier layer and the first electrode, and the first through hole penetrates the inorganic barrier layer. In this case, good adhesion is obtained between the organic barrier layer and the first electrode through the inorganic barrier layer. In addition, the inorganic barrier layer functions as an etching stop layer when the first through hole penetrates the organic barrier layer.

[0033] 〔6〕In 〔5〕, it may also be that the thickness of the inorganic barrier layer is 20 nm or more and 500 nm or less. In this case, the time required for etching the inorganic barrier layer is suppressed to be short, and it is easy for the inorganic barrier layer to function as an etching stop layer during the processing of the organic barrier layer.

[0034] 〔7〕A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes the following steps: preparing a structure including: a substrate having a first main surface and a second main surface opposite to the first main surface; an organic barrier layer provided above the first main surface; a first electrode provided above the organic barrier layer; an insulating film provided above the first electrode; and a second electrode provided above the insulating film; forming a first through hole by performing a first reactive ion etching, wherein the first through hole overlaps the first electrode in a plan view perpendicular to the first main surface, penetrates the substrate, and reaches the organic barrier layer; extending the first through hole to penetrate the organic barrier layer and reach the first electrode by performing a second reactive ion etching; and forming a metal layer, wherein the metal layer covers the second main surface and the first inner wall surface of the first through hole and is electrically connected to the first electrode.

[0035] During the first reactive ion etching, the organic barrier layer functions as an etching stop layer. Therefore, damage to the first electrode and the insulating film caused by the first reactive ion etching can be suppressed. In addition, the second reactive ion etching for extending the first through hole can be performed under conditions that are not likely to damage the first electrode and the insulating film. Therefore, a decrease in the withstand voltage of the MIM type capacitor including the first electrode, the insulating film, and the second electrode can be suppressed, and the semiconductor device can be miniaturized.

[0036] 〔8〕In [7], alternatively, the structure may have: a semiconductor layer provided on the first main surface; and a third electrode provided on the semiconductor layer, with the organic barrier layer provided on the semiconductor layer. The process of performing the first reactive ion etching has the following steps: forming a portion of the first through-hole that penetrates the substrate and reaches the semiconductor layer and forming a second through-hole by performing a third reactive ion etching, where the second through-hole overlaps with the third electrode in the top view, penetrates the substrate, and reaches the semiconductor layer; and extending the first through-hole to penetrate the semiconductor layer and reach the organic barrier layer and extending the second through-hole to penetrate the semiconductor layer and reach the third electrode by performing a fourth reactive ion etching. The metal layer covers the second inner wall surface of the second through-hole and is electrically connected to the third electrode. In this case, an MMIC including semiconductor elements such as transistors and a MIM type capacitor can be formed, where the transistor includes a semiconductor layer and a third electrode.

[0037] 〔9〕In [7] or [8], alternatively, the structure may have an inorganic barrier layer provided between the organic barrier layer and the first electrode. The process of performing the second reactive ion etching has the following steps: extending the first through-hole to penetrate the organic barrier layer and reach the inorganic barrier layer by performing a fifth reactive ion etching; and extending the first through-hole to penetrate the inorganic barrier layer and reach the first electrode by performing a sixth reactive ion etching. In this case, good adhesion is obtained between the organic barrier layer and the first electrode through the inorganic barrier layer. In addition, the inorganic barrier layer functions as an etching stop layer when the first through-hole penetrates the organic barrier layer. The inorganic barrier layer can be relatively thin, so the sixth reactive ion etching can be performed under conditions that are less likely to damage the first electrode and the insulating film.

[0038] 〔10〕In [9], alternatively, in the fifth reactive ion etching, a reactive gas containing oxygen may be used. In this case, the organic barrier layer can be easily etched.

[0039] [Details of the Embodiments of the Present Disclosure]

[0040] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. It should be noted that in this specification and the drawings, for components having substantially the same functional configuration, repeated descriptions may sometimes be omitted by assigning the same reference numerals. In addition, in the following description, an XYZ orthogonal coordinate system is used, but this coordinate system is determined for the purpose of explanation and does not limit the posture of the semiconductor device. In addition, when viewed from an arbitrary point, the +Z side may sometimes be referred to as the upper side, the upper surface, or the top, and the -Z side may sometimes be referred to as the lower side, the lower surface, or the bottom.

[0041] (Configuration of the semiconductor device)

[0042] The embodiment relates to a semiconductor device including a field effect transistor (FET) such as a GaN-based high electron mobility transistor (HEMT) and a MIM-type capacitor. Figure 1 It is a cross-sectional view showing the semiconductor device of the embodiment.

[0043] As Figure 1 shown, the semiconductor device 100 of the embodiment has a substrate 11, a semiconductor layer 12, a gate electrode 22G, a source electrode 22S, a drain electrode 22D, a lower electrode 41, an insulating film 42, an upper electrode 43, and a back electrode 72.

[0044] The substrate 11 is, for example, a silicon carbide (SiC) substrate. The substrate 11 has a first main surface 11A and a second main surface 11B opposite to the first main surface 11A. The first main surface 11A is located above the second main surface 11B (+Z side).

[0045] The semiconductor layer 12 is provided on the first main surface 11A. The semiconductor layer 12 is, for example, a nitride semiconductor layer containing gallium (Ga). The nitride semiconductor layer includes an electron transit layer (channel layer) and an electron supply layer (barrier layer) that constitute the HEMT.

[0046] The source electrode 22S and the drain electrode 22D are provided on the semiconductor layer 12. The source electrode 22S and the drain electrode 22D are in ohmic contact with the semiconductor layer 12. Alternatively, the semiconductor layer 12 may include a plurality of regrown layers, and the source electrode 22S and the drain electrode 22D may be provided on the regrown layers. The source electrode 22S is an example of the third electrode.

[0047] The semiconductor device 100 has an insulating film 21. The insulating film 21 is provided over the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12, covering the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12. Note that the insulating film 21 may have an opening over the source electrode 22S and the drain electrode 22D. The insulating film 21 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The insulating film 21 may also have a laminate of two or more of these films.

[0048] An opening 21G for a gate is formed in the insulating film 21. The opening 21G is located between the source electrode 22S and the drain electrode 22D in a plan view perpendicular to the first main surface 11A. Hereinafter, the "plan view" means a "plan view perpendicular to the first main surface 11A". In the plan view, the gate electrode 22G is provided over the insulating film 21 between the source electrode 22S and the drain electrode 22D, and makes Schottky contact with the semiconductor layer 12 through the opening 21G.

[0049] The semiconductor device 100 has an FET 20 including a semiconductor layer 12, a gate electrode 22G, a source electrode 22S, and a drain electrode 22D. The FET 20 is, for example, a HEMT.

[0050] The semiconductor device 100 further has an insulating film 51, an organic barrier layer 52, an inorganic barrier layer 53, and an interlayer insulating film 54.

[0051] The insulating film 51 is provided over the gate electrode 22G and the insulating film 21, covering the gate electrode 22G and the insulating film 21. The insulating film 51 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The insulating film 51 may also have a laminate of two or more of these films. Good adhesion is obtained between the semiconductor layer 12 and the organic barrier layer 52 through the insulating film 21 and the insulating film 51.

[0052] The organic barrier layer 52 is disposed above the insulating film 51 away from the FET 20. In other words, the organic barrier layer 52 is disposed above the first main surface 11A. The organic barrier layer 52 contains, for example, polyimide or benzocyclobutene (BCB). The thickness of the organic barrier layer 52 is, for example, 1 μm or more and 10 μm or less. The thickness of the organic barrier layer 52 can be measured by observation using a scanning electron microscope (SEM).

[0053] The inorganic barrier layer 53 is disposed above the organic barrier layer 52 and the insulating film 51, covering the organic barrier layer 52 and the insulating film 51. The inorganic barrier layer 53 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The inorganic barrier layer 53 may also have a laminate of two or more of these films. The thickness of the inorganic barrier layer 53 is, for example, 20 nm or more and 500 nm or less. The thickness of the inorganic barrier layer 53 can be measured by observation using an SEM.

[0054] The lower electrode 41 is disposed above the organic barrier layer 52 and on the inorganic barrier layer 53. In other words, the inorganic barrier layer 53 is disposed between the organic barrier layer 52 and the lower electrode 41. For example, when viewed from above, the contour of the lower electrode 41 is located inside the contour of the organic barrier layer 52. The lower electrode 41 has, for example, a titanium (Ti) film and a gold (Au) film thereon. The lower electrode 41 is an example of the first electrode.

[0055] The insulating film 42 is disposed above the lower electrode 41 and the inorganic barrier layer 53, covering the lower electrode 41 and the inorganic barrier layer 53. The insulating film 42 includes, for example, a silicon nitride (SiN) film, a silicon oxide (SiO 2 ) film, an aluminum oxide (Al 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, or a zirconium oxide (ZrO 2 ) film. The insulating film 42 may also have a laminate of two or more of these films.

[0056] The upper electrode 43 is disposed above the organic barrier layer 52 and on the insulating film 42. In other words, the insulating film 42 is disposed between the lower electrode 41 and the upper electrode 43. For example, when viewed from above, the contour of the upper electrode 43 is located inside the contour of the organic barrier layer 52. The upper electrode 43 has, for example, a titanium (Ti) film and a gold (Au) film thereon. The upper electrode 43 is an example of the second electrode.

[0057] The semiconductor device 100 includes a MIM capacitor 40 having a lower electrode 41, an insulating film 42, and an upper electrode 43.

[0058] An interlayer insulating film 54 is provided over the upper electrode 43 and the insulating film 42 to cover the upper electrode 43 and the insulating film 42. For example, the upper surface of the interlayer insulating film 54 may be planarized. An opening 61C that penetrates the interlayer insulating film 54 is formed in the interlayer insulating film 54. The opening 61C reaches the upper electrode 43. An opening 61D that penetrates the interlayer insulating film 54, the insulating film 42, the inorganic barrier layer 53, the insulating film 51, and the insulating film 21 is formed in the interlayer insulating film 54, the insulating film 42, the inorganic barrier layer 53, the insulating film 51, and the insulating film 21. The opening 61D reaches the drain electrode 22D. It should be noted that other openings may be formed in the same manner as the opening 61D, and the opening reaches the source electrode 22S.

[0059] The semiconductor device 100 includes a wiring 62C and a wiring 62D. The wiring 62C is provided over the interlayer insulating film 54 and contacts the upper electrode 43 through the opening 61C. The wiring 62D is provided over the interlayer insulating film 54 and contacts the drain electrode 22D through the opening 61D.

[0060] A through hole 71S that penetrates the substrate 11 and the semiconductor layer 12 is formed in the substrate 11 and the semiconductor layer 12. The through hole 71S reaches the source electrode 22S. A through hole 71C that penetrates the substrate 11, the semiconductor layer 12, the insulating film 21, the insulating film 51, the organic barrier layer 52, and the inorganic barrier layer 53 is formed in the substrate 11, the semiconductor layer 12, the insulating film 21, the insulating film 51, the organic barrier layer 52, and the inorganic barrier layer 53. The through hole 71C reaches the lower electrode 41. The through hole 71C is an example of a first through hole, and the through hole 71S is an example of a second through hole.

[0061] A back electrode 72 is formed on the second main surface 11B of the substrate 11, the inner wall surface of the through hole 71C, the lower surface of the lower electrode 41, the inner wall surface of the through hole 71S, and the lower surface of the source electrode 22S. The back electrode 72 is connected to the lower electrode 41 and the source electrode 22S and covers the second main surface 11B, the inner wall surface of the through hole 71C, and the inner wall surface of the through hole 71S. For example, the back electrode 72 is composed of a gold (Au) layer. The back electrode 72 has, for example, a seed layer and a plating layer. For example, the back electrode 72 is grounded to give a ground potential to the lower electrode 41 and the source electrode 22S. The back electrode 72 is an example of a metal layer.

[0062] (Method of manufacturing a semiconductor device)

[0063] Next, a method of manufacturing the semiconductor device 100 of the embodiment will be described.Figures 2 to 10 It is a cross-sectional view showing a manufacturing method of a semiconductor device 100 according to an embodiment.

[0064] First, as Figure 2 shown, for example, a semiconductor layer 12 is formed on a substrate 11 by a metal organic chemical vapor deposition (MOCVD) method. The substrate 11 has a first main surface 11A and a second main surface 11B opposite to the first main surface 11A.

[0065] Next, a source electrode 22S and a drain electrode 22D are formed on the semiconductor layer 12. In the formation of the source electrode 22S and the drain electrode 22D, growth of a metal film is achieved by an evaporation method using a growth mask, and then the growth mask is removed. That is, the source electrode 22S and the drain electrode 22D can be formed, for example, by evaporation and lift-off. Next, an insulating film 21 is formed on the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12. The insulating film 21 can be formed, for example, by a plasma CVD method or a sputtering method. The insulating film 21 covers the source electrode 22S, the drain electrode 22D, and the semiconductor layer 12.

[0066] Next, an opening 21G is formed in the insulating film 21. In the formation of the opening 21G, for example, reactive ion etching (RIE) using a resist pattern as a mask is performed. A reactive gas containing fluorine (F) or chlorine (Cl) is used in the etching of the insulating film 21. Next, a gate electrode 22G is formed on the insulating film 21. In the formation of the gate electrode 22G, growth of a metal film is achieved by an evaporation method using a growth mask, and then the growth mask is removed. That is, the gate electrode 22G can be formed, for example, by evaporation and lift-off. The gate electrode 22G makes a Schottky contact with the semiconductor layer 12 through the opening 21G.

[0067] Next, as Figure 3 shown, an insulating film 51 is formed on the gate electrode 22G and the insulating film 21. The insulating film 51 can be formed, for example, by a plasma CVD method or a sputtering method. The insulating film 51 covers the gate electrode 22G and the insulating film 21. Next, an organic barrier layer 52 is formed on the insulating film 51. In other words, the organic barrier layer 52 is formed above the first main surface 11A. The organic barrier layer 52 is formed on the insulating film 51 away from the FET 20. The organic barrier layer 52 contains, for example, polyimide or benzocyclobutene. The organic barrier layer 52 can be formed, for example, by spin coating, exposure, development, and sintering of photosensitive polyimide or photosensitive benzocyclobutene. The organic barrier layer 52 can also be formed by spin coating, sintering, and etching of non-photosensitive polyimide or non-photosensitive benzocyclobutene.

[0068] Next, as Figure 4 shown, an inorganic barrier layer 53 is formed over the organic barrier layer 52 and the insulating film 51. The inorganic barrier layer 53 can be formed, for example, by plasma CVD method or sputtering method. The inorganic barrier layer 53 covers the organic barrier layer 52 and the insulating film 51.

[0069] Next, as Figure 5 shown, a lower electrode 41 is formed over the inorganic barrier layer 53 above the organic barrier layer 52. In other words, the inorganic barrier layer 53 is formed between the organic barrier layer 52 and the lower electrode 41. In the formation of the lower electrode 41, for example, a metal film is formed over the entire surface, and then the metal film is etched. The etching can be either dry etching or wet etching. The lower electrode 41 can also be formed by evaporation and peeling of the metal film. Next, an insulating film 42 is formed over the lower electrode 41 and the inorganic barrier layer 53. The insulating film 42 can be formed, for example, by plasma CVD method or sputtering method. The insulating film 42 covers the lower electrode 41 and the inorganic barrier layer 53. Next, an upper electrode 43 is formed over the insulating film 42 above the organic barrier layer 52. In other words, the insulating film 42 is formed between the lower electrode 41 and the upper electrode 43. In the formation of the upper electrode 43, for example, a metal film is formed over the entire surface, and then the metal film is etched. The etching can be either dry etching or wet etching. The upper electrode 43 can also be formed by evaporation and peeling of the metal film.

[0070] Next, as Figure 6 shown, an interlayer insulating film 54 is formed over the upper electrode 43 and the insulating film 42. The interlayer insulating film 54 can be formed, for example, by plasma CVD method or sputtering method. The interlayer insulating film 54 covers the upper electrode 43 and the insulating film 42. The upper surface of the interlayer insulating film 54 can also be planarized. Next, an opening 61C and an opening 61D are formed. The opening 61C penetrates the interlayer insulating film 54 and reaches the upper electrode 43. The opening 61D penetrates the interlayer insulating film 54, the insulating film 42, the inorganic barrier layer 53, the insulating film 51, and the insulating film 21 and reaches the drain electrode 22D. It should be noted that other openings can also be formed in the same manner as the opening 61D, and the opening reaches the source electrode 22S.

[0071] Next, wirings 62C and 62D are formed over the interlayer insulating film 54. The wiring 62C is in contact with the upper electrode 43 through the opening 61C, and the wiring 62D is in contact with the drain electrode 22D through the opening 61D. It should be noted that other openings reaching the source electrode 22S may be provided in the same manner as the opening 61D, and the wiring in contact with the source electrode 22S through this opening is formed over the interlayer insulating film 54 in the same manner as the wiring 62D. That is, other openings may be provided above the source electrode 22S in the same manner as the opening 61D, and the wiring in contact with the source electrode 22S passes through this opening and is formed over the interlayer insulating film 54 in the same manner as the wiring 62D.

[0072] In this way, a structure 80 including the FET 20 and the MIM type capacitor 40 is prepared.

[0073] Next, as Figure 7 shown, through RIE, through holes 71C and 71S penetrating the substrate 11 are formed in the substrate 11. The through hole 71C is formed such that the contour of the through hole 71C is located inside the contour of the organic barrier layer 52 in a plan view, and the through hole 71S is formed such that the contour of the through hole 71S is located inside the contour of the source electrode 22S in a plan view. The through hole 71C overlaps with the lower electrode 41 in a plan view and reaches the semiconductor layer 12. The through hole 71S overlaps with the source electrode 22S in a plan view and reaches the semiconductor layer 12. In the formation of the through holes 71C and 71S, RIE of the substrate 11 using a resist pattern as a mask is performed. In the etching of the substrate 11, reactive gases containing fluorine (F) such as carbon tetrafluoride (CF 4 ) and sulfur hexafluoride (SF 6 ) and fluoromethane (CH x F y ) are used. As a result of this RIE, the semiconductor layer 12 is exposed from the through holes 71C and 71S. The through holes 71C and 71S may also penetrate into the semiconductor layer 12. The RIE of the substrate 11 is an example of the third reactive ion etching.

[0074] Next, as Figure 8 shown, through RIE, the through hole 71C is extended to penetrate the semiconductor layer 12, the insulating film 21, and the insulating film 51 and reach the organic barrier layer 52, and the through hole 71S is extended to penetrate the semiconductor layer 12 and reach the source electrode 22S. In the etching of the semiconductor layer 12, the insulating film 21, and the insulating film 51, chlorine (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4) reactive gases containing chlorine (Cl). The reactive gas does not contain oxygen (O 2 ). As a result of this RIE, the organic barrier layer 52 is exposed from the through hole 71C, and the source electrode 22S is exposed from the through hole 71S. In this RIE, the etching rate of the organic barrier layer 52 is about 1 / 3 times the etching rates of the semiconductor layer 12, the insulating film 21, and the insulating film 51. That is, the etching selectivity of the organic barrier layer 52 with respect to the insulating film 21 and the insulating film 51 is about 3. The through hole 71C may also penetrate into the organic barrier layer 52. In this RIE, the organic barrier layer 52 functions as an etching stop layer. Note that the source electrode 22S is also exposed to the etching atmosphere, but in the RIE using a reactive gas containing chlorine (Cl), the source electrode 22S is not etched. The RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51 is an example of the fourth reactive ion etching. The third reactive ion etching and the fourth reactive ion etching are included in the first reactive ion etching.

[0075] Note that, when the semiconductor layer 12 is thin enough, etc., after etching the substrate 11, the reactive gas may not be changed, and the RIE of the substrate 11 and the RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51 may be continuously performed.

[0076] Next, as Figure 9 shown, by performing RIE, the through hole 71C is extended to penetrate the organic barrier layer 52 and reach the inorganic barrier layer 53. In the etching of the organic barrier layer 52, a reactive gas containing oxygen (O 2 ) is used. As a result of this RIE, the inorganic barrier layer 53 is exposed from the through hole 71C. In this RIE, the etching rate of the inorganic barrier layer 53 is about 1 / 100 to 1 / 50 times the etching rate of the organic barrier layer 52. That is, the etching selectivity of the inorganic barrier layer 53 with respect to the organic barrier layer 52 is about 50 to 100. The through hole 71C may also penetrate into the inorganic barrier layer 53. In this RIE, the inorganic barrier layer 53 functions as an etching stop layer. Note that the source electrode 22S is also exposed to the etching atmosphere, but in the RIE using a reactive gas containing oxygen (O 2 ) the source electrode 22S is not etched. The RIE of the organic barrier layer 52 is an example of the fifth reactive ion etching.

[0077] Next, as Figure 10 shown, by performing RIE, the through hole 71C is extended to penetrate the inorganic barrier layer 53 and reach the lower electrode 41. In the etching of the inorganic barrier layer 53, carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), fluoromethane (CH x Fy ) reactive gases containing fluorine (F) or chlorine gas (Cl 2 ), boron trichloride (BCl 3 ), silicon tetrachloride (SiCl 4 ), carbon tetrachloride (CCl 4 ), etc., reactive gases containing chlorine (Cl). A reactive gas containing fluorine (F) and chlorine (Cl) can also be used in the etching of the inorganic barrier layer 53. This reactive gas does not contain oxygen (O 2 ). In the RIE of the inorganic barrier layer 53, the voltage for generating plasma and the voltage for inducing plasma are reduced compared to the RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51. As a result of this RIE, the lower electrode 41 is exposed from the through hole 71C. The through hole 71C can also penetrate into the lower electrode 41. It should be noted that the source electrode 22S is also exposed to the etching atmosphere, but in the RIE using a reactive gas containing fluorine (F), a reactive gas containing chlorine (Cl), or a reactive gas containing fluorine (F) and chlorine (Cl), the source electrode 22S is not etched. The RIE of the inorganic barrier layer 53 is an example of the sixth reactive ion etching. The fifth reactive ion etching and the sixth reactive ion etching are included in the second reactive ion etching.

[0078] Next, a back electrode 72 is formed (see Figure 1 ). The back electrode 72 is formed on the second main surface 11B of the substrate 11, the inner wall surface of the through hole 71C, the lower surface of the lower electrode 41, the inner wall surface of the through hole 71S, and the lower surface of the source electrode 22S.

[0079] In this way, the semiconductor device 100 of the embodiment can be manufactured.

[0080] In the semiconductor device 100 of the embodiment, an organic barrier layer 52 is provided between the substrate 11 and the lower electrode 41, and when the through hole 71C is formed in the substrate 11 and the semiconductor layer 12, the organic barrier layer 52 functions as an etch stop layer. Therefore, even if the RIE for forming the through hole 71C in the substrate 11 and the semiconductor layer 12 is performed at high power, damage to the lower electrode 41 and the insulating film 42 can be suppressed. Therefore, a reduction in the breakdown voltage of the MIM capacitor 40 can be suppressed, and miniaturization can be achieved by forming the through hole 71C to overlap the lower electrode 41 in a top view.

[0081] The MIM capacitor 40 and the FET 20 are provided on the substrate 11, so an MMIC can be formed. In addition, a part of the through hole 71C can be formed while forming the through hole 71S.

[0082] The organic barrier layer 52 contains polyimide or benzocyclobutene, whereby it is easy to obtain a desired thickness for the organic barrier layer 52. That is, such an organic barrier layer 52 can be easily formed thick, and in addition, can be easily patterned. Moreover, internal stress is not likely to remain in the organic barrier layer 52, so the organic barrier layer 52 is not likely to peel off, and in addition, stress from the organic barrier layer 52 to the FET 20 is not likely to act. When the thickness of the organic barrier layer 52 is 1 μm or more and 10 μm or less, the time required for etching the organic barrier layer 52 is suppressed to be short, and it is easy for the organic barrier layer 52 to function as an etch stop layer. The organic barrier layer 52 with a thickness of 1 μm or more and 10 μm or less can be penetrated by etching in a short time. Depending on the RIE conditions during the formation of the via hole 71C, the thickness of the organic barrier layer 52 can also be 1 μm or more and 5 μm or less, or can also be 1 μm or more and 3 μm or less. In addition, by using a reactive gas containing oxygen, the organic barrier layer 52 can be easily etched.

[0083] By providing the inorganic barrier layer 53, good adhesion between the organic barrier layer 52 and the lower electrode 41 is obtained. In addition, by providing the inorganic barrier layer 53, it is easy to suppress damage to the lower electrode 41 during RIE of the organic barrier layer 52. When the thickness of the inorganic barrier layer 53 is 20 nm or more and 500 nm or less, the time required for etching the inorganic barrier layer 53 is suppressed to be short, and it is easy for the inorganic barrier layer 53 to function as an etch stop layer. Even by etching with a low power that is not likely to cause damage to the lower electrode 41, the inorganic barrier layer 53 with a thickness of 20 nm or more and 500 nm or less can be penetrated in a short time. In addition, stress from such an inorganic barrier layer 53 to the FET 20 can be made not likely to act. The thickness of the inorganic barrier layer 53 can also be 30 nm or more and 400 nm or less, or can also be 50 nm or more and 350 nm or less.

[0084] It should be noted that the reactive gas for RIE of the semiconductor layer 12, the insulating film 21, and the insulating film 51 and the reactive gas for RIE of the inorganic barrier layer 53 do not contain oxygen (O 2 ), whereby etching of the organic barrier layer 52 in these RIEs can be suppressed.

[0085] FET 20 may not be of the Schottky type but may be of the MIS (metal insulator semiconductor) type. The present disclosure may also be applied to semiconductor devices that do not include FET 20. That is, the semiconductor layer 12 and the insulating film 21 that constitute FET 20 may not be provided. In addition, the insulating film 51 and the inorganic barrier layer 53 are not essential, and even when the insulating film 51 or the inorganic barrier layer 53 or both are not provided, it is possible to suppress a decrease in the withstand voltage of the capacitor and to miniaturize the semiconductor device.

[0086] As described above, the embodiments have been described in detail, but the present disclosure is not limited to specific embodiments, and various modifications and changes can be made within the scope described in the claims.

Claims

1. A semiconductor device comprising: A substrate having a first main surface and a second main surface opposite to the first main surface; an organic barrier layer, disposed above the first main surface; A first electrode is disposed above the organic barrier layer; an insulating film, disposed on the first electrode; A second electrode is disposed on the insulating film; a first through hole, penetrating the substrate and the organic barrier layer and reaching the first electrode; as well as The metal layer covers the second main surface and the first inner wall surface of the first through hole and is electrically connected to the first electrode.

2. The semiconductor device according to claim 1, comprising: A semiconductor layer, disposed on the first main surface; A third electrode is disposed on the semiconductor layer; as well as a second through hole penetrating the substrate and the semiconductor layer and reaching the third electrode; The organic barrier layer is disposed on the semiconductor layer. The first through hole penetrates the semiconductor layer, The metal layer covers the second inner wall surface of the second through hole and is electrically connected to the third electrode.

3. The semiconductor device according to claim 1 or 2, wherein: The organic barrier layer includes polyimide or benzocyclobutene.

4. The semiconductor device according to claim 1 or 2, wherein: The thickness of the organic barrier layer is greater than or equal to 1 μm and less than or equal to 10 μm.

5. The semiconductor device according to claim 1 or 2, comprising: an inorganic barrier layer, disposed between the organic barrier layer and the first electrode, The first through hole penetrates the inorganic barrier layer.

6. The semiconductor device according to claim 5, wherein: The inorganic barrier layer has a thickness of 20 nm or more and 500 nm or less.

7. A method for manufacturing a semiconductor device, comprising the following steps: A structure is prepared, the structure comprising: a substrate having a first main surface and a second main surface opposite to the first main surface; an organic barrier layer provided above the first main surface; and a first electrode provided above the organic barrier layer; an insulating film, disposed on the first electrode; and a second electrode disposed on the insulating film; forming a first through hole by performing a first reactive ion etching, wherein the first through hole overlaps with the first electrode when viewed from a plan view perpendicular to the first main surface, penetrates the substrate, and reaches the organic barrier layer; By performing a second reactive ion etching, the first through hole is extended to penetrate the organic barrier layer and reach the first electrode; and A metal layer is formed, wherein the metal layer covers the second main surface and the first inner wall surface of the first through hole and is electrically connected to the first electrode.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The structure comprises: a semiconductor layer provided on the first main surface; and a third electrode disposed on the semiconductor layer, wherein the organic barrier layer is disposed on the semiconductor layer. The process of performing the first reactive ion etching includes the following steps: Performing a third reactive ion etching to form a portion of the first through hole that passes through the substrate and reaches the semiconductor layer and to form a second through hole, wherein the second through hole overlaps with the third electrode in the plan view, passes through the substrate, and reaches the semiconductor layer; as well as By performing fourth reactive ion etching, the first through hole is extended to penetrate the semiconductor layer and reach the organic barrier layer, and the second through hole is extended to penetrate the semiconductor layer and reach the third electrode, The metal layer covers the second inner wall surface of the second through hole and is electrically connected to the third electrode.

9. The method for manufacturing a semiconductor device according to claim 7 or 8, wherein: The structure has an inorganic barrier layer disposed between the organic barrier layer and the first electrode, The step of performing the second reactive ion etching includes the following steps: By performing fifth reactive ion etching, the first through hole is extended to penetrate the organic barrier layer and reach the inorganic barrier layer; and By performing the sixth reactive ion etching, the first through hole is extended to penetrate the inorganic barrier layer and reach the first electrode.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: A reactive gas including oxygen is used in the fifth reactive ion etching.

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