Metal oxide semiconductor capacitor

Abstract

A metal oxide semiconductor capacitor includes a substrate of a first conductivity type including a fin surrounded by an isolation region wherein the fin protrudes from a top surface of the isolation region; the counter doped region of the second conductive type is positioned in the fin and is used as a first polar plate of the MOS capacitor; the capacitor dielectric layer covers the side wall and the top surface of the fin; and the metal grid electrode covers the capacitor dielectric layer and is used as a second pole plate of the MOS capacitor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a structure of a metal-oxide-semiconductor capacitor (MOS capacitor). Background Art

[0002] In order to fabricate integrated circuits with higher integration densities than currently feasible, such as memories, logic elements, and other components, it is necessary to find ways to further reduce the size of capacitors (such as metal-oxide-semiconductor capacitors) and field-effect transistors (such as metal-oxide-semiconductor field-effect transistors). By reducing the overall size and operating voltage of the components while maintaining their electrical characteristics, miniaturization can achieve component densification and improve component performance. Summary of the Invention

[0003] The main object of the present invention is to provide an improved metal-oxide-semiconductor capacitor to solve the deficiencies or drawbacks of the prior art.

[0004] One aspect of the present invention provides a metal-oxide-semiconductor (MOS) capacitor, comprising a substrate of a first conductivity type, including fins surrounded by isolation regions, wherein the fins protrude from the top surface of the isolation regions; an anti-doped region of a second conductivity type, located in the fins, serving as the first electrode plate of the MOS capacitor; a capacitive dielectric layer, covering the sidewalls and the top surface of the fins; and a metal gate, covering the capacitive dielectric layer, serving as the second electrode plate of the MOS capacitor.

[0005] According to an embodiment of the present invention, the metal gate covers the sidewalls and the top surface of the fins.

[0006] According to an embodiment of the present invention, the MOS capacitor further comprises an interlayer dielectric layer, located on the metal gate; and a contact structure, embedded in the interlayer dielectric layer, wherein the contact structure is electrically connected to the metal gate.

[0007] According to an embodiment of the present invention, the contact structure is disposed directly above the isolation region.

[0008] According to an embodiment of the present invention, the anti-doped region is an N + doped region.

[0009] According to an embodiment of the present invention, the first conductivity type is P-type and the second conductivity type is N-type.

[0010] According to an embodiment of the present invention, the fins extend in a first direction, and the metal gate extends in a second direction orthogonal to the first direction.

[0011] According to an embodiment of the present invention, the fin further includes a first source / drain region and a second source / drain region, which are respectively located on opposite sides of the metal gate.

[0012] According to an embodiment of the present invention, the fin further includes a first epitaxial layer located on the first source / drain region; and a second epitaxial layer located on the second source / drain region, wherein the first epitaxial layer and the second epitaxial layer are electrically connected to the retrograde doped region.

[0013] According to an embodiment of the present invention, the first epitaxial layer and the second epitaxial layer include SiP.

[0014] On the other hand, the present invention provides a metal-oxide-semiconductor (MOS) capacitor, including a substrate of a first conductivity type, including fins surrounded by isolation regions, wherein the fins protrude from the top surface of the isolation regions; a retrograde doped region of a second conductivity type, located in the fins and serving as the first electrode plate of the MOS capacitor; a capacitive dielectric layer, covering only the top surface of the fins; and a metal gate, disposed on the capacitive dielectric layer and covering only the top surface of the fins, wherein the metal gate serves as the second electrode plate of the MOS capacitor.

[0015] According to an embodiment of the present invention, the metal gate does not cover the sidewalls of the fins.

[0016] According to an embodiment of the present invention, the MOS capacitor further includes: an interlayer dielectric layer, located on the metal gate; and a contact structure, embedded in the interlayer dielectric layer, wherein the contact structure is electrically connected to the metal gate.

[0017] According to an embodiment of the present invention, the contact structure is disposed directly above the fin.

[0018] According to an embodiment of the present invention, the retrograde doped region is an N + doped region.

[0019] According to an embodiment of the present invention, the first conductivity type is P-type, and the second conductivity type is N-type.

[0020] According to an embodiment of the present invention, the fin extends in a first direction, and the metal gate extends along a second direction orthogonal to the first direction.

[0021] According to an embodiment of the present invention, the fin further includes a first source / drain region and a second source / drain region, which are respectively located on opposite sides of the metal gate.

[0022] According to an embodiment of the present invention, the fin further includes a first epitaxial layer located on the first source / drain region; a second epitaxial layer located on the second source / drain region, wherein the first epitaxial layer and the second epitaxial layer are electrically connected to the retrograde doped region.

[0023] According to an embodiment of the present invention, the first epitaxial layer and the second epitaxial layer contain SiP. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Partial top view of the semiconductor structure illustrated in an embodiment of the present invention;

[0025] Figure 2 Along Figure 1 Schematic cross-sectional view taken along the tangent line I-I' in

[0026] Figure 3 Along Figure 1 Schematic cross-sectional view taken along the tangent line II-II' in

[0027] Figure 4 Partial top view of the semiconductor structure illustrated in another embodiment of the present invention;

[0028] Figure 5 Along Figure 4 Schematic cross-sectional view taken along the tangent line I-I' in

[0029] Figure 6 Along Figure 4 Schematic cross-sectional view taken along the tangent line II-II' in

[0030] SYMBOL DESCRIPTION

[0031] 1 Semiconductor structure

[0032] 10 Circuit element

[0033] 20, 20a Metal oxide semiconductor (MOS) capacitor

[0034] 100 Substrate

[0035] 110, 120 Interlayer dielectric layer

[0036] A1 First region

[0037] A2 Second region

[0038] D1 First direction

[0039] D2 Second direction

[0040] CT-1, CT-2 Contact structure

[0041] CD Capacitor dielectric layer

[0042] CN Counter-doped region

[0043] EP-1, EP-2 Epitaxial layer

[0044] F1, F2, F3 Fin

[0045] GD gate dielectric layer

[0046] MD-1 and MD-2 conductive strips

[0047] MG-1 and MG-2 metal gates

[0048] S1 sidewall

[0049] S2 top surface

[0050] SD-1 and SD-2 source / drain regions

[0051] SP-1 and SP-2 spacer walls

[0052] ST-1 and ST-2 isolation regions

[0053] w1 and w2 widths Detailed implementation manners

[0054] In the following, details will be described with reference to the accompanying drawings, the content of which also forms a part of the detailed description of the specification and is illustrated in a specific example manner for implementing the embodiment. The following embodiments have described sufficient details for those of ordinary skill in the art to implement based on them.

[0055] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as a limitation. On the contrary, the embodiments included therein will be defined by the appended claims.

[0056] Please refer to Figures 1 to 3 , in which Figure 1 is a partial top view of a semiconductor structure illustrated according to an embodiment of the present invention, Figure 2 is a schematic cross-sectional view taken along the tangent line I-I' in Figure 1 , Figure 3 is a schematic cross-sectional view taken along the tangent line II-II' in Figure 1 . As shown in Figure 1 and Figure 2 , the semiconductor structure 1 includes a substrate 100 of a first conductivity type. For example, the substrate 100 may be a silicon substrate, but is not limited thereto, and the first conductivity type may be P-type. In the first region A1 of the substrate 100, circuit elements 10 are formed, such as fin field effect transistors. According to an embodiment of the present invention, for example, the first region A1 may be a logic circuit region or a peripheral circuit region, but is not limited thereto.

[0057] According to an embodiment of the present invention, the circuit element 10 includes a plurality of fins, for example, fin F1 and fin F2, extending along a first direction D1. According to an embodiment of the present invention, F1 and fin F2 protrude from the top surface of the isolation region ST-1, and the fins F1 and F2 have a width w1. According to an embodiment of the present invention, the isolation region ST-1 is a shallow trench isolation (STI) structure.

[0058] According to an embodiment of the present invention, the circuit element 10 further includes a metal gate MG-1 located on the fins F1 and F2 and extending along a second direction D2, and a gate dielectric layer GD. The gate dielectric layer GD is located between the metal gate MG-1 and the fins F1 and F2. According to an embodiment of the present invention, the first direction D1 is orthogonal to the second direction D2.

[0059] According to an embodiment of the present invention, the circuit element 10 further includes a spacer wall SP-1, for example, a silicon nitride layer, located on the sidewalls of the metal gate MG-1. According to an embodiment of the present invention, the metal gate MG-1 and the spacer wall SP-1 are formed in the interlayer dielectric layer 110. According to an embodiment of the present invention, an interlayer dielectric layer 120 is formed on the metal gate MG-1 and the interlayer dielectric layer 110.

[0060] According to an embodiment of the present invention, the metal gate MG-1 can be formed by a replacement metal gate (RMG) fabrication process, wherein the metal gate MG-1 can include a high-k material layer, a barrier layer, a work function layer, and a low-resistance metal layer, etc. Since it is a well-known technology, it will not be elaborated here.

[0061] According to an embodiment of the present invention, as Figure 1 shown, source / drain regions SD-1 are further included on the fins F1 and F2, located on opposite sides of the metal gate MG-1. The source / drain regions SD-1 on adjacent fins F1 and F2 can be interconnected by a conductive strip MD-1 extending along the second direction D2. An epitaxial layer EP-1, for example, SiP or SiGe, can be formed on the source / drain regions SD-1.

[0062] According to an embodiment of the present invention, a contact structure CT-1 is formed in the interlayer dielectric layer 120, electrically connecting downward to the metal gate MG-1. According to an embodiment of the present invention, for example, the contact structure CT-1 can include metal. According to an embodiment of the present invention, the contact structure CT-1 does not overlap with the fins F1 and F2. As Figure 1 shown, the contact structure CT-1 is located directly above the isolation region ST-1.

[0063] As Figure 1 and Figure 3As shown, within the second region A2 of the substrate 100, a metal-oxide semiconductor (MOS) capacitor 20 is formed. According to an embodiment of the present invention, the MOS capacitor 20 includes a substrate 100 of a first conductivity type, including fins F3 surrounded by isolation regions ST-2, where the fins F3 protrude from the top surface of the isolation regions ST-2 and extend along a first direction D1. According to an embodiment of the present invention, the fins F3 have a width w2, where the width w2 of the fins F3 is greater than the widths w1 of the fins F1 and F2.

[0064] According to an embodiment of the present invention, the MOS capacitor 20 further includes a counter-doped region CN of a second conductivity type, located in the fins F3, as the first electrode plate of the MOS capacitor 20. According to an embodiment of the present invention, the counter-doped region CN is an N + doped region. According to an embodiment of the present invention, the counter-doped region CN occupies a portion of the fins F3 above the isolation regions ST-2. According to an embodiment of the present invention, for example, the first conductivity type is P-type and the second conductivity type is N-type.

[0065] According to an embodiment of the present invention, the MOS capacitor 20 further includes a capacitive dielectric layer CD, covering the sidewalls S1 and the top surface S2 of the fins F3, and a metal gate MG-2, covering the capacitive dielectric layer CD, as the second electrode plate of the MOS capacitor 20. According to an embodiment of the present invention, the metal gate MG-2 also covers the sidewalls S1 and the top surface S2 of the fins F3. According to an embodiment of the present invention, the metal gate MG-2 extends along a second direction D2 orthogonal to the first direction D1.

[0066] The metal gate MG-2 of the MOS capacitor 20 covers a single and large-area fin F3, and the width w2 of the fin F3 is greater than the widths w1 of the fins F1 and F2. For example, w2 = 5w1 or w2 = 6w1. The advantage is that it can reduce the influence of the ion implantation manufacturing process for forming the counter-doped region CN on the subsequent fin profile.

[0067] According to an embodiment of the present invention, the MOS capacitor 20 further includes an interlayer dielectric layer 120, located on the metal gate MG-2, and a contact structure CT-2, embedded in the interlayer dielectric layer 120, where the contact structure CT-2 is electrically connected to the metal gate MG-2. According to an embodiment of the present invention, the contact structure CT-2 is disposed directly above the isolation region ST-2. According to an embodiment of the present invention, the contact structure CT-2 does not overlap with the fins F3.

[0068] According to an embodiment of the present invention, the fin F3 further includes source / drain regions SD-2, which are respectively located on opposite sides of the metal gate MG-2. The source / drain regions SD-2 on the fin F3 can be interconnected by a conductive strip MD-2 extending along the second direction D2. According to an embodiment of the present invention, the fin F3 further includes an epitaxial layer EP-2, which is located on the source / drain regions SD-2, wherein the epitaxial layer EP-2 is electrically connected to the counter-doped region CN. According to an embodiment of the present invention, for example, the epitaxial layer EP-2 includes SiP.

[0069] Please refer to Figures 4 to 6 , wherein, Figure 4 is a partial top view of a semiconductor structure illustrated according to another embodiment of the present invention, Figure 5 is a schematic cross-sectional view taken along the tangent line I-I' in Figure 4 . Figure 6 is a schematic cross-sectional view taken along the tangent line II-II' in Figure 4 . As shown in Figure 4 and Figure 5 , the semiconductor structure 2 also includes a substrate 100 of a first conductivity type. For example, the substrate 100 can be a silicon substrate, but is not limited thereto. The first conductivity type can be P-type. In the first region A1 of the substrate 100, circuit elements 10 are formed. For example, the fin field-effect transistor. According to an embodiment of the present invention, for example, the first region A1 can be a logic circuit region or a peripheral circuit region, but is not limited thereto.

[0070] According to an embodiment of the present invention, the circuit element 10 includes a plurality of fins. For example, the fins F1 and F2 extend along the first direction D1. According to an embodiment of the present invention, F1 and the fin F2 protrude from the top surface of the isolation region ST-1, and the fins F1 and F2 have a width w1. According to an embodiment of the present invention, the isolation region ST-1 is a shallow trench isolation (STI) structure.

[0071] According to an embodiment of the present invention, the circuit element 10 further includes a metal gate MG-1 located on the fins F1 and F2 and extending along the second direction D2, and a gate dielectric layer GD. The gate dielectric layer GD is located between the metal gate MG-1 and the fins F1 and F2. According to an embodiment of the present invention, the first direction D1 is orthogonal to the second direction D2.

[0072] According to an embodiment of the present invention, the circuit element 10 further includes a spacer SP-1, for example, a silicon nitride layer, located on the sidewalls of the metal gate MG-1. According to an embodiment of the present invention, the metal gate MG-1 and the spacer SP-1 are formed in the interlayer dielectric layer 110. According to an embodiment of the present invention, an interlayer dielectric layer 120 is formed on the metal gate MG-1 and the interlayer dielectric layer 110.

[0073] According to an embodiment of the present invention, the metal gate MG-1 can be formed by using a replacement metal gate (RMG) fabrication process. The metal gate MG-1 can include a high-k dielectric layer, a barrier layer, a work function layer, and a low-resistance metal layer, etc. Since this is a well-known technology, it will not be elaborated here.

[0074] According to an embodiment of the present invention, as Figure 4 shown, source / drain regions SD-1 are further included on the fins F1 and F2, located on opposite sides of the metal gate MG-1. The source / drain regions SD-1 on adjacent fins F1 and F2 can be interconnected by a conductive strip MD-1 extending along the second direction D2. An epitaxial layer EP-1, such as SiP or SiGe, can be formed on the source / drain regions SD-1.

[0075] According to an embodiment of the present invention, a contact structure CT-1 is formed in the interlayer dielectric layer 120 and is electrically connected downward to the metal gate MG-1. According to an embodiment of the present invention, the contact structure CT-1 does not overlap with the fins F1 and F2. As Figure 4 shown, the contact structure CT-1 is located directly above the isolation region ST-1.

[0076] As Figure 4 and Figure 6 shown, a metal-oxide-semiconductor (MOS) capacitor 20a is formed in the second region A2 of the substrate 100. According to an embodiment of the present invention, the MOS capacitor 20a includes a substrate 100 of a first conductivity type, including a fin F3 surrounded by an isolation region ST-2, where the fin F3 protrudes from the top surface of the isolation region ST-2 and extends along the first direction D1. According to an embodiment of the present invention, the fin F3 has a width w2, where the width w2 of the fin F3 is greater than the width w1 of the fins F1 and F2.

[0077] According to an embodiment of the present invention, the MOS capacitor 20a further includes an anti-doping region CN of a second conductivity type, located in the fin F3 and serving as the first electrode plate of the MOS capacitor 20. According to an embodiment of the present invention, the anti-doping region CN is an N + doped region. Compared with FIG. 3, the depth of the anti-doping region CN in FIG. 6 is shallower. According to an embodiment of the present invention, for example, the first conductivity type is P-type and the second conductivity type is N-type.

[0078] According to an embodiment of the present invention, the MOS capacitor 20a further includes a capacitive dielectric layer CD that only covers the top surface S2 of the fin F3, and a metal gate MG-2 that covers the capacitive dielectric layer CD and serves as the second electrode plate of the MOS capacitor 20a. According to an embodiment of the present invention, the metal gate MG-2 also only covers the top surface S2 of the fin F3. According to an embodiment of the present invention, the metal gate MG-2 does not cover the sidewall S1 of the fin F3. According to an embodiment of the present invention, the metal gate MG-2 extends along a second direction D2 that is orthogonal to the first direction D1.

[0079] The metal gate MG-2 of the MOS capacitor 20a covers a single and large-area fin F3, and the width w2 of the fin F3 is greater than the widths w1 of the fins F1 and F2. For example, w2 = 5w1 or w2 = 6w1. The advantage is that it can reduce the influence of the ion implantation process for forming the counter-doped region CN on the subsequent fin profile. In addition, the capacitive dielectric layer CD and the metal gate MG-2 do not cover the sidewall S1 of the fin F3, which can avoid the influence caused by the thickness variation of the capacitive dielectric layer.

[0080] According to an embodiment of the present invention, the MOS capacitor 20a further includes an interlayer dielectric layer 120 located on the metal gate MG-2, and a contact structure CT-2 embedded in the interlayer dielectric layer 120, where the contact structure CT-2 is electrically connected to the metal gate MG-2. According to an embodiment of the present invention, the contact structure CT-2 is disposed directly above the fin F3. According to an embodiment of the present invention, as shown in FIG. 4, the contact structure CT-2 completely overlaps with the fin F3.

[0081] According to an embodiment of the present invention, the fin F3 further includes source / drain regions SD-2 respectively located on opposite sides of the metal gate MG-2. According to an embodiment of the present invention, the fin F3 further includes an epitaxial layer EP-2 located on the source / drain regions SD-2, where the epitaxial layer EP-2 is electrically connected to the counter-doped region CN. The source / drain regions SD-2 on the fin F3 can be interconnected by a conductive strip MD-2 that extends along the second direction D2. According to an embodiment of the present invention, for example, the epitaxial layer EP-2 includes SiP.

[0082] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope covered by the present invention.

Claims

1. A metal-oxide-semiconductor (MOS) capacitor, comprising: A substrate of a first conductivity type, comprising fins surrounded by isolation regions, wherein, the fins protrude from the top surface of the isolation regions; An anti-doped region of a second conductivity type, located in the fins, serving as the first electrode plate of the metal-oxide-semiconductor capacitor; A capacitive dielectric layer, covering the sidewalls and the top surface of the fins; and A metal gate, covering the capacitive dielectric layer, serving as the second electrode plate of the metal-oxide-semiconductor capacitor.

2. The metal-oxide-semiconductor capacitor according to claim 1, wherein, the metal gate covers the sidewalls and the top surface of the fins.

3. The metal-oxide-semiconductor capacitor according to claim 1, wherein, further comprising: An interlayer dielectric layer, located on the metal gate; and A contact structure, embedded in the interlayer dielectric layer, wherein the contact structure is electrically connected to the metal gate.

4. The metal-oxide-semiconductor capacitor according to claim 3, wherein, the contact structure is disposed directly above the isolation region.

5. The metal-oxide-semiconductor capacitor according to claim 1, wherein, This counter-doped region is an N + doped region.

6. The metal-oxide-semiconductor capacitor according to claim 1, wherein, the first conductivity type is P-type and the second conductivity type is N-type.

7. The metal-oxide-semiconductor capacitor according to claim 1, wherein, the fins extend in a first direction, and the metal gate extends in a second direction orthogonal to the first direction.

8. The metal-oxide-semiconductor capacitor according to claim 1, wherein, the fins further comprise: A first source / drain region and a second source / drain region, respectively located on opposite sides of the metal gate.

9. The metal-oxide-semiconductor capacitor according to claim 8, wherein, the fins further comprise: A first epitaxial layer, located on the first source / drain region; and A second epitaxial layer, located on the second source / drain region, wherein the first epitaxial layer and the second epitaxial layer are electrically connected to the anti-doped region.

10. The metal-oxide-semiconductor capacitor according to claim 9, wherein, the first epitaxial layer and the second epitaxial layer comprise SiP.

11. A metal-oxide-semiconductor (MOS) capacitor, comprising: A substrate of a first conductivity type, comprising fins surrounded by isolation regions, wherein, the fins protrude from the top surface of the isolation regions; An anti-doped region of a second conductivity type, located in the fins, serving as the first electrode plate of the metal-oxide-semiconductor capacitor; A capacitive dielectric layer, covering only the top surface of the fins; and A metal gate, disposed on the capacitive dielectric layer, covering only the top surface of the fins, wherein the metal gate serves as the second electrode plate of the metal-oxide-semiconductor capacitor.

12. The metal-oxide-semiconductor capacitor according to claim 11, wherein, the metal gate does not cover the sidewalls of the fins.

13. The metal-oxide-semiconductor capacitor according to claim 11, wherein, further comprising: An interlayer dielectric layer, located on the metal gate; and A contact structure, embedded in the interlayer dielectric layer, wherein the contact structure is electrically connected to the metal gate.

14. The metal-oxide-semiconductor capacitor according to claim 13, wherein, The contact structure is disposed directly above the fin.

15. The metal oxide semiconductor capacitor according to claim 11, wherein, This anti-doping region is an N + doping region.

16. The metal oxide semiconductor capacitor according to claim 11, wherein, The first conductivity type is P-type and the second conductivity type is N-type.

17. The metal oxide semiconductor capacitor according to claim 11, wherein, The fin extends in a first direction, and the metal gate extends in a second direction orthogonal to the first direction.

18. The metal oxide semiconductor capacitor according to claim 11, wherein, The fin further comprises: A first source / drain region and a second source / drain region, respectively located on opposite sides of the metal gate.

19. The metal oxide semiconductor capacitor according to claim 18, wherein, The fin further comprises: A first epitaxial layer, located on the first source / drain region; A second epitaxial layer, located on the second source / drain region, wherein the first epitaxial layer and the second epitaxial layer are electrically connected to the retrograde doped region.

20. The metal oxide semiconductor capacitor according to claim 19, wherein, The first epitaxial layer and the second epitaxial layer comprise SiP.

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