Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a first surface and a second surface opposite to the first surface; the first groove structure penetrates through the first surface and extends towards the second surface, the first groove structure comprises a first polycrystalline silicon structure and a first oxide layer shielding metal layer surrounding the first polycrystalline silicon structure, and the first groove structure is located on the first surface of the substrate and covers the first groove structure; the first conductive layer is arranged on the shielding metal layer; and a second conductive layer disposed on the second surface of the substrate, wherein the top surface of the first polysilicon structure and the top surface of the first oxide layer are coplanar with the first surface.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same. More specifically, it relates to a rectifying device of a trench metal oxide semiconductor (MOS) structure and a method for manufacturing the same. Background Art

[0002] Modern power circuits require rectifiers with high power, low loss, and fast switching. For high-voltage applications, a P-N junction gate rectifier with a high switching speed is often used when a high breakdown voltage and a high operating temperature are required. For low-voltage applications, a Schottky barrier rectifier is often used when a high switching speed and a very low forward bias are required. A Schottky barrier rectifier is a majority carrier device that uses a metal oxide semiconductor (MOS) process and allows only a very small reverse leakage current to flow during the recovery process. Unfortunately, when operating at elevated temperatures, the Schottky barrier rectifier suffers from an undesirably high reverse leakage current.

[0003] Some currently adopted improvement measures are used to improve the blocking ability of the Schottky rectifier. One such improvement method is to use a Schottky Barrier Diode (SBD), which has a lower forward voltage and is beneficial to forward power loss. However, the SBD also has a higher reverse leakage current, resulting in a higher reverse power loss, which becomes a technical bottleneck for such devices. Due to the Schottky barrier lowering effect, the leakage current of the Schottky is also affected by the electric field at the metal-semiconductor interface.

[0004] Therefore, the rectifying devices of the prior art need to be further improved to obtain more ideal high power and low loss and to be applicable to fast switching applications. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a semiconductor structure. The semiconductor structure includes: a substrate having a first surface and a second surface opposite to the first surface; a first trench structure extending through the first surface towards the second surface, wherein the first trench structure includes a first polysilicon structure and a first oxide layer shielding metal layer surrounding the first polysilicon structure, located on the first surface of the substrate and covering the first trench structure; a first conductive layer disposed on the shielding metal layer; and a second conductive layer disposed on the second surface of the substrate, wherein the top surface of the first polysilicon structure and the top surface of the first oxide layer are coplanar with the first surface.

[0006] Embodiments of the present disclosure relate to a method for manufacturing a semiconductor structure. The method includes: forming first trenches and second trenches spaced apart from each other in a substrate, extending from a first surface to a second surface opposite to the first surface; forming a first oxide layer in the first trenches; forming a second oxide layer in the second trenches; forming a first polysilicon structure in the first trenches and surrounded by the first oxide layer to form a first trench structure; and forming a second polysilicon structure in the second trenches and surrounded by the second oxide layer to form a second trench structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of some embodiments of the present disclosure may be best understood when read in conjunction with the following detailed description with reference to the accompanying drawings. It should be noted that the various structures are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0008] Figure 1 Shown is a cross-sectional view of a semiconductor structure according to some embodiments of the present case;

[0009] Figure 2 Shown is a cross-sectional view of a semiconductor structure according to some embodiments of the present case;

[0010] Figure 3 Shown is a graph of depth versus electric field of a semiconductor structure according to some embodiments of the present case.

[0011] Figures 4 to 19 Shown is one or more stages in a method for manufacturing a semiconductor structure according to some embodiments of the present case.

[0012] The same or similar components are denoted by the same reference numerals in the drawings and the detailed description. From the following detailed description in conjunction with the drawings, some embodiments of the present disclosure will be immediately understood. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be limiting. In the present disclosure, a reference to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Embodiments of the present disclosure are discussed in detail below. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0015] The present disclosure provides a semiconductor structure and a method for manufacturing the same. In the semiconductor structure of the present disclosure, due to the shape and position of the polysilicon structure and the oxide layer in the trench structure, the silicon carbide substrate of the semiconductor structure of the present disclosure is not easily broken down, so it has a relatively high forward voltage and breakdown voltage. In addition, the semiconductor structure of the present disclosure has a relatively low epitaxial concentration, thereby having a relatively low forward voltage drop, a relatively low surface electric field, and a relatively low leakage current.

[0016] Figure 1 Shown is a cross-sectional view of a semiconductor structure 10 according to some embodiments of the present case. Specifically, the semiconductor structure 10 is a trench MOS rectifier device structure and has a vertical current conduction path. For example, the current of the semiconductor structure 10 can conduct vertically through the semiconductor structure 10.

[0017] As Figure 1 shown, the semiconductor structure 10 includes a substrate 11, a first trench structure 21, and a second trench structure 22. The semiconductor structure 10 may further include a shielding metal layer 35, a first conductive layer 36, and a second conductive layer 37.

[0018] In some embodiments, the substrate 11 includes a base material 111 and an epitaxial layer 112 located on the base material 111. In some embodiments, the base material 111 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. The epitaxial layer 112 includes, for example, silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), or other semiconductor materials. In some embodiments, the epitaxial layer 112 includes silicon carbide. The base material 111 is an N-type or P-type semiconductor material. The epitaxial layer 112 is an N-type or P-type semiconductor material.

[0019] The base material 111 and the epitaxial layer 112 have the same conductivity type doping. For example, both the base material 111 and the epitaxial layer 112 are N-type. In some embodiments, the base material 111 is part of a silicon substrate or a silicon wafer. The doping concentration of the base material 111 is greater than the doping concentration of the epitaxial layer 112.

[0020] The substrate may have a first surface 11A and a second surface 11B opposite to the first surface 11A. The second surface 11B and the first surface 11A may be located on opposite sides of the substrate 11. The first surface 11A and the second surface 11B may be horizontal planes. For convenience of description, the direction orthogonal to the first surface 11A and the second surface 11B is defined as the vertical direction Z, and the plane formed by the first direction X and the second direction Y is orthogonal to the vertical direction Z. In some embodiments, the first surface 11A may be the active surface of the epitaxial layer 112. The bottom surface of the substrate 111 is the second surface 11B, which can be used to contact a metal layer, such as to contact the second conductive layer 37.

[0021] The first trench structure 21 penetrates through the first surface 11A and extends towards the second surface 11B, wherein the first trench structure 21 includes a first polysilicon structure 211 and a first oxide layer 212 surrounding the first polysilicon structure 211. In some embodiments, the top surface of the first trench structure 21 is coplanar with the first surface 11A. In some embodiments, the top surface of the first polysilicon structure 211 and the top surface of the first oxide layer 212 are coplanar with the first surface 11A. Viewed from a top-down perspective, the first trench structure 21 extends in a first direction X parallel to the first surface 11A.

[0022] The first oxide layer 212 is used to electrically isolate the first polysilicon structure 211 from the epitaxial layer 112. In other words, the first polysilicon structure 211 is separated from the epitaxial layer 112 by the first oxide layer 212 in the trench. The first oxide layer 212 surrounds the first polysilicon structure 211. The sidewalls and the bottom wall of the first polysilicon structure 211 are in contact with the first oxide layer 212. The first oxide layer 212 includes a bottom wall portion 212a and a sidewall portion 212b located on the bottom wall portion 212a and surrounding the first polysilicon structure 211. The first polysilicon structure 211 is located on the bottom wall portion 212a of the first oxide layer 212, and the sidewalls of the first polysilicon structure 211 are surrounded by the sidewall portion 212b of the first oxide layer 212. In some embodiments, the first polysilicon structure 211 is a columnar structure.

[0023] The thickness T1 of the bottom wall portion 212a and the thickness T2 of the side wall portion 212b of the first oxide layer 212 can be adjusted according to the size of the first polysilicon structure 211 or the operating voltage. For example, the thickness T2 of the side wall portion 212b of the first oxide layer 212 is less than or equal to the width W211 of the first polysilicon structure 211 in the trench. The electrical stress of the first oxide layer 212 can be reduced by adjusting the thickness T1 of the bottom wall portion 212a of the first oxide layer 212, for example, making the thickness T1 of the bottom wall portion 212a greater than the thickness T2 of the side wall portion 212b. In some embodiments, the first oxide layer 212 comprises silicon oxide. The first polysilicon structure 211 comprises a polysilicon material.

[0024] The substrate 11 includes a first doped region 31. The first doped region 31 extends in the first direction X. In some embodiments, the first doped region 31 is disposed between the first surface 11A and the second surface 11B, adjacent to the first oxide layer 212 and separated from the first polysilicon structure 211. In some embodiments, the first doped region 31 is located in the epitaxial layer 112 and in contact with the first oxide layer 212. At least a portion of the first oxide layer 212 is located between the first polysilicon structure 211 and the first doped region 31. The first doped region 31 is located between the first oxide layer 212 and the second surface 11B. Viewed from a top-down perspective, the first doped region 31 is disposed below the first polysilicon structure 211 and at least partially overlaps with the first polysilicon structure 211. The wider the width W31 of the first doped region 31, the stronger the electric field intensity borne by the first doped region 31 under a reverse voltage, improving the breakdown voltage capability of the semiconductor structure 10; however, under a forward voltage, it may cause the conductive channel to constrict, increasing the resistance. Therefore, the relationship between the concentration, width, and depth of the first doped region 31 can be adjusted according to requirements. In some embodiments, the width W31 of the first doped region 31 is less than or equal to the width W211 of the first polysilicon structure 211. In other embodiments, the width W31 of the first doped region 31 is greater than the width W211 of the first polysilicon structure 211.

[0025] The first doped region 31 has a conductivity type different from that of the epitaxial layer 112. The doping concentration of the first doped region 31 is greater than the doping concentration of the epitaxial layer 112. At least a portion of the epitaxial layer 112 is disposed between the first doped region 31 and the substrate 111. In some embodiments, the first doped region 31 has a second conductivity type. In some embodiments, the first doped region 31 has a P-type, while the epitaxial layer 112 has an N-type. The first doped region 31 contains a P-type dopant, and the P-type dopant can be, for example, boron, aluminum, gallium, indium, etc. In some embodiments, the P-type dopant contained in the first doped region 31 is boron.

[0026] The first doped region 31 can reduce the electrical stress at the bottom of the first trench structure 21. The first doped region 31 has a first lower peripheral edge 31p, the first oxide layer 212 has a second lower peripheral edge 212p, and the first polysilicon structure 211 has a third lower peripheral edge 211p. The first lower peripheral edge 31p, the second lower peripheral edge 212p, and the third lower peripheral edge 211p are configured to withstand the reverse voltage of the semiconductor structure 10. In some embodiments, the horizontal height of the third lower peripheral edge 211p is higher than the horizontal height of the second lower peripheral edge 212p, and the horizontal height of the second lower peripheral edge 212p is higher than the horizontal height of the first lower peripheral edge 31p. When powered on, the electric field of the first lower peripheral edge 31p is greater than the electric field of the second lower peripheral edge 212p, and the electric field of the second lower peripheral edge 212p is greater than the electric field of the third lower peripheral edge 211p.

[0027] The second trench structure 22 is spaced apart from the first trench structure 21. The second trench structure 22 extends through the first surface 11A toward the second surface 11B, wherein the second trench structure 22 includes a second polysilicon structure 221 and a second oxide layer 222 surrounding the second polysilicon structure 221. In some embodiments, the top surface of the second trench structure 22 is coplanar with the first surface 11A. In some embodiments, the top surface of the second polysilicon structure 221 and the top surface of the second oxide layer 222 are coplanar with the first surface 11A. Viewed from a top-down perspective, the second trench structure 22 extends in a first direction X parallel to the first surface 11A.

[0028] The second oxide layer 222 is used to electrically isolate the second polysilicon structure 221 from the epitaxial layer 112. In other words, the second polysilicon structure 221 is separated from the epitaxial layer 112 by the second oxide layer 222 in the trench. The second oxide layer 222 surrounds the second polysilicon structure 221. The sidewalls and the bottom wall of the second polysilicon structure 221 are in contact with the second oxide layer 222. The second oxide layer 222 includes a bottom wall portion 222a and a side wall portion 222b located on the bottom wall portion 222a and surrounding the second polysilicon structure 221. The second polysilicon structure 221 is located on the bottom wall portion 222a of the second oxide layer 222, and the sidewalls of the second polysilicon structure 221 are surrounded by the side wall portion 222b of the second oxide layer 222. In some embodiments, the second polysilicon structure 221 is a columnar structure.

[0029] The thickness T3 of the bottom wall portion 222a and the thickness T4 of the side wall portion 222b of the second oxide layer 222 can be adjusted according to the size of the second polysilicon structure 221 or the operating voltage. For example, the thickness T4 of the side wall portion 222b of the second oxide layer 222 is less than or equal to the width W221 of the second polysilicon structure 221 in the trench. The second oxide layer 222 contains silicon oxide. In some embodiments, the second polysilicon structure 221 contains a polysilicon material. In some embodiments, the electrical stress of the second oxide layer 222 can be reduced by adjusting the thickness T3 of the bottom wall portion 222a of the second oxide layer 222, for example, making the thickness T3 of the bottom wall portion 222a greater than the thickness T4 of the side wall portion 222b.

[0030] The substrate 11 contains a second doped region 32. The second doped region 32 extends in the first direction X. In some embodiments, the second doped region 32 is disposed between the first surface 11A and the second surface 11B, adjacent to the second oxide layer 222 and separated from the second polysilicon structure 221. In some embodiments, the second doped region 32 is located in the epitaxial layer 112 and in contact with the second oxide layer 222. At least a portion of the second oxide layer 222 is located between the second polysilicon structure 221 and the second doped region 32. The second doped region 32 is located between the second oxide layer 222 and the second surface 11B. Viewed from a top-down perspective, the second doped region 32 is disposed below the second polysilicon structure 221 and at least partially overlaps with the second polysilicon structure 221.

[0031] The distance between the second doped region 32 and the first surface 11A and the distance between the first doped region 31 and the first surface 11A can be the same or different. In some embodiments, the distance between the second doped region 32 and the first surface 11A is substantially the same as the distance between the first doped region 31 and the first surface 11A. The wider the width W32 of the second doped region 32, the stronger the electric field intensity borne by the second doped region 32 under reverse voltage, improving the breakdown voltage capability of the semiconductor structure 10; however, under forward voltage, it may cause the conductive channel to constrict, increasing the resistance. Therefore, the relationship between the concentration, width, and depth of the second doped region 32 can be adjusted according to requirements. In some embodiments, the width W32 of the second doped region 32 is less than or equal to the width W221 of the second polysilicon structure 221. In other embodiments, the width W32 of the second doped region 32 is greater than the width W221 of the second polysilicon structure 221.

[0032] The second doped region 32 has a conductivity type different from that of the epitaxial layer 112. The doping concentration of the second doped region 32 is greater than that of the epitaxial layer 112. At least a part of the epitaxial layer 112 is disposed between the second doped region 32 and the substrate 111. In some embodiments, the second doped region 32 has a second-type conductivity type. In some embodiments, the second doped region 32 is of P-type, while the epitaxial layer 112 is of N-type. The second doped region 32 contains a P-type dopant, and the P-type dopant can be, for example, boron, aluminum, gallium, indium, etc. The P-type dopant contained in the second doped region 32 is boron.

[0033] The second doped region 32 can reduce the electrical stress at the bottom of the second trench structure 22. The second doped region 32 has a sixth lower peripheral edge 32p, the first oxide layer 212 has a seventh lower peripheral edge 222p, and the first polysilicon structure 211 has an eighth lower peripheral edge 221p. The sixth lower peripheral edge 32p, the seventh lower peripheral edge 222p, and the eighth lower peripheral edge 221p are configured to withstand the reverse voltage of the semiconductor structure 10. In some embodiments, the horizontal height of the eighth lower peripheral edge 221p is higher than that of the seventh lower peripheral edge 222p, and the horizontal height of the seventh lower peripheral edge 222p is higher than that of the sixth lower peripheral edge 32p. When powered on, the electric field of the sixth lower peripheral edge 32p is greater than that of the seventh lower peripheral edge 222p, and the electric field of the seventh lower peripheral edge 222p is greater than that of the eighth lower peripheral edge 221p. The closer the horizontal height of the lower peripheral edge is to the second surface 11B, the greater the electric field.

[0034] The substrate 11 between the first trench structure 21 and the second trench structure 22 forms a mesa surface. In some embodiments, the mesa separates the first trench structure 21 and the second trench structure 22. The width of the mesa can be adjusted by the positions of the first trench structure 21 and the second trench structure 22.

[0035] In some embodiments, the substrate 11 further includes a third doped region 33 disposed between the first trench structure 21 and the second trench structure 22. The third doped region 33 is located on the mesa, for example, at the center of the mesa adjacent to the first surface 11A, and is used to reduce the electric field of the mesa and reduce the leakage current. The width of the third doped region 33 is smaller than the width of the mesa. In other words, the third doped region 33 is surrounded by the epitaxial layer 112. The third doped region 33 extends from the first surface 11A to the second surface 11B. In some embodiments, the distance between the first doped region 31 and the first surface 11A is greater than the distance between the third doped region 33 and the first surface 11A. In some embodiments, the distance between the second doped region 32 and the first surface 11A is greater than the distance between the third doped region 33 and the first surface 11A.

[0036] The third doping region 33 has a conductivity type different from that of the epitaxial layer 112. The doping concentration of the third doping region 33 is greater than that of the epitaxial layer 112. In some embodiments, the third doping region 33 has a second type of conductivity type. In some embodiments, the third doping region 33 has a P-type, while the epitaxial layer 112 has an N-type. The third doping region 33 contains a P-type dopant, and the P-type dopant can be, for example, boron, aluminum, gallium, indium, etc. The P-type dopant contained in the third doping region 33 is boron.

[0037] The shielding metal layer 35 is located on the first surface 11A of the substrate 11 and covers the first trench structure 21, the second trench structure 22, and the third doping region 33. The shielding metal layer 35 is in contact with the first polysilicon structure 211, the second polysilicon structure 221, and the third doping region 33. The shielding metal layer 35 includes nickel (Ni), titanium (Ti), molybdenum (Mo), or other metals or alloys.

[0038] The first conductive layer 36 is disposed on the shielding metal layer 35. The first conductive layer 36 is in contact with and electrically connected to the shielding metal layer 35. The first conductive layer 36 contains a conductive material, such as a metal, which can be, for example but not limited to, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), titanium nitride (TiN), aluminum silicon (AlSi) alloy, aluminum silicon copper (AlSiCu) alloy, or other metals or alloys. In some embodiments, the thickness of the first conductive layer 36 is greater than the thickness of the shielding metal layer 35.

[0039] The second conductive layer 37 is disposed on the second surface 11B of the substrate 11 and is in contact with the base material 111. The second conductive layer 37 contains a conductive material, such as a metal, which can be, for example but not limited to, copper, gold, silver, aluminum, nickel, titanium, tungsten, tin, titanium nitride, aluminum silicon alloy, aluminum silicon copper alloy, or other metals or alloys. The first conductive layer 36 and the second conductive layer 37 may contain the same conductive material. The first conductive layer 36 and the second conductive layer 37 may contain different conductive materials. In some embodiments, the thickness of the first conductive layer 36 is greater than the thickness of the second conductive layer 37.

[0040] Figure 2 Shown is a cross-sectional view of the semiconductor structure 20 according to certain embodiments of the present case. Specifically, the semiconductor structure 20 is a trench MOS rectifier device structure and has a vertical current conduction path. For example, the current of the semiconductor structure 20 can conduct vertically through the semiconductor structure 20. As Figure 2 shown, the semiconductor structure 20 has a similar Figure 1 semiconductor structure 10 as shown, except for the shapes of the first polysilicon structure 211 and the second polysilicon structure 221.

[0041] In some embodiments, the first polysilicon structure 211 is a stepped structure. In some embodiments, the first polysilicon structure 211 is a stepped structure that is wider at the top and narrower at the bottom, and the width of the first polysilicon structure 211 has a tendency to decrease from the first surface 11A to the second surface 11B in the vertical direction Z. In some embodiments, the first polysilicon structure 211 includes a first portion 211a and a second portion 211b connected to the first portion 211a. The width of the second portion 211b is greater than the width of the first portion 211a, and the first portion 211a and the second portion 211b form a stepped structure. The first portion 211a and the second portion 211b of the first polysilicon structure 211 are surrounded by the sidewall portion 212b of the first oxide layer 212. In some embodiments, by adjusting the shape or structure of the sidewall portion 212b of the first oxide layer 212, the electric field distribution in the epitaxial layer 112 can be changed, so that the semiconductor structure 10 has a higher breakdown voltage, or the semiconductor structure 10 can reach a similar breakdown voltage with a lower epitaxial concentration.

[0042] The structure of the sidewall portion 212b of the first oxide layer 212 can be adjusted according to the structure of the first polysilicon structure 211 or the operating voltage. For example, the sidewall portion 212b of the first oxide layer 212 also has a stepped structure. In some embodiments, corresponding to the stepped structure of the first polysilicon structure 211 that is wider at the top and narrower at the bottom, the sidewall portion 212b of the first oxide layer 212 is a stepped configuration that is narrower at the top and wider at the bottom, and the width of the sidewall portion 212b of the first oxide layer 212 has a tendency to increase from the first surface 11A to the second surface 11B in the vertical direction Z.

[0043] In some embodiments, the first doped region 31 has a first lower peripheral edge 31p, the first oxide layer 212 has a second lower peripheral edge 212p, the first portion 211a of the first polysilicon structure 211 has a fourth lower peripheral edge 211d, and the second portion 211b of the first polysilicon structure 211 has a fifth lower peripheral edge 211e. The first lower peripheral edge 31p, the second lower peripheral edge 212p, the fourth lower peripheral edge 211d, and the fifth lower peripheral edge 211e are configured to withstand the reverse voltage of the semiconductor structure 20. The horizontal height of the fifth lower peripheral edge 211e is higher than the horizontal height of the fourth lower peripheral edge 211d, the horizontal height of the fourth lower peripheral edge 211d is higher than the horizontal height of the second lower peripheral edge 212p, and the horizontal height of the second lower peripheral edge 212p is higher than the horizontal height of the first lower peripheral edge 31p.

[0044] Figure 3 Shown is a graph of the relationship between the depth and the electric field of the semiconductor structure 20 according to certain embodiments of the present case. As Figure 2 and Figure 3As shown, in some embodiments, the depth of the first lower peripheral edge 31p is greater than that of the second lower peripheral edge 212p, the depth of the second lower peripheral edge 212p is greater than that of the fourth lower peripheral edge 211d, and the depth of the fourth lower peripheral edge 211d is greater than that of the fifth lower peripheral edge 211e. When energized, the peak value of the electric field E1 of the first lower peripheral edge 31p is greater than the peak value of the electric field E2 of the second lower peripheral edge 212p, the peak value of the electric field E2 of the second lower peripheral edge 212p is greater than the peak value of the electric field E4 of the fourth lower peripheral edge 211d, and the peak value of the electric field E4 of the fourth lower peripheral edge 211d is greater than the peak value of the electric field E5 of the fifth lower peripheral edge 211e. In short, the deeper the lower peripheral edge is located in the epitaxial layer 112 relative to the first surface 11A, the higher the electric field. Through the configuration and configuration of the first polysilicon structure 211, the first oxide layer 212 and the first doped region 31 in this case, the semiconductor structure 20 has a high breakdown voltage.

[0045] Please refer to Figure 2 . In some embodiments, the second polysilicon structure 221 is a stepped structure. In some embodiments, the second polysilicon structure 221 is a stepped structure that is wider at the top and narrower at the bottom, and the width of the second polysilicon structure 221 has a tendency to decrease along the vertical direction Z from the first surface 11A to the second surface 11B. In some embodiments, the second polysilicon structure 221 includes a first portion 221a and a second portion 221b connected to the first portion 221a. The width of the second portion 221b is greater than the width of the first portion 221a, and the first portion 221a and the second portion 221b form a stepped structure. The first portion 221a and the second portion 211b of the second polysilicon structure 221 are surrounded by the sidewall portion 222b of the second oxide layer 222.

[0046] The structure of the sidewall portion 222b of the second oxide layer 222 can be adjusted according to the structure of the second polysilicon structure 221 or the operating voltage. For example, the sidewall portion 222b of the second oxide layer 222 also has a stepped structure. In some embodiments, corresponding to the stepped structure of the second polysilicon structure 221 that is wider at the top and narrower at the bottom, the sidewall portion 222b of the second oxide layer 222 is a stepped configuration that is narrower at the top and wider at the bottom, and the width of the sidewall portion 222b of the second oxide layer 222 has a tendency to increase along the vertical direction Z from the first surface 11A to the second surface 11B. The electrical distribution in the epitaxial layer 112 can be adjusted by adjusting the shape or structure of the sidewall portion 222b of the second oxide layer 222, so that the semiconductor structure 10 has a higher breakdown voltage, or a similar breakdown voltage can be achieved through a lower epitaxial concentration.

[0047] In some embodiments, the second doped region 32 has a sixth lower peripheral edge 32p, the second oxide layer 222 has a seventh lower peripheral edge 222p, a first portion 221a of the second polysilicon structure 221 has a ninth lower peripheral edge 221d, and a second portion 221b of the second polysilicon structure 221 has a tenth lower peripheral edge 221e. The sixth lower peripheral edge 32p, the seventh lower peripheral edge 222p, the ninth lower peripheral edge 221d, and the tenth lower peripheral edge 221e are configured to withstand the reverse voltage of the semiconductor structure 20. The horizontal height of the tenth lower peripheral edge 221e is higher than the horizontal height of the ninth lower peripheral edge 221d, the horizontal height of the ninth lower peripheral edge 221d is higher than the horizontal height of the seventh lower peripheral edge 222p, and the horizontal height of the seventh lower peripheral edge 222p is higher than the horizontal height of the sixth lower peripheral edge 32p.

[0048] In some embodiments, the depth of the sixth lower peripheral edge 32p is greater than the depth of the seventh lower peripheral edge 222p, the depth of the seventh lower peripheral edge 222p is greater than the depth of the ninth lower peripheral edge 221d, and the depth of the ninth lower peripheral edge 221d is greater than the depth of the tenth lower peripheral edge 221e. When powered on, the electric field of the sixth lower peripheral edge 32p is greater than the electric field of the seventh lower peripheral edge 222p, the electric field of the seventh lower peripheral edge 222p is greater than the electric field of the ninth lower peripheral edge 221d, and the electric field of the ninth lower peripheral edge 221d is greater than the electric field of the tenth lower peripheral edge 221e. The relationship between the electric fields of the foregoing sixth lower peripheral edge 32p, seventh lower peripheral edge 222p, ninth lower peripheral edge 221d, and tenth lower peripheral edge 221e is similar to the relationship between the depths and electric fields as Figure 3 shown, where the deeper the depth of the lower peripheral edge in the epitaxial layer 112 relative to the first surface 11A, the higher the electric field.

[0049] Figures 4 to 19 Shown are one or more stages in a method of manufacturing a semiconductor structure according to certain embodiments of the present disclosure. At least some of these figures have been simplified for a better understanding of aspects of the present disclosure.

[0050] Referring to Figure 4 , the substrate 11 may include a substrate material 111 and an epitaxial layer 112 located on the substrate material 111. The manufacturing method includes epitaxial growth of the substrate material 111 to form the epitaxial layer 112. The epitaxial layer 112 has a first surface 11A of the substrate 11, and the substrate material 111 has a second surface 11B of the substrate 11, and the first surface 11A and the second surface 11B are opposite to each other. In some embodiments, ion implantation is performed simultaneously during epitaxial growth by implanting ions with N-type electrical properties to form an N-type epitaxial layer 112.

[0051] Referring to Figure 5, a first patterned mask layer 113 is formed on the epitaxial layer 112 to define the position of the third doped region 33. The first patterned mask layer 113 has a first opening 41, and the manufacturing method includes forming the third doped region 33 on the first surface 11A exposed by the first opening 41. The third doped region 33 can be formed by diffusion or ion implantation process from the first surface 11A. In some embodiments, the third doped region 33 extends in the first direction X. After the ion implantation process, an annealing process is performed to diffuse the doped ions. The doped ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In some embodiments, boron ions are implanted into the third doped region 33, and after the third doped region 33 is formed, the first patterned mask layer 113 is removed.

[0052] Referring to Figure 6 , a second patterned mask layer 114 is formed on the epitaxial layer 112 and the third doped region 33 to define the positions of the first trench 210 and the second trench 220, and the epitaxial layer 112 is etched (such as plasma dry etching process) through the second patterned mask layer 114 to form the first trench 210 and the second trench 220. The third doped region 33 is located between the first trench 210 and the second trench 220. The etching process removes the epitaxial layer 112 from the first surface 11A and stops in the epitaxial layer 112. According to the position of the second patterned mask layer 114, the first trench 210 and the second trench 220 are formed at intervals in the substrate 11 along the first direction X and extend from the first surface 11A to the second surface 11B relative to the first surface 11A. After the first trench 210 and the second trench 220 are formed, the second patterned mask layer 114 is removed.

[0053] In some embodiments, the first trench 210 and the second trench 220 may have vertical sidewalls. The first trench 210 and the second trench 220 may have an arc-shaped bottom surface. In addition, the first trench 210 and the second trench 220 may be circular, elliptical, rectangular or polygonal. In some embodiments, the first trench 210 and the second trench 220 have the same width. In some embodiments, the first trench 210 and the second trench 220 have the same depth.

[0054] Referring to Figure 7 , Figure 8 and Figure 9, the manufacturing method includes forming a third patterned shielding layer 115 on the epitaxial layer 112 and the third doped region 33, and in the first trench 210 and the second trench 220, for defining the positions of the first doped region 31 and the second doped region 32. The third patterned shielding layer 115 has a second opening 42 and a third opening 43. The second opening 42 is formed in the first trench 210 to expose a part of the epitaxial layer 112, and the third opening 42 is formed in the second trench 220 to expose a part of the epitaxial layer 112. The manufacturing method includes forming a first doped region 31 in the substrate 11, the first doped region 31 being adjacent to the bottom of the first trench 210, and includes forming a second doped region 32 in the substrate 11, the second doped region 32 being adjacent to the bottom of the second trench 220.

[0055] The first doped region 31 can be formed by diffusion or ion implantation from the second opening 42. The second doped region 32 can be formed by diffusion or ion implantation from the third opening 43. The first doped region 31 and the second doped region 32 can be formed simultaneously. The first doped region 31 and the second doped region 32 extend in the first direction X. An annealing process is performed after the ion implantation process to diffuse the doped ions. In some embodiments, the doped ions are, for example, boron ions, aluminum ions, gallium ions, indium ions, etc. In some embodiments, boron ions are implanted into the first doped region 31 and the second doped region 32. In some embodiments, the third doped region 33 is formed before the first doped region 31 and the second doped region 32 are formed. As Figure 9 shown, after the first doped region 31 and the second doped region 32 are formed, the third patterned shielding layer 115 is removed.

[0056] Referring to Figure 10 , the manufacturing method includes forming a first trench inner oxide layer 231 in the first trench 210 and the second trench 220. The first trench inner oxide layer 231 covers the first surface 11A. The first trench inner oxide layer 231 can be formed by thermal oxidation technology or other deposition processes. The first trench inner oxide layer 231 can be conformally or coplanarly deposited on the inner surfaces (including the opposite sidewalls and the bottom extending between the sidewalls) of the first trench 210 and the second trench 220. In some embodiments, the first trench inner oxide layer 231 can be filled into the first trench 210 and the second trench 220 by a deposition process, so that the first trench inner oxide layer 231 covers at least the first doped region 31 and the second doped region 32 in the first trench 210 and the second trench 220 respectively. In some embodiments, the first trench inner oxide layer 231 includes silicon oxide.

[0057] Referring to Figure 11, the first trench inner oxide layer 231 outside the first trench 210 and the second trench 220 and the first trench inner oxide layer 231 in part of the first trench 210 and the second trench 220 are removed by methods such as dry etching, other etching, etc., to form a bottom 212a in the first trench 210 and a bottom 222a in the second trench 220. The etching process is, for example, a dry etching process and will stop at a predetermined depth in the first trench 210 and the second trench 220. In some embodiments, the bottom 212a and the bottom 222a are formed simultaneously.

[0058] Referring to Figure 12 , the manufacturing method includes forming a second trench inner oxide layer 232 in the first trench 210 and the second trench 220. The second trench inner oxide layer 232 covers the first surface 11A and is located on the bottom 212a and the bottom 222a. The second trench inner oxide layer 232 can be conformally or coplanarly deposited on the inner surfaces of the first trench 210 and the second trench 220 and on the bottom 212a and the bottom 222a. In some embodiments, the second trench inner oxide layer 232 can be formed by thermal oxidation technology or other deposition processes. In some embodiments, the second trench inner oxide layer 232 can be filled into the first trench 210 and the second trench 220 via a deposition process, so that the second trench inner oxide layer 232 forms a groove 218 in the first trench 210 and a groove 228 in the second trench 220. In some embodiments, the second trench inner oxide layer 232 includes silicon oxide.

[0059] Referring to Figure 13 , the manufacturing method includes forming a first protective layer 233 in the groove 218 and a second protective layer 234 in the groove 228. The first protective layer 233 is formed on the bottom 212a, and the second protective layer 234 is formed on the bottom 222a. The first protective layer 233 and the second protective layer 234 have different etching selectivity ratios from the second trench inner oxide layer 232. The first protective layer 233 and the second protective layer 234 can be filled into the groove 218 and the groove 228 respectively via a deposition process. In some embodiments, the first protective layer 233 and the second protective layer 234 are formed simultaneously.

[0060] In some embodiments, the first protective layer 233 and the second protective layer 234 include silicon nitride. The first protective layer 233 may be conformally or coplanarly deposited on a part of the inner surface of the groove 218, and a part of the inner surface of the groove 218 is not in contact with the first protective layer 233. In some embodiments, the first protective layer 233 contacts a part of the sidewalls of the groove 218 and the bottom extending between the sidewalls, and a part of the sidewalls of the groove 218 is exposed from the first protective layer 233. The second protective layer 234 may be conformally or coplanarly deposited on a part of the inner surface of the groove 228, and a part of the inner surface of the groove 228 is not in contact with the second protective layer 234. In some embodiments, the second protective layer 234 contacts a part of the sidewalls of the groove 228 and the bottom extending between the sidewalls, and a part of the sidewalls of the groove 228 is exposed from the second protective layer 234.

[0061] Referring to Figure 14 , the manufacturing method includes removing the second trench inner oxide layer 232 that is not in contact with the first protective layer 233 or the second protective layer 234. The aforementioned part of the second trench inner oxide layer 232 is removed by methods such as etching to form the first sidewall 212c in the first trench 210 and the second sidewall 212c in the second trench 220. In some embodiments, the first sidewall 212c is coplanar with the top of the first protective layer 233, and the second sidewall 212c is coplanar with the top of the second protective layer 234. In some embodiments, the first sidewall 212c and the second sidewall 212c are formed simultaneously.

[0062] Referring to Figure 15 , the manufacturing method includes removing the first protective layer 233 and the second protective layer 234. The first protective layer 233 and the second protective layer 234 are removed after the first sidewall 212c and the second sidewall 212c are formed, exposing a part of the bottom 212a and a part of the bottom 222a.

[0063] Referring to Figure 16 , the manufacturing method includes forming a third trench inner oxide layer 235 in the first trench 210 and the second trench 220. The third trench inner oxide layer 235 covers the first surface 11A and is located on the first sidewall 212c and the second sidewall 212c. The third trench inner oxide layer 235 can be formed by thermal oxidation technology or other deposition processes. In some embodiments, the third trench inner oxide layer 235 can be conformally or coplanarly deposited on the inner surfaces of the first trench 210 and the second trench 220 and contact the top surfaces of the first sidewall 212c and the second sidewall 212c. In some embodiments, the third trench inner oxide layer 235 can be filled into the first trench 210 and the second trench 220 through a deposition process, forming a space 219 in the first trench 210 and a space 229 in the second trench 220. In some embodiments, the third trench inner oxide layer 235 includes silicon oxide.

[0064] In some embodiments, the thickness of the third trench inner oxide layer 235 is less than the thickness of the first sidewall 212c. The thickness of the third trench inner oxide layer 235 is less than the thickness of the second sidewall 212c. The spaces 219 and 229 have stepped sidewalls.

[0065] Referring to Figure 17 , the manufacturing method includes forming a first polysilicon structure 211 in a first trench 210 and forming a second polysilicon structure 221 in a second trench 220. The manufacturing method includes forming a first polysilicon structure 211 in the space 219 and forming a second polysilicon structure 221 in the space 229. In some embodiments, in the first trench 210, the first polysilicon structure 211 is formed on the bottom 212a and is surrounded by the first sidewall 212c and the third trench inner oxide layer 235. In some embodiments, in the second trench 220, the second polysilicon structure 221 is formed on the bottom 222a and is surrounded by the second sidewall 222c and the third trench inner oxide layer 235.

[0066] The first polysilicon structure 211 and the second polysilicon structure 221 can be formed by physical vapor deposition (PVD), such as sputtering or spraying. The first polysilicon structure 211 and the second polysilicon structure 221 can be formed by electroplating or CVD. The polysilicon material can cover the third trench inner oxide layer 235, and then a dry etching process is performed to remove the polysilicon material outside the first trench 210 and the second trench 220 by methods such as etching to form the first polysilicon structure 211 and the second polysilicon structure 221.

[0067] The shapes of the first polysilicon structure 211 and the second polysilicon structure 221 respectively correspond to the shapes of the spaces 219 and 229. In some embodiments, the spaces 219 and 229 have stepped sidewalls, and the first polysilicon structure 211 and the second polysilicon structure 221 also have stepped structures.

[0068] In some embodiments, the first polysilicon structure 211 includes a first portion 211a and a second portion 211b connected to the first portion 211a. The width of the second portion 211b is greater than the width of the first portion 211a, and the first portion 211a and the second portion 211b are integrally formed. In some embodiments, the second polysilicon structure 221 includes a first portion 221a and a second portion 221b connected to the first portion 221a. The width of the second portion 221b is greater than the width of the first portion 221a, and the first portion 221a and the second portion 221b are integrally formed.

[0069] Referring to Figure 18, the manufacturing method includes removing the third trench inner oxide layer 235 other than the first trench 210 and the second trench 220 by methods such as etching to form a first trench structure 21 and a second trench structure 22. The first trench structure 21 is formed in the first trench 210 and includes a first oxide layer 212 and a first polysilicon structure 211 surrounded by the first oxide layer 212. The second trench structure 22 is formed in the second trench 220 and includes a second oxide layer 222 and a second polysilicon structure 221 surrounded by the second oxide layer 222. In some embodiments, the first trench structure 21 and the second trench structure 22 are formed simultaneously. In some embodiments, the manufacturing method includes making the top surfaces of the first trench structure 21 and the second trench structure 22 coplanar with the first surface 11A.

[0070] In some embodiments, the third trench inner oxide layer 235 other than the first trench 210 and the second trench 220 is removed to form a third sidewall 212d in the first trench 210 and a fourth sidewall 212d in the second trench 220. In some embodiments, the third sidewall 212d and the fourth sidewall 212d are formed simultaneously. The top of the third sidewall 212d is coplanar with the first surface 11A, and the top of the fourth sidewall 212d is coplanar with the first surface 11A. The first sidewall 212c and the third sidewall 212d constitute a sidewall portion 212b of the first oxide layer 212, and the sidewall portion 212b and the bottom 212a constitute the first oxide layer 212. The sidewall portion 212b of the first oxide layer 212 has a stepped structure. The second sidewall 222c and the fourth sidewall 222d constitute a sidewall portion 222b of the second oxide layer 222, and the sidewall portion 222b and the bottom 222a constitute the second oxide layer 222. The sidewall portion 222b of the second oxide layer 222 has a stepped structure.

[0071] In some embodiments, if it is desired to form as Figure 1The semiconductor structure 10 shown, the manufacturing method includes making the top of the formed first sidewall 212d coplanar with the first surface 11A, the top of the second sidewall 212d coplanar with the first surface 11A, and omitting the steps of forming the first protective layer 233, the second protective layer 234, the third trench inner oxide layer 235, the third sidewall 212d, and the fourth sidewall 212d. The first polysilicon structure 211 is formed in the groove 218, and the second polysilicon structure 221 is formed in the groove 228. In some embodiments, the first polysilicon structure 211 formed in the groove 218 has a columnar structure, and the second polysilicon structure 221 formed in the groove 228 has a columnar structure. In some embodiments, after the first polysilicon structure 211 is formed in the groove 218 and the second polysilicon structure 221 is formed in the groove 228, the second trench inner oxide layer 232 other than the first trench 210 and the second trench 220 is removed to form the first trench structure 21 located in the first trench 210 and the second trench structure 22 located in the second trench 220.

[0072] Referring to Figure 19 , the manufacturing method includes forming a shielding metal layer 35 on the first trench structure 21, the second trench structure 22, and the first surface 11A, and making the shielding metal layer 35 contact the first trench structure 21 and the second trench structure 22. The manufacturing method further includes forming a first conductive layer 36 on the shielding metal layer 35, and forming a second conductive layer 37 on the second surface 12B.

[0073] The semiconductor structure 20 formed through the above steps can be Figure 2 substantially the same as the semiconductor structure 20 shown. The semiconductor structure 20 has a first doping region 31 and a second doping region 32 respectively disposed under the first trench structure 21 and the second trench structure 22, and a third doping region 33 between the first trench structure 21 and the second trench structure 22, achieving the effects of increasing the breakdown voltage and reducing the surface electric field.

[0074] According to the structure and process of the present disclosure described above, under the same purpose and concept, the steps in the above process can be adjusted or the order can be permuted to achieve the same or similar semiconductor structures.

[0075] In this document, spatial relative terms such as "below", "beneath", "lower", "above", "upper", "left", "right", etc. may be used for ease of description to describe the relationship of one component or feature to another or multiple other components or features as shown in the accompanying drawings. In addition to the orientation depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0076] As used herein, the terms "about", "substantially", "essentially" and "approximately" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of the given value or range. Ranges herein may be expressed as from one endpoint to another endpoint or as between two endpoints. All ranges disclosed herein include the endpoints unless otherwise specified. The term "substantially coplanar" may refer to a positional difference between two surfaces positioned along the same plane that is within a few micrometers (μm), such as within 10 μm, within 5 μm, within 1 μm or within 0.5 μm of being positioned along the same plane. When a numerical value or characteristic is referred to as being "substantially" the same, the term may refer to a value that is within ±10%, ±5%, ±1% or ±0.5% of the average value of the said value.

[0077] The foregoing outlines the features of several embodiments and the detailed aspects of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and structures so as to facilitate the implementation of the same or similar purposes and / or achieve the same or similar advantages of the embodiments presented herein. Such equivalent constructs do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and alterations can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate having a first surface and a second surface opposite to the first surface; a first trench structure extending from the first surface towards the second surface, wherein the first trench structure includes a first polysilicon structure and a first oxide layer shielding metal layer surrounding the first polysilicon structure, located on the first surface of the substrate and covering the first trench structure; a first conductive layer is disposed on the shielding metal layer; and a second conductive layer is disposed on the second surface of the substrate, wherein a first doped region is included in the substrate between the first surface and the second surface, adjacent to the first oxide layer and separated from the first polysilicon structure.

2. The semiconductor structure according to claim 1, wherein the first oxide layer includes a bottom wall portion and a side wall portion, and the thickness of the bottom wall portion is greater than the thickness of the side wall portion.

3. The semiconductor structure according to claim 1, wherein at least a portion of the first oxide layer is located between the first polysilicon structure and the first doped region.

4. The semiconductor structure according to claim 1, wherein the first doped region has a first lower peripheral edge, the first oxide layer has a second lower peripheral edge, the first polysilicon structure has a third lower peripheral edge, and the first lower peripheral edge, the second lower peripheral edge, and the third lower peripheral edge are configured to withstand the reverse voltage of the semiconductor structure.

5. The semiconductor structure according to claim 1, wherein the first doped region is located between the first oxide layer and the second surface.

6. The semiconductor structure according to claim 1, wherein the first polysilicon structure includes a first portion and a second portion connected to the first portion, the width of the second portion is greater than the width of the first portion, and the first portion and the second portion form a stepped structure.

7. The semiconductor structure according to claim 6, wherein the first doped region has a first lower peripheral edge, the first oxide layer has a second lower peripheral edge, the first portion of the first polysilicon structure has a fourth lower peripheral edge, the second portion of the first polysilicon structure has a fifth lower peripheral edge, and the first lower peripheral edge, the second lower peripheral edge, the fourth lower peripheral edge, and the fifth lower peripheral edge are configured to withstand the reverse voltage of the semiconductor structure.

8. The semiconductor structure according to claim 1, wherein the substrate includes silicon carbide.

9. The semiconductor structure according to claim 1, which further comprises: a second trench structure extending from the first surface towards the second surface, wherein the second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure; wherein a second doped region and a third doped region are further included in the substrate, the second doped region is disposed between the first surface and the second surface, adjacent to the second oxide layer and separated from the second polysilicon structure, the third doped region is disposed between the first trench structure and the second trench structure, and the top surface of the second polysilicon structure and the top surface of the second oxide layer are coplanar with the first surface.

10. The semiconductor structure according to claim 9, wherein the third doped region extends from the first surface toward the second surface.

11. The semiconductor structure according to claim 9, wherein the distance between the first doped region and the first surface is greater than the distance between the third doped region and the first surface, and the distance between the second doped region and the first surface is greater than the distance between the third doped region and the first surface.

12. A method for manufacturing a semiconductor structure, characterized in that, comprising: forming first trenches and second trenches spaced apart in a substrate from a first surface toward a second surface opposite to the first surface; forming a first oxide layer in the first trench; forming a second oxide layer in the second trench; forming a first polysilicon structure in the first trench and surrounded by the first oxide layer to form a first trench structure; and forming a second polysilicon structure in the second trench and surrounded by the second oxide layer to form a second trench structure.

13. The manufacturing method according to claim 12, further comprising: forming a first doped region in the substrate, the first doped region being adjacent to the bottom of the first trench; and forming a second doped region in the substrate, the second doped region being adjacent to the bottom of the second trench.

14. The manufacturing method according to claim 13, further comprising: forming a third doped region in the substrate, the third doped region being adjacent to the first surface and located between the first trench and the second trench.

15. The manufacturing method according to claim 14, wherein, the third doped region is formed before forming the first doped region and the second doped region.

16. The manufacturing method according to claim 12, wherein forming the first oxide layer in the first trench further comprises: forming a bottom portion in the first trench; forming a sidewall portion in the first trench and on the bottom portion.

17. The manufacturing method according to claim 16, wherein the sidewall portion and the bottom portion jointly define a space, and the first polysilicon structure is formed in the space.

18. The manufacturing method according to claim 17, wherein the space has a stepped structure, such that the first polysilicon structure formed in the space also has a stepped structure.

19. The manufacturing method according to claim 12, wherein the first trench structure and the second trench structure are formed simultaneously.

20. The manufacturing method according to claim 12, further comprising: forming a shielding metal layer on the first trench structure and the second trench structure, and forming a conductive layer on the shielding metal layer.

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