Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device

Abstract

The invention provides a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device, in a trench gate type silicon carbide semiconductor device, a main region and a main electrode can be in ohmic contact, and leakage current between a source electrode and a drain electrode can be suppressed. The method includes: forming a second conductivity type base region on an upper surface side of a first conductivity type drift layer formed of silicon carbide; forming a main region of the first conductivity type on the upper surface side of the base region; forming a groove penetrating through the main region and the base region; a gate electrode embedded inside the trench via a gate insulating film; and forming a main electrode in contact with the main region, in which the step of forming the main region includes: forming a first region including a 4H structure by performing ion implantation of a first conductivity type impurity at room temperature; and forming a second region including the 3C structure by performing ion implantation of at least any one of silicon, carbon, and argon at room temperature.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device. Background Art

[0002] Patent Document 1 discloses the following semiconductor device: an amorphous layer is formed by ion-implanting phosphorus into a hexagonal single-crystal silicon carbide substrate, and the amorphous layer is recrystallized into a cubic single-crystal n-type silicon carbide by performing heat treatment, and an electrode is formed by vapor-depositing nickel on the upper surface of the n-type silicon carbide.

[0003] Patent Document 2 discloses the following semiconductor device: in an n-type epitaxial growth layer formed on a first main surface of n-type SiC formed of 4H-SiC, an n-type source region, an n-type 3C-SiC region formed in the n-type source region, and a p-type potential fixing region are provided. A barrier metal film is formed in contact with the n-type 3C-SiC region and the p-type potential fixing region, and an electrode for source wiring is formed on the barrier metal film. + , + , + , - , + , + , + , + type SiC, an n - type epitaxial growth layer, an n + type source region, and an n + type source region, an n + type 3C-SiC region and a p + type potential fixing region, and a barrier metal film is formed in contact with the n + type 3C-SiC region and the p + type potential fixing region, and an electrode for source wiring is formed on the barrier metal film.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-49198

[0007] Patent Document 2: International Publication No. 2017 / 042963 Summary of the Invention

[0008] Problems to be Solved by the Invention

[0009] In a trench gate type silicon carbide semiconductor device, it has been studied to form a source region (main region) of 3C-SiC for ohmic contact with a source electrode (main electrode). However, compared with 4H-SiC, 3C-SiC has more crystal defects and larger surface irregularities, so there is a possibility of leakage current (Idss) flowing between the source and the drain.

[0010] In view of the above problems, an object of the present disclosure is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device that can achieve ohmic contact between the main region and the main electrode and suppress leakage current between the source and the drain in a trench gate type silicon carbide semiconductor device.

[0011] Solutions to Solve the Problems

[0012] In order to achieve the above object, the gist of one aspect of the present disclosure is a method for manufacturing a silicon carbide semiconductor device, including the following steps: forming a base region of a second conductivity type formed of silicon carbide on the upper surface side of a drift layer of a first conductivity type formed of silicon carbide; forming a main region of a first conductivity type formed of silicon carbide on the upper surface side of the base region; forming a trench penetrating the main region and the base region; forming a gate insulating film inside the trench; burying a gate electrode inside the trench with the gate insulating film interposed therebetween; and forming a main electrode in contact with the main region, wherein the step of forming the main region includes: forming a first region including a 4H structure on the upper surface side of the base region by ion-implanting an impurity of a first conductivity type at room temperature; and forming a second region including a 3C structure on the upper surface side of the first region in contact with the main electrode by ion-implanting at least any one of silicon, carbon, and argon at room temperature.

[0013] The gist of another aspect of the present disclosure is a silicon carbide semiconductor device including: a drift layer of a first conductivity type formed of silicon carbide; a base region of a second conductivity type provided on the upper surface side of the drift layer and formed of silicon carbide; a main region of a first conductivity type provided on the upper surface side of the base region and formed of silicon carbide; a gate insulating film provided inside a trench penetrating the main region and the base region; a gate electrode buried inside the trench with the gate insulating film interposed therebetween; and a main electrode provided in contact with the main region, wherein the main region includes: a first region provided on the upper surface side of the base region and including a 4H structure; and a second region provided in contact with the main electrode on the upper surface side of the first region, and the ratio of the 3C structure on at least the upper surface side of the second region is 70% or more.

[0014] Effects of the Invention

[0015] According to the present disclosure, it is possible to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device that can achieve ohmic contact between a main region and a main electrode and can suppress leakage current between a source and a drain in a trench gate type silicon carbide semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic cross-sectional view showing an example of a silicon carbide semiconductor device according to the first embodiment.

[0017] Figure 2 is Figure 1 a schematic cross-sectional view in which the region A in

[0018] Figure 3 is a schematic cross-sectional view of a silicon carbide semiconductor device according to a comparative example.

[0019] Figure 4 is a flowchart of a method for manufacturing a silicon carbide semiconductor device according to the first embodiment.

[0020] Figure 5 It is a cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment.

[0021] Figure 6 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 5 after that.

[0022] Figure 7 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 6 after that.

[0023] Figure 8 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 7 after that.

[0024] Figure 9 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 8 after that.

[0025] Figure 10 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 9 after that.

[0026] Figure 11 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 10 after that.

[0027] Figure 12 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 11 after that.

[0028] Figure 13 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 12 after that.

[0029] Figure 14 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 13 after that.

[0030] Figure 15 It is a subsequent cross-sectional schematic diagram showing an example of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment. Figure 14Subsequent cross-sectional schematic diagram.

[0031] Figure 16 It is a flowchart of a method for manufacturing a silicon carbide semiconductor device according to a second embodiment.

[0032] Figure 17 It is a flowchart of a method for manufacturing a silicon carbide semiconductor device according to a third embodiment. Detailed implementation manners

[0033] Hereinafter, the first to third embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may sometimes be different from the actual ones. In addition, there may also be parts with different dimensional relationships and ratios between the drawings. In addition, the first to third embodiments shown below exemplify devices and methods for embodying the technical idea of the present disclosure, and the technical idea of the present disclosure does not specify the material, shape, structure, configuration, etc. of the structural components as the following material, shape, structure, configuration, etc.

[0034] In this specification, the source region of a metal-oxide-semiconductor field-effect transistor (MOSFET) is the "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In addition, in thyristors such as a MOS-controlled static induction thyristor (SI thyristor), the "one main region" can be selected as the cathode region. The drain region of the MOSFET is the "other main region (second main region)" of the semiconductor device that can be selected as the collector region in the IGBT and as the anode region in the thyristor. When only referred to as the "main region" in this specification, it means either the first main region or the second main region that is appropriate according to the technical common sense of those skilled in the art.

[0035] In addition, the definitions of directions such as up and down in the following description are only for convenience of explanation and are not used to limit the technical idea of the present disclosure. For example, if the object is rotated by 90° for observation, then up and down are changed to left and right for reading, and if the object is rotated by 180° for observation, then up and down are flipped for reading, which is self-evident. In addition, the "upper surface" can also be read as the "surface", and the "lower surface" can also be read as the "back surface".

[0036] In addition, in the following description, a case where the first conductivity type is n-type and the second conductivity type is p-type is illustratively described. However, the conductivity types can also be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. In addition, the + and - attached to n and p indicate semiconductor regions in which the impurity concentrations are relatively high or relatively low, respectively, compared to the semiconductor regions to which + and - are not attached. However, even for semiconductor regions labeled with the same n and n, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0037] In addition, SiC crystals exist in polytypes, mainly cubic 3C and hexagonal 4H, 6H. Regarding the bandgap width at room temperature, a value of 2.23 eV has been reported for 3C-SiC, a value of 3.26 eV for 4H-SiC, and a value of 3.02 eV for 6H-SiC. In the following description, cases mainly using 4H-SiC and 3C-SiC are illustratively described.

[0038] (First Embodiment)

[0039] <Structure of SiC Semiconductor Device>

[0040] Regarding the SiC semiconductor device according to the first embodiment, as Figure 1 shown, a case where a trench gate type MOSFET is included as an active element is illustratively described. In addition, in Figure 1 , a unit cell including an insulated gate electrode structure (11, 12) buried in one trench 10 is illustratively described, but in reality, a large number of such unit cells are periodically arranged.

[0041] The SiC semiconductor device according to the first embodiment includes a drift layer 2 of the first conductivity type (n - -type). The drift layer 2 is formed of an epitaxial growth layer made of SiC such as 4H-SiC, for example. The impurity concentration of the drift layer 2 is, for example, 1×10 15 cm -3 or more and 5×10 16 cm -3 or less, approximately. The thickness of the drift layer 2 is, for example, 1 μm or more and 100 μm or less, approximately. The impurity concentration and thickness of the drift layer 2 can be appropriately adjusted according to the withstand voltage specifications and the like.

[0042] On the upper surface side of the drift layer 2, a current spreading layer (CSL) 3 of the first conductivity type (n-type) having an impurity concentration higher than that of the drift layer 2 is selectively provided. The lower surface of the current spreading layer 3 is in contact with the upper surface of the drift layer 2. The current spreading layer 3 is formed of an epitaxial growth layer made of SiC such as 4H-SiC, for example. The impurity concentration of the current spreading layer 3 is, for example, 5×10 16 cm -3 or more and 1×1018 cm -3 to the left and right below. In addition, it is not necessary to specifically provide the current diffusion layer 3. In the case where the current diffusion layer 3 is not provided, the drift layer 2 can be extended and provided up to the region of the current diffusion layer 3.

[0043] On the upper surface side of the current diffusion layer 3, base regions 6a and 6b of the second conductivity type (p-type) are provided. The lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the current diffusion layer 3. In addition, in the case where the current diffusion layer 3 is not provided, the lower surfaces of the base regions 6a and 6b are in contact with the upper surface of the drift layer 2. The base regions 6a and 6b are formed of an epitaxial growth layer made of SiC such as 4H-SiC, for example. The base regions 6a and 6b may also be regions obtained by ion-implanting p-type impurities into the current diffusion layer 3. The impurity concentration of the base regions 6a and 6b is, for example, 1×10 16 cm -3 or more and 1×10 18 cm -3 or less, approximately.

[0044] On the upper surface side of the base regions 6a and 6b, first main regions (source regions) 7a and 7b of the first conductivity type (n + -type) with an impurity concentration higher than that of the drift layer 2 are selectively provided. The source regions 7a and 7b are regions formed of SiC obtained by ion-implanting n-type impurities into the base regions 6a and 6b, for example.

[0045] The source region 7a has a double-layer structure including an n + -type source extension part (also referred to as "first region" or "4H-SiC layer") 71a containing a 4H structure (4H-SiC) as the lower layer, and an n + -type source contact part (also referred to as "second region" or "3C-SiC layer") 72a containing a 3C structure (3C-SiC) as the upper layer. The lower surface of the source extension part 71a is in contact with the upper surface of the base region 6a. The upper surface of the source extension part 71a is in contact with the lower surface of the source contact part 72a. The source region 7b has a double-layer structure including an n + -type source extension part (also referred to as "first region" or "4H-SiC layer") 71b containing a 4H structure (4H-SiC) as the lower layer, and an n + -type source contact part (also referred to as "second region" or "3C-SiC layer") 72b containing a 3C structure (3C-SiC) as the upper layer. The lower surface of the source extension part 71b is in contact with the upper surface of the base region 6b. The upper surface of the source extension part 71b is in contact with the lower surface of the source contact part 72b. Details of the source regions 7a and 7b will be described later.

[0046] A trench 10 penetrating the source regions 7a, 7b and the base regions 6a, 6b is provided in the normal direction (depth direction) from the upper surfaces of the source regions 7a, 7b toward the upper surfaces of the source regions 7a, 7b. The lower surface of the trench 10 reaches the current diffusion layer 3. The width of the trench 10 is, for example, about 1 μm or less. The source region 7a and the base region 6a are in contact with the left side surface of the trench 10. The source region 7b and the base region 6b are in contact with the right side surface of the trench 10. The trench 10 may have a planar pattern extending in a strip shape in the depth direction and the front direction of the paper surface of Figure 1 or may have a dot-like planar pattern.

[0047] A gate insulating film 11 is provided along the lower surface and the side surfaces on both sides of the trench 10. A gate electrode 12 is buried inside the trench 10 with the gate insulating film 11 interposed therebetween. The gate insulating film 11 and the gate electrode 12 constitute a trench gate type insulated gate electrode structure (11, 12).

[0048] As the gate insulating film 11, in addition to a silicon oxide film (SiO 2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si 3 N 4 ) film, an aluminum oxide (Al 2 O 3 ) film, a magnesium oxide (MgO) film, a yttrium oxide (Y 2 O 3 ) film, a hafnium oxide (HfO 2 ) film, a zirconium oxide (ZrO 2 ) film, a tantalum oxide (Ta 2 O 5 ) film, a bismuth oxide (Bi 2 O 3 ) film, a single-layer film of any one of them, or a composite film obtained by laminating a plurality of them can be used. As the material of the gate electrode 12, for example, a polysilicon layer (doped polysilicon layer) doped with a p-type impurity or an n-type impurity at a high impurity concentration, a high melting point metal such as titanium (Ti), tungsten (W), or nickel (Ni) can be used.

[0049] A gate bottom protection region 4b of the second conductivity type (p + type) is provided inside the current diffusion layer 3 and at the bottom of the trench 10. The upper surface of the gate bottom protection region 4b is in contact with the lower surface of the trench 10. The upper surface of the gate bottom protection region 4b may not be in contact with the lower surface of the trench 10. The impurity concentration of the gate bottom protection region 4b is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less.

[0050] Inside the current diffusion layer 3, a first buried region 4a, 4c of the second conductivity type (p + type) is provided separately from the gate bottom protection region 4b. The first buried regions 4a, 4c are provided at a depth similar to that of the gate bottom protection region 4b. The impurity concentration of the first buried regions 4a, 4c is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less, approximately. The first buried regions 4a, 4c and the gate bottom protection region 4b are, for example, regions formed of SiC obtained by ion-implanting p-type impurities into the current diffusion layer 3. In addition, a p Figure 1 type connection portion that connects the first buried regions 4a, 4c and the gate bottom protection region 4b may be selectively provided on the near front side or the depth side of the paper surface of + .

[0051] On the upper part of the current diffusion layer 3 and on the upper surface side of the first buried regions 4a, 4c, second buried regions 5a, 5b of the second conductivity type (p-type) are provided. The second buried regions 5a, 5b electrically connect the first buried regions 4a, 4c and the base regions 6a, 6b. The lower surface of the second buried regions 5a, 5b abuts on the upper surface of the first buried regions 4a, 4c. The side surfaces of the second buried regions 5a, 5b abut on the current diffusion layer 3 and the base regions 6a, 6b. The second buried regions 5a, 5b are, for example, regions formed of SiC obtained by ion-implanting p-type impurities into the current diffusion layer 3 and the base regions 6a, 6b. The impurity concentration of the second buried regions 5a, 5b may be of the same degree as that of the first buried regions 4a, 4c, or may be lower or higher than that of the first buried regions 4a, 4c. The impurity concentration of the second buried regions 5a, 5b is, for example, 1×10 17 cm -3 or more and 1×10 19 cm -3 or less, approximately.

[0052] On the upper surface side of the second buried regions 5a, 5b, base contact regions 8a, 8b of the p + type having an impurity concentration higher than that of the second buried regions 5a, 5b are provided. The base contact regions 8a, 8b are, for example, regions formed of SiC obtained by ion-implanting p-type impurities into the base regions 6a, 6b. The impurity concentration of the base contact regions 8a, 8b is, for example, 5×10 18 cm -3 or more and 5×10 20 cm -3 or less, approximately. The base contact regions 8a, 8b may be composed of 3C-SiC or 4H-SiC.

[0053] The lower surface of the base contact region 8a is in contact with the upper surface of the second buried region 5a, and the side surface of the base contact region 8a is in contact with the source extension 71a and the source contact portion 72a of the source region 7a. The side surface of the base contact region 8a may not necessarily be in contact with the source contact portion 72a. For example, a part of the source extension 71a may be provided between the side surface of the base contact region 8a and the source contact portion 72a. The lower surface of the base contact region 8b is in contact with the upper surface of the second buried region 5b, and the side surface of the base contact region 8b is in contact with the source extension 71b and the source contact portion 72b of the source region 7b. The side surface of the base contact region 8b may not necessarily be in contact with the source contact portion 72b. For example, a part of the source extension 71b may be provided between the side surface of the base contact region 8b and the source contact portion 72b.

[0054] The lower surfaces of the base contact regions 8a and 8b and the lower surfaces of the source extensions 71a and 71b of the source regions 7a and 7b are at the same depth level, but may also be shallower or deeper than the lower surfaces of the source extensions 71a and 71b of the source regions 7a and 7b. The upper surfaces of the second buried regions 5a and 5b may not be in contact with the lower surfaces of the p + -type base contact regions 8a and 8b. For example, base regions 6a and 6b may be provided between the second buried regions 5a and 5b and the p + -type base contact regions 8a and 8b.

[0055] An interlayer insulating film 13 is provided on the upper surface side of the gate electrode 12. The interlayer insulating film 13 is composed of, for example, a single-layer film such as a silicon oxide film doped with boron (B) and phosphorus (P) (BPSG film), a silicon oxide film doped with phosphorus (P) (PSG film), an undoped silicon oxide film called "NSG" that does not contain phosphorus (P) or boron (B), a silicon oxide film doped with boron (B) (BSG film), a silicon nitride film (Si 3 N 4 film), or a stacked film thereof. Contact holes 13a and 13b are provided in the interlayer insulating film 13 to expose the upper surfaces of the source contact portions 72a and 72b and the base contact regions 8a and 8b.

[0056] A first main electrode (source electrode) (14, 15) is provided so as to cover the interlayer insulating film 13 and the upper surfaces of the source contact portions 72a, 72b and the base region contact regions 8a, 8b exposed from the contact holes 13a, 13b of the interlayer insulating film 13. The source electrodes (14, 15) include a lower barrier metal layer 14 and an upper source wiring electrode 15. For example, the barrier metal layer 14 is made of a metal such as titanium nitride (TiN), titanium (Ti), or a stacked structure of TiN / Ti with Ti as the lower layer. The barrier metal layer 14 is directly connected to the source contact portions 72a, 72b and the base region contact regions 8a, 8b, and makes a low-resistance ohmic contact with the source contact portions 72a, 72b and the base region contact regions 8a, 8b.

[0057] The source wiring electrode 15 is electrically connected to the source regions 7a, 7b and the base region contact regions 8a, 8b via the barrier metal layer 14. The source wiring electrode 15 is provided separately from a gate wiring electrode (not shown) electrically connected to the gate electrode 12. The source wiring electrode 15 is made of a metal such as aluminum (Al), copper (Cu), aluminum-silicon (Al-Si), aluminum-copper (Al-Cu), or aluminum-silicon-copper (Al-Si-Cu).

[0058] On the lower surface side of the drift layer 2, a second main region (drain region) 1 of the first conductivity type (n + type) having an impurity concentration higher than that of the drift layer 2 is provided. The drain region 1 is made of, for example, a semiconductor substrate (SiC substrate) formed of 4H-SiC. The impurity concentration of the drain region 1 is, for example, 1×10 19 cm -3 or more and 3×10 20 cm -3 or less. The thickness of the drain region 1 is, for example, 30 μm or more and 500 μm or less. In addition, an n-type buffer layer, that is, a dislocation conversion layer and a recombination promotion layer, having an impurity concentration higher than that of the drift layer 2 and lower than that of the drain region 1 may be provided between the drift layer 2 and the drain region 1.

[0059] A second main electrode (drain electrode) 16 is provided on the lower surface side of the drain region 1. As the drain electrode 16, for example, a single-layer film formed of gold (Au), a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au from the drain region 1 side can be used, and a metal film such as molybdenum (Mo) or tungsten (W) can be further laminated on its lowermost layer. In addition, a drain contact layer such as a nickel silicide (NiSi x ) film for ohmic contact may be provided between the drain region 1 and the drain electrode 16.

[0060] In Figure 2 it shows that Figure 1The cross-section of the region A indicated by the dashed line, which includes the source extension 71a including the source region 7a, the source contact portion 72a, the gate insulating film 11, and the gate electrode 12, is magnified. Refer to Figure 2 to describe the structures of the source extension 71a and the source contact portion 72a, and the positional relationship between the source extension 71a and the source contact portion 72a and the gate electrode 12.

[0061] The source extension 71a is a region where the crystal defects are fewer than those of the source contact portion 72a and do not continue the crystal defects of the source contact portion 72a. The source extension 71a is mainly composed of 4H-SiC. The proportion of 4H-SiC contained in the source extension 71a is, for example, about 90% or more and 100% or less. In the source extension 71a, in addition to containing 4H-SiC, it may also slightly contain an amorphous structure, 3C-SiC, etc. As a method (observation method) for measuring the crystal structure of the source extension 71a and the source contact portion 72a, for example, the area ratio of the crystal structure on the surface can be measured by a field emission scanning electron microscope (FE-SEM) and electron backscatter diffraction (EBSD).

[0062] The depth d1 from the upper surface of the source contact portion 72a to the lower surface of the source extension 71a is, for example, about 200 nm or more and 450 nm or less. The thickness of the source extension 71a is, for example, about 150 nm or more and 400 nm or less. The impurity concentration of the source extension 71a is lower than that of the source contact portion 72a. The impurity concentration of the source extension 71a is, for example, 1×10 16 / cm 3 or more and 1×10 19 / cm 3 or less. The source extension 71a contains, for example, phosphorus (P), nitrogen (N), or arsenic (As) as n-type impurities. When the source contact portion 72a contains argon (Ar) as an inert element, the source extension 71a may also contain Ar on its upper surface side.

[0063] The source contact portion 72a is a region containing 3C-SiC. The source contact portion 72a may also be a mixed crystal of 3C-SiC and 4H-SiC. In the source contact portion 72a, in addition to containing 3C-SiC, it may also contain an amorphous structure, 4H-SiC, etc. The bandgap width of 3C-SiC is narrower than that of 4H-SiC. Therefore, by making the source contact portion 72a contain 3C-SiC, a low-resistance ohmic contact can be made with the source electrodes (14, 15).

[0064] Regarding the proportion of 3C-SiC contained in the source contact portion 72a, it is, for example, about 10% or more and 100% or less, or may be about 70% or more and 100% or less, or may also be about 85% or more and 100% or less, at least on the upper surface side of the source contact portion 72a. In order to achieve good ohmic contact with the source electrodes (14, 15), it is preferable that the proportion of 3C-SiC contained in the source contact portion 72a is 70% or more, and more preferably 85% or more.

[0065] The depth (thickness of the source contact portion 72a) d2 from the upper surface to the lower surface of the source contact portion 72a is, for example, about 30 nm or more and 100 nm or less. The impurity concentration of the source contact portion 72a is higher than that of the source extension portion 71a. The impurity concentration of the source contact portion 72a is, for example, 1×10 18 / cm 3 or more and 5×10 19 / cm 3 or less, approximately. The source contact portion 72a contains the same n-type impurity as the source extension portion 71a. The source contact portion 72a contains, for example, phosphorus (P), nitrogen (N), or arsenic (As) as the n-type impurity. The source contact portion 72a may also contain argon (Ar) as an inert element in addition to the n-type impurity.

[0066] Regarding the separate formation of the crystal structures of the source extension portion 71a and the source contact portion 72a, it can be achieved by separately changing the element to be ion-implanted, the temperature during ion implantation, the dose (impurity concentration), and the activation temperature, etc., for the source extension portion 71a and the source contact portion 72a.

[0067] As a method for forming the source extension portion 71a of the silicon carbide semiconductor device according to the first embodiment, the source extension portion 71a of 4H-SiC can be formed while maintaining 4H-SiC by ion-implanting an n-type impurity at a concentration that does not damage the structure of 4H-SiC at room temperature.

[0068] As a method for forming the source contact portion 72a of the silicon carbide semiconductor device according to the first embodiment, by ion-implanting argon (Ar) as a noble gas, or silicon (Si) or carbon (C) as a group IV element, without ion-implanting an n-type impurity into 4H-SiC at room temperature, the structure of 4H-SiC is damaged by the ion implantation to form an amorphous structure. Then, activation annealing is performed, and thus the amorphous structure becomes 3C-SiC during recrystallization, whereby the source contact portion 72a containing 3C-SiC can be formed.

[0069] As Figure 2As shown, the upper surface (upper end) 12a of the end portion of the gate electrode 12 in contact with the gate insulating film 11 is located deeper than the lower surface (lower end) 72x of the position of the source contact portion 72a in contact with the gate insulating film 11 and shallower than the lower surface (lower end) 71x of the position of the source extension portion 71a in contact with the gate insulating film 11. Further, it is also possible that the source contact portion 72a is separated from the gate insulating film 11, and a part of the source extension portion 71a is provided between the source contact portion 72a and the gate insulating film 11. In this case, the upper surface (upper end) 12a of the end portion of the gate electrode 12 in contact with the gate insulating film 11 may also be shallower than the lower surface (lower end) 72x of the source contact portion 72a on the side of the gate insulating film 11.

[0070] The upper surface 12a of the position of the gate electrode 12 in contact with the gate insulating film 11 may be the uppermost surface of the gate electrode 12. For example, in the case where the entire upper surface of the gate electrode 12 is a curved surface convex downward, the upper surface of the central portion of the gate electrode 12 may also be located deeper than the upper surface 12a of the end portion of the gate electrode 12.

[0071] The gate electrode 12 and the source extension portion 71a face each other across the gate insulating film 11. The gate electrode 12 and the source contact portion 72a do not face each other across the gate insulating film 11. The source contact portion 72a faces the interlayer insulating film 13 across the gate insulating film 11. The depression amount d0 of the gate electrode 12 starting from the upper surface of the source contact portion 72a is, for example, about 100 nm or more and 300 nm or less. The depression amount d0 of the gate electrode 12 and the position of the upper surface 12a of the position of the gate electrode 12 in contact with the gate insulating film 11 can be controlled, for example, by adjusting the etching conditions of the gate electrode 12.

[0072] Figure 1 The source extension portion 71b and the source contact portion 72b of the source region 7b shown are respectively the same structure as the source extension portion 71a and the source contact portion 72a of the source region 7a, so repeated descriptions are omitted. In addition, the positional relationship between the source extension portion 71b and the source contact portion 72b of the source region 7b and the gate electrode 12 is the same as the positional relationship between the source extension portion 71a and the source contact portion 72a of the source region 7a and the gate electrode 12, so repeated descriptions are omitted.

[0073] When the silicon carbide semiconductor device according to the first embodiment operates, when the source electrodes (14, 15) are set to the ground potential, a positive voltage is applied to the drain electrode 16, and a positive voltage equal to or higher than the threshold value is applied to the gate electrode 12, an inversion layer (channel) is formed on the side surfaces of the base regions 6a and 6b close to the trench 10, and the device becomes in an on state. In the on state, current flows from the drain electrode 16 through the drain region 1, the drift layer 2, the current diffusion layer 3, the inversion layers of the base regions 6a and 6b, and the source regions 7a and 7b to the source electrodes (14, 15). On the other hand, when the voltage applied to the gate electrode 12 is less than the threshold value, no inversion layer is formed in the base regions 6a and 6b, so the device becomes in an off state, and no current flows from the drain electrode 16 to the source electrodes (14, 15).

[0074] According to the silicon carbide semiconductor device according to the first embodiment, the source region 7a has a double-layer structure of a source extension portion 71a and a source contact portion 72a. The upper-layer source extension portion 71a in contact with the source electrodes (14, 15) contains 3C-SiC. Thus, without forming a silicide layer such as nickel (Ni) silicide, the source contact portion 72a can make a low-resistance ohmic contact with the source electrodes (14, 15). Therefore, problems such as peeling of the silicide layer can be suppressed compared with the case of forming a silicide layer.

[0075] In addition, as Figure 3 shown, assume a case where a source region 7x containing 3C-SiC is formed in a single-layer structure, and the source region 7x faces the gate electrode 12 across the gate insulating film 11. In this case, since the source region 7x contains 3C-SiC, the source region 7x can make an ohmic contact with the source electrodes (14, 15). However, since 3C-SiC has more crystal defects and larger surface irregularities than 4H-SiC, there may be a leakage current I1 flowing between the gate electrode 12 and the source region 7x.

[0076] In contrast, according to the silicon carbide semiconductor device according to the first embodiment, as Figure 2 shown, the upper surface 12a of the gate electrode 12 is deeper than the lower surface 72x of the source contact portion 72a and shallower than the lower surface 71x of the source extension portion 71a. Thus, the source extension portion 71a with fewer crystal defects in the source region 7a faces the gate electrode 12 across the gate insulating film 11, and the source contact portion 72a with more crystal defects in the source region 7a does not face the gate electrode 12 across the gate insulating film 11. Therefore, the occurrence of leakage current between the source region 7a and the gate electrode 12 can be suppressed.

[0077] <Manufacturing method of silicon carbide semiconductor device>

[0078] Next, an example of a method for manufacturing a silicon carbide semiconductor device according to the first embodiment will be described. In addition, the method for manufacturing a silicon carbide semiconductor device described below is an example, and as long as it is within the scope of the gist described in the claims, including its modified examples, it can be realized by various other manufacturing methods, which goes without saying. Figure 4 is a flowchart of a part of the process of the method for manufacturing a silicon carbide semiconductor device according to the first embodiment, and will be appropriately referred to in the following description Figure 4 for explanation.

[0079] First, a semiconductor substrate (SiC substrate) 1 formed of n-type 4H-SiC doped with an n-type impurity such as nitrogen (N) is prepared (refer to + ). The upper surface of the SiC substrate 1 has an inclination angle of, for example, 3 degrees or more and 8 degrees or less with respect to the {0001} plane. An epitaxial drift layer 2 formed of n-type 4H-SiC doped with N and other n-type impurities and having an impurity concentration lower than that of the SiC substrate 1 is grown on the upper surface of the SiC substrate 1 (refer to Figure 1 ). Then, as - shown, an n-type layer 3a formed of n-type 4H-SiC doped with N and other n-type impurities and having an impurity concentration higher than that of the drift layer 2 is grown on the upper surface of the drift layer 2. In addition, the n-type layer 3a can also be formed by ion-implanting an n-type impurity such as nitrogen (N) into the upper part of the drift layer 2. Figure 1 ) Figure 5 Next, an oxide film is deposited on the upper surface of the n-type layer 3a by a chemical vapor deposition (CVD) technique or the like. A photoresist film is coated on the upper surface of the oxide film, and the oxide film is patterned using a photolithography technique and a dry etching technique or the like. The patterned oxide film is used as a mask for ion implantation to selectively perform ion implantation of a p-type impurity such as aluminum (Al). In addition, a photoresist film can also be used instead of the oxide film as a mask for ion implantation. After that, the oxide film used as a mask for ion implantation is removed. As a result, as

[0080] shown, p-type first buried regions 4a, 4c and a p-type gate bottom protection region 4b are selectively formed on the upper part of the n-type layer 3a. Figure 6 Next, an n-type layer 3b formed of n-type 4H-SiC is grown on the upper surfaces of the n-type layer 3a, the first buried regions 4a, 4c, and the gate bottom protection region 4b (refer to + ). As a result, a current diffusion layer 3 formed of the n-type layer 3a and the n-type layer 3b is formed. Then, as + shown,

[0081] Next, an n-type layer 3b formed of n-type 4H-SiC is grown on the upper surfaces of the n-type layer 3a, the first buried regions 4a, 4c, and the gate bottom protection region 4b (refer to Figure 7 ). As a result, a current diffusion layer 3 formed of the n-type layer 3a and the n-type layer 3b is formed. Then, as Figure 7As shown, a base region 6 formed of p-type 4H-SiC is epitaxially grown on the upper surface of the current diffusion layer 3. The n-type layer 3b and the base region 6 may also be formed by ion implantation instead of epitaxial growth.

[0082] Next, an oxide film is deposited on the upper surface of the base region 6 by means of CVD technology or the like. A photoresist film is coated on the upper surface of the oxide film, and the oxide film is patterned using photolithography technology, dry etching technology, etc. The patterned oxide film is used as a mask for ion implantation to selectively perform ion implantation of p-type impurities such as aluminum (Al). In addition, a photoresist film may be used instead of the oxide film as a mask for ion implantation. After that, the oxide film used as a mask for ion implantation is removed. As a result, as Figure 8 shown, p-type second buried regions 5a and 5b are selectively formed on the upper surface sides of the first buried regions 4a and 4c.

[0083] Next, the Figure 4 step S11 of n + type source extension formation process is performed. In this n + type source extension formation process, an oxide film 21 (refer to Figure 9 ) is deposited on the upper surface of the base region 6 by means of CVD technology or the like. A photoresist film is coated on the upper surface of the oxide film 21, and the oxide film 21 is patterned using photolithography technology, dry etching technology, etc. The patterned oxide film 21 is used as a mask for ion implantation. As Figure 9 shown, ion implantation of n-type impurities such as phosphorus (P), nitrogen (N), or arsenic (As) is performed in a non-heated state at room temperature (RT). The room temperature is, for example, about 1°C or higher and 40°C or lower, and may also be about 15°C or higher and 30°C or lower. In addition, a photoresist film may be used instead of the oxide film 21 as a mask for ion implantation. As a result, an n + type source extension 71 is formed on the upper part of the base region 6.

[0084] When performing ion implantation for forming the source extension 71, in order to be less damaged compared to the ion implantation of the source contact portion 72 described later, as the n-type impurity, compared to As (atomic number 33) with a relatively large atomic weight, P (atomic number 15) with a relatively small atomic weight is preferred, and N (atomic number 7) with an even smaller atomic weight is more preferred.

[0085] The ion implantation for forming the source extension 71 can be performed in one step. When the P ion implantation is in one step, the acceleration energy is, for example, about 100 keV or higher and 140 keV or lower, and more preferably, it can be about 110 keV or higher and 130 keV or lower. When the ion implantation is in one step, the dose is, for example, 1×10 13 / cm 2 or higher and 5×1013 / cm 2 Preferably, it can be 3×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, preferably, it can be 2×10

[0086] The ion implantation for forming the source extension 71 can also be performed in two or more steps. For example, as the first ion implantation, the ion implantation of an n-type impurity such as P, N, or As is performed in a non-heated state at room temperature. Then, as the second ion implantation, the ion implantation of an n-type impurity such as P, N, or As is performed at a lower acceleration energy and dose than the first ion implantation in a non-heated state at room temperature. In the first ion implantation and the second ion implantation, the same n-type impurity can be implanted, or different n-type impurities can be implanted. In addition, the order of the first ion implantation and the second ion implantation can be reversed, and the first ion implantation can be performed after the second ion implantation.

[0087] The acceleration energy of the first ion implantation is, for example, about 150 keV or more and 250 keV or less, preferably, it can be about 180 keV or more and 220 keV or less. The dose of the first ion implantation is, for example, 1×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, preferably, it can be 2×10 13 / cm 2 or more and 4×10 13 / cm 2 or less, preferably, it can be 2×10

[0088] The acceleration energy of the second ion implantation is, for example, about 50 keV or more and 120 keV or less, preferably, it can be about 60 keV or more and 100 keV or less. The dose of the second ion implantation is, for example, 1×10 13 / cm 2 or more and 5×10 13 / cm 2 or less, preferably, it can be 2×10 13 / cm 2 or more and 4×10 13 / cm 2 or less, preferably, it can be 2×10

[0089] By performing the ion implantation for forming the source extension 71 in two or more steps (several steps) rather than in one step, the surface concentration of the source contact portion 72 can be increased and the contact resistance can be reduced compared with the case of performing the ion implantation for forming the source extension 71 in one step. On the other hand, by performing the ion implantation for forming the source extension 71 in one step, the manufacturing cost can be reduced compared with the case of performing the ion implantation for forming the source extension 71 in two or more steps (several steps).

[0090] By ion implantation of n-type impurities for forming the source extension 71, for example, the region from the upper surface of the source extension 71 to a depth of 350 nm or more and 400 nm or less is set to an impurity concentration of about 1×10 17 cm -3 or more and about 1×10 19 cm -3 or less, so that it can serve as a current path.

[0091] Next, the n Figure 4 -type source contact portion forming step of step S12 is performed. In this n + -type source contact portion forming step, as + shown, next, using the oxide film 21 as an ion implantation mask, in a non-heated state at room temperature, ion implantation of at least any one of Ar, Si, or C is performed without performing ion implantation of n-type impurities. The room temperature is, for example, about 1°C or more and 40°C or less, and may also be about 15°C or more and 30°C or less. The room temperature during ion implantation may be the same as or different from the room temperature during the ion implantation for forming the source extension 71. In addition, a photoresist film may be used instead of the oxide film 21 as the ion implantation mask. As a result, an n Figure 10 -type source contact portion 72 is formed on the upper surface side of the source extension 71. + -type source contact portion 72 is formed on the upper surface side of the source extension 71.

[0092] By the ion implantation for forming the source contact portion 72, the structure of 4H-SiC on the upper surface side of the source extension 71 is damaged to form an amorphous structure. In order to cause higher damage compared with the ion implantation of the aforementioned source extension 71, Si (atomic number 14) having a relatively large atomic weight is preferred over C (atomic number 6) having a relatively small atomic weight, and Ar (atomic number 18) having an even larger atomic weight is more preferred.

[0093] Regarding the acceleration energy of the ion implantation for forming the source contact portion 72, in the case of performing ion implantation of Ar, for example, it is about 50 keV or more and 100 keV or less, and more preferably, it can be about 60 keV or more and 80 keV or less. In the case of performing ion implantation of Si, for example, it is about 60 keV or more and 120 keV or less, and more preferably, it can be about 70 keV or more and 100 keV or less. In the case of performing ion implantation of C, for example, it is about 20 keV or more and 60 keV or less, and more preferably, it can be about 25 keV or more and 40 keV or less.

[0094] Regarding the dose of the ion implantation for forming the source contact portion 72, in the case of performing ion implantation of Ar, for example, it is 2×10 14 / cm 2 or more and 2×10 15 / cm 2 or less, and more preferably, it can be 2×10 14 / cm 2 or more and 1×10 15 / cm 2 or less. In the case of performing ion implantation of Si, for example, it is 2×10 14 / cm 2 or more and 2×10 16 / cm 2 or less, and more preferably, it can be 2×10 14 / cm 2 or more and 1×10 15 / cm 2 or less. In the case of performing ion implantation of C, for example, it is 1×10 15 / cm 2 or more and 5×10 15 / cm 2 or less, and more preferably, it can be 1×10 15 / cm 2 or more and 3×10 15 / cm 2 or less. The higher the dose during ion implantation, the greater the ratio of 3C contained in the source contact portion 72 can be.

[0095] Next, perform the Figure 4 step S13 of the p + type contact region formation process. In this p +In the step of forming the type contact region, an oxide film 22 is deposited on the upper surface of the base region 6 by CVD technology or the like. A photoresist film is applied to the upper surface of the oxide film 22, and the oxide film 22 is patterned by photolithography technology and dry etching technology or the like. The patterned oxide film 22 is used as a mask for ion implantation, such as Figure 11 As shown in FIG. 1 , ion implantation of p-type impurities such as aluminum (Al) and boron (B) is performed. Alternatively, a photoresist film may be used as an ion implantation mask instead of the oxide film 22. As a result, p-type impurities are selectively formed on the upper surface side of the second buried regions 5a and 5b. + Thereafter, the oxide film 22 used as a mask for ion implantation is removed.

[0096] In addition, the order of ion implantation for forming the base region 6, ion implantation for forming the source extension portion 71, ion implantation for forming the source contact portion 72, ion implantation for forming the second buried regions 5a, 5b, and ion implantation for forming the base contact regions 8a, 8b is not limited to this, and the order may be reversed.

[0097] Next, proceed Figure 4 The activation annealing (heat treatment) process of step S14 is performed. In this activation annealing process, for example, the activation annealing is performed at a temperature of about 1600°C or more and about 1900°C or less, thereby activating the p-type impurities or n-type impurities ion-implanted into the first buried regions 4a, 4c, the gate bottom protection region 4b, the second buried regions 5a, 5b, the source extension 71, the source contact 72, and the base contact regions 8a, 8b, etc., respectively. At this time, the amorphous structure of the source contact 72 is recrystallized to become 3C-SiC, thereby forming a source contact 72 containing 3C-SiC.

[0098] In addition, although the case where activation annealing is performed once after all ion implantation steps is illustrated here, activation annealing may be performed multiple times after each ion implantation step. In addition, a cap film formed of carbon (C) may be formed before activation annealing, activation annealing may be performed in a state covered with the cap film, and the cap film may be removed after activation annealing.

[0099] Next, proceed Figure 4 In the trench forming step S15, an oxide film 23 is deposited on the upper surface of the base contact regions 8a, 8b and the source contact portion 72 by CVD technology or the like (see Figure 12 ). A photoresist film is applied to the upper surface of the oxide film 23, and the oxide film is patterned using photolithography technology and dry etching technology. The patterned oxide film 23 is used as an etching mask, and a dry etching technology such as reactive ion etching (RIE) is used. Figure 12As shown, a trench 10 is selectively formed in the depth direction from the upper surface of the source contact portion 72. In addition, a photoresist film may be used instead of the oxide film 23 as an etching mask.

[0100] The trench 10 penetrates the source extension portion 71, the source contact portion 72, and the base region 6, and digs into the upper portion of the current diffusion layer 3 to reach the gate bottom protection region 4b. The source extension portion 71 is divided into source extension portions 71a and 71b, the source contact portion 72 is divided into source contact portions 72a and 72b, and the base region 6 is divided into base regions 6a and 6b. Source regions 7a and 7b are formed by the source extension portions 71a and 71b and the source contact portions 72a and 72b. After that, the oxide film 23 used as an etching mask is removed. The trench 10 only needs to reach the current diffusion layer 3 and may not reach the gate bottom protection region 4b.

[0101] Next, perform Figure 4 the gate insulating film / gate electrode forming process of step S16. In this gate insulating film / gate electrode forming process, a gate insulating film 11 (refer to Figure 13 ) is formed on the lower surface and side surfaces of the trench 10, and on the upper surfaces of the source contact portions 72a and 72b and the base region contact regions 8a and 8b by CVD technology, high-temperature oxidation (HTO) method, thermal oxidation method, etc. When forming the gate insulating film 11, for example, heat treatment (PDA: PostDeposition Annealing) is performed at about 900 °C or higher and 1350 °C or lower.

[0102] Next, a polysilicon layer (doped polysilicon layer) doped with impurities such as phosphorus (P) and boron (B) at a high concentration is deposited by CVD technology or the like in a manner of filling the inside of the trench 10. After that, a part of the polysilicon layer is selectively removed by photolithography technology and dry etching. As a result, as Figure 13 shown, an insulated gate type electrode structure (11, 12) formed by the gate insulating film 11 and the gate electrode 12 is formed. At this time, the depression amount d0 of the gate electrode 12 is adjusted so that, as Figure 2 shown, the upper surface 12a of the position of the gate electrode 12 in contact with the gate insulating film 11 is deeper than the lower surface (lower end) 72x of the source contact portion 72a and shallower than the lower surface (lower end) 71x of the source extension portion 71a.

[0103] Next, an interlayer insulating film 13 is deposited on the upper surface of the insulated gate type electrode structure (11, 12) by CVD technology or the like (refer to Figure 14 ). A part of the interlayer insulating film 13 and the gate insulating film 11 is selectively removed by photolithography technology, dry etching technology, etc. to be as Figure 14As shown, contact holes 13a and 13b are formed in the opening of the interlayer insulating film 13 to expose the upper surfaces of the source contact portions 72a and 72b and the base region contact regions 8a and 8b. Thereafter, heat treatment (reflow) for planarizing the interlayer insulating film 13 may be performed.

[0104] Next, by sputtering technology or evaporation method, etc., as Figure 15 shown, a barrier metal layer 14 and a source wiring electrode 15 are sequentially formed so as to cover the upper surface and side surfaces of the interlayer insulating film 13 and the upper surfaces of the source contact portions 72a and 72b and the base region contact regions 8a and 8b, thereby forming a source electrode (14, 15). The barrier metal layer 14 makes a low-resistance ohmic contact with the source contact portions 72a and 72b of the source regions 7a and 7b and the base region contact regions 8a and 8b.

[0105] Next, the SiC substrate 1 is thinned from the lower surface side by grinding or chemical mechanical polishing (CMP), etc. to adjust the thickness, thereby forming the drain region 1. Next, a drain electrode 16 made of gold (Au), etc. is formed on the entire lower surface of the drain region 1 by sputtering method or evaporation method (refer to Figure 1 ). Thus, Figure 1 the silicon carbide semiconductor device shown is completed.

[0106] According to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, the source region 7a is a double-layer structure of a source extension portion 71a of 4H-SiC and a source contact portion 72a of 3C-SiC, and the source region 7b is a double-layer structure of a source extension portion 71b of 4H-SiC and a source contact portion 72b of 3C-SiC. Thus, a trench gate type silicon carbide semiconductor device can be realized in which the source contact portions 72a and 72b can make a low-resistance ohmic contact with the source electrode (14, 15) without forming a silicide layer such as nickel (Ni) silicide.

[0107] And, according to the silicon carbide semiconductor device according to the first embodiment, as Figure 2 shown, the upper surface 12a of the gate electrode 12 is deeper than the lower surface 72x of the source contact portion 72a and shallower than the lower surface 71x of the source extension portion 71a. Thus, the source extension portion 71a with fewer crystal defects in the source region 7a faces the gate electrode 12 across the gate insulating film 11, and the source contact portion 72a with more crystal defects in the source region 7a does not face the gate electrode 12 across the gate insulating film 11. Therefore, the occurrence of leakage current between the source region 7a and the gate electrode 12 can be suppressed.

[0108] Further, according to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, during ion implantation for forming the source contact portion 72, ion implantation of Si, C, or Ar is performed at room temperature without performing ion implantation of n-type impurities. Thereby, the dose of n-type impurities for ion implantation for forming the source extension portion 71 and the source contact portion 72 can be set low, so that the formation of crystal defects can be suppressed during the 3C conversion of the crystal structure, and the leakage current between the source and the drain can be suppressed. Also, the dose of n-type impurities for ion implantation for forming the source extension portion 71 and the source contact portion 72 can be set low, so heating during ion implantation of n-type impurities for forming the source extension portion 71 is not required, and ion implantation of n-type impurities can be performed at room temperature. Therefore, compared with the case where ion implantation of n-type impurities for forming the source extension portion 71 is performed at a high temperature (for example, about 200 °C or higher and 600 °C or lower), the manufacturing cost can be reduced.

[0109] Further, according to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, by performing ion implantation of Si or C during ion implantation for forming the source contact portion 72, compared with the case of performing Ar ion implantation, the crystal structure is more easily repaired by heating, so that the leakage current between the source and the drain can be suppressed to a lower level. Also, when an upper limit is set for the leakage current between the source and the drain, the dose of Si or C that can be implanted is higher than the dose of Ar. Therefore, the ratio of forming 3C can be increased by increasing the dose of Si or C, and the contact resistance can be further reduced. Also, the impurity concentration on the surface side of the source contact portion 72 can be set low, so it is easier to reduce the number of implantation steps.

[0110] Further, according to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, by performing Ar ion implantation during ion implantation for forming the source contact portion 72, compared with the case of performing Si or C ion implantation, since the atomic weight of Ar is small, it is easy to introduce damage and the dose can be reduced.

[0111] Next, with reference to Table 1 below, the first embodiment to the sixth embodiment and the comparative example will be described.

[0112]

Table 1

[0113]

[0114] <First Embodiment>

[0115] As the first embodiment, ion implantation was performed in two steps, namely the first ion implantation and the second ion implantation. In the first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 P was implanted+ Ion implantation was carried out. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 P + ion implantation was carried out. After that, at room temperature, with an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 Ar + ion implantation was carried out, thereby manufacturing a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0116] Regarding the silicon carbide semiconductor device of the first embodiment, when the ratio of the crystal phase was calculated by analyzing the SiC surface by EBSD, the ratio of 3C was 70%. In addition, regarding the silicon carbide semiconductor device of the first embodiment, when the leakage current (Idss) between the source and drain was measured, it was 5×10 -6 A.

[0117] <Second Embodiment>

[0118] As the second embodiment, ion implantation was carried out in two steps, namely the first ion implantation and the second ion implantation, in the same manner as in the first embodiment. In this first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 P + ion implantation was carried out. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 P + ion implantation was carried out. After that, compared with the first embodiment, the dose was changed to a higher value, and at room temperature, with an acceleration energy of 70 keV and a dose of 1×10 15 cm -2 Ar + ion implantation was carried out. Other manufacturing conditions were set to be the same as those in the first embodiment to manufacture a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0119] Regarding the silicon carbide semiconductor device of the second embodiment, when the ratio of the crystal phase was calculated by analyzing the SiC surface by EBSD, the ratio of 3C was 85%. Therefore, it can be seen that, compared with the first embodiment, by increasing the dose of Ar + , the ratio of 3C increased.

[0120] <Third Embodiment>

[0121] As the third embodiment, ion implantation was carried out in two steps, namely the first ion implantation and the second ion implantation, in the same manner as in the first embodiment. In this first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×1013 cm -2 Perform P + ion implantation. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 Perform P + ion implantation. After that, compared with the first embodiment, the ion species was changed, and at room temperature, with an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 Si + ion implantation was performed. Other manufacturing conditions were set the same as those in the first embodiment to fabricate a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0122] Regarding the silicon carbide semiconductor device of the third embodiment, when the ratio of the crystal phase was calculated by analyzing the SiC surface by EBSD, the ratio of 3C was 70%. Therefore, it can be seen that compared with the first embodiment, when Si + was implanted instead of Ar + the ratio of 3C was the same.

[0123] <Fourth Embodiment>

[0124] As the fourth embodiment, ion implantation was performed in two steps, namely the first ion implantation and the second ion implantation, in the same manner as in the first embodiment. In this first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 Perform P + ion implantation. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 Perform P + ion implantation. After that, compared with the first embodiment, the implanted element was changed, and the dose was increased compared with the first embodiment. At room temperature, with an acceleration energy of 70 keV and a dose of 1×10 15 cm -2 Si + ion implantation was performed. Other manufacturing conditions were set the same as those in the first embodiment to fabricate a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0125] Regarding the silicon carbide semiconductor device of the fourth embodiment, when the ratio of the crystal phase was calculated by analyzing the SiC surface by EBSD, the ratio of 3C was 85%. Therefore, it can be seen that compared with the third embodiment, by increasing the dose of Si + the ratio of 3C increased.

[0126] <Fifth Embodiment>

[0127] As a fifth embodiment, ion implantation was performed in two steps of first ion implantation and second ion implantation in the same manner as in the first embodiment. In this first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 ion implantation of P + was performed. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 ion implantation of P + was performed. After that, compared with the first embodiment, the ion species was changed, and at room temperature, with an acceleration energy of 70 keV and a dose of 1×10 15 cm -2 ion implantation of carbon ions (C + ) was performed. Other manufacturing conditions were set to be the same as those in the first embodiment to manufacture a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0128] Regarding the silicon carbide semiconductor device of the fifth embodiment, when the ratio of the crystal phase was calculated by analyzing the SiC surface by EBSD, the ratio of 3C was 70%. Therefore, it can be seen that compared with the first embodiment, when C + was implanted instead of Ar + , the ratio of 3C was the same.

[0129] <Sixth Embodiment>

[0130] As a sixth embodiment, ion implantation was performed in two steps of first ion implantation and second ion implantation in the same manner as in the first embodiment. In this first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 ion implantation of P + was performed. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 ion implantation of P + was performed. After that, compared with the first embodiment, the implanted element was changed, and the dose was increased compared with the first embodiment. At room temperature, with an acceleration energy of 70 keV and a dose of 3×10 15 cm -2 ion implantation of C + was performed. Other manufacturing conditions were set to be the same as those in the first embodiment to manufacture a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0131] Regarding the silicon carbide semiconductor device of the sixth embodiment, when analyzing the SiC surface by EBSD to calculate the ratio of crystal phases, the ratio of 3C is 85%. Therefore, it can be seen that compared with the fifth embodiment, by increasing the dose of C + the ratio of 3C has increased.

[0132] <Comparative Example>

[0133] As a comparative example, ion implantation was performed in two steps, namely the first ion implantation and the second ion implantation, in the same manner as in the first embodiment. In this first ion implantation, at room temperature, with an acceleration energy of 200 keV and a dose of 4×10 13 cm -2 P + ion implantation was performed. In this second ion implantation, at room temperature, with an acceleration energy of 85 keV and a dose of 3×10 13 cm -2 P + ion implantation was performed. After that, compared with the first embodiment, the ion species was changed, and at room temperature, with an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 P + as an n-type impurity was implanted. Other manufacturing conditions were set to be the same as those in the first embodiment to manufacture a silicon carbide semiconductor device with a breakdown voltage of 1200 V.

[0134] Regarding the silicon carbide semiconductor device of the comparative example, when measuring the leakage current (Idss) between the source and the drain, it was 1×10 -5 A. Therefore, it can be seen that compared with the first embodiment, when P + ion implantation was performed instead of Ar+, the leakage current increased.

[0135] Next, with reference to Table 2 below, the seventh to ninth embodiments will be described.

[0136]

Table 2

[0137]

[0138] <Seventh Embodiment>

[0139] As the seventh embodiment, compared with the first embodiment, the number of steps, the acceleration energy, and the dose were changed. At room temperature, with an acceleration energy of 120 keV and a dose of 5×10 13 cm -2 P + ion implantation was performed in one step. After that, in the same manner as in the first embodiment, at room temperature, with an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 Ar+ Ion implantation was carried out. Other manufacturing conditions were set the same as those in the first embodiment to fabricate a silicon carbide semiconductor device with a breakdown voltage of 1200V.

[0140] Regarding the silicon carbide semiconductor device of the seventh embodiment, when the leakage current (Idss) between the source and drain was measured, it was 5×10 -6 A. Therefore, it can be seen that the leakage current is equivalent to that of the first embodiment, and the leakage current can be suppressed compared with the comparative example.

[0141] <Eighth Embodiment>

[0142] As the eighth embodiment, in the same manner as the seventh embodiment, at room temperature, with an acceleration energy of 120 keV and a dose of 5×10 13 cm -2 a one-step P + ion implantation was carried out. After that, compared with the seventh embodiment, the ion species was changed, and at room temperature, with an acceleration energy of 70 keV and a dose of 2×10 14 cm -2 Si + ion implantation was carried out. Other manufacturing conditions were set the same as those in the first embodiment to fabricate a silicon carbide semiconductor device with a breakdown voltage of 1200V.

[0143] Regarding the silicon carbide semiconductor device of the eighth embodiment, when the leakage current (Idss) between the source and drain was measured, it was 1×10 -6 A. Therefore, it can be seen that compared with the seventh embodiment, when Si + ion implantation was carried out instead of Ar + , the leakage current can be further suppressed. Based on this, it can be speculated that when Si + ion implantation is carried out, compared with the case of carrying out Ar + ion implantation, the formation of crystal defects is suppressed during the 3C conversion of the crystal structure.

[0144] <Ninth Embodiment>

[0145] As the ninth embodiment, in the same manner as the seventh embodiment, at room temperature, with an acceleration energy of 120 keV and a dose of 5×10 13 cm -2 a one-step P + ion implantation was carried out. After that, compared with the seventh embodiment, the ion species, acceleration energy, and dose were changed, and at room temperature, with an acceleration energy of 30 keV and a dose of 1×10 15 cm -2 C + ion implantation was carried out. Other manufacturing conditions were set the same as those in the first embodiment to fabricate a silicon carbide semiconductor device with a breakdown voltage of 1200V.

[0146] Regarding the silicon carbide semiconductor device of the ninth embodiment, when measuring the leakage current (Idss) between the source and the drain, it is 1×10 -6 A. Therefore, it can be seen that, compared with the seventh embodiment, when substituting Ar + with C + for ion implantation, the leakage current can be further suppressed. Accordingly, it can be speculated that, when performing C + ion implantation, compared with the case of performing Ar + ion implantation, the formation of crystal defects is suppressed during the 3C conversion of the crystal structure.

[0147] (Second Embodiment)

[0148] The silicon carbide semiconductor device according to the second embodiment has the same structure as the silicon carbide semiconductor device according to the first embodiment Figure 1 shown. The difference between the manufacturing method of the silicon carbide semiconductor device according to the second embodiment and the manufacturing method of the silicon carbide semiconductor device according to the first embodiment is that, as Figure 16 shown, the activation annealing process for the ion implantation region other than the source contact portion 72 in step S23 and the activation annealing process for the source contact portion 72 in step S25 are performed separately.

[0149] In Figure 16 the process before the n + type source extension portion forming process in step S21 is substantially the same as the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, so the repeated description is omitted. Figure 16 the n + type source extension portion forming process in step S21 of Figure 4 is the same as the n + type source extension portion forming process in step S11 of Figure 9 shown. By performing ion implantation of n-type impurities such as P at room temperature, an n + type source extension portion 71 is formed.

[0150] Figure 16 the p + type contact region forming process in step S22 of Figure 4 is the same as the p + type contact region forming process in step S13 of Figure 11 shown. By performing ion implantation of p-type impurities, p + type base region contact regions 8a and 8b are formed. In addition, at this time, the n + type source contact portion 72 is not yet formed.

[0151] Figure 16 The activation annealing process of step S23 is Figure 4 The activation annealing process of step S14 is the same, for example, by performing activation annealing at a temperature of 1600°C or higher and 1900°C or lower, the p-type impurities or n-type impurities ion-implanted into the first buried regions 4a, 4c, the gate bottom protection region 4b, the second buried regions 5a, 5b, the source extension 71, and the base contact regions 8a, 8b are activated together. In addition, the n + Type source contact 72.

[0152] Figure 16 Step S24 + Type source contact formation process and Figure 4 Step S12 + The process of forming the source contact of the type is the same as Figure 10 As shown, n is formed by ion implantation of Ar, Si or C at room temperature. + The source contact portion 72 of the type is formed. Due to the damage of ion implantation, the 4H-SiC contained in the source contact portion 72 is destroyed, and an amorphous structure is formed.

[0153] exist Figure 16 In the activation annealing process of step S25, Figure 16 The activation annealing process of step S23 is performed at a low temperature, for example, 1300° C. to 1500° C., to activate the n-type impurities ion-implanted into the source contact 72. At this time, the amorphous structure of the source contact 72 is recrystallized to become 3C-SiC, thereby forming the source contact 72 including 3C-SiC.

[0154] Figure 16 The groove forming process of step S26 is Figure 4 The groove forming process of step S15 is the same as Figure 12 As shown, trench 10 is selectively formed in the depth direction from the upper surface of source contact portion 72 by dry etching technology or the like.

[0155] Figure 16 The gate insulating film / gate electrode forming step of step S27 is Figure 4 The gate insulating film / gate electrode forming process of step S16 is the same as Figure 13 As shown, an insulated gate type electrode structure (11, 12) formed of a gate insulating film 11 and a gate electrode 12 is buried inside the trench 10. Figure 16 The process after the gate insulating film / gate electrode forming step S27 is substantially the same as that of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, and therefore repeated description is omitted.

[0156] According to the manufacturing method of the silicon carbide semiconductor device according to the second embodiment, similarly to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, a trench gate type silicon carbide semiconductor device can be realized that enables ohmic contact between the source regions 7a and 7b and the source electrodes (14, 15) and can suppress the leakage current between the source and the drain.

[0157] Moreover, according to the manufacturing method of the silicon carbide semiconductor device according to the second embodiment, the activation annealing process for the ion implantation regions other than the source contact portion 72 in step S23 and the activation annealing process for the source contact portion 72 in step S25 are carried out separately. Crystal defects of 3C-SiC in the source contact portion 72 occur during the recrystallization of the amorphous structure during activation annealing. However, since the activation annealing process in step S25 is carried out at a temperature lower than that of the activation annealing process in step S23, the propagation of crystal defects from the source contact portion 72 to the source extension portion 71 can be reduced or suppressed.

[0158] (Third Embodiment)

[0159] The silicon carbide semiconductor device according to the third embodiment has the same structure as the silicon carbide semiconductor device according to the first embodiment shown in Figure 1 . The difference between the manufacturing method of the silicon carbide semiconductor device according to the third embodiment and the manufacturing method of the silicon carbide semiconductor device according to the first embodiment is that, as shown in Figure 17 , the heat treatment (PDA) in the gate insulating film / gate electrode formation process of step S36 also serves as the activation annealing of the source contact portion 72.

[0160] Figure 17 The process before the n + type source extension portion formation process of step S31 in Figure 17 is substantially the same as the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, so repeated descriptions are omitted. + The n Figure 4 type source extension portion formation process of step S31 in + is the same as the n Figure 9 type source extension portion formation process of step S11 in + . As shown in

[0161] Figure 17 , the p + type contact region formation process of step S32 in Figure 4 is the same as the p + type contact region formation process of step S13 inFigure 11 As shown, by performing ion implantation of p-type impurities, a p-type base contact region 8a, 8b is formed. + At this time, an n-type source contact portion 72 has not been formed yet. +

[0162] Figure 17 The activation annealing process of step S33 of Figure 4 is the same as the activation annealing process of step S14 of + At this time, an n-type source contact portion 72 has not been formed yet. For example, by performing activation annealing at about 1600 °C or higher and 1900 °C or lower, the p-type impurities or n-type impurities respectively ion-implanted into the first buried regions 4a, 4c, the gate bottom protection region 4b, the second buried regions 5a, 5b, the source extension portion 71, and the base contact regions 8a, 8b are activated together.

[0163] Figure 17 The n-type source contact portion forming process of step S34 of + is the same as the n-type source contact portion forming process of step S12 of Figure 4 As shown in + , by performing ion implantation of Ar, Si, or C at room temperature, an n-type source contact portion 72 is formed. Due to the damage caused by ion implantation, the 4H-SiC contained in the source contact portion 72 is damaged and an amorphous structure is formed. Figure 10 +

[0164] Figure 17 The trench forming process of step S35 of Figure 4 is the same as the trench forming process of step S15 of Figure 12 As shown in

[0165] Figure 17 The gate insulating film / gate electrode forming process of step S36 of Figure 4 is the same as the gate insulating film / gate electrode forming process of step S16 of Figure 13 As shown in Figure 17The heat treatment in the activation annealing process of step S33 has a low temperature, for example, about 900 °C or higher and 1350 °C or lower. Through this heat treatment, the n-type impurities implanted into the source contact portion 72 are activated. At this time, the amorphous structure of the source contact portion 72 recrystallizes into 3C-SiC, thereby forming a source contact portion 72 containing 3C-SiC. After that, the gate electrode 12 is buried inside the trench 10 to form an insulated gate electrode structure (11, 12) formed by the gate insulating film 11 and the gate electrode 12.

[0166] Figure 17 The process after the gate insulating film / gate electrode formation process of step S36 is substantially the same as that of the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, so repeated descriptions are omitted.

[0167] According to the manufacturing method of the silicon carbide semiconductor device according to the third embodiment, similarly to the manufacturing method of the silicon carbide semiconductor device according to the first embodiment, it is possible to realize a trench gate type silicon carbide semiconductor device that can achieve ohmic contact between the source regions 7a and 7b and the source electrodes (14, 15) and can suppress the leakage current between the source and the drain.

[0168] Moreover, according to the manufacturing method of the silicon carbide semiconductor device according to the third embodiment, crystal defects of 3C-SiC in the source contact portion 72 occur during the recrystallization of the amorphous structure during activation annealing. However, since the heat treatment in the gate insulating film / gate electrode formation process of step S36 is performed at a temperature lower than that of the activation annealing process of step S33, the propagation of crystal defects from the source contact portion 72 to the source extension portion 71 can be reduced or suppressed. And the heat treatment in the gate insulating film / gate electrode formation process of step S36 also serves as the activation annealing of the source contact portion 72, so an increase in man-hours can be suppressed.

[0169] (Other Embodiments)

[0170] Although the first to third embodiments of the present disclosure have been described as above, it should not be construed that the discussions and drawings forming a part of the present disclosure are used to limit the present disclosure. According to the present disclosure, those skilled in the art can clarify various alternative embodiments, examples, and application techniques.

[0171] For example, although a MOSFET is exemplified as the semiconductor device according to the first to third embodiments, it can also be applied to replace the n + type drain region 1 with a p +An insulated gate bipolar transistor (IGBT) having a structure of a collector region of a certain type. In addition, in addition to the IGBT element, it can also be applied to a reverse-conducting IGBT (RC-IGBT) and a reverse-blocking insulated gate bipolar transistor (RB-IGBT).

[0172] In addition, the structures disclosed in the first to third embodiments can be appropriately combined within a range where no contradiction occurs. As such, it goes without saying that the present disclosure includes various embodiments not described herein. Therefore, the technical scope of the present disclosure is defined only by the inventive features related to the claims that are appropriate according to the above description.

[0173] Description of Reference Numerals

[0174] 1: Drain region (SiC substrate); 2: Drift layer; 3: Current diffusion layer; 3a, 3b: n-type layer; 4a, 4c: First buried region; 4b: Gate bottom protection region; 5a, 5b: Second buried region; 6, 6a, 6b: Base region; 7a, 7b, 7x: Source region; 8a, 8b: Base contact region; 10: Trench; 11: Gate insulating film; 12: Gate electrode; 12a: Upper surface; 13: Interlayer insulating film; 13a, 13b: Contact hole; 14: Barrier metal layer; 15: Source wiring electrode; 16: Drain electrode; 21 to 23: Oxide film; 71, 71a, 71b: Source extension; 71x: Lower surface; 72, 72a, 72b: Source contact portion; 72x: Lower surface.

Claims

1. A method for manufacturing a silicon carbide semiconductor device, comprising the following steps: forming a second conductivity type base region formed of silicon carbide on an upper surface side of a first conductivity type drift layer formed of silicon carbide; forming a main region of a first conductivity type formed of silicon carbide on an upper surface side of the base region; forming a trench penetrating the main region and the base region; forming a gate insulating film inside the trench; burying a gate electrode inside the trench via the gate insulating film; as well as forming a main electrode connected to the main region, The process of forming the main area includes: Forming a first region including a 4H structure on the upper surface side of the base region by performing ion implantation of first conductivity type impurities at room temperature; and By performing ion implantation of at least any one of silicon, carbon, and argon at room temperature, a second region including a 3C structure is formed on the upper surface side of the first region so as to be in contact with the main electrode.

2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein: The first conductivity type impurity is phosphorus or nitrogen.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein: The ion implantation dose of the first conductivity type impurity is 5×10 13 cm -2 the following.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein: The second region is formed by performing ion implantation of silicon or carbon.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein: The second region is formed by implanting argon ions.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein: An upper surface of the gate electrode at a position in contact with the gate insulating film is located deeper than a lower surface of the second region and shallower than a lower surface of the first region.

7. A silicon carbide semiconductor device comprising: A drift layer of a first conductivity type, formed of silicon carbide; A base region of a second conductivity type, which is disposed on the upper surface side of the drift layer and is formed of silicon carbide; A main region of a first conductivity type, which is provided on the upper surface side of the base region and is formed of silicon carbide; a gate insulating film disposed inside a trench penetrating the main region and the base region; a gate electrode embedded in the inner side of the trench via the gate insulating film; and A main electrode is disposed in contact with the main region, Wherein, the main area has: A first region, which is disposed on the upper surface side of the base region and includes a 4H structure; and The second region is provided on the upper surface side of the first region so as to be in contact with the main electrode, and the ratio of the 3C structure on at least the upper surface side of the second region is 70% or more.

8. The silicon carbide semiconductor device according to claim 7, wherein: The second zone comprises argon.

9. The silicon carbide semiconductor device according to claim 7 or 8, wherein: The ratio of the 3C structure on at least the upper surface side of the second region is 85% or more.

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