Method of forming transistor gate stack

Abstract

A dipole engineering technique is provided that may be implemented in fabricating a gate stack, such as a gate stack of a transistor. An exemplary method for forming a gate stack of a transistor includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process of driving aluminum from the p-dipole dopant source layer into the high-k dielectric layer, and after removing the p-dipole dopant source layer, performing a thermal drive-in process of driving aluminum from the p-dipole dopant source layer into the high-k dielectric layer. At least one conductive gate layer is formed over the high-k dielectric layer. The p-dipole dopant source layer includes an aluminum layer. The p-dipole dopant source layer may also include an aluminum oxide layer and / or an aluminum nitride layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method of forming a transistor gate stack. Background Art

[0002] The electronics industry has an ever-growing demand for smaller, faster electronic devices that can simultaneously support a large number of increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry continues to develop a trend towards low-cost, high-performance, and low-power ICs. So far, these goals have been largely achieved by shrinking the IC size (e.g., the minimum IC feature size), thereby improving production efficiency and reducing associated costs. However, this size reduction also increases the complexity of the IC manufacturing process. Therefore, similar advancements in IC manufacturing processes and technologies are needed to achieve continuous progress in IC devices and their performance.

[0003] One area of advancement involves providing ICs with transistors having multiple threshold voltages (Vt), which can improve the performance of some transistors in the IC while reducing the power consumption of other transistors in the IC. However, providing multiple threshold voltages has been a challenge for multi-gate devices, such as fin field-effect transistors, gate-all-around transistors including nanowires and / or nanosheets, and other types of multi-gate devices, because the multi-gate devices become very small, leaving minimal room for adjusting the threshold voltage using different work function metals. Although dipole engineering can provide multiple threshold voltages for multi-gate devices while minimizing and / or eliminating the need to use different work function metals, dipole engineering techniques pose challenges in achieving device stacks for further scaling. Therefore, although existing threshold voltage tuning techniques are generally sufficient for their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] Embodiments of the present invention provide an exemplary method for forming a gate stack of a transistor, including forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives aluminum from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. The p-dipole dopant source layer includes an aluminum layer.

[0005] Embodiments of the present invention provide a method, including forming a first interface layer over a first channel member and a second interface layer over a second channel member, forming a first gate dielectric over the first interface layer and a second gate dielectric over the second interface layer, performing a dipole engineering process including a dipole cycle, and forming a gate over the first gate dielectric and the second gate dielectric. The dipole cycle includes performing an atomic layer deposition (ALD) process to form an aluminum layer over the first gate dielectric but not over the second gate dielectric, performing a thermal drive-in process to drive the aluminum from the aluminum layer into the first gate dielectric, thereby increasing the aluminum layer to reduce the concentration in the first gate dielectric by about 5%, and removing the aluminum layer.

[0006] Embodiments of the present invention provide a method, including forming a device including a first gate region and a second gate region. The first gate region includes a first channel member, a first gate dielectric over the first channel member, and a first gate layer over the first gate dielectric. The second gate region includes a second channel member, a second gate dielectric over the second channel member, and a second gate layer over the second gate dielectric. The first gate dielectric and the second gate dielectric include different concentrations of aluminum. The formation of the device includes forming an aluminum layer over the first gate dielectric but not over the second gate dielectric, performing an annealing process to drive the aluminum from the aluminum layer into the first gate dielectric, thereby increasing the atomic concentration of aluminum in the first gate dielectric by less than about 5%, removing the aluminum layer, and forming a first gate layer over the first gate dielectric and a second gate layer over the second gate dielectric. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure.

[0009] Figure 2 is according to various aspects of the present disclosure Figure 1 of a block of the method.

[0010] Figure 3 is according to various aspects of the present disclosure Figure 2 of a block of the method.

[0011] Figure 4 is related to according to various aspects of the present disclosure Figure 1 of a method of an exemplary workpiece of a manufacturing stage.

[0012] Figure 5A 、 5B, 6A, 6B, 7A, 7B, 8A, 8B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, and 14B are Figure 4 partial cross-sectional views of exemplary workpieces at various manufacturing stages related to the Figure 1 methods according to various aspects of the present disclosure.

[0013] Figure 9A , 9B , 9C, and 9D are enlarged cross-sectional views of a portion of an exemplary workpiece according to various aspects of the present disclosure. Figure 8B

[0014] Figure 15 is an exemplary diagram showing a first dipole patterning process that can be used in conjunction with the Figure 1 methods according to various aspects of the present disclosure.

[0015] Figure 16 and Figure 17 are exemplary diagrams showing a second dipole patterning process that can be used in conjunction with the Figure 1 methods according to various aspects of the present disclosure.

[0016] Figure 18A , 18B , 19A, and 19B are partial cross-sectional views of alternative workpieces at various manufacturing stages associated with the Figure 1 methods according to various aspects of the present disclosure.

[0017] Figure 20 is a partial cross-sectional view of another alternative workpiece that can be manufactured according to the Figure 1 methods according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0018] The present disclosure generally relates to integrated circuit (IC) devices, and more particularly, to methods for adjusting the threshold voltage (Vt) in IC devices, such as fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors, IC devices having a stacked device structure, such as a transistor stack having n-type and p-type transistors (i.e., complementary field-effect transistors (CFETs)).

[0019] It should be understood that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject matter. The following describes specific examples of each component and its arrangement in order to simplify the description of the disclosure. Of course, these are only examples and are not intended to limit the present invention. For example, the following disclosure describes forming a first component on or above a second component, which means it includes embodiments where the formed first component and the second component are in direct contact, and also includes embodiments where additional components can be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. In addition, the same reference symbols and / or words may be used in different examples in the disclosure. These repeated symbols or words are for the purpose of simplification and clarity, and are not intended to limit the relationship between each embodiment and / or the described appearance structure. Furthermore, the following description of a component being formed on, connected to, and / or coupled to another component may include embodiments where the components are in direct contact with each other, and may also include embodiments where other components can be formed between these components such that these components are not in direct contact with each other. In addition, for the convenience of describing the relationship between a component and another component in an embodiment of the present invention, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "on", "under", "top", "bottom", etc. and the foregoing derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) may be used. Spatially relative terms are used to cover different orientations of a device including components.

[0020] Furthermore, when numbers or numerical ranges are described using terms such as "about", "approximately" and similar terms, this term is intended to cover a reasonable range of the described numbers, such as within + / - 10% of the described number or other values that those skilled in the art to which the present invention pertains should understand. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. In addition, in view of the inherent differences in any manufacturing process, when a device feature is described as having "substantially" properties and / or characteristics, this term is intended to cover the properties and / or characteristics within the manufacturing process tolerances. For example, a feature that is "substantially vertical" or "substantially horizontal" is intended to cover features that are approximately vertical and horizontal but not mathematically or completely vertical and horizontal within the given tolerances of the manufacturing process for manufacturing such features.

[0021] An IC can include many transistors. Providing transistors with multiple threshold voltages (Vt) for an IC can maximize its performance and / or reliability, for example, by increasing the speed / performance of some transistors of the IC while reducing the power consumption of other transistors of the IC. However, providing a multi-gate device with multiple threshold voltages is challenging because the multi-gate device becomes very small, leaving minimal room for adjusting its threshold voltage using different work function metals. Dipole engineering can flexibly provide multi-gate devices with different threshold voltages by incorporating dipole dopants into its gate dielectric and minimizing and / or eliminating the need to use different work function metals. This may eliminate the need to pattern the work function metal, making dipole engineering well-suited for nanoscale transistors such as FinFETs and GAA transistors. Although existing dipole engineering techniques are generally sufficient for their intended purposes, they are not entirely satisfactory in all aspects.

[0022] The present disclosure provides dipole engineering techniques for multi-threshold voltage (Vt) tuning. In an embodiment, the present disclosure provides a method of forming a p-dipole layer including an aluminum layer over a high dielectric constant (k) dielectric layer and performing a thermal drive-in process to drive p-dipole dopants (aluminum) from the p-dipole layer into the high-k dielectric layer. The aluminum layer can be formed using an atomic layer deposition (ALD) process with precursors of aluminum chloride and trimethylaluminum. The aluminum layer includes an increased concentration (e.g., greater than 90%) of aluminum compared to an aluminum oxide layer and / or an aluminum nitride layer that can be used as a p-dipole layer. Accordingly, the thermal drive-in efficiency of aluminum is increased, thereby increasing the Vt tuning efficiency. For example, the amount of aluminum driven into the high-k dielectric layer at a certain time and a certain temperature is increased. This can save time and effort in the dipole engineering process. The p-dipole layer can also include an aluminum oxide layer and / or an aluminum nitride layer. This method can be used in combination with a dipole patterning process to form high-k dielectric layers with p-dipole dopants having various concentrations and / or compositions in various parts of a semiconductor structure. The efficiency of multi-Vt tuning can be increased by implementing the disclosed method.

[0023] Figure 1 is a flowchart of a method 100 for manufacturing a gate stack of a transistor according to various aspects of the present disclosure. Figure 2 is Figure 1 a flowchart of a method of the block. Figure 3 is Figure 2 a flowchart of a method of the block. Figure 4 is in connection with the various aspects according to the present disclosure Figure 1 a partial schematic top view of an exemplary workpiece 200 at a manufacturing stage related to the method 100. Figures 5A to 8A and Figures 10A to 14A are according to various aspects of the present disclosure at various manufacturing stages related to Figure 1 the method 100 along Figure 4Partial cross-sectional view of an exemplary workpiece 200 along line A-A. Figures 5B to 8B and Figures 10B to 14B are partial cross-sectional views of an exemplary workpiece 200 along line B-B at various manufacturing stages related to method 100 according to various aspects of the present disclosure. Figure 1 along Figure 4 are partial cross-sectional views of an exemplary workpiece 200 along line B-B at various manufacturing stages related to method 100 according to various aspects of the present disclosure. Figures 9A to 9D is an enlarged cross-sectional view of a portion of an exemplary workpiece 200 of FIG. 8 according to various aspects of the present disclosure. Figures 15 to 17 is an exemplary diagram showing a dipole patterning process 300 and a dipole patterning process 400 that can be used in combination with method 100 according to various aspects of the present disclosure. Figures 18A to 19B is a partial cross-sectional view of an alternative workpiece 500 at various manufacturing stages related to Figure 1 method 100 according to various aspects of the present disclosure. Figure 20 is a partial cross-sectional view of an alternative workpiece 600 that can be manufactured according to Figure 1 method 100 according to various aspects of the present disclosure. For clarity, Figures 1 to 20 has been simplified to better understand the inventive concept of the present disclosure. Additional steps can be provided before, during, and after method 100, and for additional embodiments of method 100, some of the described steps can be repeated, moved, replaced, or eliminated. Since workpieces 200, 500, and 600 will be manufactured into semiconductor structures, workpieces 200, 500, and 600 can be referred to herein as semiconductor structures 200, 500, and 600, respectively, as required by the context. To avoid ambiguity, Figures 4 to 14B and Figures 18A to 20 the X, Y, and Z directions are perpendicular to each other.

[0024] Referring to Figure 1 , Figure 4 and Figures 5A to 5B , method 100 includes forming a gate structure over a channel layer at block 105. The gate structure includes a dummy gate and gate spacer walls. This can include receiving and / or forming workpiece 200, which includes a substrate (chip) 202, a mesa 202' (i.e., a patterned protrusion of substrate 202), isolation features 208, epitaxial source / drain 214, a gate structure 220 (described as having a dummy gate 230 and gate spacer walls 232), and a dielectric layer 250. In an embodiment, workpiece 200 includes a plurality of active regions 204 (e.g., active regions 204a, 204b, 204c, referred to individually or collectively as active region 204 depending on the context). As Figure 4 shown, each active region 204 extends longitudinally along the X direction. Each active region 204 can have a fin structure and is thus referred to as a fin 204 or a fin structure 204. Figure 4The number of active regions 204 shown is for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. In the depicted embodiment, each active region 204 includes a respective mesa 202' in the channel region C and a respective epitaxial source / drain 214 in the source / drain region S / D. The mesa 202' extends between the epitaxial source / drains 214 in the X direction. In the depicted embodiment, the mesa 202' may also be referred to as a channel layer or a channel member 202'. A gate structure 220 is disposed on top of the mesa 202' and between the epitaxial source / drains 214. In the XZ plane, the gate structure 220 is located on top of the mesa 202'. In the YZ plane, the gate structure 220 is located on top of and on the sides of the mesa 202'. In some embodiments, the gate structure 220 and the active region 204 may form a transistor (e.g., transistor T1) at their intersection in a subsequent process.

[0025] The substrate 202 includes elemental semiconductors such as silicon and / or germanium; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. In the depicted embodiment, the substrate 202 is a silicon substrate. In some embodiments, the substrate 202 is a semiconductor-on-insulator substrate such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 202 (and the mesa 202') may include various doped regions such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. The n-type doped regions include n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof. The p-type doped regions include p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. In some embodiments, the doped regions include a combination of p-type dopants and n-type dopants. The doped regions may be formed directly on and / or in the substrate 202, e.g., to provide a p-well structure, an n-well structure, a dual-well structure, a raised structure, other suitable structures, or combinations thereof. In some embodiments, the substrate 202 and the mesa 202' include an n-well, e.g., in the case where the transistor T1 is a p-type transistor, or include a p-well, e.g., in the case where the transistor T1 is an n-type transistor.

[0026] The isolation feature 208 electrically isolates the active device regions and / or passive device regions of the device from each other. For example, the isolation feature 208 separates and electrically isolates the active region 204 of the transistor T1 (e.g., the mesa 202’ and / or its epitaxial source / drain 214) from other device regions and / or devices. The isolation feature 208 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.), or a combination thereof. The isolation feature 208 can have a multi-layer structure. For example, the isolation feature 208 includes a bulk dielectric (e.g., an oxide layer) over a dielectric liner (including, for example, silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride, or a combination thereof). In another example, the isolation feature 208 includes a dielectric layer over a doped liner (e.g., a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner). The size and / or properties of the isolation feature 208 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof. In the depicted embodiment, the isolation feature 208 can be an STI.

[0027] The epitaxial source / drain 214 includes semiconductor material and can be doped with an n-type dopant and / or a p-type dopant. When forming part of a p-type transistor, such as in the depicted embodiment, the epitaxial source / drain 214 can include silicon germanium or germanium doped with boron, other p-type dopants, or a combination thereof. When forming part of an n-type transistor, the epitaxial source / drain 214 can include silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof. The epitaxial source / drain 214 can include more than one layer of semiconductor material, where the semiconductor layers include the same or different materials and / or the same or different dopant concentrations. The epitaxial source / drain 214 can include materials and / or dopants that achieve a desired tensile stress and / or compressive stress in the channel region C. In some embodiments, doped regions, such as heavily doped source / drain (HDD) regions, lightly doped source / drain regions, lightly doped drain (LDD) regions, other doped regions, or a combination thereof are set in the epitaxial source / drain 214. In some embodiments, a doped region, such as an LDD region, can extend into the channel region C. As used herein, source / drain regions, epitaxial source / drains, epitaxial source / drain devices, etc. can refer to the source and / or drain of a transistor and / or device, or the source and / or drain of multiple devices (e.g., including transistor T1 and / or device T1).

[0028] The dummy gate 230 extends longitudinally in a direction different from (e.g., orthogonal to) the length direction of the active region 204. For example, the dummy gate 230 extends longitudinally along the Y direction, having a length along the Y direction, a width along the X direction, and a height along the Z direction. In the XZ plane, the dummy gate 230 is disposed on top of the mesa 202'. In the YZ plane, the dummy gate 230 is disposed on top of and over the sidewalls of the mesa 202'. The dummy gate 230 may include a dummy gate and a dummy gate dielectric. The dummy gate includes a suitable dummy gate material, and the dummy gate dielectric includes a suitable dielectric material. For example, the dummy gate includes polysilicon (i.e., polysilicon gate) and the dummy gate dielectric includes silicon oxide (i.e., dummy oxide). The dummy gate 230 may include additional layers, such as a hard mask layer, a capping layer, other suitable layers, or a combination thereof.

[0029] The gate spacer 232 is adjacent to and along the sidewalls of the dummy gate 230. The gate spacer 232 may include a seal spacer, an offset spacer, a sacrificial spacer, a dummy spacer, a main spacer, other suitable spacers, or a combination thereof. The gate spacer 232 may have a single-layer structure or a multi-layer structure. The gate spacer 232 includes a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable components, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, carbon silicon nitride, carbon silicon oxide, carbon oxynitride silicon, etc.). For example, the gate spacer 232 may include silicon, oxygen, nitrogen, carbon, and hydrogen (i.e., the gate spacer 232 is a SiONCH layer).

[0030] The dielectric layer 250 is disposed over the substrate 202, the isolation features 208, the epitaxial source / drain 214, and the gate structure 220. The dielectric layer 250 may have a multi-layer structure, such as an ILD layer 252 over a contact etch stop layer (CESL) 254. The ILD layer 252 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, oxide formed by tetraethyl orthosilicate (TEOS), BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorocarbon, parylene, benzocyclobutene-based (BCB) dielectric material, polyimide, other suitable dielectric materials, or a combination thereof. In some embodiments, the ILD layer 252 includes a dielectric material having a dielectric constant less than that of silicon oxide (e.g., k < 3.9). In some embodiments, the ILD layer 252 includes a dielectric material having a dielectric constant less than about 2.5 (i.e., a very low-k dielectric material), such as porous silicon oxide, silicon carbide, carbon-doped oxide (e.g., SiCOH-based material (having, for example, Si-CH 3a key)) or a combination thereof, each of which is adjusted / configured to have a dielectric constant of less than about 2.5. The CESL 254 includes a dielectric material different from the dielectric material of the ILD layer 252. For example, when the ILD layer 252 includes a low-k dielectric material (e.g., porous silica), the CESL 254 can include silicon and nitrogen, such as silicon nitride, silicon carbonitride, or silicon carbon oxynitride.

[0031] Forming the dielectric layer 250 can include depositing a dielectric material over the substrate 202, the isolation features 208, the epitaxial source / drain 214, and the gate structure 220, and performing a planarization process, such as chemical mechanical polishing (CMP), on the dielectric material. The planarization process removes any dielectric material above the gate structure 220. The dummy gate 230 can be used as a planarization stop layer, and the planarization process can be performed until the dummy gate 230 is reached. The planarization process can planarize the top surface of the dielectric layer 250 and, in some embodiments, the dielectric layer 250 is a device-level dielectric layer of a multilayer interconnect (MLI) feature that electrically connects devices (e.g., transistors, resistors, capacitors, inductors, etc.), components of the devices (e.g., gates and / or source / drains), devices within the MLI feature, components of the MLI feature, or a combination thereof to the top surface of the gate structure 220 such that the devices and / or components can operate as designed.

[0032] Reference Figure 1 and Figures 6A to 6B and, method 100 includes, at block 110, removing the dummy gate 230 to form a gate opening 255. In the depicted embodiment, the gate opening 255 exposes the mesa 202'. The gate opening 255 has sidewalls formed by the gate spacer 232 and a bottom formed by the mesa 202' and / or the isolation features 208. The gate opening 255 can also be referred to as the gate region 255. In some embodiments, an etching process selectively removes the dummy gate 230 relative to the gate spacer 232, the dielectric layer 250, or a combination thereof. For example, the etching process substantially removes the dummy gate 230 but does not remove or substantially does not remove the gate spacer 232, the isolation features 208, the dielectric layer 250, the mesa 202', etc. In some embodiments, an etchant is selected for an etching process that etches polysilicon (i.e., the dummy gate 230) at a higher rate than the dielectric material (i.e., the gate spacer 232, the dielectric layer 250, etc.) and the semiconductor material (i.e., the mesa 202') (i.e., the etchant has a high etch selectivity relative to polysilicon). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, a patterned masking layer (etch mask) covers and protects the dielectric layer 250 and / or the gate spacer 232 but exposes the dummy gate 230 during the etching process.

[0033] Reference Figure 1 and Figures 7A to 14B , method 100 includes forming a gate stack in gate opening 255 at block 120. The gate stack includes a gate dielectric 260 (e.g., at least one dielectric gate layer, such as a high-k dielectric layer) and a gate 280 (e.g., at least one conductive gate layer, such as a work function layer and / or a bulk metal layer). The gate stack fills gate opening 255 (see Figure 14A and Figure 14B ). In the XZ plane ( Figure 14A ), the gate stack is disposed between gate spacer walls 232. In the YZ plane ( Figure 14B ), the gate stack partially surrounds mesa 202’ (e.g., covers the top surface and sidewalls of mesa 202’). The gate stack may include a number of layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. The gate stack and the gate spacer walls 232 are collectively referred to as gate structure 220’.

[0034] Reference Figure 1 and Figures 7A to 7B , method 100 includes forming a gate dielectric, such as gate dielectric 260, in gate opening 255 and over mesa 202’ at block 125. In the illustrated embodiment, gate dielectric 260 includes an interface layer 262 and a gate dielectric layer 264. Interface layer 262 partially fills gate opening 255 and is formed on the semiconductor surface such that interface layer 262 is located between mesa 202’ and gate dielectric layer 264 in the XZ plane, and interface layer 262 covers the top surface of mesa 202’. In the YZ plane, interface layer 262 partially surrounds mesa 202’ (e.g., covers the top surface and sidewalls of mesa 202’). Interface layer 262 is formed by thermal oxidation, chemical oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), other suitable processes, or a combination thereof.

[0035] Interface layer 262 includes a dielectric material, such as SiO 2, SiGeOx, HfSiO, SiON, other dielectric materials, or combinations thereof. In some embodiments, the interface layer 262 is a Group-IV-based oxide layer, which generally refers to an oxide of a Group-IV-based material (i.e., including at least one Group-IV element such as Si, Ge, C, etc.). In some embodiments, the interface layer 262 is a Group-III-V-based oxide layer, which generally refers to an oxide of a Group-III-V-based material (i.e., including at least one Group-III element such as Al, Ga, In, B, etc., and at least one Group-V element such as N, P, As, Sb, etc.). The thickness of the interface layer 262 is less than the thickness of the gate dielectric layer 264. In some embodiments, the thickness of the interface layer 262 is from about 0.5 nm to about 2 nm. In the depicted embodiment, the interface layer 262 has a substantially uniform thickness.

[0036] The gate dielectric layer 264 partially fills the gate opening 255 and is formed on the interface layer 262, the gate spacer 232, the isolation feature 208, and the dielectric layer 250. In the XZ plane, the gate dielectric layer 264 has a U-shaped profile in the top portion of the gate opening 255. In the YZ plane, the gate dielectric layer 264 partially surrounds the mesa 202'. The gate dielectric layer 264 has a substantially uniform thickness. In some embodiments, the thickness of the gate dielectric layer 264 is from about 1 nm to about 5 nm. The gate dielectric layer 264 is formed by ALD, CVD, physical vapor deposition (PVD), an oxide-based deposition process, other suitable processes, or combinations thereof.

[0037] The gate dielectric layer 264 includes a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide (k≈3.9), such as HfO 2 , HfSiO, HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrO 2 , ZrSiO 2 , AlO, AlSiO, Al 2 O 3 , TiO, TiO 2 , LaO, LaSiO, LaO 3 , La 2 O 3 , Ta 2 O 3 , Ta 2 O 3 , Ta 2 O 3 , Ta 2 O 3 , Ta 2 O 3, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 , BaZrO, BaTiO 3 (BTO), (Ba, Sr)TiO 3 (BST), Si 3 N 4 , HfO 2 -Al 2 O 3 , other high-k dielectric materials or combinations thereof. For example, the gate dielectric layer 264 is a hafnium-based oxide (e.g., HfO 2 ) layer or a zirconium-based oxide (e.g., ZrO 2 ) layer. In some embodiments, the gate dielectric layer 264 has a multi-layer structure.

[0038] Refer to Figure 1 and Figures 8A to 11B , dipole engineering is implemented after forming the gate dielectric 260 to regulate the threshold voltage of the transistor T1. For example, the processes associated with blocks 130, 150, and 155 of method 100 can form dipoles in the gate dielectric 260 that shift the threshold voltage of the transistor T1. In some embodiments, the processes associated with block 130, block 150, and block 155 or combinations thereof are repeated, as indicated by arrows B1 and B2. The dipoles can be formed in the gate dielectric layer 264, and the process parameters associated with blocks 130, 150, and 155 of method 100 can be adjusted to achieve a desired threshold voltage shift and / or desired threshold voltage characteristics of the transistor T1. In the depicted embodiment, p-dipole dopants are incorporated into the gate dielectric 260 to change (e.g., lower) the threshold voltage of the transistor T1 configured as a p-type transistor or an n-type transistor. In some embodiments, the transistor T1 is configured as a p-type transistor. As described below, the disclosed dipole engineering techniques are threshold voltage regulation processes with improved efficiency.

[0039] Refer to Figure 1 and Figures 8A to 8B , method 100 includes forming a dipole dopant source layer 266 over the gate dielectric 260 at block 130. The dipole dopant source layer 266 is formed on the gate dielectric layer 264 and partially fills the gate opening 255. In the XZ plane, the dipole dopant source layer 266 covers the gate dielectric layer 264 and has a U-shaped profile in the top portion of the gate opening 255. In the YZ plane, the dipole dopant source layer 266 covers the gate dielectric layer 264 (e.g., on the exposed surface) and partially surrounds the mesa 202'.

[0040] In some embodiments, the dipole dopant source layer 266 is a metal-containing layer comprising a p-dipole dopant, and the p-dipole dopant can be driven into the gate dielectric layer 264 to change the threshold voltage of the transistor T1. For example, the dipole dopant source layer 266 includes a p-dipole dopant (e.g., a metal). In some embodiments, the dipole dopant source layer 266 includes chlorine, oxygen, nitrogen, carbon, or a combination thereof (e.g., a non-metal). In some embodiments, the p-dipole dopant is aluminum (Al) and the dipole dopant source layer 266 includes an aluminum layer.

[0041] Figure 9A An enlarged view of portion A1 of workpiece 200 in FIG. 8 is shown. Figures 9B to 9D Shows Figure 9A an enlarged view of the dipole dopant source layer 266. In Figure 9B the embodiment shown, the dipole dopant source layer 266 includes a single layer 266-1. The single layer 266-1 is an aluminum layer. In some embodiments, the aluminum layer includes aluminum equal to or greater than 90%. In some embodiments, the aluminum layer includes aluminum equal to or greater than 95%. If the aluminum in the aluminum layer is too low (e.g., less than 90%), the benefits from the aluminum layer (e.g., increased diffusion efficiency) may be too small. The aluminum layer may include less than about 10% chlorine, carbon, oxygen, or a combination thereof.

[0042] In Figure 9C the embodiment shown, the dipole dopant source layer 266 includes a sub-layer 266-1 and a sub-layer 266-2. In some embodiments, the sub-layers 266-1 and 266-2 include an aluminum layer and an aluminum oxide (AlOx) layer as described above. x can range from about 1 to about 1.5. The aluminum layer and the AlOx layer can be arranged in any order on the gate dielectric layer 264. In an example, the AlOx layer is disposed on the surface of the gate dielectric layer 264, and the aluminum layer is disposed above the AlOx layer (i.e., sub-layer 266-1 is the AlOx layer and sub-layer 266-2 is the aluminum layer). In another example, the aluminum layer is disposed on the surface of the gate dielectric layer 264 and the AlOx layer is disposed above the aluminum layer (i.e., sub-layer 266-1 is the aluminum layer and sub-layer 266-2 is the AlOx layer). In some embodiments, the sub-layers 266-1 and 266-2 include an aluminum layer and an aluminum nitride (AlN) layer as described above. The aluminum layer and the AlN layer can be arranged in any order on the gate dielectric layer 264. In an example, the AlN layer is disposed on the surface of the gate dielectric layer 264, and the aluminum layer is disposed above the AlN layer (i.e., sub-layer 266-1 is the AlN layer and sub-layer 266-2 is the aluminum layer). In another example, the aluminum layer is disposed on the surface of the gate dielectric layer 264 and the AlN layer is disposed above the aluminum layer (i.e., sub-layer 266-1 is the aluminum layer and sub-layer 266-2 is the AlN layer).

[0043] In Figure 9DIn the illustrated embodiment, the dipole dopant source layer 266 includes three sub-layers, such as sub-layer 266-1, sub-layer 266-2, and sub-layer 266-3. Sub-layers 266-1, 266-2, and 266-3 may include an aluminum layer, an AlOx layer, and an AlN layer as described above. The aluminum layer, the AlOx layer, and the AlN layer may be disposed on the gate dielectric layer 264 in any order. For example, the aluminum layer is disposed on the surface of the gate dielectric layer 264, the AlN layer is disposed above the aluminum layer, and the AlOx layer is disposed above the AlN layer (i.e., sub-layer 266-1 is the aluminum layer, sub-layer 266-2 is the AlN layer, and sub-layer 266-3 is the AlOx layer). In another example, the AlN layer is disposed on the surface of the gate dielectric layer 264, the aluminum layer is disposed above the AlN layer, and the AlOx layer is disposed above the aluminum layer (i.e., sub-layer 266-1 is the AlN layer, sub-layer 266-2 is the aluminum layer, and sub-layer 266-3 is the AlOx layer). In another example, the AlOx layer is disposed on the surface of the gate dielectric layer 264, the aluminum layer is disposed above the AlOx layer, and the AlN layer is disposed above the aluminum layer (i.e., sub-layer 266-1 is the AlOx layer, sub-layer 266-2 is the aluminum layer, and sub-layer 266-3 is the AlN layer).

[0044] The present disclosure contemplates other orders and combinations of the aluminum layer with the AlOx layer and / or the AlN layer. For example, the aluminum layer is sandwiched between two AlOx layers (i.e., sub-layer 266-1 is the first AlOx layer, sub-layer 266-2 is the aluminum layer, and sub-layer 266-3 is the second AlOx layer). In another example, the aluminum layer is sandwiched between two AlN layers (i.e., sub-layer 266-1 is the first AlN layer, sub-layer 266-2 is the aluminum layer, and sub-layer 266-3 is the second AlN layer). In some embodiments, the dipole dopant source layer 266 includes more than three sub-layers. In some embodiments, the dipole dopant source layer 266 includes other types of sub-layers, such as other metal oxide layers, other metal nitride layers. In the disclosed combinations, at least one sub-layer is an aluminum layer.

[0045] The dipole dopant source layer 266 may be formed using any suitable method. Referring to Figure 2 , in some embodiments, block 130 includes a method including block 132, wherein an aluminum layer is formed above the gate dielectric layer 264. In some embodiments, a deposition temperature of about 300 °C to about 480 °C may be used to form the aluminum layer. In some embodiments, a pressure of about 2 Torr to about 50 Torr may be used to form the aluminum layer. In some embodiments, the aluminum layer may be formed by an ALD process that sequentially flows a first precursor and a second precursor over the gate dielectric layer 264. Referring to Figure 3 , the method of block 132 may include block 134 of flowing aluminum chloride (AlCl 3)'s first precursor (e.g., the first precursor gas) flows over the gate dielectric layer 264 in the processing chamber. Molecules of the first precursor can adsorb on the surface of the workpiece 200 (e.g., the surface of the gate dielectric layer 264). In some embodiments, the first precursor forms a first monolayer on the surface of the gate dielectric layer 264. After flowing the first precursor, a first purge process is performed at block 136 using an inert gas such as argon (Ar) or nitrogen (N 2 ) to remove excess first precursor and / or any by-products from the processing chamber. The method of block 132 may also include block 138, which includes flowing a second precursor (e.g., the second precursor gas) including trimethylaluminum (TMA) over the gate dielectric layer 264 in the processing chamber. In some embodiments, molecules of the second precursor adsorb on the surface of the workpiece 200 (e.g., the first monolayer). In some embodiments, the second precursor forms a second monolayer on the first monolayer. The second precursor (e.g., in the second monolayer) may react with the first precursor (e.g., in the first monolayer) to form an aluminum sublayer. Without being limited by theory, the reaction is a surface reaction. In some embodiments, the aluminum sublayer is a monolayer. After flowing the second precursor, a second purge process using an inert gas such as Ar or N 2 is performed at block 140 to purge excess second precursor and / or any by-products from the processing chamber. Blocks 134, 136, 138, and 140 may be repeated for M cycles to form multiple aluminum sublayers that together form an aluminum layer and the total thickness of the aluminum sublayers meets the designed thickness of the aluminum layer. M is an integer. In some embodiments, Figure 3 the method of block 132 is an ALD process, and blocks 134, 136, 138, and 140 may be cycles of the ALD process. The cycles of the ALD process may be repeated until the aluminum layer has the desired thickness.

[0046] Return to reference Figure 2 , the method of block 130 optionally further includes block 142, where an AlOx dipole layer is formed above the gate dielectric, such as the AlOx layer formed above the gate dielectric layer 264 as described above, and / or optionally further includes block 144, where an AlN dipole layer is formed above the gate dielectric, such as the AlN layer formed above the gate dielectric layer 264 as described above. The formation of the AlOx layer and the formation of the AlN layer may include any suitable method, such as an ALD process and / or a CVD process.

[0047] At blocks 132, 142, and 144, workpiece 200 may be located in the same chamber or different chambers. The formation of the aluminum layer, AlOx layer, and AlN layer may be performed in a vacuum environment (e.g., 2 Torr to 50 Torr). In some embodiments, between the formation of two adjacent sub-layers, the method of block 130 may include breaking the vacuum (which may be referred to as having a vacuum break), where workpiece 200 is moved to a non-vacuum environment (e.g., atmosphere). For example, the vacuum may be broken between the formation of the aluminum layer and the AlOx layer and / or the AlN layer. The non-vacuum environment may include oxygen and / or water vapor. Blocks 132, 142, and 144 may be in any suitable order, depending on the order of the aluminum layer, AlN layer, and AlOx layer over gate dielectric layer 264.

[0048] The dipole dopant source layer 266 may have a substantially uniform thickness. In some embodiments, the thickness of the dipole dopant source layer 266 is from about 0.3 nm to about 4 nm. If the dipole dopant source layer 266 is too thin (e.g., less than 0.3 nm), it may not cover the gate dielectric layer 264 uniformly, which can affect the uniformity of the dipole engineering of the gate dielectric layer 264 and / or the uniformity of the threshold voltage tuning of transistor T1 (i.e., inconsistent threshold voltage tuning may occur). If the dipole dopant source layer 266 is too thick (e.g., greater than 4 nm), it may be difficult to remove and thus undesirably remain in the gate stack. For example, if too thick, residues of the dipole dopant source layer 266 may remain on the channel layer 202'. This can affect subsequent processes, e.g., leaving insufficient space for the gate (e.g., work function metal and / or body metal layer) to fill the gate opening 255 and / or causing transistor T1 to have electrical characteristics different from those expected (e.g., different threshold voltage). Additionally, the composition and thickness of the dipole dopant source layer 266 may be designed based on the desired amount of threshold voltage tuning. For example, a thicker dipole dopant source layer 266 may provide a greater threshold voltage change in transistor T1. In an embodiment, each sub-layer (e.g., the aluminum layer, AlN layer, and AlOx layer) has a uniform thickness. In some embodiments, the composition and thickness of each sub-layer may be designed together to achieve the desired threshold voltage.

[0049] Reference Figure 1 and Figures 10A to 10B, Method 100 includes performing a thermal drive-in process 270 at block 150, which drives (diffuses) dopants from the dipole dopant source layer 266 into the gate dielectric layer 264. For example, the thermal drive-in process 270 drives p-dipole dopants (e.g., aluminum) from the dipole dopant source layer 266 into the gate dielectric layer 264. The thermal drive-in process 270 can be an annealing process, such as rapid thermal annealing (RTA), millisecond annealing (MSA), microsecond annealing (μSA), microwave annealing, laser annealing, spike annealing, soak annealing, furnace annealing, other suitable annealing processes, or a combination thereof. In some embodiments, the thermal drive-in process 270 is performed in an inert gas environment, which includes, for example, argon (Ar), helium (He), nitrogen (N 2 ), other inert gases, or a combination thereof. In the depicted embodiment, aluminum can be driven from an aluminum layer into the gate dielectric layer 264. In some embodiments, aluminum can also be driven from an AlOx layer and / or an AlN layer into the gate dielectric layer 264, depending on which sub-layers are included in the dipole dopant source layer 266. Without being bound by theory, since the association energy of aluminum in the aluminum layer is less than the association energy of aluminum in the AlOx layer and / or the AlN layer, the diffusion efficiency of aluminum from the aluminum layer is greater than that from the AlOx layer and / or the AlN layer. Without being bound by theory, due to the relatively low association energy of aluminum in the aluminum layer, the average association energy of aluminum in the dipole dopant source layer 266 is reduced, which improves the diffusion efficiency of aluminum. In other words, by having an aluminum layer, the diffusion efficiency of aluminum from the dipole dopant source layer 266 to the gate dielectric layer 264 can be increased. For example, at a specific temperature and during a specific time period, the amount of aluminum diffusing from the dipole dopant source layer 266 into the gate dielectric layer 264 can be increased. In some embodiments, the amount of aluminum diffusing from the aluminum layer into the gate dielectric layer 264 can be greater than the amount of aluminum diffusing from the AlOx layer and / or the AlN layer into the gate dielectric layer 264. In some embodiments, during a specific time period for diffusing a certain amount of aluminum, the temperature required in the thermal drive-in process 270 can be reduced. Therefore, the increased efficiency can reduce the time of the thermal drive-in process 270 and / or lower the temperature, which can save the manufacturing time of the semiconductor device and / or reduce the impact on the existing structure and / or the surrounding structures of the transistor T1, and still be sufficient to enable the p-dipole dopants to migrate (or diffuse) into the gate dielectric layer 264.

[0050] After the thermal drive-in process 270, since the p-dipole dopants are driven into the gate dielectric layer 264, the gate dielectric layer 264 becomes the gate dielectric layer 264’ (i.e., the doped gate dielectric layer), as Figures 11A to 11B shown. For example, the gate dielectric layer 264’ is a high-k dielectric layer, such as a hafnium-based oxide (e.g., HfO 2 ) layer or a zirconium-based oxide (e.g., ZrO 2) layer, which also includes aluminum. In some embodiments, a p-dipole dopant (e.g., aluminum) also diffuses into the interface layer 262, such that the interface layer 262 becomes a doped interface layer 262. For example, the doped interface layer 262 can be a dielectric layer, such as a Group-IV III-V based oxide (e.g., SiO 2 ) layer or a Group-III-V based oxide layer, which further contains aluminum.

[0051] Reference Figure 1 and Figures 11A to 11B , method 100 includes removing the dipole dopant source layer 266 at block 155. By removing the dipole dopant source layer 266, the dipole engineering process of the present disclosure provides non-volumetric threshold voltage tuning. In other words, the dipole engineering process can tune the threshold voltage of the transistor T1 by driving a p-dipole dopant (e.g., aluminum) into the gate dielectric layer 264, but the material layer used for this threshold voltage tuning is not retained, so no volume of any final gate stack is consumed, such that the size of the gate opening 255 is maximized for subsequent gate formation. In some embodiments, the etching process selectively removes the dipole dopant source layer 266 relative to the gate dielectric layer 264'. For example, the etching process substantially removes the dipole dopant source layer 266, but does not remove or substantially does not remove the gate dielectric layer 264'. In some embodiments, an etchant of an etching process is selected that etches the dipole dopant source layer 266 (e.g., a separate aluminum layer or in combination with an AlN layer and / or an AlOx layer) at a higher rate than the gate dielectric layer 264' (e.g., an HfO 2 layer, a ZrO 2 layer, or another high-k dielectric material containing aluminum). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. As shown in the partial enlarged view of A2 in Figure 11B , a p-dipole dopant 275 (e.g., aluminum) has diffused into the gate dielectric layer 264.

[0052] The thickness of the gate dielectric layer 264 is designed such that the p-dipole dopant can effectively penetrate through the gate dielectric layer 264 to reach the interface 276 between the gate dielectric layer 264 and the interface layer 262. Additionally, the composition and / or thickness of the dipole dopant source layer 266, the composition and / or thickness of the gate dielectric layer 264, and the parameters of the thermal driving-in process 270 (e.g., driving-in temperature, time, environment, pressure, etc.) can be configured to provide a doped gate dielectric layer 264' having a desired dipole dopant concentration in the doped gate dielectric layer 264'. In some embodiments, the concentration of the p-dipole dopant gradually decreases from the top surface of the gate dielectric layer 264' to the interface 276 within the gate dielectric layer 264'.

[0053] Reference Figure 1 and Figures 12A to 12B, in some embodiments, method 100 includes forming an additional gate dielectric layer 268 over the gate dielectric layer 264' at block 160. Block 160 is optional. Figures 13A to 14B A workpiece 200 without block 160 is shown. The additional gate dielectric layer 268 may include a material similar to the undoped gate dielectric layer 264 and may be formed using a method similar to that of the undoped gate dielectric layer 264. The additional gate dielectric layer 268 may have a substantially uniform thickness. After forming the additional gate dielectric layer 268, p-dipole dopants 275 may be trapped within the gate dielectric layer 264'. In other words, most (e.g., greater than 95%) of the p-dipole dopants 275 diffused into the gate dielectric layer 264 remain within the gate dielectric layer 264 and do not diffuse into the additional gate dielectric layer 268 or the interface layer 262 during subsequent processes.

[0054] Reference Figure 1 and Figures 13A to 14B , at block 165 of method 100, a gate 280 is formed over the gate dielectric layer 264'. The gate 280 fills the remainder of the gate opening 255, and the gate 280 includes at least one conductive gate layer. The conductive gate layer includes a conductive material such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof.

[0055] Reference Figures 13A to 13B , in some embodiments, forming the gate 280 may include depositing a work function layer 282 over the gate dielectric layer 264', depositing a barrier layer 284 over the work function layer 282, and depositing a bulk (fill) layer 286 over the barrier layer 284. The work function layer 282 partially fills the gate opening 255, the barrier layer 284 partially fills the gate opening 255, and the bulk layer 286 fills the remainder of the gate opening 255. The work function layer 282 and the barrier layer 284 have a substantially uniform thickness. In some embodiments, each layer (work function layer 282, barrier layer 284, and bulk layer 286) of the gate 280 has a thickness of about 0.5 nm to about 5 nm. The work function layer 282, the barrier layer 284, and the bulk layer 286 may be formed by ALD, PVD, CVD, high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable processes, or combinations thereof.

[0056] The work function layer 282 is a conductive layer adjusted to have a desired work function, such as an n-type work function or a p-type work function. For example, in the case where the transistor T1 is configured as an n-type transistor or a p-type transistor, the work function layer 282 may include an n-type work function material or a p-type work function material, respectively. The n-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. The p-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 , MoSi 2 , TaSi 2 , NiSi 2 , WN, other p-type work function materials, or combinations thereof. In some embodiments, the work function layer 282 has a multi-layer structure. In some embodiments, by using the disclosed dipole dopant source layer 266 to drive p-dipole dopants (e.g., aluminum) into the gate dielectric layer 264, multiple threshold voltages can be flexibly provided for both p-type and n-type transistors even with the same work function material. This can eliminate the need to pattern the work function material, making the disclosed dipole engineering process very suitable for nano-scale transistors, such as FinFETs and GAA transistors.

[0057] The body layer 286 includes a suitable conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or their alloys, or combinations thereof. For example, the body layer 286 is a tungsten layer formed by PVD or CVD. In some embodiments, a barrier layer 284 is optionally formed (e.g., by ALD) above the work function layer 282 before forming the body layer 286, such that the barrier layer 284 is disposed between the body layer 286 and the work function layer 282. As shown, the barrier layer 284 includes materials that prevent or eliminate the diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers (e.g., between the work function layer 282 and the body layer 286). In some embodiments, the barrier layer 284 includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride (e.g., W 2 N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), other suitable metal nitrides, or combinations thereof.

[0058] Reference Figures 14A to 14B, A planarization process is performed to remove the excess gate material, such as the gate material disposed above the dielectric layer 250. For example, a CMP process is performed to remove the body layer 286, the barrier layer 284, the work function layer 282, and the gate dielectric layer 264' disposed above the dielectric layer 250. The CMP process is performed until the top surface of the dielectric layer 250 is reached (exposed). In some embodiments, the CMP process continues and reduces the thickness of the dielectric layer 250, and correspondingly reduces the height of the gate structure 220'. In the depicted embodiment, after the CMP process, the top of the gate structure 220' is substantially flush with the top of the dielectric layer 250, and the remaining portion of the gate material filling the gate opening 255 forms the gate stack of the gate structure 220'. As described above, the gate stack includes a gate dielectric 260 (e.g., an interface layer 262 and a gate dielectric layer 264' (and, in some embodiments, a gate dielectric layer 268)) and a gate 280 (e.g., a body layer 286, a barrier layer 284, and a work function layer 282). Since the gate dielectric layer 264' is a high-k dielectric layer, the gate stack can be referred to as a high-k / metal gate. In some embodiments not depicted, the process may further include etching back the gate 280 and / or the gate dielectric 260 (i.e., its gate dielectric layer 264') and forming a hard mask for the gate stack over the etched-back gate 280 and / or gate dielectric 260.

[0059] In some embodiments, the fabrication of the transistor T1 may also include forming various contacts that facilitate its operation. For example, similar to the dielectric layer 250, one or more dielectric layers may be formed over the gate structure 220' and the dielectric layer 250. Then, contacts may be formed in the dielectric layer 250 and / or the dielectric layer disposed above the dielectric layer 250. Then, contacts are formed that physically and / or electrically couple to the gate stack of the gate structure 220' (e.g., the gate 280) and at least one epitaxial source / drain 214 of the transistor T1, respectively. For example, source / drain contacts are formed in the dielectric layer 250, and the source / drain contacts are disposed on the epitaxial source / drain 214. The contacts include a conductive material, such as a metal. The metal includes aluminum, aluminum alloy (e.g., aluminum / silicon / copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, rubidium silicide, palladium silicide, or combinations thereof. In some embodiments, the dielectric layer disposed above the dielectric layer 250 and the contacts (e.g., gate contacts and / or source / drain contacts extending through the dielectric layer 250 and / or the dielectric layer disposed above it) are part of the MLI features disposed above the substrate 202.

[0060] In some embodiments, workpiece 200 includes a plurality of transistors (e.g., transistor T1), and each transistor includes a gate dielectric layer 264 in gate region 255. The plurality of transistors can be tuned to have various Vt's using method 100 described above in embodiments in combination with a dipole patterning process.

[0061] For example, Figure 15 FIG. shows an exemplary diagram of a dipole patterning process 300 that can be used in combination with blocks 130, 150, and 155 of method 100. The plurality of transistors can include gate regions 255 (e.g., 255-1, 255-2, … 255-n, 255-(n+1)). The dipole patterning process 300 can include n dipole cycles. n is an integer greater than 1. Each dipole cycle can include the patterning process and operations at block 130 as described above to form a dipole dopant source layer 266 in certain gate regions 255. The patterning process includes masking certain gate regions 255 while exposing other gate regions 255. Figure 15Shows a substrate 202, channels 202' (e.g., 202'-1, 202'-2, …, 202'-n, 202'-(n + 1)) above the substrate 202, interface layers 262 (e.g., 262-1, 262-2, …, 262-n, 262-(n + 1)) above the respective channels 202', and gate dielectric layers 264 (e.g., 264-1, 264-2, …, 264-n, 264-(n + 1)) above the respective interface layers 262. As shown, the first cycle DL1 of the n dipole cycles provides dopants to be driven into the gate dielectric layer 264 in the gate region 255-1, but not in the gate regions 255-2 to 255-(n + 1). In some examples (Method I), the first cycle DL1 includes forming a capping layer (e.g., a hard capping layer) above the gate regions 255-2 to 255-(n + 1), while using any suitable process to expose the gate region 255-1 (e.g., deposition, patterning using lithography, etching), depositing a dipole dopant source layer (e.g., as described in block 130) above the gate dielectric layer 264-1 in the gate region 255-1, while the capping layer covers the gate regions 255-2 to 255-(n + 1). Removing the capping layer from the gate regions 255-2 to 255-(n + 1) using any appropriate process, performing a thermal drive-in process to drive the dopants from the dipole dopant source layer into the gate dielectric layer 264-1 (e.g., as described in block 150), and removing the dipole dopant source layer from the gate region 255-1 (e.g., as described in block 155). In some alternative examples (Method II), the first cycle DL1 includes depositing a dipole dopant source layer (e.g., as described in block 130) above the gate dielectric layers 264 in the gate regions 255-1 to 255-(n + 1), forming a capping layer above the gate region 255-1 but exposing the gate regions 255-2 to 255-(n + 1), removing the dipole dopant source layer from the gate regions 255-2 to 255-(n + 1), removing the capping layer from the gate region 255-1, performing a thermal drive-in process to drive the dopants from the dipole dopant source layer into the gate dielectric layer 264-1 in the gate region 255-1 (e.g., as described in block 150), and removing the dipole dopant source layer in the gate region 255-1 (e.g., as described in block 155).

[0062] Then, a second cycle DL2 among the n dipole cycles provides dopants to be driven into the gate dielectric layers 264 in the gate regions 255-1 and 255-2, but not in the gate regions 255-3 to 255-(n+1). In some examples, the second cycle DL2 includes steps similar to the above-described Method I. In such examples, a mask is formed in the gate regions 255-3 to 255-(n+1), a dipole dopant source layer is deposited over the gate dielectric layers 264-1 and 264-2 in the gate regions 255-1 and 255-2, and a thermal drive-in process drives the dopants from the dipole dopant source layer into the gate dielectric layers 264-1 and 264-2. In some other examples, the second cycle DL2 includes steps similar to the steps disclosed in the above-described Method II. In such a cycle, a mask is formed in the gate regions 255-1 and 255-2, but the gate regions 255-3 to 255-(n+1) are exposed, and a thermal drive-in process drives the dopants from the dipole dopant source layer into the gate dielectric layers 264-1 and 264-2. Then, a third cycle DL3 among the n dipole cycles provides dopants to be driven into the gate dielectric layer 264 in the gate regions 255-1 to 255-3, but not in the gate regions 255-4 to 255-(n+1). The third cycle DL3 may include steps similar to the above-described Method I and Method II. For example, when the third cycle DL3 is performed, the gate regions 255-4 to 255-(n+1) are shielded. At the end of the third cycle DL3, the gate region 255-1 has undergone the dipole cycle process 3 times, the gate region 255-2 has undergone the dipole cycle process 2 times, the gate region 255-3 has undergone the dipole cycle process 1 time, and the gate regions 255-4 to 255-(n+1) have undergone the dipole cycle process 0 times.

[0063] Note that in the case of having an additional number of gate regions, additional dipole cycles can be performed. Each dipole cycle among the n dipole cycles (e.g., DL1, DL2, DL3) can increase the atomic concentration of dopants (e.g., aluminum) in the corresponding gate dielectric layer 264 by about 0% to about 5%. For example, the first cycle DL1 can drive the dopants into the gate dielectric layer 264-1, increasing the atomic concentration of the dopants (e.g., aluminum) in the gate dielectric layer 264-1 by about 0% to about 5%. For example, before the first cycle DL1, the atomic concentration of aluminum atoms in the gate dielectric layer 264-1 can be 0%; and after the first cycle DL1, the atomic concentration of aluminum in the gate dielectric layer 264-1 can increase to greater than 0% and less than or equal to about 5%. After the dipole patterning process 300, the gate 280 is deposited over the gate regions 255.

[0064] Note also that in the dipole patterning process 300, when method I is used for all n dipole cycles, after each of the n dipole cycles, the number of masked gate regions 255 is reduced until one gate region 255 is masked. This can be done by forming a mask in each dipole cycle as described above for method I. Alternatively, this can be done by removing a portion of the same original hard mask from one end (e.g., the right end) after each dipole cycle. When method I is used for all n dipole cycles, the thermal drive-in process and removal of the dipole dopant source layers (blocks 150 and 155) can be performed in each of the n dipole cycles. Alternatively, the thermal drive-in process and removal of the dipole dopant source layers can be performed together after all or some of the n dipole cycles are executed, driving different amounts of dopant from one or more of the dipole dopant source layers into the gate dielectric layer 264 in different gate regions and resulting in different dopant concentrations therein.

[0065] The resulting structure can include (n + 1) structures reflected in the embodiments of Figure 14A and 14B wherein the gate dielectric layers 264' of the n structures have various p-dipole dopant concentrations. The gate dielectric layer 264-(n + 1) in the gate region 255-(n + 1) is not subject to dipole engineering. Due to the number of cycles performed, the p-dipole dopant concentration varies from gate region 255-1 to 255-(n + 1) (e.g., the p-dipole dopant concentration can decrease from gate dielectric layer 264-1 to 264-(n + 1)). For example, performing 3 dipole cycles results in 4 different Vts for gate regions 255-1 to 255-4. In any case, in the dipole patterning process 300, where n is the number of dipole cycles, (n + 1) Vts are obtained. In other words, each cycle provides more than one Vt. For example, 1 cycle results in 2 Vts, 2 cycles result in 3 Vts, 3 cycles result in 4 Vts, and so on. Each Vt can be an NFET Vt or a PFET Vt. In some embodiments, each Vt is a PFET Vt.

[0066] As another example, Figure 16 is an exemplary diagram showing a dipole patterning process 400 that can be used in conjunction with blocks 130, 150, and 155 of method 100. Multiple transistors can include gate regions 255 (e.g., 255-1, 255-2,..., 255-8). In the exemplary illustration shown, the dipole patterning process 400 includes three dipole cycles. Each dipole cycle can include the steps in method I or method II as described above, such as including the patterning process and operations at block 130 as described above. In some embodiments, the patterning process includes masking certain gate regions 255 while exposing other gate regions 255. Figure 16A simplified version of a substrate 202, channels 202' (e.g., 202'-1, 202'-2, …, 202'-8) above the substrate 202, and interface layers 262 (e.g., 262-1, 262-2, …, 262-8) is shown. Above their respective channels 202', gate dielectric layers 264 (e.g., 264-1, 264-2, …, 264-8) are above their respective interface layers 262. After each of the 3 dipole cycles is performed, the operations of blocks 150 and 155 as described above are performed. In some embodiments, after all 3 dipole cycles are performed, the operations of blocks 150 and 155 as described above are performed. As shown, the first cycle DL1 is applied to gate regions 255-1 to 255-4, but not to gate regions 255-5 to 255-8. For example, when the first cycle DL1 is performed, gate regions 255-5 to 255-8 are shielded. Then, the second cycle DL2 is applied to gate regions 255-1, 255-2, 255-5, and 255-6, but not to gate regions 255-3, 255-4, 255-7, and 255-8. For example, when the second cycle DL2 is performed, gate regions 255-3, 255-4, 255-7, and 255-8 are shielded. Then, the third cycle DL3 is applied to gate regions 255-1, 255-3, 255-5, and 255-7, but not to gate regions 255-2, 255-4, 255-6, and 255-8. For example, when the third cycle DL3 is performed, gate regions 255-2, 255-4, 255-6, and 255-8 are shielded. By the end of the third cycle DL3, gate region 255-1 has undergone cycles DL1, DL2, and DL3, gate region 255-2 has undergone cycles DL1 and DL2, gate region 255-3 has undergone cycles DL1 and DL3. Gate region 255-4 has undergone cycle DL1, gate region 255-5 has undergone cycles DL2 and DL3, gate region 255-6 has undergone cycle DL2, gate region 255-7 has undergone cycle DL3, and gate region 255-8 has not undergone any DL cycles. Although some of the gate regions 255-1 to 255-8 have undergone the same number of dipole cycles (e.g., both gate regions 255-4 and 255-6 have undergone 1 dipole cycle), all gate regions 255 have undergone different combinations of dipole cycles (e.g., no two gate regions have undergone the same amount of the same dipole cycles and thus no two gate regions have the same dipole dopant concentration and / or the same dipole dopant composition). For example, both gate regions 255-4 and 255-7 have undergone 1 dipole cycle, but one has undergone DL1 and the other has undergone DL3. After the second dipole patterning process 400, a gate 280 is deposited above the gate regions 255.

[0067] By varying the amount of p-dipole dopant driven into the gate dielectric in each application cycle (e.g., more p-dipole dopant is driven in the first cycle, less in the second cycle, and even less in the third cycle), thus, 3 dipole cycles are performed, resulting in 8 different Vts across gate regions 255-1 to 255-8.

[0068] Figure 17 FIG. is an exemplary diagram showing the dipole patterning process 400, in which additional dipole cycles can be performed in the case of additional transistors having an additional number of gate regions 255. Figure 17 A more simplified version of the substrate 202, the channel 202' above the substrate 202, the interface layer 262 above the corresponding channel 202', and the gate dielectric layer 264 above the interface layer 262 is shown. In any case, in the dipole patterning process 400, where N is the number of dipole cycles, N cycles may result in 2N different Vts. In other words, each cycle doubles the Vt options (through patterning). For example, 1 cycle results in 2 Vts, 2 cycles result in 4 Vts, 3 cycles result in 8 Vts, and so on. After each of the N dipole cycles is performed, the operations at blocks 150 and 155 as described above are performed. In some embodiments, after all N dipole cycles are performed, the operations at blocks 150 and 155 as described above are performed. In some embodiments, each Vt is an NFET Vt or a PFET Vt. In an embodiment, each Vt is a PFET Vt. As shown, combining blocks 130, 150, and 155 of method 100 with the dipole patterning process 400 in each cycle number produces more threshold voltages than combining blocks 130, 150, and 155 of method 100 with the dipole patterning process 300.

[0069] The dipole patterning processes 300 and 400 target different gate regions 255 and can be implemented through any suitable lithography and patterning techniques. The patterning involved in the dipole patterning processes 300 and 400 can be achieved through any suitable method. These combinations allow for variation of the p-dipole dopant in the gate dielectric layer 264 of the workpiece 200.

[0070] As described above, the transistor T1 is fabricated as a FinFET. In such embodiments, the channel 202' is part of a semiconductor fin extending from the substrate 202. In such embodiments, the gate dielectric 260, the dipole dopant source layer 266, and the gate 280 are formed above the top and sidewalls of the semiconductor fin.

[0071] Although the above examples relate to the formation of FinFETs, the principles described herein can be applied to other semiconductor structures, such as planar transistors, GAA devices, stacked transistors, such as complementary field effect transistors (CFETs), etc.

[0072] In some other embodiments, the transistor is fabricated as a planar transistor. In such an embodiment, the gate stack is disposed on one side (e.g., the top surface) of the channel. For example, the channel is part of a semiconductor substrate, and the gate stack is disposed on the top surface of the semiconductor substrate in the XZ plane and the YZ plane. In such an embodiment, the gate dielectric 260, the dipole dopant source layer 266, and the gate 280 are formed above the top of the channel region of the semiconductor substrate.

[0073] In some other embodiments, the transistor is fabricated as a GAA transistor (i.e., a transistor having a gate surrounding at least one suspended channel (e.g., nanowire, nanosheet, nanorod, etc.), where at least one suspended channel, to distinguish it from the above FinFET transistor, the GAA transistor is referred to as transistor T2 as part of the alternative workpiece 500, e.g., in Figures 18A to 19B In comparison with the above description regarding Figures 1 to 17 the following disclosure briefly discusses the method 100 for applying the above-described embodiments to transistor T2 and exemplary differences of the dipole patterning processes 300 and 400 as shown in Figure 1 and Figures 15 to 17 Transistor T2 can be an n-type or p-type transistor. In some embodiments, transistor T2 is a p-type transistor. Note that the components shared by workpiece 200 and workpiece 500 are denoted with the same symbols in Figures 18A to 19B as in Figures 4 to 17

[0074] Referring to Figure 4 and Figures 18A to 19B workpiece 500 includes transistor T2, and transistor T2 includes a channel (e.g., channel layer 506), a mesa 202', source / drain (e.g., epitaxial source / drain 214), and a gate (e.g., the gate stack includes gate dielectric 260 and gate 280). The gate engages the channel extending between the source / drain, and current can flow between the source / drain during operation (e.g., between the source and the drain or vice versa). In the depicted embodiment, the gate is located on the top and bottom of the channel in the XZ plane, and the gate surrounds the channel in the YZ plane (e.g., the gate stack is disposed on the top, bottom, and sidewalls of channel layer 506). Transistor T2 can be an n-type or p-type GAA transistor. In some embodiments, transistor T2 is a p-type GAA transistor.

[0075] Referring to Figure 1 and Figures 18A to 18B ​, fabricating workpiece 500 at block 105 may include depositing semiconductor layer stack 510 (including first semiconductor layer 506 and a second semiconductor layer not depicted) over substrate 202 and patterning semiconductor layer stack 510 and optionally substrate 202 to form fin structures 204 (or active regions 204) extending from substrate 202. Fin structures 204 may include a patterned portion of semiconductor layer stack 510 (i.e., first semiconductor layer 506 and the second semiconductor layer) and a patterned portion of substrate 202 (i.e., mesa 202’). The composition of the first semiconductor layer 506 is different from the composition of the second semiconductor layer to achieve etch selectivity and / or different oxidation rates during subsequent processing. The first semiconductor layer 506 and the second semiconductor layer include different materials, composition atomic percentages, composition weight percentages, thicknesses, or combinations thereof to achieve a desired etch selectivity during an etching process, such as an etching process implemented to form a suspended channel layer in channel region C. For example, the first semiconductor layer 506 may be a silicon layer and the second semiconductor layer may be a silicon germanium layer. In some embodiments, the first semiconductor layer 506 and the second semiconductor layer are alternately epitaxially grown over substrate 202. In some embodiments, a lithography process and an etching process are used to pattern semiconductor layer stack 510. In some embodiments, fin structures 204 are formed through a fin fabrication process.

[0076] Workpiece 500 includes inner spacer 519 disposed under gate spacer 232 and along the sidewalls of the second semiconductor layer. Inner spacer 519 is disposed between and separates the second semiconductor layer and epitaxial source / drain 214. Inner spacer 519 is also disposed between adjacent first semiconductor layers 506 and between the bottommost first semiconductor layer 506 and mesa 202’. Inner spacer 519 includes a dielectric material, which includes silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbon oxynitride, etc. In some embodiments, inner spacer 519 includes a low-k dielectric material. In some embodiments, dopants (e.g., p-type dopants, n-type dopants, or combinations thereof) are driven into the dielectric material, and inner spacer 519 includes a doped dielectric material.

[0077] Reference Figure 1 and Figures 18A to 18B, in such an embodiment, after block 110, method 100 also includes block 115 of performing a channel release process. For example, the second semiconductor layer exposed by the gate opening 255 in the semiconductor layer stack 510 is selectively removed to form an air gap 261 between the first semiconductor layers 506 and between the first semiconductor layer 506 and the mesa 202', thereby suspending the first semiconductor layer 506 therein. In the depicted embodiment, two suspended first semiconductor layers 506 are vertically stacked in the Z direction and provide two channels through which current can flow between the epitaxial source / drain 214. The suspended first semiconductor layer 506 is thus hereinafter referred to as the channel layer 506. In embodiments where the workpiece is formed of FinFETs, planar transistors, or other types of transistors (such as transistor T1 described above), the channel release process may be omitted from method 100.

[0078] Reference Figure 1 and Figures 19A to 19B , at block 125, a gate dielectric 260 is formed in the gate opening 255 and above the channel layer 506. Figure 7A With Figure 7B embodiments including an interface layer 262 partially filling the gate opening 255 and the air gap 261 such that the interface layer 262 is located between the channel layer 506 and the gate dielectric layer 264 and between the mesa 202' and the gate dielectric layer 264. The interface layer 262 covers the top surface, the bottom surface of the channel layer 506, and the top surface of the mesa 202'. In the YZ plane, the interface layer 262 surrounds the channel layer 506 and covers the top surface of the mesa 202'. The gate dielectric layer 264 partially fills the gate opening 255 and the air gap 261 and is formed on the interface layer 262, the gate gap wall 232, the inner gap wall 519, the isolation feature 208, and the dielectric layer 250. In the YZ plane, the gate dielectric layer 264 surrounds the channel layer 506.

[0079] At block 130, a dipole dopant source layer 266 is formed on the gate dielectric layer 264 and partially fills the gate opening 255 and the air gap 261. With Figure 8A and 8B an example of the differences from the embodiments reflected in, including in the YZ plane the dipole dopant source layer 266 covering the gate dielectric layer 264 and surrounding the channel layer 506. Thus, the dipole dopant source layer 266 can be disposed between the channel layers 506 and between the channel layer 506 and the mesa 202'. In some embodiments, the dipole dopant source layer 266 fills the air gap 261.

[0080] At block 160, shown is with Figure 12A and Figure 12BExamples of differences in the embodiments reflected therein include that in the YZ plane, an additional gate dielectric layer 268 covers the gate dielectric layer 264' and surrounds the channel layer 506. Accordingly, the additional gate dielectric layer 268 can be disposed between the channel layers 506 and between the channel layer 506 and the mesa 202'. In some embodiments, the additional gate dielectric layer 268 fills the air gap 261.

[0081] At block 165, an example of a difference in the embodiment reflected in Figure 14A and Figure 14B is shown, including that the gate 280 (e.g., the work function layer 280, the barrier layer 282, the body layer 284) fills the remaining portion of the air gap 261. Accordingly, the gate 280 can be disposed between the channel layers 506 and between the channel layer 506 and the mesa 202'. In some embodiments, the gate 280 fills the air gap 261.

[0082] In some embodiments, the workpiece 500 includes a plurality of GAA transistors (e.g., transistor T2), which include a plurality of gate dielectric layers 264 in different gate regions 255, wherein the gate stack is designed to have different Vt for the plurality of GAA transistors. The above dipole patterning processes 300 and 400 can also be applied to the workpiece 500.

[0083] Figure 20 Another alternative workpiece 600 including stacked transistors (e.g., complementary field effect transistors (CFETs)) is shown, which can provide further density reduction for advanced IC technology nodes (especially when the IC technology node advances to 3 nm (N3) and below). Note that in Figure 20 the components common to the workpieces 200, 500, and 600 are denoted by the same symbols as Figures 4 to 19B but with the endings "A" or "B".

[0084] In an embodiment, the workpiece 600 includes devices 612A, devices 612B, a substrate 202, and an insulating layer 616. The devices 612B are vertically stacked above the devices 612A, and the insulating layer 616 is disposed between the devices 612B and the devices 612A and separates the devices 612B from the devices 612A. The devices 612A and the devices 612B are disposed above the substrate 202. In the depicted embodiment, the devices 612A and the devices 612B are stacked from back to front. For example, the back surface of the device 612B is attached and / or bonded to the front surface of the device 612A through the insulating layer 616, and the insulating layer 616 includes an insulating layer 616A and an insulating layer 616B. In some embodiments, the insulating layer 616A is formed on the front surface of the device 612A, the insulating layer 616B is formed on the back surface of the device 612B, and the insulating layer 616B is attached to the insulating layer 616A. For clarity, Figure 20has been simplified to better understand the inventive concept of the present disclosure. Additional features can be added to the workpiece 600, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the workpiece 600.

[0085] Devices 612A and 612B each include at least one electrical functional device, such as transistor TA and transistor TB, respectively. Thus, the workpiece 600 includes a transistor stack having a top transistor (e.g., transistor TB) and a bottom transistor (e.g., transistor TA) separated and isolated by an insulating layer 616. In some embodiments, transistors TA and TB are transistor types with opposite conductivities. For example, transistor TA is an n-type transistor and transistor TB is a p-type transistor, or vice versa. In such embodiments, transistors TA and TB form a CFET. In some embodiments, transistors TA and TB are transistors of the same conductivity type. For example, both transistors TA and TB are n-type transistors or p-type transistors.

[0086] In the depicted embodiment, transistors TA and TB are GAA transistors similar to transistor T2 described above. Devices 612A and 612B can each include various features and / or components, such as semiconductor layers 506A / 506B, inner spacer walls 519A / 519B, epitaxial source / drain 214A / 214B and a gate structure

[0087] 220A’ / 220B’, similar to those described herein. The gate stack can also include a hard mask layer 642A / 642B, such as a self-aligned capping (SAC) layer. The hard mask layer 642A / 642B can include a dielectric material, such as silicon nitride. Devices 612A and 612B can also include source / drain contacts 651A / 651B disposed on the epitaxial source / drain 214A / 214B.

[0088] Transistors (e.g., transistors TA and TB) of a stacked transistor structure such as the workpiece 600 can be fabricated separately, monolithically, or sequentially. When fabricated separately, the top transistor and the bottom transistor can be fabricated separately and then the top transistor is bonded / attached to the bottom transistor. When fabricated monolithically, the top transistor and the bottom transistor are fabricated from an initial device precursor. For example, a first set of semiconductor layers can be bonded / attached to a second set of semiconductor layers and then processed separately to form the top transistor and the bottom transistor. When fabricated sequentially, a first set of semiconductor layers can be processed to form the bottom transistor, and then a second set of semiconductor layers is attached / bonded to the bottom transistor and processed to form the top transistor (i.e., the top transistor is fabricated on the bottom transistor).

[0089] A first device that forms a stacked device structure, such as device 612A for workpiece 600, can be formed similar to that of workpiece 500 described above. Similar to gate dielectric 260, dipole engineering is performed on gate dielectric 260A during the gate replacement process such that gate dielectric 260A also includes p-dipole dopant aluminum.

[0090] The fabrication of device 612A can also include forming interconnects of device 612A, such as gate contacts and / or source / drain contacts 651A. In some embodiments, forming source / drain contact 651A includes forming a source / drain contact opening in dielectric layer 250A that exposes epitaxial source / drain 214A, and forming at least one layer of conductive layer (e.g., metal) in the source / drain contact opening. The source / drain contact can include a metal silicide layer, a barrier / liner layer, and a bulk metal layer, where the barrier / liner layer is located between the bulk metal layer and dielectric layer 250A (e.g., CESL 254A) and between the bulk metal layer and the metal silicide layer. In some embodiments, one or more insulating layers can be formed in the source / drain contact opening and processed to form contact sidewalls, such as dielectric layers and / or air gaps, along the sidewalls of the conductive portions (e.g., barrier layer and / or bulk metal layer) of source / drain contact 651A.

[0091] Then, device 612A of workpiece 600 and a second device of the stacked device structure (e.g., a precursor for manufacturing device 612B) can be attached and / or bonded. The precursor for manufacturing device 612B can include a semiconductor layer stack 510B disposed over a substrate (not shown). In some embodiments, the substrate is a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate is a carrier substrate that includes silicon, soda-lime glass, fused silica, fused quartz, calcium fluoride, other suitable carrier substrate materials, or combinations thereof.

[0092] As Figure 20 shown, device 612A is bonded and / or attached to the precursor of device 612B through insulating layer 616 (also referred to as a bonding layer). In some embodiments, dielectric-dielectric bonding is used to bond device 612A to the precursor. In some embodiments, insulating layer 616 is an oxide layer that attaches device 612A to the precursor for manufacturing device 612B. In some embodiments, the dielectric-dielectric bonding process is an oxide-to-oxide bonding process that includes bonding an oxide layer formed on device 612A to an oxide layer formed on the precursor of device 612B. In some embodiments, the thickness of insulating (bonding) layer 616 is from about 10 nm to about 100 μm.

[0093] After bonding, a thinning process and / or a liftoff process may be performed to remove the substrate from the front side of device 612B. For example, a planarization process such as CMP or an etching process may be performed to remove the substrate. When removing the substrate, the top second semiconductor layer of semiconductor layer stack 510B may be used as a CMP stop layer and / or an etch stop layer. Thereafter, the top second semiconductor layer may be removed from semiconductor layer stack 510B, for example, via an etching process. Removing the top second semiconductor layer provides device 612B with a top first semiconductor layer 506B, which will provide the top channel of device 612B as described herein. Other methods and / or techniques for removing the substrate and / or the top second semiconductor layer are contemplated.

[0094] Thereafter, similar to the formation of device 612A and workpiece 500 as described above, a second device of a stacked device structure is formed, such as device 612B of workpiece 600.

[0095] Since device 612B is fabricated on device 612A, the processes implemented to form transistor TB (e.g., its gate stack) may have a negative impact on the characteristics and / or reliability of device 612A. For example, a high-temperature process may undesirably change the doping profile of transistor TA, which may undesirably change its threshold voltage, and / or reduce the structural integrity of transistor TA, which may undesirably reduce its reliability. To minimize and / or eliminate such negative impacts, the gate stack and channel layer 506B of transistor TB are formed as described above such that the temperature or time of the thermal drive-in process at block 150 can be reduced. For example, the process may include performing the disclosed dipole engineering process on gate dielectric layer 264B to form doped gate dielectric layer 264B'.

[0096] The gate stack of transistor TA may be configured to be the same as or different from the gate stack of transistor TB. In some embodiments, since transistor TA is configured as an n-type transistor and transistor TB is configured as a p-type transistor, or vice versa, gate dielectric 260A and gate dielectric 260B may include different dipole dopant conduction types. For example, the gate dielectric of an n-type transistor includes an n-dipole dopant (e.g., lanthanum), while the gate dielectric of a p-type transistor includes a p-dipole dopant (e.g., aluminum) driven in from the disclosed dipole dopant source layer. Additionally, in such examples, gate 280A and gate 280B may include different work function materials. For example, the gate of an n-type transistor may include an n-type work function material, and the gate of a p-type transistor may include a p-type work function material. In some embodiments, gate dielectric 260A and gate dielectric 260B include different dipole dopant conduction types, and gate 280A and gate 280B include the same conductive material (e.g., the same work function material).

[0097] In some embodiments where both transistor TA and transistor TB are configured as the same type of transistor (e.g., a p-type transistor), gate dielectrics 260A and 260B include the same dipole dopant conduction type (e.g., p-dipole dopants). Since transistor TA is the bottom transistor of workpiece 600 and is thus fabricated first, the fabrication of transistor TA does not affect the already fabricated device and the process temperature, such as the thermal drive-in temperature and time, can be relaxed. For example, in some embodiments, gate dielectric 260A may include p-dipole dopants (e.g., aluminum) driven in from a first dipole dopant source layer that does not include an aluminum layer at a first temperature and for a first time period, while gate dielectric 260B may include p-dipole dopants driven in from a second dipole dopant source layer that includes an aluminum layer at a second temperature and for a second time period. The second temperature may be lower than the first temperature, and / or the second time period may be less than the first time period. In some other embodiments, gate dielectric 260A and gate dielectric 260B include the same p-dipole dopant aluminum, and the first and second dipole dopant source layers may both include the aluminum layer disclosed herein. In such embodiments, for both gate dielectric 260A and gate dielectric 260B, the thermal drive-in temperature and / or time period for driving in the p-dipole dopant aluminum can be reduced.

[0098] In some embodiments, workpiece 600 includes a stacked device structure that includes a plurality of transistors (e.g., transistors TA and TB). The plurality of transistors may include a plurality of gate dielectric layers in different gate regions, where the gate stacks are designed to have different Vts for the plurality of transistors. The above dipole patterning processes 300 and 400 can also be applied to workpiece 600.

[0099] The devices and / or structures described herein, such as workpieces 200, 500, and 600, etc., may be included in a microprocessor, memory, other IC devices, or combinations thereof. In some embodiments, the structures described herein are part of an IC chip, a system-on-chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), stacked device structures, complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other components, or combinations thereof.

[0100] The present disclosure provides a method for fabricating a gate stack (e.g., high-k / metal gate) that implements dipole engineering using a dipole dopant source layer including an aluminum layer, and provides many advantages. The temperature and / or duration of the thermal drive-in process of the semiconductor structure can be reduced, which can reduce the negative impact on the existing parts of the semiconductor structure. The disclosed method also provides volume-free threshold voltage (Vt) tuning without changing the metal gate structure dimensions from one device to another. Another exemplary advantage is that the dopant concentration in different gate regions can be flexibly changed.

[0101] The gate stack can be implemented in a variety of device types. For example, the gate stacks described herein are applicable to planar field-effect transistors (FETs), multi-gate transistors such as FinFETs, GAA transistors, omega-gate (Ω-gate) devices, pi-gate devices, stacked device structures, or combinations thereof, as well as strained semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI devices, fully depleted SOI devices, other devices, or combinations thereof. The present disclosure also anticipates that one of ordinary skill in the art will recognize that other semiconductor devices can benefit from the material layer stacks and dipole engineering techniques described herein, such as capacitors.

[0102] An exemplary method for forming a gate stack for a transistor includes forming a high-k dielectric layer, forming a p-dipole dopant source layer over the high-k dielectric layer, performing a thermal drive-in process that drives aluminum from the p-dipole dopant source layer into the high-k dielectric layer, and forming at least one conductive gate layer over the high-k dielectric layer after removing the p-dipole dopant source layer. The p-dipole dopant source layer includes an aluminum layer.

[0103] In some embodiments, the p-dipole dopant source layer further includes an aluminum oxide layer. In some embodiments, the formation of the p-dipole dopant source layer includes forming an aluminum layer over the high-k dielectric layer and forming an aluminum oxide layer over the aluminum layer. In some embodiments, the formation of the p-dipole dopant source layer includes forming an aluminum oxide layer over the high-k dielectric layer and forming an aluminum layer over the aluminum oxide layer. In some embodiments, the p-dipole dopant source layer further includes an aluminum nitride layer. In some embodiments, the p-dipole dopant source layer further includes an aluminum oxide layer and an aluminum nitride layer. In some embodiments, the formation of the p-dipole dopant source layer includes using aluminum chloride (AlCl 3)Precursor and trimethylaluminum (TMA) precursor form an aluminum layer. In some embodiments, the transistor includes a channel layer stack, and forming the high-k dielectric layer includes forming a high-k dielectric layer around each channel layer of the channel layer stack. In some embodiments, the p-dipole dopant source layer is the first p-dipole dopant source layer and the thermal drive-in process is the first thermal drive-in process, and the method further includes forming a second p-dipole dopant source layer over the high-k dielectric layer and performing a second thermal drive-in process to drive aluminum from the second p-dipole dopant source layer into the high-k dielectric layer. In some embodiments, the high-k dielectric layer is the first high-k dielectric layer, and the method further includes forming a second high-k dielectric layer over the first high-k dielectric layer after removing the p-dipole dopant source layer and before forming at least one conductive gate layer over the high-k dielectric layer.

[0104] Another exemplary method includes forming a first interface layer over a first channel member and a second interface layer over a second channel member, forming a first gate dielectric over the first interface layer and a second gate dielectric over the second interface layer, performing a dipole engineering process including a dipole cycle, and forming a gate over the first gate dielectric and the second gate dielectric. The dipole cycle includes performing an atomic layer deposition (ALD) process to form an aluminum layer over the first gate dielectric but not over the second gate dielectric, performing a thermal drive-in process to drive aluminum from the aluminum layer into the first gate dielectric, thereby increasing the aluminum layer to reduce the concentration in the first gate dielectric by about 5%, and removing the aluminum layer.

[0105] In some embodiments, the cycle of the ALD process includes flowing a first deposition gas into the processing chamber, performing a first purge process, flowing a second deposition gas into the processing chamber, and performing a second purge process. The first deposition gas includes aluminum chloride (AlCl 3) The second deposition gas includes trimethylaluminum (TMA). The method includes repeating the cycles of the ALD process until the aluminum layer has a target thickness. In some embodiments, the ALD process is a first ALD process, and the dipole cycle further includes performing a second ALD process to form an aluminum oxide layer over the first gate dielectric, and the performance of the thermal driving-in process further drives aluminum from the aluminum oxide layer into the first gate dielectric. In some embodiments, the ALD process is a first ALD process, and the dipole cycle further includes performing a second ALD process to form an aluminum nitride layer over the first gate dielectric, and the performance of the thermal driving-in process further drives aluminum from the aluminum nitride layer into the first gate dielectric. In some embodiments, the ALD process is a first ALD process, and the dipole cycle further includes performing a second ALD process to form an aluminum oxide layer over the first gate dielectric, performing a third ALD process to form an aluminum nitride layer over the first gate dielectric, and the performance of the thermal driving-in process further drives aluminum from the aluminum oxide layer and the aluminum nitride layer into the first gate dielectric. In some embodiments, the dipole cycle is a first dipole cycle, the aluminum layer is a first aluminum layer, the ALD process is a first ALD process, the thermal driving-in process is a first thermal driving-in process, and the dipole engineering process further includes a second dipole cycle. The second dipole cycle includes performing a second ALD process to form a second aluminum layer over the second gate dielectric, performing a second thermal driving-in process that drives aluminum from the second aluminum layer into the second gate dielectric, thereby increasing the aluminum concentration in the second gate dielectric by less than about 5%, and removing the second aluminum layer. In some embodiments, performing the second ALD process further forms a second aluminum layer over the first gate dielectric, and performing the second thermal driving-in process further drives aluminum from the second aluminum layer into the first gate dielectric, thereby increasing the aluminum concentration in the first gate dielectric by less than about 5%.

[0106] An exemplary method includes forming a device including a first gate region and a second gate region. The first gate region includes a first channel member, a first gate dielectric over the first channel member, and a first gate layer over the first gate dielectric. The second gate region includes a second channel member, a second gate dielectric over the second channel member, and a second gate layer over the second gate dielectric. The first gate dielectric and the second gate dielectric include different concentrations of aluminum. Forming the device includes forming an aluminum layer over the first gate dielectric but not over the second gate dielectric, performing an annealing process that drives aluminum from the aluminum layer into the first gate dielectric, thereby increasing the atomic concentration of aluminum in the first gate dielectric by less than about 5%, removing the aluminum layer, and forming a first gate layer over the first gate dielectric and a second gate layer over the second gate dielectric.

[0107] In some embodiments, the aluminum layer is a first aluminum layer and the annealing process is a first annealing process. The formation of the device further includes forming a second aluminum layer over the first gate dielectric and the second gate dielectric, performing a second annealing process to drive aluminum from the second aluminum layer into the first gate dielectric and the second gate dielectric, thereby increasing the atomic concentration of aluminum in the second gate dielectric and the atomic concentration of aluminum in the first gate dielectric to less than about 5%, and removing the second aluminum layer. In some embodiments, the device further includes a third gate region. The third gate region includes a third channel member, a third gate dielectric over the third channel member, and a third gate layer over the third gate dielectric. The first gate dielectric, the second gate dielectric, and the third gate dielectric include different concentrations of aluminum. The formation of the device further includes forming a third aluminum layer over the first gate dielectric, the second gate dielectric, and the third gate dielectric, performing a third annealing process to drive aluminum from the third aluminum layer into the first gate dielectric, the second gate dielectric, and the third gate dielectric, and removing the third aluminum layer.

[0108] The features of several embodiments are outlined above so that those skilled in the art may better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a transistor gate stack, characterized in that: include: forming a high dielectric constant dielectric layer; forming a p-dipole dopant source layer over the high-k dielectric layer, wherein the p-dipole dopant source layer comprises an aluminum layer; performing a thermal drive-in process to drive aluminum from the p-dipole dopant source layer into the high-k dielectric layer; and After removing the p-dipole dopant source layer, at least one conductive gate layer is formed above the high-k dielectric layer.

2. The method according to claim 1, characterized in that: The p-dipole dopant source layer also includes an aluminum oxide layer.

3. The method according to claim 1, characterized in that The p-dipole dopant source layer also includes an aluminum nitride layer.

4. The method according to claim 1, characterized in that: Forming the p-dipole dopant source layer includes forming the aluminum layer using an aluminum chloride precursor and a trimethylaluminum precursor.

5. The method according to claim 1, characterized in that The p-dipole dopant source layer is a first p-dipole dopant source layer, and the thermal drive-in process is a first thermal drive-in process; as well as The method further comprises: forming a second p-dipole dopant source layer over the high-k dielectric layer, and A second thermal drive-in process is performed to drive aluminum from the second p-dipole dopant source layer into the high-k dielectric layer.

6. A method for forming a transistor gate stack, characterized in that: include: forming a first interface layer over the first channel member and forming a second interface layer over the second channel member; forming a first gate dielectric over the first interface layer and forming a second gate dielectric over the second interface layer; performing a dipole engineering process comprising a dipole cycle, wherein the dipole cycle comprises: performing an atomic layer deposition process to form an aluminum layer over the first gate dielectric but not over the second gate dielectric, performing a thermal drive-in process to drive aluminum from the aluminum layer into the first gate dielectric, thereby increasing the aluminum concentration in the first gate dielectric by less than about 5%, and removing the aluminum layer; and A gate is formed over the first gate dielectric and the second gate dielectric.

7. The method according to claim 6, characterized in that The atomic layer deposition process is a first atomic layer deposition process; as well as The dipole cycle also includes: performing a second atomic layer deposition process to form an aluminum oxide layer over the first gate dielectric, performing a third atomic layer deposition process to form an aluminum nitride layer over the first gate dielectric, and The thermal drive-in process is performed to further drive aluminum from the aluminum oxide layer and the aluminum nitride layer into the first gate dielectric.

8. The method according to claim 6, characterized in that The dipole cycle is a first dipole cycle, the aluminum layer is a first aluminum layer, the atomic layer deposition process is a first atomic layer deposition process, the thermal drive-in process is a first thermal drive-in process, and The dipole engineering process also includes a second dipole cycle, including: performing a second atomic layer deposition process to form a second aluminum layer over the second gate dielectric, performing a second thermal drive-in process to drive aluminum from the second aluminum layer into the second gate dielectric, thereby increasing the aluminum concentration in the second gate dielectric by less than about 5%, and The second aluminum layer is removed.

9. A method for forming a transistor gate stack, characterized in that: include: forming a device including a first gate region and a second gate region, wherein the first gate region includes a first channel component, a first gate dielectric above the first channel component, and a first gate layer above the first gate dielectric, wherein the second gate region includes a second channel component, a second gate dielectric above the second channel component, and a second gate layer above the second gate dielectric, wherein the first gate dielectric and the second gate dielectric include different concentrations of aluminum, and Wherein forming the device comprises: forming an aluminum layer over the first gate dielectric but not over the second gate dielectric, performing an annealing process to drive aluminum from the aluminum layer into the first gate dielectric, thereby increasing the concentration of aluminum atoms in the first gate dielectric to less than about 5%, removing the aluminum layer, and The first gate layer is formed over the first gate dielectric and the second gate layer is formed over the second gate dielectric.

10. The method according to claim 9, characterized in that The aluminum layer is a first aluminum layer, the annealing process is a first annealing process, and Forming the device also includes: forming a second aluminum layer over the first gate dielectric and the second gate dielectric, performing a second annealing process to drive aluminum from the second aluminum layer into the first gate dielectric and the second gate dielectric, thereby increasing the aluminum atomic concentration in the second gate dielectric and the aluminum atomic concentration in the first gate dielectric to less than about 5%, and The second aluminum layer is removed.

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