Semiconductor structure and manufacturing method thereof, semiconductor device and electronic equipment
By designing a special layout of heavily doped drain structure, intrinsic region, source structure and channel structure in the semiconductor structure, the problem of large leakage current of the ionization-positive feedback transistor in the off state is solved, and the effect of reducing leakage current and increasing the open state current is achieved.
Patent Information
- Application Number
- CN202311590824.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-24
- Publication Date
- 2025-05-30
AI Technical Summary
The leakage current of the ionization-positive feedback transistor is relatively large in the off state, which affects its performance.
A semiconductor structure is designed, in which the heavily doped drain structure, intrinsic region, source structure and channel structure are all arranged on the substrate, the channel structure is located between the intrinsic region and the source structure, the intrinsic region is in contact with the heavily doped drain structure and channel structure, the gate structure is arranged on the side of the channel structure facing away from the substrate, the gate structure is in contact with the channel structure, and at least part of the intrinsic region is located outside the gate structure.
By increasing the minority tunneling barrier, the leakage current of the transistor in the closed state is reduced, the performance of the semiconductor structure is increased, and the heavily doped drain structure and metal contact form an ohmic contact, increasing the open state current.
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Figure CN120076369A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor structure technology, and specifically to a semiconductor structure and a manufacturing method thereof, a semiconductor device and an electronic device. Background Art
[0002] The impact ionization feedback field effect transistor (II-FB-FET) includes a gate, a metal drain, a source, and a channel. The channel is located between the metal drain and the source. The channel is in contact with both the metal drain and the source. The gate is in contact with the channel. When working, the majority carriers (electrons, taking NMOS as an example) in the strong electric field region between the metal drain and the channel under the source-drain voltage collide and ionize to produce electron-hole pairs. The minority carriers (holes, taking NMOS as an example) are swept into the silicon on insulator (SOI) floating body under the action of the electric field to reduce the potential barrier of the electrons. The electrons further trigger collision ionization to form a positive feedback to turn on the transistor. The switching process of its transfer characteristics is steep, and the subthreshold swing (SS) is extremely low. However, when this transistor is in the off state, the leakage current between the metal drain and the source is large. Summary of the invention
[0003] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, a semiconductor device and an electronic device, which are intended to reduce the leakage current of an ionization-positive feedback transistor.
[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure, including a transistor, wherein the transistor includes: a gate structure, a substrate, and an intrinsic region, a heavily doped drain structure, a source structure, and a channel structure arranged on the substrate, the channel structure is located between the intrinsic region and the source structure, and the intrinsic region is in contact with both the heavily doped drain structure and the channel structure; the gate structure is arranged on a side of the channel structure away from the substrate, the gate structure is in contact with the channel structure, and at least part of the intrinsic region is located outside the gate structure.
[0005] Through the above arrangement, the heavily doped drain structure, the intrinsic region, the source structure and the channel structure are all arranged on the substrate, the channel structure is located between the intrinsic region and the source structure, the intrinsic region is in contact with both the heavily doped drain structure and the channel structure, the gate structure is arranged on the side of the channel structure away from the substrate, the gate structure is in contact with the channel structure, and at least part of the intrinsic region is located outside the gate structure. The drain of the transistor is a heavily doped drain structure, and the concentration of doped ions in the heavily doped drain structure is high, which can increase the minority carrier (hole, taking NMOS as an example) tunneling barrier, thereby reducing the leakage of the transistor in the off state, increasing the performance of the semiconductor structure, and at the same time, the heavily doped drain structure and the metal contact can form an ohmic contact, which is not limited by the metal semiconductor contact barrier, and increases the on-state current.
[0006] In some embodiments that may include the above embodiments, the doping concentration of the heavily doped drain structure is 1e19 cm -3 -1e21 cm -3 . With such a setting, on the premise of ensuring that the transistor has a small leakage current, the doping concentration of the heavily doped drain structure is not too high or too low, reducing the manufacturing difficulty of the semiconductor structure.
[0007] In some embodiments that may include the above embodiments, the doping concentration of the intrinsic region is less than 1e16 cm -3 . With such a setting, the doping concentration of the intrinsic region is small, and there is no need to additionally dope the intrinsic region to reduce the manufacturing difficulty.
[0008] In some embodiments that may include the above embodiments, along the carrier transport direction, the length of the intrinsic region is 10 nm - 50 nm. It can be understood that by adjusting the length of the intrinsic region, the ultra-steep switching range, the leakage current in the off state, and the hysteresis of the transistor can be adjusted. By making the length of the intrinsic region 10 nm - 50 nm, the performance of the ultra-steep switching range, the leakage current in the off state, and the hysteresis of the transistor can be balanced to improve the performance of the transistor.
[0009] In some embodiments that may include the above embodiments, the heavily doped drain structure is located on the side of the intrinsic region away from the channel structure. That is to say, the heavily doped drain structure, the intrinsic region, and the channel structure can be arranged in approximately the same layer; correspondingly, the interface between the heavily doped drain structure and the intrinsic region is located on the side of the intrinsic region away from the channel. With such a setting, during manufacturing, the semiconductor materials of the heavily doped drain structure, the intrinsic region, and the channel structure can be formed simultaneously, and then ion doping can be performed separately, reducing the manufacturing difficulty of the semiconductor structure.
[0010] In some embodiments that may include the above embodiments, the heavily doped drain structure is located on the side of the intrinsic region away from the substrate. That is to say, the intrinsic region and the source structure are arranged in approximately the same layer, and the interface between the heavily doped drain structure and the intrinsic region is located on the side of the intrinsic region away from the substrate, that is, this interface can correspond to the gate structure. With such a setting, the projected area of the transistor structure on the substrate can be reduced, facilitating the miniaturization of the semiconductor structure and semiconductor device.
[0011] In some embodiments that may include the above embodiments, the doping concentration of the channel structure is 1e17 cm -3 -1e20 cm -3 . With such a setting, the doping concentration of the channel structure is moderate, reducing the manufacturing difficulty of the semiconductor structure.
[0012] In some embodiments that may include the above embodiments, the source structure is a heavily doped structure. With such a setting, the doping concentration of the source structure is relatively high, which can reduce the resistance of the source structure.
[0013] In some embodiments that may include the above embodiments, the doping concentration of the source structure is 1e19 cm -3 -1e21 cm -3 . Through the above setting, the doping concentration of the source structure is close to that of the heavily doped drain structure, and the source structure and the heavily doped drain structure can be formed simultaneously to reduce the manufacturing difficulty.
[0014] In some embodiments that may include the above embodiments, the gate structure includes a gate conductive layer and a gate dielectric layer, and the gate dielectric layer is located between the gate conductive layer and the channel structure. By controlling the voltage of the gate conductive layer, the on and off of the transistor can be controlled.
[0015] In a second aspect, an embodiment of the present application further provides a semiconductor device, including: a circuit board and the semiconductor structure as described above, and the semiconductor structure is disposed on the circuit board.
[0016] The semiconductor device provided by the embodiment of the present application includes the semiconductor structure in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.
[0017] In a third aspect, an embodiment of the present application further provides an electronic device, including: a housing and the semiconductor device as described above, and the semiconductor device is disposed on the housing.
[0018] The electronic device provided by the embodiment of the present application includes the semiconductor device in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.
[0019] In a fourth aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a source structure, an intrinsic region, a channel structure, and a heavily doped drain structure on the substrate, the channel structure is located between the intrinsic region and the source structure, and the intrinsic region is in contact with both the heavily doped drain structure and the channel structure; forming a gate structure on a side of the channel structure facing away from the substrate, the gate structure is in contact with the channel structure, and at least part of the intrinsic region is located outside the gate structure.
[0020] For the semiconductor structure fabricated by the semiconductor structure fabrication method provided in the embodiments of the present application, a heavily doped drain structure, an intrinsic region, a source structure, and a channel structure are all disposed on a substrate. The channel structure is located between the intrinsic region and the source structure. The intrinsic region is in contact with both the heavily doped drain structure and the channel structure. A gate structure is disposed on a side of the channel structure away from the substrate, and the gate structure is in contact with the channel structure. At least a part of the intrinsic region is located outside the gate structure. The drain of the transistor is the heavily doped drain structure. The ion concentration doped in the heavily doped drain structure is relatively high. Forming a PIN structure can increase the tunneling barrier of minority carriers (holes, taking NMOS as an example), thereby reducing the leakage current of the transistor in the off state. At the same time, an ohmic contact can be formed between the heavily doped drain structure and the metal contact, which is not limited by the Schottky contact barrier, increasing the on-state current and improving the performance of the semiconductor structure.
[0021] In some embodiments that may include the above embodiments, forming the source structure, the intrinsic region, the channel structure, and the heavily doped drain structure on the substrate includes: forming the heavily doped drain structure, the intrinsic region, and the channel structure on the substrate, where the heavily doped drain structure is located on a side of the intrinsic region away from the channel structure, and the intrinsic region is in contact with both the heavily doped drain structure and the channel structure.
[0022] With such a setting, during fabrication, the semiconductor materials of the heavily doped drain structure, the intrinsic region, and the channel structure can be formed simultaneously. After that, ion doping can be performed separately, which can reduce the fabrication difficulty of the semiconductor structure. In addition, the doping concentration of the intrinsic region is lower than that of the heavily doped drain structure. By setting the intrinsic region, the tunneling path between the heavily doped drain structure and the channel structure can be lengthened to reduce the leakage current of the transistor in the off state. In addition, the intrinsic region helps the transistor to form an ultra-steep switching device, increasing the ultra-steep range, and can also make the SS of the transistor lower than 5 mV / dec.
[0023] In some embodiments that may include the above embodiments, forming the source structure, the intrinsic region, the channel structure, and the heavily doped drain structure on the substrate includes: forming the intrinsic region and the channel structure on the substrate, where the intrinsic region is in contact with the channel structure; forming the heavily doped drain structure on a side of the intrinsic region away from the substrate, and the heavily doped drain structure is in contact with the intrinsic region.
[0024] With such a setting, the projected area of the transistor structure on the substrate can be reduced, facilitating the miniaturization of the semiconductor structure and semiconductor devices. In addition, the doping concentration of the intrinsic region is lower than that of the heavily doped drain structure. By setting the intrinsic region, the tunneling path between the heavily doped drain structure and the channel structure can be lengthened to reduce the leakage current of the transistor in the off state. In addition, the intrinsic region helps the transistor to form an ultra-steep switching device, increasing the ultra-steep range, and can also make the SS of the transistor lower than 5 mV / dec. Description of the Drawings
[0025] Figure 1 Schematic diagram of the structure of the electronic device provided by the embodiment of the present application;
[0026] Figure 2 Schematic diagram of the structure of the transistor in the semiconductor structure provided by the embodiment of the present application Figure 1 ;
[0027] Figure 3 Schematic diagram of the structure of the transistor in the semiconductor structure provided by the embodiment of the present application Figure 2 ;
[0028] Figure 4 Schematic diagram of the doping concentration of the transistor in the semiconductor structure provided by the embodiment of the present application;
[0029] Figure 5 Schematic diagram of the structure of the transistor in the semiconductor structure provided by the embodiment of the present application Figure 3 ;
[0030] Figure 6 Schematic diagram of the doping concentration of the transistor in the semiconductor structure in the related art;
[0031] Figure 7 is Figure 6 Energy band schematic diagram of the drain structure in the transistor shown;
[0032] Figure 8 is Figure 4 Energy band schematic diagram of the heavily doped drain structure in the transistor shown;
[0033] Figure 9 is Figure 4 Energy band simulation result diagram of the transistor shown;
[0034] Figure 10 Energy band simulation result diagram when the transistor is NMOS;
[0035] Figure 11 Diagram of the change in the number of holes during the switching process when the transistor is NMOS;
[0036] Figure 12 Current simulation results between the source and the drain of the transistor in the embodiment of the present application under different gate voltages Figure 1 ;
[0037] Figure 13 Current simulation results between the source and the drain of the transistor in the embodiment of the present application under different gate voltages Figure 2 ;
[0038] Figure 14 Current simulation results between the source and the drain of the transistor in the embodiment of the present application under different gate voltages Figure 3 ;
[0039] Figure 15 The current distribution diagram of the drain structure of a transistor in the on state when the transistor is an NMOS in the related art;
[0040] Figure 16 The current distribution diagram of the heavily doped drain structure of a transistor in the on state when the transistor is an NMOS in an embodiment of the present application;
[0041] Figure 17 The structural schematic diagram of a transistor in the semiconductor structure provided by an embodiment of the present application Figure 4 ;
[0042] Figure 18 The structural schematic diagram of a transistor in the semiconductor structure provided by an embodiment of the present application Figure 5 ;
[0043] Figure 19 The structural schematic diagram of a transistor in the semiconductor structure provided by an embodiment of the present application Figure 6 ;
[0044] Figure 20 The structural schematic diagram of a transistor in the semiconductor structure in the related art;
[0045] Figure 21 The current schematic diagram between the source and the drain of a transistor with a fully surrounding gate transistor under different gate voltages;
[0046] Figure 22 The flowchart of the manufacturing method of the semiconductor structure provided by an embodiment of the present application;
[0047] Figure 23 The structural schematic diagram after forming a substrate in the manufacturing method of the semiconductor structure provided by an embodiment of the present application;
[0048] Figure 24 The structural schematic diagram after forming a source structure, a channel structure, and a heavily doped drain structure in the manufacturing method of the semiconductor structure provided by an embodiment of the present application Figure 1 ;
[0049] Figure 25 The structural schematic diagram after forming a source structure, a channel structure, and a heavily doped drain structure in the manufacturing method of the semiconductor structure provided by an embodiment of the present application Figure 2 ;
[0050] Figure 26 The structural schematic diagram after forming a gate structure in the manufacturing method of the semiconductor structure provided by an embodiment of the present application.
[0051] Explanation of the reference numerals: 10: electronic device; 11: display panel; 12: middle frame; 13: back cover; 14: semiconductor device; 15: main board; 100: crystal hanger; 110: substrate; 120: heavily doped drain structure; 130: channel structure; 140: source structure; 150: intrinsic region; 160: gate structure; 161: gate conductive layer; 162: gate dielectric layer; 170: drain structure; 180: transition layer. DETAILED DESCRIPTION
[0052] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0053] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.
[0054] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components placed in the drawings.
[0055] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.
[0056] The embodiment of the present application provides an electronic device, which may include a mobile phone, a computer, a tablet computer, a smart bracelet, a smart watch, AR, VR, etc. The embodiment of the present application does not limit the electronic device. The electronic device may include a housing and a semiconductor device disposed on the housing, wherein the semiconductor device may include a central processing unit (CPU), a memory, etc.
[0057] Please refer to Figure 1, in an implementation where the electronic device 10 includes a mobile phone, the housing may include a middle frame 12. The mobile phone may further include a main board 15, a display panel 11, and a rear cover 13. The main board 15 is disposed on the middle frame 12, the display panel 11 covers one side of the middle frame 12, and the rear cover 13 covers the other side of the middle frame 12. The semiconductor device 14 may include a central processing unit (CPU) or a memory, etc., and the semiconductor device 14 may be disposed on the main board 15.
[0058] In an implementation where the electronic device includes a computer, the housing may include a chassis, and the computer further includes a main board disposed inside the chassis; correspondingly, the semiconductor device may be disposed on the main board, where the semiconductor device may include a central processing unit (CPU) or a memory, etc.
[0059] Please refer to Figure 2 , in the embodiments of the present application, the semiconductor device may include a circuit board and a semiconductor structure disposed on the circuit board, where the semiconductor structure may include a transistor 100. In an implementation where the semiconductor device includes a central processing unit, the transistor 100 may be used as a logic device of the central processing unit, and the transistor 100 may be connected to the main board through the circuit board; in an implementation where the semiconductor device includes a memory, the transistor 100 may be used as a switching transistor of the memory, and the transistor 100 may be connected to the main board through the circuit board.
[0060] Continue to refer to Figure 2 , in the embodiments of the present application, the transistor 100 includes a substrate 110, and a heavily doped drain structure 120, an intrinsic region 150, a source structure 140, and a channel structure 130 disposed on the substrate 110. Among them, the channel structure 130 is located between the intrinsic region 150 and the source structure 140, and the intrinsic region 150 is in contact with both the heavily doped drain structure 120 and the channel structure 130. The source structure 140 may be in contact with the channel structure 130, and the source structure 140 may serve as the source of the transistor 100; the heavily doped drain structure 120 is in contact with the intrinsic region 150, and the heavily doped drain structure 120 may serve as the drain of the transistor 100; the channel structure 130 serves as the channel of the transistor 100.
[0061] In some implementations, the material of the substrate 110 may include one or more combinations of silicon (Si), germanium (Ge), germanium silicon (GeSi), or III-V group semiconductor materials. The embodiments of the present application do not limit this. In some embodiments, such as Figure 3As shown, the semiconductor structure may include a buried oxide layer 111 (referred to as BOX for short) and a top semiconductor layer 112 that are stacked on the substrate 110. The buried oxide layer is located between the top semiconductor layer and the substrate 110. The substrate 110, the buried oxide layer, and the top semiconductor layer may form a silicon on insulator (SOI) structure. Among them, the material of the buried oxide layer may include silicon dioxide (SiO2), germanium oxide (GeO2), etc., and the material of the top semiconductor layer may include one or a combination of silicon, germanium, silicon germanium, or III-V group semiconductor materials.
[0062] In the above implementation, the heavily doped drain structure 120, the intrinsic region 150, the source structure 140, and the channel structure 130 may be located in the top semiconductor layer. That is to say, doping the semiconductor materials in different regions of the top semiconductor layer can obtain the heavily doped drain structure 120, the intrinsic region 150, the source structure 140, and the channel structure 130. Of course, different regions of the substrate 110 may also be directly doped to obtain the heavily doped drain structure 120, the intrinsic region 150, the source structure 140, and the channel structure 130.
[0063] Continue to refer to Figure 2 , in the embodiment of the present application, the transistor 100 further includes a gate structure 160. The gate structure 160 is disposed on the side of the channel structure 130 away from the substrate 110. The gate structure 160 is in contact with the channel structure 130, and at least part of the intrinsic region 150 is located outside the gate structure 160. The gate structure 160 can control the on and off of the transistor 100. Exemplarily, when the gate structure 160 has a high level, the transistor 100 may be in the on state. Correspondingly, when the gate structure 160 has a low level, the transistor 100 is in the off state; or, when the gate structure 160 has a low level, the transistor 100 may be in the on state. Correspondingly, when the gate structure 160 has a high level, the transistor 100 is in the off state.
[0064] Exemplarily, the gate structure 160 may include a gate conductive layer 161 and a gate dielectric layer 162. The gate dielectric layer 162 may be located between the gate conductive layer 161 and the channel structure 130. The gate dielectric layer 162 is in contact with both the gate conductive layer 161 and the channel structure 130. Controlling the voltage of the gate conductive layer 161 can achieve the control of the on and off of the transistor 100. Among them, the material of the gate dielectric layer 162 may include silicon dioxide, silicon nitride, high-k dielectric, etc., and the material of the gate conductive layer 161 may include titanium nitride, tungsten, etc. The embodiments of the present application do not limit the materials of the gate conductive layer 161 and the gate dielectric layer 162.
[0065] Please refer toFigure 4 , in the embodiments of the present application, the ion concentration of the semiconductor material doped in the heavily doped drain structure 120 is relatively high, which can increase the tunneling barrier of minority carriers (holes, taking NMOS as an example), thereby reducing the leakage current of the transistor 100 in the off state and improving the performance of the semiconductor structure.
[0066] Exemplarily, the doping concentration of the heavily doped drain structure 120 can be 1e19 cm -3 -1e21 cm -3 ; Exemplarily, the doping concentration of the heavily doped drain structure 120 can be 1e19 cm -3 、3e20 cm -3 、1e21 cm -3 etc. With such a setting, on the premise of ensuring that the transistor 100 has a small leakage current, the doping concentration of the heavily doped drain structure 120 is not too high or too low, reducing the manufacturing difficulty of the semiconductor structure.
[0067] It can be understood that the doping concentration of each part of the semiconductor material in the heavily doped drain structure 120 can be the same or different. In the implementation where the doping concentration of each part of the semiconductor material in the heavily doped drain structure 120 is different, the doping concentration of the part of the semiconductor material far from the channel structure 130 is relatively high, and the doping concentration of the part of the semiconductor material close to the channel structure 130 is relatively low; and / or, the doping concentration of the part of the semiconductor material far from the substrate 110 is relatively high, and the doping concentration of the part of the semiconductor material close to the gate structure 160 is relatively low. The embodiments of the present application do not limit this.
[0068] Continue to refer to Figure 4 , in some implementations, the source structure 140 is also a heavily doped structure, that is, the ion concentration of the semiconductor material doped in the source structure 140 is relatively high. With such a setting, the doping concentration of the source structure 140 is relatively high, which can reduce the resistance of the source structure 140.
[0069] Exemplarily, the doping concentration of the source structure 140 can be 1e19 cm -3 -1e21 cm -3 ; Exemplarily, the doping concentration of the source structure 140 can be 1e19 cm -3 、3e20 cm -3 、1e21 cm -3 etc. Through the above settings, the doping concentration of the source structure 140 is close to that of the heavily doped drain structure 120, and the source structure 140 and the heavily doped drain structure 120 can be formed simultaneously to reduce the manufacturing difficulty.
[0070] It can be understood that the doping concentration everywhere in the semiconductor material of the source structure 140 may be the same or different. In the implementation where the doping concentration everywhere in the semiconductor material of the source structure 140 is different, the doping concentration of the part of the semiconductor material far from the channel structure 130 is relatively high, and the doping concentration of the part of the semiconductor material close to the channel structure 130 is relatively low; and / or, the doping concentration of the part of the semiconductor material far from the substrate 110 is relatively high, and the doping concentration of the part of the semiconductor material close to the gate structure 160 is relatively low. The embodiments of the present application do not limit this.
[0071] Continuing to refer to Figure 4 , in some embodiments, the doping concentration of the semiconductor material in the channel structure 130 may be 1e17 cm -3 -1e20 cm -3 (such as 1e17 cm -3 , 1e18 cm -3 , 1e20 cm -3 etc.). With such a setting, the doping concentration of the channel structure 130 is moderate, which can reduce the manufacturing difficulty of the semiconductor structure.
[0072] It can be understood that the doping concentration everywhere in the semiconductor material of the channel structure 130 may be the same or different. In the implementation where the doping concentration everywhere in the semiconductor material of the channel structure 130 is different, the doping concentration of the part of the semiconductor material far from the substrate 110 is relatively high, and the doping concentration of the part of the semiconductor material close to the gate structure 160 is relatively low. The embodiments of the present application do not limit this.
[0073] Continuing to refer to Figure 2 and Figure 4 , the transistor 100 further includes an intrinsic region 150. The intrinsic region 150 is located between the heavily doped drain structure 120 and the channel structure 130, and the intrinsic region 150 is in contact with both the heavily doped drain structure 120 and the channel structure 130; that is to say, the heavily doped drain structure 120 is connected to the channel through the intrinsic region 150. Among them, the doping concentration of the intrinsic region 150 is lower than that of the heavily doped drain structure 120.
[0074] Through the above setting, the tunneling path between the heavily doped drain structure 120 and the channel structure 130 can be increased to further reduce the leakage current of the transistor 100 in the off state. In addition, the intrinsic region 150 helps the transistor 100 to form an ultra-steep switching device, increase the ultra-steep range, and can also make the SS of the transistor 100 lower than 5 mV / dec.
[0075] In some implementation manners, the doping concentration of the intrinsic region 150 is less than 1e16 cm -3 (such as 0, 1e15 cm -3etc.). It can be understood that when the doping concentration of the intrinsic region 150 is 0, it means no doping; the intrinsic region 150 may also contain certain ions. With such a setting, there is no need to additionally dope the intrinsic region to reduce the manufacturing difficulty.
[0076] In some implementation manners, a transition layer 180 may be provided between the intrinsic region 150 and the heavily doped drain structure 120, and the heavily doped drain structure 120 is in contact with the intrinsic region 150 through the transition layer 180; exemplarily, the doping concentration of the transition layer 180 may be 1.0e16 cm -3 -1.0e19 cm -3 .
[0077] In the embodiments of the present application, at least a part of the intrinsic region 150 is located outside the gate structure 160, which can be understood as that at least a part of the intrinsic region 150 is not covered by the gate structure 160. For example, the projection of at least a part of the intrinsic region 150 on the substrate 110 is located outside the projection of the gate structure 160 on the substrate 110.
[0078] Continue to refer to Figure 2 , in some implementation manners, the transistor 100 is an N-type metal oxide semiconductor transistor (N - metal oxide semiconductor, abbreviated as NMOS). Correspondingly, both the heavily doped drain structure 120 and the source structure 140 are N-type semiconductors (N ++ ), the channel structure 130 is a P-type semiconductor (P + ), and the heavily doped drain structure 120, the intrinsic region 150, and the source structure 140 form an NIP structure; exemplarily, the elements doped in the semiconductor materials of the heavily doped drain structure 120 and the source structure 140 may include phosphorus (P), arsenic (As), antimony (Sb), etc., and the elements doped in the semiconductor material of the channel structure 130 may include boron (B), indium (In), etc.
[0079] Please refer to Figure 5 , in other implementation manners, the transistor 100 may be a P-type metal oxide semiconductor transistor (P - metal oxide semiconductor, abbreviated as PMOS). Correspondingly, both the heavily doped drain structure 120 and the source structure 140 are P-type semiconductors (P ++ ), the channel structure 130 is an N-type semiconductor (N + ), and the heavily doped drain structure 120, the intrinsic region 150, and the source structure 140 form a PIN structure; exemplarily, the elements doped in the semiconductor materials of the heavily doped drain structure 120 and the source structure 140 may include boron (B), etc., and the elements doped in the semiconductor material of the channel structure 130 may include phosphorus (P), arsenic (As), antimony (Sb), etc.
[0080] In the embodiment of the present application, the transistor 100 can be an impact ionization feedback field effect transistor (abbreviated as II-FB-FET). During operation, at a certain source-drain voltage, the electric field in the intrinsic region 150 between the heavily doped drain structure 120 and the source structure 140 is relatively high. Electron-hole pairs are generated in the intrinsic region due to impact ionization. Minority carriers (holes, taking NMOS as an example) are swept into silicon-on-insulator under the action of the electric field, thereby reducing the potential barrier of majority carriers (electrons, taking NMOS as an example). The majority carriers further trigger impact ionization, forming a positive feedback to turn on the transistor 100.
[0081] Continue to refer to Figure 2 and Figure 5 In the semiconductor structure provided by the embodiment of the present application, the heavily doped drain structure 120, the intrinsic region 150, the source structure 140, and the channel structure 130 are all disposed on the substrate 110. The channel structure 130 is located between the intrinsic region 150 and the source structure 140. The intrinsic region 150 is in contact with both the heavily doped drain structure 120 and the channel structure 130. The gate structure 160 is disposed on the side of the channel structure 130 away from the substrate 110. The gate structure 160 is in contact with the channel structure 130. At least a part of the intrinsic region 150 is located outside the gate structure 160. The drain of the transistor is the heavily doped drain structure 120. The ion concentration doped in the heavily doped drain structure 120 is relatively high. Forming a PIN structure can increase the tunneling barrier of minority carriers (holes, taking NMOS as an example), thereby reducing the leakage current when the transistor is in the off state and improving the performance of the semiconductor structure. At the same time, the heavily doped drain structure 120 and the metal contact can form an ohmic contact, which is not limited by the Schottky contact barrier and increases the on-state current.
[0082] Please refer to Figure 6 In the related art, the transistor 100 includes a source structure 140, a channel structure 130, and a drain structure 170 disposed on the substrate 110. The channel structure 130 is located between the source structure 140 and the drain structure 170. Among them, the source structure 140 is a heavily doped structure. The drain structure 170 includes an intrinsic region and a metal layer (not shown) disposed on the upper surface of the intrinsic region. Correspondingly, the drain structure 170 is a metal drain. The material of the metal layer includes metals such as copper and aluminum. The transistor 100 further includes a gate structure 160 disposed on the side of the channel structure 130 away from the substrate 110. The gate structure 160 is in contact with the channel structure 130. The on and off of the transistor 100 can be controlled through the gate structure 160.
[0083] Figure 7 For Figure 6Energy band schematic diagram of the drain structure 170 in the transistor 100 shown. In the figure, L1 corresponds to the conduction band of the drain structure 170, L2 corresponds to the valence band of the drain structure 170. The horizontal width of the shaded area is the tunneling width of the drain structure 170, and the vertical height of the shaded area is the tunneling height of the drain structure 170. The horizontal arrows respectively represent hole tunneling and thermionic emission. Figure 8 is Figure 4 Energy band schematic diagram of the heavily doped drain structure 120 in the transistor 100 shown. In the figure, L3 corresponds to the conduction band of the heavily doped drain structure 120, L4 corresponds to the valence band of the heavily doped drain structure 120. The horizontal width of the shaded area is the tunneling width of the drain structure 170, and the vertical height of the shaded area is the tunneling height of the drain structure 170. The horizontal arrow represents hole tunneling. Figure 9 is Figure 4 Energy band simulation result diagram of the transistor 100 shown. In the figure, L5 corresponds to the conduction band of the transistor 100, L6 corresponds to the valence band of the transistor 100. ell is the electron current generated by impact ionization, hll is the hole current generated by impact ionization, and R represents the recombination of electrons and holes. From Figures 7 - 9 it can be seen that in the transistor 100 of the embodiment of the present application, the holes in the heavily doped drain structure 120 have higher tunneling barriers and thermionic emission barriers compared with the metal drain structure 170, which can reduce the leakage current when the transistor 100 is in the off state. In addition, problems of materials and interfaces are likely to occur between the metal drain structure 170 and the work function metal contact, such as large contact resistance, reduction of the on-state current, and reduction of reliability; while in the embodiment of the present application, the heavily doped drain structure can adopt a conventional metal silicide contact, which will not cause problems of materials and interfaces and can increase the on-state current.
[0084] Figure 10 is the energy band simulation result diagram when the transistor 100 is an NMOS, and the gate voltage Vg ( Figure 4 the voltage between the gate structure 160 and the source structure 140 shown) is 0. In the figure, the abscissa Y is the dimension in the direction from the source structure 140 to the channel structure 130, and the ordinate E is the energy. The curve a1 represents the conduction band in the forward sweep state (the gate voltage gradually increases) of the transistor 100 in the related art, and the curves a2, b2, a4, and b4 all represent the quasi-Fermi levels; the curve a3 represents the valence band in the forward sweep state of the transistor 100 in the related art; the curve b1 represents the conduction band in the forward sweep state of the transistor 100 in the embodiment of the present application, and the curve b3 represents the valence band in the forward sweep state of the transistor 100 in the embodiment of the present application. From Figure 10It is known that the drain structure 170 of the transistor 100 in the related art includes metal (metal drain). When the transistor 100 is in the off state, the band bending of the drain structure 170 is strong, and hole tunneling is likely to occur. The holes cause the surface potential to increase and the electron barrier to decrease, making leakage current likely to occur. In the transistor 100 according to the embodiment of the present application, the heavily doped drain structure 120 has a large hole tunneling path and barrier, making tunneling difficult to occur, and the electron barrier is large, making leakage current difficult to occur, thereby reducing the leakage current in the off state.
[0085] Figure 11 FIG. is a diagram showing the change in the number of holes during the switching process when the transistor 100 is an NMOS. The abscissa Vg is the gate voltage, the ordinate is the charge amount, the curve a5 corresponds to the transistor 100 in the related art, the curve b5 corresponds to the transistor 100 according to the embodiment of the present application, and the drain voltage Vd is 1.8V. From Figure 11 It can be seen that the drain structure 170 of the transistor 100 in the related art is composed of metal, the hole mutation during the switching process is small, and the super-steep range of the transistor 100 is small. The drain of the transistor 100 according to the embodiment of the present application includes a heavily doped drain structure 120, the hole mutation during the switching process is large, and the super-steep range of the transistor 100 is large.
[0086] Figure 12 is the simulation result of the current Id between the source and the drain of the transistor 100 according to the embodiment of the present application under different gate voltages Vg (the voltage between the gate structure 160 and the source structure 140) Figure 1 , in the figure, the curve a6 corresponds to the transistor 100 in the related art when the drain voltage Vd is 1.8V, the curve a7 corresponds to the transistor 100 in the related art when the drain voltage Vd is 1.2V, the curve b6 corresponds to the transistor 100 according to the embodiment of the present application when the drain voltage Vd is 1.8V, and the curve b7 corresponds to the transistor 100 according to the embodiment of the present application when the drain voltage Vd is 1.2V. From Figure 12 It can be seen that when the transistor 100 is in the off state (when the gate voltage is less than 1V), the current between the source and the drain of the transistor 100 in the related art is higher than the current between the source and the drain of the transistor 100 according to the embodiment of the present application. It can be seen that the leakage current of the transistor 100 according to the embodiment of the present application in the off state is significantly lower than the leakage current of the transistor 100 in the related art in the off state, and the leakage current can be reduced by approximately 1-3 orders of magnitude. In addition, the transistor 100 according to the embodiment of the present application has a larger steep switching range, enabling the transistor 100 to be applied in low-power circuits.
[0087] Figure 13 is the simulation result of the current between the source and the drain of the transistor 100 according to the embodiment of the present application under different gate voltages (the voltage between the gate structure 160 and the source structure 140) Figure 2 , fromFigure 13 It can be seen that when the transistor 100 is in the on state (when the gate voltage is greater than 2V), the current between the source and drain of the transistor 100 in the related art is lower than the current between the source and drain of the transistor 100 in the embodiment of the present application. It can be seen that the on-state current of the transistor 100 in the embodiment of the present application is larger, improving the performance of the transistor 100.
[0088] Continue to refer to Figure 2 and Figure 4 , in some embodiments, along the carrier transport direction ( Figure 4 the horizontal direction shown), the length m2 of the intrinsic region 150 is 10nm - 50nm. It can be understood that by adjusting the length of the intrinsic region 150, the ultra-steep switching range, the leakage current in the off state, and the hysteresis of the transistor 100 can be adjusted. By making the length of the intrinsic region 150 be 10nm - 50nm, the performance of the ultra-steep switching range, the leakage current in the off state, and the hysteresis of the transistor 100 can be balanced to improve the performance of the transistor 100.
[0089] Continue to refer to Figure 4 , the heavily doped drain structure 120 is located on the side of the intrinsic region 150 away from the channel structure 130, and the total length (the sum of m1 and m2) of the heavily doped drain structure 120 and the intrinsic region 150 is 50nm. Figure 14 is the simulation result of the current between the source and drain of the transistor 100 in the embodiment of the present application under different gate voltages (the voltage between the gate structure 160 and the source structure 140). Figure 3 , curve b8 is the curve in the forward sweep state (the gate voltage gradually increases from 0) when the length m1 of the heavily doped drain structure 120 is 20nm (the length m2 of the intrinsic region 150 is 30nm), curve b9 is the curve in the reverse sweep state (the gate voltage gradually decreases from high voltage) when the length m1 of the heavily doped drain structure 120 is 20nm (the length m2 of the intrinsic region 150 is 30nm), curve b10 is the curve in the forward sweep state (the gate voltage gradually increases from 0) when the length m1 of the heavily doped drain structure 120 is 30nm (the length m2 of the intrinsic region 150 is 20nm), curve b11 is the curve in the reverse sweep state (the gate voltage gradually decreases from high voltage) when the length m1 of the heavily doped drain structure 120 is 30nm (the length m2 of the intrinsic region 150 is 20nm), curve b12 is the curve in the forward sweep mode (the gate voltage gradually increases from 0) when the length m1 of the heavily doped drain structure 120 is 40nm (the length m2 of the intrinsic region 150 is 10nm). From Figure 14 it can be seen that as the length m2 of the intrinsic region 150 gradually increases, the ultra-steep switching range of the transistor 100 gradually increases, and the leakage current in the off state gradually decreases.
[0090] Figure 15The current distribution diagram of the drain structure 170 of the transistor 100 in the on-state when the transistor 100 is an NMOS in the related art. Figure 16 The current distribution diagram of the heavily doped drain structure 120 of the transistor 100 in the on-state when the transistor 100 is an NMOS in the embodiment of the present application. The abscissa in the figure is the dimension along the source structure 140 and the channel structure 130 direction, and it can be seen from Figure 15 and Figure 16 that in the related art, the current distribution of the drain structure 170 is on its top surface, and the parasitic resistance of the drain structure 170 is relatively large; while in the transistor 100 of the embodiment of the present application, the current of the heavily doped drain structure 120 is concentrated in region A, and the parasitic resistance is relatively small.
[0091] Continuing to refer to Figure 2 and Figure 5 , in some embodiments, the heavily doped drain structure 120 is located on the side of the intrinsic region 150 away from the channel structure 130. That is to say, the heavily doped drain structure 120, the intrinsic region 150, and the channel structure 130 can be arranged substantially in the same layer; correspondingly, the interface between the heavily doped drain structure 120 and the intrinsic region 150 is located on the side of the intrinsic region 150 away from the channel. With such an arrangement, when manufacturing, the semiconductor materials of the heavily doped drain structure 120, the intrinsic region 150, and the channel structure 130 can be formed simultaneously, and then, ion doping can be carried out respectively, which can reduce the manufacturing difficulty of the semiconductor structure.
[0092] Please refer to Figure 17 , in other embodiments, the heavily doped drain structure 120 is located on the side of the intrinsic region 150 away from the substrate 110. That is to say, the intrinsic region 150 and the source structure 140 are arranged substantially in the same layer, and the interface between the heavily doped drain structure 120 and the intrinsic region 150 is located on the side of the intrinsic region 150 away from the substrate 110, that is, this interface can correspond to the gate structure 160. With such an arrangement, the projected area of the transistor 100 structure on the substrate 110 can be reduced, so as to facilitate the miniaturization of the semiconductor structure and the semiconductor device.
[0093] It can be understood that the embodiment of the present application does not limit the position of the heavily doped drain structure 120 and the position of the interface between the heavily doped drain structure 120 and the intrinsic region 150, as long as it is ensured that the heavily doped drain structure 120 is connected to the channel structure 130 through the intrinsic region 150. In addition, the interface between the heavily doped drain structure 120 and the intrinsic region 150 can be a regular shape such as a plane or a curved surface, and of course, it can also be other irregular shapes. The embodiment of the present application does not limit the shape of the interface.
[0094] In the embodiment of the present application, the structure of the transistor 100 can be various. Exemplarily, the transistor 100 can be a planar transistor (as shown in Figure 2 ), SOI (as shown in Figure 3as shown, fin field-effect transistor (FinFET), gate-all-around FET (GAA) structure, etc.
[0095] As Figure 18 shown, in the implementation where the transistor 100 is a fin field-effect transistor, fins are disposed on the substrate 110. The fins include a heavily doped drain structure 120, a channel structure 130 (not shown), and a source structure 140. The channel structure 130 is located between the heavily doped drain structure 120 and the source structure 140. The gate structure 160 covers the top surface of the channel structure 130 and the side surfaces between the top and bottom surfaces. By setting like this, the contact area between the gate structure 160 and the channel structure 130 can be increased, and thus the control ability of the gate structure 160 can be improved.
[0096] As Figure 19 shown, in the implementation where the transistor 100 is a gate-all-around FET, the channel structure 130 is disposed between the heavily doped drain structure 120 and the source structure 140, and the gate structure 160 is disposed around the channel structure 130. By setting like this, the contact area between the gate structure 160 and the channel structure 130 can be further increased, and the control ability of the gate structure 160 can be improved.
[0097] Figure 20 FIG. is a schematic structural diagram of the transistor 100 as a gate-all-around FET in the related art. The channel structure 130 is disposed between the source structure 140 and the drain structure 170. The drain structure 170 includes an intrinsic region and a metal layer (not shown) disposed on the upper surface of the intrinsic region. Correspondingly, the drain structure 170 is a metal drain, and the material of the metal layer includes metals such as copper and aluminum. The gate structure 160 is disposed around the channel structure 130. Figure 21 FIG. is a schematic diagram of the current between the source and the drain of the transistor 100 as a gate-all-around FET under different gate voltages (the voltage between the gate structure 160 and the source structure 140). In the figure, the curve a8 corresponds to the NMOS in the related art with a drain voltage of 1.2V, the curve a9 corresponds to the PMOS in the related art with a drain voltage of 1.2V, the curve b13 corresponds to the NMOS in the embodiment of the present application with a drain voltage of 1.2V, and the curve b14 corresponds to the PMOS in the embodiment of the present application with a drain voltage of 1.2V. From Figure 21It can be known that the off-state leakage current between the source and drain of the transistor 100 in the related art is higher than that between the source and drain of the transistor 100 in the embodiment of the present application. It can be seen that the leakage current of the transistor 100 in the embodiment of the present application in the off state is significantly lower than that of the transistor 100 in the related art in the off state. In addition, the transistor 100 in the embodiment of the present application has a larger on-state current and a larger steep switching range, and the subthreshold swing (SS) is extremely low.
[0098] Please refer to Figure 22 , the embodiment of the present application further provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure in the above embodiment. The method for manufacturing the semiconductor structure includes:
[0099] S101: Provide a substrate.
[0100] Exemplarily, as Figure 23 shown, the material of the substrate 110 may include one or more combinations of silicon (Si), germanium (Ge), germanium-silicon (GeSi), or III-V group semiconductor materials.
[0101] After forming the substrate 110, the method for manufacturing the semiconductor structure provided by the embodiment of the present application further includes:
[0102] S102: Form a source structure, an intrinsic region, a channel structure, and a heavily doped drain structure on the substrate. The channel structure is located between the intrinsic region and the source structure, and the intrinsic region is in contact with both the heavily doped drain structure and the channel structure.
[0103] Please refer to Figure 24 , exemplarily, different regions on the substrate 110 can be doped by ion implantation or epitaxial in-situ doping to form the source structure 140, the channel structure 130, and the heavily doped drain structure 120. It can be understood that by reasonably setting the dose of ion implantation or the energy during implantation, the doping concentration can be adjusted.
[0104] In some embodiments, after forming the substrate 110, a buried oxide layer and a top semiconductor layer can be formed on the substrate 110 in a stacked manner. The buried oxide layer is located between the top semiconductor layer and the substrate 110, and the substrate 110, the buried oxide layer, and the top semiconductor layer can form a silicon-on-insulator structure. Among them, the material of the buried oxide layer may include silicon oxide, germanium oxide, etc., and the material of the top semiconductor layer may include one or more combinations of silicon, germanium, germanium-silicon, or III-V group semiconductor materials. Correspondingly, the top semiconductor layer can be doped to form the source structure 140, the channel structure 130, and the heavily doped drain structure 120.
[0105] Continue to refer to Figure 24In some embodiments, forming the source structure 140, the intrinsic region 150, the channel structure 130 and the heavily doped drain structure 120 on the substrate includes: forming the heavily doped drain structure 120, the intrinsic region 150 and the channel structure 130 on the substrate, the heavily doped drain structure 120 is located on the side of the intrinsic region 150 away from the channel structure 130, and the intrinsic region 150 is in contact with both the heavily doped drain structure 120 and the channel structure 130. In other words, the heavily doped drain structure 120, the intrinsic region 150 and the channel structure 130 can be arranged in roughly the same layer; accordingly, the interface between the heavily doped drain structure 120 and the intrinsic region 150 is located on the side of the intrinsic region 150 away from the channel structure 130. With such an arrangement, during the manufacturing process, the semiconductor materials of the heavily doped drain structure 120, the intrinsic region 150 and the channel structure 130 can be formed simultaneously, and then ion doping is performed separately, which can reduce the difficulty of manufacturing the semiconductor structure.
[0106] In addition, the doping concentration of the intrinsic region 150 is lower than the doping concentration of the heavily doped drain structure 120. By providing the intrinsic region 150, the tunneling path between the heavily doped drain structure 120 and the channel structure 130 can be increased to reduce the leakage current of the transistor 100 in the off state. In addition, the intrinsic region 150 helps the transistor 100 to form an ultra-steep switching device, increase the ultra-steep range, and also make the SS of the transistor 100 lower than 5mV / dec.
[0107] It is understandable that the embodiment of the present application does not limit the order of forming the source structure 140, the channel structure 130, and the heavily doped drain structure 120, that is, the doping order of different regions of the substrate 110 is not limited. Exemplarily, the substrate 110 may have a drain region, an intrinsic region, a source region, and a channel region. When doping is performed, a first protective layer may be first formed on the channel region and the intrinsic region, and then the source region and the drain region are heavily doped to form the source structure 140 in the source region, and at the same time, the heavily doped drain structure 120 is formed in the drain region. The first protective layer may protect the channel region and the intrinsic region when doping the source region and the drain region. A second protective layer is then formed on the source structure 140, the intrinsic region and the heavily doped drain structure 120, and the first protective layer is removed. The channel region is then doped to form the channel structure 130. The second protective layer can protect the source structure 140 and the heavily doped drain structure 120 when the channel region and the intrinsic region are doped.
[0108] Of course, in other implementation manners, a first protective layer may also be formed on the source region, the intrinsic region, and the drain region first, and then the channel region is doped to form a channel structure 130 in the channel region. The first protective layer may protect the source region, the intrinsic region, and the drain region when the channel region is doped. Then, a second protective layer is formed on the channel structure 130 and the intrinsic region, and the first protective layer is removed. Then, the source region and the drain region are heavily doped to form a source structure 140 and a heavily doped drain structure 120. The second protective layer may include the channel structure 130 and the intrinsic region when the source region and the drain region are doped.
[0109] Please refer to Figure 25 , in other embodiments, forming the source structure 140, the intrinsic region 150, the channel structure 130, and the heavily doped drain structure 120 on the substrate 110 includes: forming the intrinsic region 150 and the channel structure 130 on the substrate 110, where the intrinsic region 150 is in contact with the channel structure 130; forming the heavily doped drain structure 120 on a side of the intrinsic region 150 away from the substrate 110, where the heavily doped drain structure 120 is in contact with the intrinsic region 150. That is to say, the intrinsic region 150 and the source structure 140 are disposed substantially in the same layer, and an interface between the heavily doped drain structure 120 and the intrinsic region 150 is located on a side of the intrinsic region 150 away from the substrate 110, that is, the interface may correspond to the gate structure 160. With such an arrangement, the projection area of the transistor 100 structure on the substrate 110 can be reduced, facilitating miniaturization of the semiconductor structure and the semiconductor device.
[0110] In addition, the doping concentration of the intrinsic region 150 is lower than that of the heavily doped drain structure 120. By providing the intrinsic region 150, the tunneling path between the heavily doped drain structure 120 and the channel structure 130 can be increased to reduce the leakage current of the transistor 100 in the off state. In addition, the intrinsic region 150 helps the transistor 100 to form an ultra-steep switching device, increase the ultra-steep range, and can also make the SS of the transistor 100 lower than 5 mV / dec.
[0111] The semiconductor structure manufacturing method provided by the embodiments of the present application further includes:
[0112] S103: Forming a gate structure on a side of the channel structure away from the substrate, where the gate structure is in contact with the channel structure, and at least part of the intrinsic region is located outside the gate structure.
[0113] Please refer to Figure 26 , in the above implementation manner, the gate structure 160 may serve as the gate of the transistor 100, the source structure 140 may serve as the source of the transistor 100, and the heavily doped drain structure 120 may serve as the drain of the transistor 100.
[0114] Exemplarily, a gate dielectric layer 162 may be first formed on the channel structure 130, and then a gate conductive layer 161 may be formed on the gate dielectric layer 162. That is, the gate dielectric layer 162 is located between the gate conductive layer 161 and the channel structure 130, and by controlling the voltage of the gate conductive layer 161, the turning on and off of the transistor 100 can be controlled.
[0115] For the semiconductor structure fabricated by the semiconductor structure manufacturing method provided in the embodiments of the present application, the heavily doped drain structure 120, the intrinsic region 150, the source structure 140, and the channel structure 130 are all disposed on the substrate 110. The channel structure 130 is located between the intrinsic region 150 and the source structure 140. The intrinsic region 150 is in contact with both the heavily doped drain structure 120 and the channel structure 130. The gate structure 160 is disposed on a side of the channel structure 130 away from the substrate 110. The gate structure 160 is in contact with the channel structure 130, and at least a part of the intrinsic region 150 is located outside the gate structure 160. The drain of the transistor is the heavily doped drain structure 120. The ion concentration doped in the heavily doped drain structure 120 is relatively high. Forming a PIN structure can increase the tunneling barrier of minority carriers (holes, taking NMOS as an example), thereby reducing the leakage current when the transistor is in the off state and improving the performance of the semiconductor structure. At the same time, an ohmic contact can be formed between the heavily doped drain structure 120 and the metal contact, which is not limited by the Schottky contact barrier, and the on-state current is increased.
[0116] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.
[0117] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor structure, characterized in that, it includes: a transistor, and the transistor includes: a substrate; a heavily doped drain structure, an intrinsic region, a source structure, and a channel structure disposed on the substrate, the channel structure being located between the intrinsic region and the source structure, and the intrinsic region being in contact with both the heavily doped drain structure and the channel structure; a gate structure, the gate structure being disposed on a side of the channel structure away from the substrate, the gate structure being in contact with the channel structure, and at least a part of the intrinsic region being located outside the gate structure.
2. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the heavily doped drain structure is 1e19 cm -3 -1e21 cm -3 .
3. The semiconductor structure according to claim 1 or 2, characterized in that, The doping concentration of the intrinsic region is less than 1e16 cm -3 .
4. The semiconductor structure according to any one of claims 1 - 3, characterized in that, along the carrier transport direction, the length of the intrinsic region is 10nm - 50nm.
5. The semiconductor structure according to any one of claims 1 - 4, characterized in that, the heavily doped drain structure is located on a side of the intrinsic region away from the channel structure.
6. The semiconductor structure according to any one of claims 1 - 4, characterized in that, the heavily doped drain structure is located on a side of the intrinsic region away from the substrate.
7. The semiconductor structure according to any one of claims 1 - 6, characterized in that, The doping concentration of the channel structure is 1e17 cm -3 -1e20 cm -3 .
8. The semiconductor structure according to any one of claims 1 - 7, characterized in that, the source structure is a heavily doped structure.
9. The semiconductor structure according to claim 8, characterized in that, The doping concentration of the source structure is 1e19 cm -3 -1e21 cm -3 .
10. The semiconductor structure according to any one of claims 1 - 9, characterized in that, the gate structure includes a gate conductive layer and a gate dielectric layer, and the gate dielectric layer is located between the gate conductive layer and the channel structure.
11. A semiconductor device, characterized in that, it includes: a circuit board and the semiconductor structure according to any one of claims 1 - 10, and the semiconductor structure is disposed on the circuit board.
12. An electronic device, characterized in that, it includes: a housing and the semiconductor device according to claim 11, and the semiconductor device is disposed on the housing.
13. A method for manufacturing a semiconductor structure, characterized in that, it includes: providing a substrate; forming a source structure, an intrinsic region, a channel structure, and a heavily doped drain structure on the substrate, the channel structure being located between the intrinsic region and the source structure, and the intrinsic region being in contact with both the heavily doped drain structure and the channel structure; forming a gate structure on a side of the channel structure away from the substrate, the gate structure being in contact with the channel structure, and at least a part of the intrinsic region being located outside the gate structure.
14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, Forming a source structure, an intrinsic region, a channel structure and a heavily doped drain structure on the substrate includes: forming the heavily doped drain structure, the intrinsic region and the channel structure on the substrate, the heavily doped drain structure is located on a side of the intrinsic region away from the channel structure, and the intrinsic region is in contact with both the heavily doped drain structure and the channel structure.
15. The method for manufacturing a semiconductor structure according to claim 13, It is characterized in that Forming a source structure, an intrinsic region, a channel structure and a heavily doped drain structure on the substrate includes: forming the intrinsic region and the channel structure on the substrate, wherein the intrinsic region is in contact with the channel structure; and forming the heavily doped drain structure on a side of the intrinsic region away from the substrate, wherein the heavily doped drain structure is in contact with the intrinsic region.