Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof

Abstract

The invention provides a wide bandgap semiconductor trench MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure and a manufacturing method thereof, and the structure comprises an epitaxial layer which grows on a substrate; the multi-stage P-type shielding region is arranged in the epitaxial layer along the vertical direction, and the width size of the multi-stage P-type shielding region is gradually reduced along the vertical direction; the multi-stage N-type doped region is arranged on the outer wall side of the multi-stage P-type shielding region in a wrapping manner; the source P + region and the source N + region are arranged in the epitaxial layer in a side-by-side contact manner, and the source P + region is electrically connected with the multi-stage P-type shielding region through the P-well region; the source electrode is arranged at the tops of the source electrode P + region and the source electrode N + region; the drain electrode is arranged at the bottom of the substrate; the gate structure penetrates through the source P + region and the source N + region into the epitaxial layer, and the bottom of the gate structure is in contact with the multi-stage P-type shielding region; and the P-type connecting layer is arranged on the outer wall side of a part of the gate structure, and the bottom of the P-type connecting layer is in contact with the multi-stage P-type shielding region and the multi-stage N-type doped region so as to realize grounding of the multi-stage P-type shielding region. The structure has the effects of high power density, low power consumption and high voltage resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a wide-bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] Due to the limitations of its own material properties, the performance improvement of traditional silicon-based devices has approached a bottleneck and it is difficult to meet the growing demands for high power density and low power consumption. Therefore, researching and developing higher-performance semiconductor materials has become an inevitable trend.

[0003] The third-generation and fourth-generation wide-bandgap semiconductor materials represented by silicon carbide (SiC) and gallium oxide ( ), have emerged as the times require. Compared with traditional silicon materials, wide-bandgap semiconductor materials have significant advantages in key physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. Research shows that the Baliga figures of merit of SiC and are 340 times and 3400 times that of silicon materials respectively. Power devices prepared based on SiC and , such as diodes, transistors, and power integrated circuits, not only have a smaller chip area but also exhibit more excellent electrical characteristics. The research value and market application prospects of SiC and materials are particularly prominent.

[0004] In the doping technology of wide-bandgap semiconductor materials, P-type doping of silicon carbide (SiC) devices can be achieved through ion implantation or epitaxial growth. However, for materials with a larger bandgap width, such as gallium nitride (GaN), gallium oxide ( ), diamond (C), and aluminum nitride (AlN), it is difficult to achieve P-type doping through ion implantation. Currently, there are mainly two technical solutions: one is the " semi-encapsulated asymmetric trench structure" adopted by Infineon Technologies AG of Germany, and the other is the solution adopted by Rohm Co., Ltd. of Japan to construct source double trenches on both sides of the gate trench to shield the bottom of the middle gate trench. However, these existing technologies still have the following defects: 1. High electric field problem: The high electric field in the drift region of the material will cause a significant increase in the electric field strength on the gate dielectric layer, especially at the trench corners, where this problem is more prominent. At high drain voltages, the gate dielectric layer is prone to rapid breakdown and has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit.

[0005] 2. On-resistance problem: The depletion region of the PN junction formed by the P shield region set at the bottom of the trench and the N drift region cannot conduct current, resulting in an increase in the on-resistance of the device and affecting the overall performance of the device.

[0006] 3. Process limitation issues: Due to the limited depth of ion implantation, many targeted trench gate protection structures and surge protection designs are difficult to implement in the process, restricting the further improvement of device performance.

[0007] In summary, there are still many deficiencies in the existing technologies in terms of high power density, low power consumption, and high breakdown voltage performance. There is an urgent need for a new technical solution to solve the above problems to meet the growing market demand. Summary of the Invention

[0008] Based on the above description, the present invention provides a wide bandgap semiconductor trench MOSFET device structure and its manufacturing method, which can effectively solve the technical problems of the existing MOSFET device structure having many deficiencies in terms of high power density, low power consumption, and high breakdown voltage performance.

[0009] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure, including: An epitaxial layer grown on a substrate; Multiple levels of P-type shielding regions disposed vertically in the epitaxial layer, and the width dimension gradually decreases vertically; Multiple levels of N-type doped regions wrapped on the outer wall side of the multiple levels of P-type shielding regions; A source P+ region and a source N+ region disposed side by side in contact in the epitaxial layer, and the source P+ region is electrically connected to the multiple levels of P-type shielding regions through a P-well region; A source disposed on the top of the source P+ region and the source N+ region; A drain disposed at the bottom of the substrate; A gate structure penetrating the source P+ region and the source N+ region into the epitaxial layer, and the bottom is in contact with the multiple levels of P-type shielding regions; A P-type connection layer disposed on the outer wall side of a part of the gate structure, and the bottom is in contact with the multiple levels of P-type shielding regions and the multiple levels of N-type doped regions, for grounding the multiple levels of P-type shielding regions.

[0010] Based on the above technical solution, the present invention can also be improved as follows.

[0011] Further, the device structure further includes multiple levels of gate trenches; The multiple levels of gate trenches are disposed vertically in the epitaxial layer, and the bottom of the multiple levels of gate trenches has a radian; The multiple levels of P-type shielding regions are formed by implantation from the bottom of the multiple levels of gate trenches, and the width of the multiple levels of P-type shielding regions gradually decreases in the depth direction of the multiple levels of gate trenches.

[0012] Further, the multi-level gate trench includes a first-level gate trench and a second-level gate trench; The overall cross-section of the first-level gate trench and the second-level gate trench is stepped.

[0013] Further, the multi-level P-type shielding region includes a first-level P-type shielding region and a second-level P-type shielding region; The first-level P-type shielding region and the second-level P-type shielding region are arranged in sequence along the vertical direction; There is a first overlapping region between the first-level P-type shielding region and the second-level P-type shielding region, and the P-type doping concentration in the first overlapping region is higher than that in the non-first overlapping region.

[0014] Further, the multi-level N-type doping region includes a first-level N-type doping region and a second-level N-type doping region; The first-level N-type doping region and the second-level N-type doping region are arranged in sequence along the vertical direction, and are respectively arranged in corresponding wrapping with the first-level P-type shielding region and the second-level P-type shielding region; There is a second overlapping region between the first-level N-type doping region and the second-level N-type doping region, and the N-type doping concentration in the second overlapping region is higher than that in the non-second overlapping region.

[0015] Further, the gate structure includes a gate dielectric layer and gate polysilicon; The gate dielectric layer is arranged on the inner wall side of the multi-level gate trench; The gate polysilicon is filled in the trench inside the gate dielectric layer.

[0016] Further, the device structure further includes an interlayer dielectric layer; The interlayer dielectric layer is arranged on the top of the gate dielectric layer and the gate polysilicon.

[0017] Further, the device structure further includes a P buried layer; The P buried layer is arranged in the epitaxial layer; the P buried layer overlaps with the multi-level P-type shielding region in the vertical direction to ground the multi-level P-type shielding region.

[0018] In a second aspect, the present invention further provides a manufacturing method for manufacturing the wide-bandgap semiconductor trench MOSFET device structure as described in the first aspect, including the following steps: S1. Epitaxially grow an epitaxial layer on a substrate; S2. Etch the first-level trench and retain the hard mask, and the bottom of the first-level trench has a radian; S3. Perform P-type and N-type ion implantation at the bottom of the first-level trench to obtain a first-level P-type shielding region and a first-level N-type doped region; S4. Prepare sidewalls at the first-level trench and etch a second-level trench; S5. Horizontally etch a trench at the bottom of the first-level P-type shielding region, and perform P-type ion implantation to form a second-level P-type shielding region; there is an overlapping region between the second-level P-type shielding region and the first-level P-type shielding region; S6. Horizontally etch a trench at the bottom of the first-level N-type doped region, and implant to form a second-level N-type doped region; there is an overlapping region between the second-level N-type doped region and the first-level N-type doped region; S7. Remove the sidewalls and the hard mask; S8. Thermally oxidize to generate a gate oxide to obtain a gate dielectric layer, and deposit polysilicon to obtain gate polysilicon; S9. Deposit metal to form an interlayer dielectric layer, source and drain, thus obtaining the device.

[0019] Based on the above technical solutions, the present invention can be further improved as follows.

[0020] Further, in step S3, the concentration of P-type ion implantation is higher than that of N-type ion implantation, and the energy of N-type ion implantation is higher than that of P-type ion implantation.

[0021] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects: Compared with the prior art, the wide-bandgap semiconductor trench MOSFET device structure and its manufacturing method provided by the present invention have the following advantages: (1) The device structure forms multiple-level gate trenches and multiple-level P-type shielding regions through self-aligned etching; among them, the multiple-level gate trenches and multiple-level P-type shielding regions can introduce additional electric field concentration points, reducing the electric field intensity concentrated in the corners of the gate oxide; in an optional example, a P-type connection layer is provided to ground the P-type shielding region.

[0022] (2) In the forward conduction current flow direction of the multiple-level P-type shielding regions, the width of the P-type shielding regions gradually decreases, the current path width of the forward conduction current increases, and through the self-aligned process, the multiple-level stepped P-type shielding regions are wrapped by multiple-level N-type doped regions, and the concentration of the multiple-level N-type doped regions is higher than that of the epitaxial layer. The multiple-level N-type doped regions have the following advantages: the high-concentration N-type doping can prevent the P-type shielding region from forming an overly wide depletion region in the N-type doped region, reducing the influence of the P-type shielding region on the device conduction characteristics.

[0023] (3) The multiple-level P-type shielding regions are directly implanted from the bottom after etching, using a lower implantation energy on the premise of achieving the same depth of the P-type shielding regions.

[0024] In summary, the wide-bandgap semiconductor trench MOSFET device structure provided by the present invention has the effects of high power density, low power consumption, and high breakdown voltage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a three-dimensional structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention; Figure 2 is a structure schematic diagram at cross-section 1 and cross-section 2 of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention; Figures 3 - 6 is an effect verification schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 1 of the present invention; Figure 7 is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 2 of the present invention; Figure 8 is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 3 of the present invention; Figure 9 is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 4 of the present invention; Figure 10 is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 5 of the present invention; Figure 11 is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 6 of the present invention; Figure 12 is a structure schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 7 of the present invention; Figures 13 - 21 is a manufacturing method schematic diagram of the wide-bandgap semiconductor trench MOSFET device structure provided in Embodiment 8 of the present invention; In the drawings, the list of components represented by each reference numeral is as follows: 1. Substrate; 2. Epitaxial layer; 3. Multi-stage P-type shielding region; 301. First-stage P-type shielding region; 302. Second-stage P-type shielding region; 4. Multi-stage N-type doping region; 401. First-stage N-type doping region; 402. Second-stage N-type doping region; 5. Source P+ region; 6. Source N+ region; 7. Source; 8. Drain; 9. Gate structure; 901. Gate dielectric layer; 902. Gate polysilicon; 10. P well region; 11. P-type connection layer; 12. Interlayer dielectric layer; 13. P buried layer. Detailed implementation manners

[0026] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0027] The present invention provides a new wide-bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. The embodiments of the present invention will be further described in detail below in conjunction with the drawings and embodiments. The following embodiments are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0028] Embodiment 1 As Figure 1 and Figure 2 shown, the embodiment of the present invention provides a wide-bandgap semiconductor trench MOSFET device structure. It should be noted that: the device structure includes a first cross-section (cross-section 1) and a second cross-section (cross-section 2), which specifically include: substrate 1, epitaxial layer 2, multi-level P-type shielding region 3, multi-level N-type doping region 4, source P+ region 5, source N+ region 6, P-type connection layer 11, source 7, drain 8 and gate structure 9.

[0029] The epitaxial layer 2 is grown on the substrate 1.

[0030] The multi-level P-type shielding region 3 is disposed in the epitaxial layer 2 along the vertical direction, and the width dimension gradually decreases along the vertical direction.

[0031] The multi-level N-type doping region 4 is wrapped and disposed on the outer wall side of the multi-level P-type shielding region 3.

[0032] The source P+ region 5 and the source N+ region 6 are disposed in the epitaxial layer 2, and the source P+ region 5 is electrically connected to the multi-level P-type shielding region 3 through the P-well region.

[0033] The source 7 is disposed on the top of the source P+ region 5 and the source N+ region 6.

[0034] The drain 8 is disposed at the bottom of the substrate 1.

[0035] The gate structure 9 penetrates through the source P+ region 5 and the source N+ region 6 to the epitaxial layer 2, and the bottom contacts the multi-level P-type shielding region 3.

[0036] On cross-section 2, a multi-level P-type connection layer 11 is provided. The P-type connection layer 11 is disposed on the outer wall side of a part of the gate structure 9, and its bottom contacts the multi-level P-type shielding region 3 and the multi-level N-type doping region 4, and is used to ground the multi-level P-type shielding region 3.

[0037] In an alternative embodiment, as Figure 1 shown, the device structure further includes multi-level gate trenches; the multi-level gate trenches are disposed in the epitaxial layer 2 in the vertical direction, and the bottom of the multi-level gate trenches has a curvature.

[0038] The multi-level P-type shielding region 3 is formed by implantation from the bottom of the multi-level gate trenches, and the width of the multi-level P-type shielding region 3 gradually decreases in the depth direction of the multi-level gate trenches.

[0039] Specifically, the multi-level gate trenches include a first-level gate trench and a second-level gate trench; the overall cross-section of the first-level gate trench and the second-level gate trench is in a stepped shape.

[0040] In a specific embodiment, as Figure 1 shown, the above-mentioned multi-level P-type shielding region 3 includes a first-level P-type shielding region 301 and a second-level P-type shielding region 302.

[0041] The first-level P-type shielding region 301 and the second-level P-type shielding region 302 are arranged in sequence in the vertical direction.

[0042] There is a first overlapping region between the first-level P-type shielding region 301 and the second-level P-type shielding region 302, and the P-type doping concentration in the first overlapping region is higher than that in the non-first overlapping region.

[0043] Correspondingly, as Figure 1 shown, the multi-level N-type doping region 4 includes a first-level N-type doping region 401 and a second-level N-type doping region 402.

[0044] The first-level N-type doping region 401 and the second-level N-type doping region 402 are arranged in sequence in the vertical direction, and are respectively arranged corresponding to and wrapping the first-level P-type shielding region 301 and the second-level P-type shielding region 302.

[0045] There is a second overlapping region between the first-level N-type doping region 401 and the second-level N-type doping region 402, and the N-type doping concentration in the second overlapping region is higher than that in the non-second overlapping region.

[0046] It should be noted that the number of levels of the multi-level P-type shielding region 3, the multi-level gate trenches, and the multi-level N-type doping region 4 is not limited to the above two levels. In actual operation, the number of levels can be set as required. Therefore, in the embodiments of the present invention, the number of levels of the multi-level P-type shielding region 3, the multi-level gate trenches, and the multi-level N-type doping region 4 is defined as greater than or equal to 2.

[0047] In a specific embodiment, asFigure 1 As shown, the gate structure 9 includes a gate dielectric layer 901 and a gate polysilicon 902.

[0048] The gate dielectric layer 901 is disposed on the inner wall side of the multi-level gate trench; the gate polysilicon 902 is filled in the trench inside the gate dielectric layer 901.

[0049] Furthermore, the device structure further includes an interlayer dielectric layer 12; the interlayer dielectric layer 12 is disposed on the top of the gate dielectric layer 901 and the gate polysilicon 902.

[0050] Effect description: Regarding the technical defect 1 in the prior art: The device structure provided by this embodiment forms a multi-level gate trench and multi-level P-type shielding regions 3 (a first-level P-type shielding region 301 and a second-level P-type shielding region 302) through self-aligned etching. The multi-level gate trench and the multi-level P-type shielding regions 3 can introduce additional electric field concentration points and reduce the electric field intensity concentrated in the gate oxide corner; on cross-section 2, a P-type connection layer 11 is provided to ground the P-type shielding region.

[0051] The doping concentration distribution of the device simulation structure is as Figure 3 shown (the left figure is a normal gate / the right figure is the multi-level gate trench of this embodiment). Comparing the two structures, the structure proposed in this patent introduces a multi-level gate trench, a multi-level P-type shielding region 3 structure, and multi-level N-type doping regions 4 surrounding the multi-level P-type shielding region 3 (since the concentration of the multi-level N-type doping regions 4 is not much different from the concentration of the surrounding drift region, it is not shown in the figure).

[0052] The electric field distribution of the device in the blocking state is as Figure 4 shown (the left figure is a normal gate / the right figure is the multi-level gate trench of this embodiment). Comparing the two structures, due to the structure proposed in this patent introducing a multi-level gate trench and a multi-level P-type shielding region 3 structure, additional electric field concentration points are introduced, reducing the electric field of the gate oxide. The maximum electric field intensity of the gate oxide of the device structure proposed in this embodiment is 1.78 MV / cm (V ds = 1200 V, V gs = 0 V), which is reduced by 12.3% compared with the traditional structure.

[0053] Regarding the technical defect 2 in the prior art: In the current flowing direction of the forward conduction current of the multi-level P-type shielding region 3, the width of the P-type shielding region gradually decreases, and the current path width of the forward conduction current increases. And through the self-aligned process, the multi-level stepped P-type shielding region is wrapped by the multi-level N-type doping regions 4, and the concentration of the multi-level N-type doping regions 4 is higher than that of the epitaxial layer 2. The multi-level N-type doping regions 4 have the following advantages: The high-concentration N-type doping can prevent the P-type shielding region from forming an over-wide depletion region in the N-type epitaxial layer 2 region, reducing the influence of the P-type shielding region on the conduction characteristics of the device.

[0054] The device current distribution in the on-state is as Figure 5 shown (the figure shows a common gate / the right figure shows the multi-level gate trench of this embodiment). The device output characteristic curve in the on-state is as Figure 6 shown. Comparing the two structures, in the multi-level P-type shielding region in the forward conduction current flow direction, the width of the P-type shielding region gradually decreases, the width of the current path of the forward conduction current increases, and the stepped highly doped N-type doping region around the P-type shielding region can minimize the impact of the new structure on the device conduction energy. The on-resistance of the device proposed in this embodiment and the traditional structure device is .

[0055] In summary, the structure provided in this embodiment can reduce the gate oxide electric field strength by 12.3% without affecting the device conduction ability.

[0056] Regarding the technical defect 3 in the prior art: A feasible process step for this structure is proposed for the device structure provided in this embodiment. In this process flow, both the multi-level P-type shielding region 3 and the multi-level N-type doping region 4 are implanted from the bottom of the trench. The advantage of doing this is to reduce the energy required for ion implantation.

[0057] Embodiment 2 Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 7 shown, the multi-level trench may not be provided, and the stepped multi-level P-type shielding region 3 and multi-level N-type doping region 4 are realized through multi-layer layout and increasing the energy of N-type ion implantation.

[0058] Embodiment 3 Based on Embodiment 1, the difference from Embodiment 1 is that since Figure 1 the cross-section 1 can conduct current and the cross-section 2 cannot conduct current, by adjusting the ratio of the cross-section 1 and the cross-section 2 in the chip (as Figure 8 shown, only the layout of the P-type connection layer 11 in the trench extension direction is shown in the top view), the control of current and heat distribution can be realized, and finally the purpose of improving the extreme stress reliability of the device can be achieved.

[0059] Embodiment 4 Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 9 shown, a P buried layer 13 can be provided in the epitaxial layer - the P buried layer 13 is provided in the epitaxial layer; the P buried layer 13 overlaps with the multi-level P-type shielding region in the vertical direction to ground the multi-level P-type shielding region.

[0060] The advantage of doing this is to further reduce the electric field strength of the gate oxide, as Figure 9As shown in (Cross-section 2), the P buried layer 13 overlaps with the P-type shielding region in the vertical direction. The advantage of this is that the P buried layer 13 can ground the P-type shielding region through layout design, as shown in Cross-section 2. Moreover, by adjusting the size and position of the opening of the P-type shielding region, the control of current and heat distribution can be achieved, and ultimately the purpose of improving the extreme stress reliability of the device can be realized.

[0061] Example 5 Based on Example 4, the difference from Example 4 is that: on the basis of the above solution, further, as Figure 10 shown, by adding a layout, deeper multi-level P-type shielding region 3 ion implantation can be achieved on the cross-section, and the P buried layer 13 can be grounded through the deeper multi-level P-type shielding region 3.

[0062] Example 6 Based on Example 4, the difference from Example 4 is that: on the basis of the above solution, further, as Figure 11 shown, the electrical connection between the P buried layer 13 and the source (GND) can be achieved by increasing the ion implantation energy of the source P+ region 5.

[0063] Example 7 Based on Example 4, the difference from Example 4 is that: on the basis of the above solution, further, as Figure 12 shown, by adding a layout, a deeper-level sub-trench can be achieved on some cross-sections - to obtain a deeper gate structure 9, and deeper multi-level P-type shielding region 3 ion implantation can be achieved based on the deeper-level sub-trench, and the P buried layer 13 can be grounded through the deeper multi-level P-type shielding region 3.

[0064] Example 8 The embodiment of the present invention provides a manufacturing method for the wide-bandgap semiconductor trench MOSFET device structure corresponding to Example 1. Referring to Figures 13 - 21 shown, the operations are as follows: Step S1, ( Figure 13 shown) epitaxially grow an epitaxial layer on the substrate.

[0065] Step S2, ( Figure 14 shown) etch the first-level trench and retain the hard mask. The bottom of the first-level trench has a radian.

[0066] Step S3, ( Figure 15 shown) perform P-type and N-type ion implantation at the bottom of the first-level trench to obtain the first-level P-type shielding region and the first-level N-type doped region.

[0067] Among them, the concentration of P-type ion implantation is higher than that of N-type ion implantation, and the energy of N-type ion implantation is higher than that of P-type ion implantation.

[0068] Due to the curvature at the bottom of the trench, the N-type and P-type regions generated by ion implantation will not be entirely at the bottom of the channel. Some ions will be implanted into both sides of the trench bottom and cause diffusion. The concentration of P-type ion implantation is higher than that of N-type ion implantation (to avoid compensation of P-type ion implantation by N-type ion implantation), and the energy of N-type ion implantation is higher than that of P-type ion implantation (to achieve a deeper depth and lateral diffusion for N-type ion implantation).

[0069] Step S4, ( Figure 16 as shown) prepare sidewalls at the first-level trench and etch the second-level trench.

[0070] Step S5, ( Figure 17 as shown) laterally etch a trench at the bottom of the first-level P-type shielding region, and perform P-type ion implantation to form the second-level P-type shielding region; there is an overlapping region between the second-level P-type shielding region and the first-level P-type shielding region, and the P-type doping concentration in this overlapping region is higher, providing a better protection ability for the gate oxide.

[0071] Step S6, ( Figure 18 as shown) laterally etch a trench at the bottom of the first-level N-type doping region, and implant to form the second-level N-type doping region. There is an overlapping region between the second-level N-type doping region and the first-level N-type doping region, and the N-type doping concentration in this overlapping region is higher, which can limit the influence of the depletion region of the high-concentration P-type shielding region on the current path.

[0072] Step S7, ( Figure 19 as shown) remove the sidewalls and the hard mask.

[0073] Step S8, ( Figure 20 as shown) thermally oxidize to generate the gate oxide to obtain the gate dielectric layer, and deposit polysilicon to obtain the gate polysilicon.

[0074] Step S9, ( Figure 21 as shown) deposit metal to form the interlayer dielectric layer, source, and drain, thus obtaining the device.

[0075] Since this manufacturing method is used for manufacturing the wide-bandgap semiconductor trench MOSFET device structure, the beneficial effects of the wide-bandgap semiconductor trench MOSFET device structure also apply to this manufacturing method. For its beneficial effects, reference can be made to the above effect description, and no further elaboration will be provided here.

[0076] In this specification, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide bandgap semiconductor trench MOSFET device structure, characterized in that: include: Epitaxial layer, grown on the substrate; A multi-level P-type shielding region is disposed in the epitaxial layer along a vertical direction, and a width dimension thereof gradually decreases along the vertical direction; A multi-level N-type doping region, wrapped around the outer wall side of the multi-level P-type shielding region; A source P+ region and a source N+ region are arranged in contact with each other in the epitaxial layer, and the source P+ region is electrically connected to the multi-level P-type shielding region through a P-well region; A source, disposed on top of the source P+ region and the source N+ region; A drain electrode, disposed at the bottom of the substrate; A gate structure, penetrating the source P+ region and the source N+ region to the epitaxial layer, and having a bottom in contact with the multi-level P-type shielding region; The P-type connection layer is arranged on the outer wall side of part of the gate structure, and the bottom thereof is in contact with the multi-level P-type shielding area and the multi-level N-type doping area, so as to realize the grounding of the multi-level P-type shielding area.

2. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The device structure also includes a multi-level gate trench; The multi-level gate trenches are arranged in the epitaxial layer along a vertical direction, and the bottoms of the multi-level gate trenches have a curvature; The multi-level P-type shielding region is formed by implanting from the bottom of the multi-level gate trench, and the width of the multi-level P-type shielding region is gradually reduced along the depth direction of the multi-level gate trench.

3. The wide bandgap semiconductor trench MOSFET device structure according to claim 2, characterized in that: The multi-level gate trenches include a first-level gate trench and a second-level gate trench; The overall cross-section of the first-stage gate trench and the second-stage gate trench is in a step shape.

4. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The multi-level P-type shielding region includes a first-level P-type shielding region and a second-level P-type shielding region; The first-level P-type shielding region and the second-level P-type shielding region are arranged in sequence along the vertical direction; There is a first overlapping region between the first-level P-type shielding region and the second-level P-type shielding region, and the P-type doping concentration in the first overlapping region is higher than that in the non-first overlapping region.

5. The wide bandgap semiconductor trench MOSFET device structure according to claim 4, characterized in that: The multi-level N-type doping region includes a first-level N-type doping region and a second-level N-type doping region; The first-level N-type doping region and the second-level N-type doping region are arranged in sequence along the vertical direction, and are respectively wrapped with the first-level P-type shielding region and the second-level P-type shielding region; There is a second overlapping region between the first-level N-type doping region and the second-level N-type doping region, and the N-type doping concentration in the second overlapping region is higher than that in the non-second overlapping region.

6. The wide bandgap semiconductor trench MOSFET device structure according to claim 2, characterized in that: The gate structure includes a gate dielectric layer and gate polysilicon; The gate dielectric layer is arranged on the inner wall side of the multi-level gate trench; The gate polysilicon is filled in the trench inside the gate dielectric layer.

7. The wide bandgap semiconductor trench MOSFET device structure according to claim 6, characterized in that: The device structure also includes an interlayer dielectric layer; The interlayer dielectric layer is arranged on top of the gate dielectric layer and the gate polysilicon.

8. The wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The device structure also includes a P buried layer; The P buried layer is arranged in the epitaxial layer; the P buried layer overlaps with the multi-level P-type shielding region in a vertical direction, so that the multi-level P-type shielding region is grounded.

9. A method for manufacturing a wide bandgap semiconductor trench MOSFET device structure as claimed in any one of claims 1 to 8, characterized in that: The following steps are involved: S1, epitaxially growing an epitaxial layer on a substrate; S2, etching a first-level trench and retaining a hard mask, wherein the bottom of the first-level trench has a curvature; S3, performing P-type and N-type ion implantation at the bottom of the first-level trench to obtain a first-level P-type shielding region and a first-level N-type doping region; S4, preparing a sidewall at the first-level groove, and etching a second-level groove; S5, etching a groove laterally at the bottom of the first-level P-type shielding region, and implanting P-type ions to form a second-level P-type shielding region; the second-level P-type shielding region and the first-level P-type shielding region have an overlapping area; S6, laterally etching a trench at the bottom of the first-level N-type doping region, and implanting to form a second-level N-type doping region, wherein the second-level N-type doping region and the first-level N-type doping region have an overlapping region; S7, removing the sidewall spacer and the hard mask; S8, thermally oxidizing to generate a gate oxide to obtain a gate dielectric layer, and depositing polysilicon to obtain gate polysilicon; S9. Deposit metal to form an interlayer dielectric layer, a source electrode and a drain electrode.

10. The manufacturing method according to claim 9, characterized in that: In step S3 , the concentration of the P-type ion implantation is higher than that of the N-type ion implantation, and the energy of the N-type ion implantation is higher than that of the P-type ion implantation.

Images