LDMOS device and manufacturing method thereof

Abstract

The invention relates to an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a manufacturing method thereof, the LDMOS device comprises a substrate, a drift region, a body electrode, a source region, a drain region, a gate oxide layer, a gate electrode, an isolation oxide layer and a side wall, and further comprises a first field plate, the first field plate is positioned on the surface of the drift region between the gate electrode and the source region, partially covers the surface of the side wall, and is connected with a zero potential; and the second field plate and the first field plate are horizontally arranged, and the second field plate is located between the drift region and the grid electrode and is close to the first field plate. The two horizontally arranged field plate structures can introduce another collision ionization peak value on the basis of a single field plate structure, and the collision ionization peak value at the weak part of the single field plate structure is reduced, so that the overall breakdown voltage of the device is improved. Moreover, the structure is relatively simple, is easy to prepare, and can be applied to tape-out of an actual production line.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to an LDMOS device and a manufacturing method thereof. Background Art

[0002] In the post-Moore era, the development trend of integrated circuits has shifted from miniaturization to functionality. Power integrated circuits have been widely used in many fields such as power control, automotive electronics, consumer, and communication electronics. BCD technology is currently the most critical single-chip power integrated circuit technology, which is a manufacturing process that integrates Bipolar, CMOS, and DMOS structures. Compared with traditional bipolar power processes, BCD technology has significant advantages. Its most fundamental advantage lies in that designers can flexibly choose between high-precision analog bipolar, highly integrated CMOS, and DMOS as the power stage. Since the process of DMOS is compatible with the CMOS process and has characteristics such as high efficiency (low loss), high strength (no second breakdown), and high breakdown voltage, the DMOS structure is particularly suitable for power integrated circuits.

[0003] In the DMOS structure adopted in BCD technology, the Lateral Double-Diffused Metal Oxide Semiconductor (LDMOS) is widely used in power integrated circuits. LDMOS uses the lateral double-diffusion technology to simultaneously dope two kinds of ions, B (boron) and P (phosphorus), in the same window, and forms a channel structure by using the different diffusion rates of different ions. The lateral double-diffusion technology can accurately control the device channel size, making LDMOS have a large input impedance, low power consumption in driving applications, and being easy to couple with the front stage. In addition, LDMOS has a negative temperature characteristic, and the drain current can be automatically equalized at high temperatures, so it is not easy to form local hot spots and has high reliability. Since the source, drain, and gate of the LDMOS device are all on the chip surface, it can be integrated with CMOS and Bipolar, and is very suitable for use as a power output device. With the development of medium and low voltage consumer electronics applications such as motor drive, power management, and automotive electronics, the high-density small-size BCD process technology integrated with LDMOS devices has gradually become the mainstream platform technology, and LDMOS has also become the focus and difficulty of device design in BCD technology. Therefore, researching how to develop a stable LDMOS process has important economic benefits.

[0004] At present, how to balance the off-state breakdown voltage and on-state conduction resistance of LDMOS is a difficult point in the research and development of LDMOS devices. The traditional LDMOS structure relies on a lightly doped drift region to bear the voltage. A lower doping concentration means a decrease in the number of carriers. According to the formula σ = nqμn + pqμp and ρ = 1 / σ, it can be known that the resistivity will increase due to low doping, which makes the conduction resistance larger and the current smaller. If you want to reduce the conduction resistance, you need to increase the doping concentration of the drift region, which will in turn lead to an increase in the peak value of the electric field when the off-state bears voltage and reduce the off-state breakdown voltage. Therefore, there is an irreconcilable contradiction between the on-state conduction resistance and off-state breakdown voltage of traditional LDMOS. A trade-off needs to be made between the two during device research and development, and this contradiction can only be solved through the research and development of a new LDMOS device structure. Summary of the Invention

[0005] Based on this, it is necessary to provide an LDMOS device and its manufacturing method for the above problems, so as to optimize the device structure and improve the off-state breakdown voltage on the premise of keeping the conduction resistance unchanged.

[0006] In order to achieve the above object, the technical solutions adopted by the present invention are as follows:

[0007] An LDMOS device includes: a substrate and a drift region located on the surface of the substrate. A body region is provided on one side of the drift region. A body electrode and a source region are provided inside the surface of the body region. A drain region is provided on the other side of the drift region. A gate oxide layer is provided on the surface of the drift region. Part of the gate oxide layer covers the surface of the source region. A gate electrode, an isolation oxide layer and a sidewall are provided on the surface of the gate oxide layer. It also includes:

[0008] A first field plate, which is located on the surface of the drift region between the gate electrode and the source region, partially covers the surface of the sidewall, and the first field plate is connected to zero potential;

[0009] A second field plate, which is horizontally arranged with the first field plate, is located between the drift region and the gate electrode and is close to the first field plate.

[0010] In one embodiment, the second field plate is provided on the surface of the drift region, penetrates the gate oxide layer and is connected to the gate electrode.

[0011] In one embodiment, the manufacturing material of the second field plate is low-temperature oxide.

[0012] In one embodiment, the second field plate is a LOCOS field plate, and the second field plate penetrates the gate oxide layer and is connected to the gate electrode.

[0013] In one embodiment, the second field plate is a STI field plate, and the second field plate is located below the gate oxide layer.

[0014] Another embodiment discloses a manufacturing method of an LDMOS device, including:

[0015] Providing a substrate;

[0016] Forming a drift region on the surface of the substrate;

[0017] Doping one side of the drift region to form a body region;

[0018] Forming a second field plate on the surface of the drift region;

[0019] Forming a gate oxide layer on the surface of the drift region;

[0020] Forming a gate, an isolation oxide layer, and sidewalls on the surface of the gate oxide layer;

[0021] Forming a first field plate on the other side surface of the drift region;

[0022] Doping the drift region and the body region to form a source region, a drain region, and a body electrode;

[0023] Wherein, the first field plate is located on the surface of the drift region between the gate and the source region, partially covers the surface of the sidewall, and the first field plate is connected to the zero potential; the second field plate is horizontally arranged with the first field plate, located between the drift region and the gate and close to the first field plate.

[0024] In one embodiment, the second field plate is disposed on the surface of the drift region, penetrates through the gate oxide layer and is connected to the gate.

[0025] In one embodiment, the manufacturing material of the second field plate is low-temperature oxide.

[0026] In one embodiment, the second field plate is a LOCOS field plate, and the second field plate penetrates through the gate oxide layer and is connected to the gate.

[0027] In one embodiment, the second field plate is a STI field plate, and the second field plate is located under the gate oxide layer.

[0028] For the LDMOS device and its manufacturing method disclosed by the present invention, field plate structures are respectively arranged on the surface of the drift region and on one side of the gate region close to the drain region. The two horizontally arranged field plate structures can introduce another impact ionization peak on the basis of the single field plate structure, reduce the impact ionization peak at the weak part of the single field plate structure, thereby improving the breakdown voltage of the overall device. Moreover, this structure is relatively simple, easy to prepare, and can be applied to actual production line chip flow. Description of the Drawings

[0029] Figure 1Schematic diagram of an LDMOS device structure provided by an embodiment of the present invention;

[0030] Figure 2 Schematic diagram of the output characteristic curves of a dual-field-plate LDMODS device with a CFP field plate + an LTO field plate and a single-field-plate LDMODS device with a CFP field plate provided by the present invention;

[0031] Figure 3 Breakdown voltage images of a dual-field-plate LDMODS device with a CFP field plate + an LTO field plate and a single-field-plate LDMODS device with a CFP field plate provided by the present invention;

[0032] Figure 4 Current density simulation diagrams of a dual-field-plate LDMODS device with a CFP field plate + an LTO field plate and a single-field-plate LDMODS device with a CFP field plate provided by the present invention;

[0033] Figure 5 Impact ionization images of a dual-field-plate LDMODS device with a CFP field plate + an LTO field plate and a single-field-plate LDMODS device with a CFP field plate provided by the present invention;

[0034] Figure 6 Electric field intensity images of a dual-field-plate LDMODS device with a CFP field plate + an LTO field plate and a single-field-plate LDMODS device with a CFP field plate provided by the present invention;

[0035] Figure 7 Schematic diagram of another LDMOS device structure provided by another embodiment of the present invention;

[0036] Figure 8 Schematic diagram of another LDMOS device structure provided by another embodiment of the present invention;

[0037] Figure 9 Output characteristic curves of a single-field-plate LDMODS device with a CFP field plate, a dual-field-plate LDMODS device with a CFP field plate + a LOCOS field plate, and a dual-field-plate LDMODS device with a CFP field plate + a STI field plate provided by the present invention;

[0038] Figure 10 Current density simulation diagrams of a single-field-plate LDMODS device with a CFP field plate, a dual-field-plate LDMODS device with a CFP field plate + a LOCOS field plate, and a dual-field-plate LDMODS device with a CFP field plate + a STI field plate provided by the present invention;

[0039] Figure 11Breakdown voltage images of the single-field-plate LDMODS device with a CFP field plate, the dual-field-plate LDMODS device with a CFP field plate + LOCOS field plate, and the dual-field-plate LDMODS device with a CFP field plate + STI field plate provided by the present invention;

[0040] Figure 12 Impact ionization images of the single-field-plate LDMODS device with a CFP field plate, the dual-field-plate LDMODS device with a CFP field plate + LOCOS field plate, and the dual-field-plate LDMODS device with a CFP field plate + STI field plate provided by the present invention;

[0041] Figure 13 Electric field intensity images of the single-field-plate LDMODS device with a CFP field plate, the dual-field-plate LDMODS device with a CFP field plate + LOCOS field plate, and the dual-field-plate LDMODS device with a CFP field plate + STI field plate provided by the present invention;

[0042] Figure 14a - 14i Structural diagrams of each step of a method for manufacturing an LDMOS device provided by the present invention;

[0043] Figure 15 Schematic diagram of an LDMOS device with specific dimensions provided by an embodiment of the present invention;

[0044] Figure 16 Schematic diagram of another LDMOS device with specific dimensions provided by another embodiment of the present invention;

[0045] Figure 17 Schematic diagram of another LDMOS device with specific dimensions provided by another embodiment of the present invention.

[0046] In the figure, 1, substrate; 2, drift region; 3, body region; 4, body electrode; 5, source region; 6, drain region; 7, gate oxide layer; 8, gate electrode; 9, isolation oxide layer; 10, sidewall; 11, first field plate; 12, second field plate. Detailed implementation manners

[0047] To facilitate the understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the description of the present invention herein are for the purpose of describing specific embodiments or examples only and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, as well as any and all combinations of the related listed items, and the any and all combinations include combinations of any two related listed items, any more than two related listed items, or all related listed items.

[0049] As Figure 1 shown, an embodiment of the present invention discloses an LDMOS device, including: a substrate 1 and a drift region 2 located on the surface of the substrate 1. A body region 3 is provided on one side of the drift region 2. A body electrode 4 and a source region 5 are provided inside the surface of the body region 3. A drain region 6 is provided on the other side of the drift region 2. A gate oxide layer 7 is provided on the surface of the drift region 2. Part of the gate oxide layer 7 covers the surface of the source region 5. A gate electrode 8, an isolation oxide layer 9 and a sidewall 10 are provided on the surface of the gate oxide layer 7. In addition, the LDMOS device further includes:

[0050] A first field plate 11, which is located on the surface of the drift region 2 between the gate electrode 8 and the source region 5, partially covers the surface of the sidewall 10, and the first field plate 11 is connected to a zero potential;

[0051] A second field plate 12, which is horizontally arranged with the first field plate 11, is located between the drift region 2 and the gate electrode 8 and is close to the first field plate 11.

[0052] In this embodiment, the drift region 2 is lightly doped with the first conductivity type, the body region 3 is doped with the second conductivity type with a doping concentration slightly higher than that of the drift region, the body electrode 4 is heavily doped with the first conductivity type, the source region 5 is heavily doped with the second conductivity type, and the drain region 6 is heavily doped with the first conductivity type. The first field plate 11 is located on the surface of the drift region 2 and is connected to a zero potential, that is, a CFP (Contact Filed Plate) field plate structure is formed. Compared with other field plates, since the field oxide of the first field plate 11 is not inside the silicon, the current path will be better than that of field plates such as STI and LOCOS, and the on-resistance Ron will also be smaller than that of the remaining field plate structures.

[0053] In addition, the substrate in this embodiment may include semiconductor elements, such as silicon or silicon germanium (SiGe) with single-crystalline, polycrystalline or amorphous structures, or may also include hybrid semiconductor structures, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. Although several examples of materials that can form the substrate are described herein, any material that can be used as a semiconductor substrate falls within the spirit and scope of the present invention.

[0054] In the LDMOS device disclosed in the embodiment of the present invention, field plate structures are respectively provided on the surface of the drift region and on one side of the gate region close to the drain region. The two horizontally arranged field plate structures can introduce another impact ionization peak on the basis of the single field plate structure, reducing the impact ionization peak at the weak part of the single field plate structure, thereby increasing the breakdown voltage of the overall device. Moreover, this structure is relatively simple and easy to fabricate, and can be applied to actual production line wafer fabrication.

[0055] In another embodiment, as Figure 1 shown, the second field plate 12 is disposed on the surface of the drift region 2, penetrates the gate oxide layer 7 and is connected to the gate 8.

[0056] Specifically, the material for fabricating the second field plate is low temperature oxide (LTO).

[0057] Low temperature oxide (LTO) has good insulation performance, can effectively isolate the electric field, reduce the leakage phenomenon, and provides a stable insulation basis for the field plate structure. It can better adapt to various process steps in the semiconductor manufacturing process and has good compatibility with other semiconductor materials and processes.

[0058] In yet another embodiment of the present invention, electrical characteristics tests were performed on the above-mentioned dual-field plate LDMODS device with a CFP field plate + LTO field plate, and the results are as Figure 2 and Figure 3 shown.

[0059] Among them, Figure 2 is a schematic diagram of the output characteristic curves of the dual-field plate LDMODS device with a CFP field plate + LTO field plate and the single-field plate LDMODS device with a CFP field plate. As can be seen from Figure 2 this, the two output curves almost coincide, indicating that the on-resistance of the dual-field plate LDMODS device with a CFP field plate + LTO field plate structure is almost the same as that of the single-field plate LDMODS device with a single CFP field plate.

[0060] Figure 3 is an image of the breakdown voltage of the dual-field plate LDMODS device with a CFP field plate + LTO field plate and the single-field plate LDMODS device with a CFP field plate. As can be seen from Figure 3It can be seen that the double-field-plate LDMODS device with the CFP field plate + LTO field plate structure significantly has a better breakdown voltage.

[0061] In another embodiment of the present invention, a simulation experiment is carried out on the double-field-plate LDMODS device with the CFP field plate + LTO field plate, and the results are as Figures 4 - 6 shown.

[0062] Among them, Figure 4 is the current density simulation diagram of the double-field-plate LDMODS device with the CFP field plate + LTO field plate and the single-field-plate LDMODS device with the CFP field plate. It can be seen that the current density and path of the two structures are almost the same. This is also the reason why the on-resistance of this structure is almost unchanged.

[0063] In the prior art, the peak of off-state impact ionization is generally used to represent the weak point of device breakdown. Therefore, the inventor carried out a simulation on the impact ionization images of the double-field-plate LDMODS device with the CFP field plate + LTO field plate and the single-field-plate LDMODS device with the CFP field plate under the off-state and the same drain terminal voltage (20V), and the results are as Figure 5 shown.

[0064] It can be seen that the double-field-plate LDMODS device with the CFP field plate + LTO field plate reduces the peak of impact ionization at the weak point of the CFP field plate structure of the single-field-plate LDMODS device with the CFP field plate by introducing another peak of impact ionization, thereby increasing the overall breakdown voltage of the device.

[0065] Figure 6 is the electric field intensity image of the double-field-plate LDMODS device with the CFP field plate + LTO field plate and the single-field-plate LDMODS device with the CFP field plate under the off-state and the same drain terminal voltage (20V). Since the increase in breakdown voltage is generally attributed to the decrease in electric field intensity at the weak point, the above embodiment reduces the peak of the electric field at the weak point of the single CFP structure by introducing another peak of electric field intensity, thereby increasing the overall breakdown voltage of the device.

[0066] From the above electrical characteristic tests and simulation results, it can be seen that for the LDMOS device disclosed in the present invention, a field plate structure is respectively arranged on the surface of the drift region and the side of the gate region close to the drain region. That is, in one embodiment, the first field plate structure is a CFP field plate, and the second field plate structure is an LTO field plate. The two horizontally arranged field plate structures can introduce another peak of impact ionization on the basis of the single-field-plate structure, reduce the peak of impact ionization at the weak point of the single-field-plate structure, and thereby increase the overall breakdown voltage of the device. Moreover, this structure is relatively simple, easy to fabricate, and can be applied to actual production line wafer processing.

[0067] Another embodiment discloses another LDMOS device, which is different from the above embodiment in that, as Figure 7 shown, the second field plate 12 is a LOCOS field plate, and the second field plate 12 penetrates the gate oxide layer 7 and is connected to the gate 8.

[0068] That is, the second field plate 12 is composed of a silicon dioxide layer grown on the surface of the drift region, a part of which is embedded in the surface of the drift region, and another part penetrates the gate oxide layer 7 and is connected to the gate 8.

[0069] Another embodiment discloses another LDMOS device, which is different from the above embodiment in that, as Figure 8 shown, the second field plate 12 is a STI field plate, and the second field plate 12 is located below the gate oxide layer 7.

[0070] That is, the second field plate 12 is formed by etching a shallow trench on the surface of the drift region and filling it with an insulating material such as silicon dioxide. Its whole is located on the surface of the drift region and does not penetrate the gate oxide layer 7 as in the above embodiment, but is entirely located between the gate oxide layer 7 and the drift region.

[0071] Another embodiment of the present invention still takes the single-field-plate LDMODS device with a CFP field plate as a reference, and conducts electrical characteristic tests on the above double-field-plate LDMODS devices with a CFP field plate + LOCOS field plate and a CFP field plate + STI field plate. The output characteristic curves are as Figure 9 shown. As can be seen from Figure 9 it, although the on-resistance of the double-field-plate LDMODS device with a CFP field plate + LOCOS field plate and the double-field-plate LDMODS device with a CFP field plate + STI field plate shows a certain degree of deterioration, the deterioration amplitude is still within an acceptable range.

[0072] This embodiment still takes the single-field-plate LDMODS device with a CFP field plate as a reference, and conducts current density simulation on the above double-field-plate LDMODS devices with a CFP field plate + LOCOS field plate and a CFP field plate + STI field plate. The simulation images are as Figure 10As shown. It can be seen that the current path of the single field plate LDMODS device with a CFP field plate is bent. For the dual field plate LDMODS devices with a CFP field plate + LOCOS field plate and a CFP field plate + STI field plate, since the drift region needs to be etched, a part of the original drift region through which the current flows is etched away. Therefore, the on-state current will decrease to a certain extent, which in turn leads to an increase in the on-resistance, but the increase amplitude is not high and is still within an acceptable range. Relatively speaking, for the dual field plate LDMODS device with a CFP field plate + LTO field plate, since the LTO field plate is fabricated on the surface of the drift region and does not affect the overall structure of the drift region, it will not occupy the current path. Therefore, its current path is basically the same as that of the single field plate LDMODS device with a CFP field plate, and thus has basically the same on-resistance.

[0073] Figure 11 It is the breakdown voltage image of the single field plate LDMODS device with a CFP field plate, the dual field plate LDMODS device with a CFP field plate + LOCOS field plate, and the dual field plate LDMODS device with a CFP field plate + STI field plate. From Figure 11 it can be seen that the dual field plate LDMODS devices with a CFP field plate + LOCOS field plate and a CFP field plate + STI field plate still have better breakdown voltages.

[0074] Figure 12 It is the simulation diagram of the impact ionization image of the single field plate LDMODS device with a CFP field plate, the dual field plate LDMODS device with a CFP field plate + LOCOS field plate, and the dual field plate LDMODS device with a CFP field plate + STI field plate in the off state and at the same drain terminal voltage (20V). Figure 13 It is the electric field intensity image of the single field plate LDMODS device with a CFP field plate, the dual field plate LDMODS device with a CFP field plate + LOCOS field plate, and the dual field plate LDMODS device with a CFP field plate + STI field plate in the off state and at the same drain terminal voltage (20V). Further combining Figure 5 and Figure 6 it can be seen that the dual field plate LDMODS device with a CFP field plate + LTO field plate reduces the electric field near the breakdown point without changing the position of the breakdown point, thus increasing the breakdown voltage; while the dual field plate LDMODS devices with a CFP field plate + LOCOS field plate and a CFP field plate + STI field plate change the position of the breakdown point, completely changing the original electric field distribution, and thus changing the breakdown voltage. This also leads to different conductive characteristics of the three second field plate structures.

[0075] If the dual-field-plate LDMODS devices with CFP field plate + LTO field plate, the dual-field-plate LDMODS devices with CFP field plate + LOCOS field plate, and the dual-field-plate LDMODS devices with CFP field plate + STI field plate are compared, the structural superiority can be measured by FOM (Figure of merit) = BV2 / Rsp. The results obtained by calculation are as follows:

[0076] The dual-field-plate LDMODS device with CFP field plate + LTO field plate is superior to the dual-field-plate LDMODS device with CFP field plate + STI field plate, which is superior to the dual-field-plate LDMODS device with CFP field plate + LOCOS field plate.

[0077] However, comprehensively, the performances of the dual-field-plate LDMODS devices with CFP field plate + LTO field plate, the dual-field-plate LDMODS devices with CFP field plate + LOCOS field plate, and the dual-field-plate LDMODS devices with CFP field plate + STI field plate are all superior to the single-field-plate LDMODS device with CFP field plate, and are even more superior to the single-field-plate LDMODS devices with LOCOS, STI or LTIO field plates.

[0078] Another embodiment of the present invention discloses a manufacturing method of an LDMOS device, including:

[0079] Providing a substrate;

[0080] Forming a drift region on the surface of the substrate;

[0081] Doping one side of the drift region to form a body region;

[0082] Forming a second field plate on the surface of the drift region;

[0083] Forming a gate oxide layer on the surface of the drift region;

[0084] Forming a gate, an isolation oxide layer and a sidewall on the surface of the gate oxide layer;

[0085] Forming a first field plate on the surface of the other side of the drift region;

[0086] Doping the drift region and the body region to form a source region, a drain region and a body electrode;

[0087] Wherein, the first field plate is located on the surface of the drift region between the gate and the source region, partially covers the surface of the sidewall, and the first field plate is connected to a zero potential; the second field plate is horizontally arranged with the first field plate, located between the drift region and the gate and close to the first field plate.

[0088] The drift region is lightly doped with the first conductivity type, the body region is doped with the second conductivity type with a doping concentration slightly higher than that of the drift region, the body electrode is heavily doped with the first conductivity type, the source region is heavily doped with the second conductivity type, and the drain region is heavily doped with the first conductivity type.

[0089] In the manufacturing method of the LDMOS device disclosed in this embodiment, field plate structures are respectively arranged on the surface of the drift region and on one side of the gate region close to the drain region. The two horizontally arranged field plate structures can introduce another impact ionization peak on the basis of a single field plate structure, reducing the impact ionization peak at the weak part of the single field plate structure, thereby increasing the breakdown voltage of the overall device. Moreover, this structure is relatively simple, easy to fabricate, and can be applied to actual production line chip fabrication.

[0090] Another embodiment discloses a manufacturing method of another LDMOS device, as Figure 14a - Figure 14i shown, the method includes:

[0091] As Figure 14a shown, a substrate is provided. The substrate may include semiconductor elements, such as silicon or silicon germanium (SiGe) in single-crystal, polycrystalline or amorphous structures, or may also include a mixed semiconductor structure, such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductors or combinations thereof. Although several examples of materials that can form the substrate are described herein, any material that can serve as a semiconductor substrate falls within the spirit and scope of the present invention. In this embodiment, the substrate further includes an epitaxy doped with the second conductivity type.

[0092] As Figure 14b shown, a drift region is formed on the surface of the substrate. Specifically, the surface of the substrate can be lightly doped with impurities of the first conductivity type to form the drift region.

[0093] As Figure 14c shown, one side of the drift region is doped to form a body region. Specifically, the one side of the drift region is doped with impurities of the second conductivity type to form a second conductivity type body region with a slightly higher doping concentration.

[0094] As Figure 14d shown, a second field plate is formed on the surface of the drift region.

[0095] Specifically, a layer of oxide is deposited, specifically LTO (low temperature oxide), to prepare for the formation of the second field plate, and then the second field plate is formed through an etching process.

[0096] As Figure 14e shown, a gate oxide layer is formed on the surface of the drift region. Specifically, the gate oxide layer is grown on the part of the device surface except for the second field plate.

[0097] As Figure 14f shown, a gate, an isolation oxide layer, and sidewalls are formed on the surface of the gate oxide layer.

[0098] Specifically, a layer of polysilicon is first deposited on the surface of the gate oxide layer to prepare for the formation of the gate. Then, the gate is formed by an etching process, and a part of the protruding gate can be polished flat by CMP (Chemical Mechanical Polishing). To prevent stress, the isolation oxide layer and sidewalls are formed on both sides of the gate. Among them, the material of the sidewall is silicon nitride. Finally, the redundant gate oxide layer is etched away. At this time, the second field plate is disposed on the surface of the drift region, penetrating the gate oxide layer and connecting to the gate.

[0099] As Figure 14g shown, the redundant gate oxide layer is etched away to expose the drift layer.

[0100] As Figure 14h shown, a first field plate is formed on the other surface of the drift region. Specifically, a layer of oxide is deposited and etched to form a field plate with a CFP structure as the first field plate.

[0101] As Figure 14i shown, the drift region and the body region are doped to form a source region, a drain region, and a body electrode. Among them, the body electrode is heavily doped with the first conduction type, the source region is heavily doped with the second conduction type, and the drain region is heavily doped with the first conduction type.

[0102] Another embodiment discloses a manufacturing method of another LDMOS device. The difference from the above embodiment is that the second field plate is a LOCOS field plate, and the second field plate penetrates the gate oxide layer and connects to the gate.

[0103] At this time, the process flow for forming the second field plate is as follows:

[0104] Grow a pre-oxidation layer → Grow a silicon nitride layer → Active region lithography and etching → Field oxidation → Etch away the silicon nitride layer → Obtain the second field plate.

[0105] Another embodiment discloses a manufacturing method of another LDMOS device. The difference from the above embodiment is that the second field plate is a STI field plate, and the second field plate is located under the gate oxide layer.

[0106] At this time, the process flow for forming the second field plate is as follows:

[0107] Grow a pre-oxidation layer and a silicon nitride layer → Trench etching → Remove photoresist → Trench thermal oxidation to generate silicon dioxide → Deposit polysilicon → Chemical mechanical polishing → Etch away the silicon nitride layer → Obtain the second field plate.

[0108] And the gate oxide layer formed on the surface of the drift region will cover the surface of the second field plate.

[0109] It should be noted that the position of the second field plate is adjustable but cannot be too far away from the first field plate, and the closer it is to the first field plate, the better the effect. The reason is that the closer the two are, the better the electric field modulation effect, and at the same time, the closer they are, the less likely it is to affect the current path bent by the structure of the first field plate.

[0110] Another embodiment also discloses an LDMOS device with specific dimensions. The LDMOS device is a dual-field-plate LDMODS device with a CFP field plate + LTO field plate, and the specific dimensions of the device are as Figure 15 shown.

[0111] Another embodiment also discloses another LDMOS device with specific dimensions. The LDMOS device is a dual-field-plate LDMODS device with a CFP field plate + LOCOS field plate, and the specific dimensions of the device are as Figure 16 shown.

[0112] Another embodiment also discloses another LDMOS device with specific dimensions. The LDMOS device is a dual-field-plate LDMODS device with a CFP field plate + STI field plate, and the specific dimensions of the device are as Figure 17 shown.

[0113] In the specific production process, the dimensions of each structure in the LDMODS device are adjustable, especially the dimensions of the second field plate. By adjustment, different forms of current distribution inside the device can be achieved, so corresponding adjustments can be made according to requirements.

[0114] It should be noted that Figures 15 - 17 The device dimensions shown are only for better illustration of the present invention and are not a limitation on the LDMOS device. And in the present invention, the first conductivity type can be N-type, and the corresponding second conductivity type is P-type. Conversely, the first conductivity type can be P-type, and the corresponding second conductivity type is N-type.

[0115] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification. The "first" and "second" mentioned in the text are only for distinction and are not a limitation on the content of the present invention.

[0116] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. An LDMOS device, comprising: A substrate and a drift region located on the surface of the substrate, a body region is arranged on one side of the drift region, a body electrode and a source region are arranged on the surface of the body region, a drain region is arranged on the other side of the drift region, a gate oxide layer is arranged on the surface of the drift region, a portion of the gate oxide layer covers the surface of the source region, a gate, an isolation oxide layer and a sidewall are arranged on the surface of the gate oxide layer, characterized in that it also includes: A first field plate, the first field plate is located on the surface of the drift region between the gate and the source region, partially covers the surface of the sidewall, and the first field plate is connected to a zero potential; The second field plate is arranged horizontally with the first field plate, and is located between the drift region and the gate and close to the first field plate.

2. The LDMOS device according to claim 1, characterized in that: The second field plate is arranged on the surface of the drift region, penetrates the gate oxide layer and is connected to the gate.

3. The LDMOS device according to claim 2, characterized in that: The second field plate is made of low temperature oxide.

4. The LDMOS device according to claim 1, characterized in that: The second field plate is a LOCOS field plate, and the second field plate penetrates the gate oxide layer and is connected to the gate.

5. The LDMOS device according to claim 1, characterized in that: The second field plate is an STI field plate, and the second field plate is located below the gate oxide layer.

6. A method for manufacturing an LDMOS device, characterized in that: include: providing a substrate; forming a drift region on the surface of the substrate; Doping one side of the drift region to form a body region; forming a second field plate on the surface of the drift region; forming a gate oxide layer on the surface of the drift region; Forming a gate, an isolation oxide layer and a sidewall on the surface of the gate oxide layer; forming a first field plate on the other side surface of the drift region; Doping the drift region and the body region to form a source region, a drain region and a body electrode; Among them, the first field plate is located on the surface of the drift region between the gate and the source region, partially covers the surface of the side wall, and the first field plate is connected to zero potential; the second field plate is arranged horizontally with the first field plate, located between the drift region and the gate and close to the first field plate.

7. The method for manufacturing the LDMOS device according to claim 6, characterized in that: The second field plate is arranged on the surface of the drift region, penetrates the gate oxide layer and is connected to the gate.

8. The method for manufacturing the LDMOS device according to claim 7, characterized in that: The second field plate is made of low temperature oxide.

9. The method for manufacturing the LDMOS device according to claim 6, characterized in that: The second field plate is a LOCOS field plate, and the second field plate penetrates the gate oxide layer and is connected to the gate.

10. The method for manufacturing the LDMOS device according to claim 6, characterized in that: The second field plate is an STI field plate, and the second field plate is located below the gate oxide layer.

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