Reconfigurable transistor based on self-bias grid electrode and preparation method thereof

Abstract

The invention belongs to the technical field of two-dimensional transistor devices, and particularly relates to a reconfigurable transistor based on a self-bias grid electrode and a preparation method thereof, and the reconfigurable transistor comprises an insulating substrate, a bottom grid electrode, a dielectric layer, a channel two-dimensional material, a drain electrode, a source electrode and a bottom self-bias grid electrode. The bottom gate and the self-bias gate are located below the dielectric layer, the channel two-dimensional material is located above the dielectric layer, and the drain electrode and the source electrode are built above the two-dimensional material; and the self-biased grid electrode penetrates through the dielectric layer and the channel two-dimensional material to be connected with the source electrode. When the device works, the drain electrode, the source electrode and the bottom grid electrode form a three-end field effect transistor device, and when positive and negative bias voltages are applied to the drain electrode and the source electrode, opposite potential differences are generated between the self-bias grid electrode and a channel, so that different doping effects are generated on the channel, and the transistor shows different polarities. According to the reconfigurable transistor, the process complexity of circuit manufacturing can be reduced, the number of transistors is reduced, power consumption is reduced, and the development requirements of integrated circuits in the future are met.

Description

Technical Field

[0001] The present invention belongs to the technical field of two-dimensional transistor device fabrication, and particularly relates to a reconfigurable transistor based on a self-biased gate and a fabrication method thereof. Background Art

[0002] Since the discovery of graphene, two-dimensional materials have been widely studied in next-generation high-performance electronic devices. This is mainly attributed to their excellent electrical properties, such as high carrier mobility, easy Fermi level regulation, no dangling bonds on the surface, and flexibility. For the application of two-dimensional material electronic devices in integrated circuits, effective control of polarity is required. Currently, the main methods for controlling the polarity of two-dimensional materials are as follows: Chemical doping: Changing the carrier type of the material by atomic substitution or chemical adsorption. This method has strong doping ability, but the impurity atoms will cause carrier scattering and reduce the electrical properties of the material; Charge transfer doping: Contacting the two-dimensional material with a charge transfer layer to cause charge transfer, thereby changing the polarity of the two-dimensional material. This method can avoid impurity scattering, but the transfer method is not compatible with the CMOS process and is difficult to apply in integrated circuits; Electrostatic field doping: Changing the charge type in the material by an electrostatic field. This method is easy to control the doping type and concentration, but the device structure is complex, and the additional electrostatic field will increase power consumption; Electrode contact regulation: Changing the barrier between the electrode and the material by changing the electrode material and preparation method, thereby changing the conduction type of the carrier. This method has a simple process, but the ability to control polarity is limited.

[0003] The current polarity control methods limit the further application of two-dimensional materials in integrated circuits. In view of the above problems, it is necessary to develop an effective polarity control method to solve the main problems in the application of two-dimensional materials in integrated circuits. Summary of the Invention

[0004] The purpose of the present invention is to provide a reconfigurable transistor based on a self-biased gate and a fabrication method thereof. By the self-biased voltage between the self-biased gate and the channel two-dimensional semiconductor, doping effect is generated on the channel. By changing the positive and negative of the drain bias voltage, the control of the carrier type in the channel can be realized, and a p-type or n-type transistor can be formed.

[0005] To achieve the above object, the present invention provides a reconfigurable transistor based on a self-biased gate, comprising an insulating substrate, a bottom gate, a dielectric layer, a two-dimensional semiconductor material, a drain electrode, a source electrode, and a bottom self-biased gate;

[0006] The bottom gate and the bottom self - biased gate are arranged at intervals on the insulating substrate; the dielectric layer is arranged on the bottom gate and the bottom self - biased gate and covers the gap between the bottom gate and the bottom self - biased gate. The dielectric layer completely covers the bottom gate, partially covers the bottom self - biased gate, and the uncovered part is located at the outer edge of the bottom self - biased gate;

[0007] The two - dimensional semiconductor material is arranged on the dielectric layer, and the drain electrode and the source electrode are arranged at intervals at both ends of the two - dimensional semiconductor material, with a channel formed in the middle;

[0008] The source electrode passes through the two - dimensional semiconductor material and the dielectric layer and is connected to the part of the bottom self - biased gate that is not covered by the dielectric layer. The material of the side - connection part is the same as that of the source electrode.

[0009] Further, the two - dimensional semiconductor material is a bipolar semiconductor material, including one or both of tungsten diselenide and black phosphorus; the thickness of the two - dimensional semiconductor material is 1 - 20 nm.

[0010] Further, the material of the dielectric layer is hafnium oxide, aluminum oxide, silicon oxide or boron nitride, and the thickness is 5 - 20 nm.

[0011] Further, the thicknesses of the bottom gate and the bottom self - biased gate are each independently 5 - 10 nm.

[0012] Further, the thicknesses of the drain electrode and the source electrode are each independently 5 - 10 nm.

[0013] Further, the material of the bottom gate is any one or more of chromium, titanium, gold or platinum;

[0014] The material of the bottom self - biased gate is any one or more of chromium, titanium, gold or platinum.

[0015] Further, the material of the drain electrode (5) is any one or more of chromium, bismuth, indium or gold; the material of the source electrode (6) is any one or more of chromium, bismuth, indium or gold.

[0016] The bottom self - biased gate is connected to the source and grounded during device operation. When a bias voltage is applied to the drain, the potential of the bottom self - biased gate is zero, and a bias voltage is generated between it and the channel, and the direction of the bias voltage is related to the direction of the drain bias voltage. When positive and negative bias voltages are applied to the drain, the bottom self - biased gate generates negative and positive self - bias voltages relative to the channel, respectively, thereby producing p - type and n - type doping effects on the channel.

[0017] Preferably, when a positive bias voltage is applied to the drain, the transistor transfer characteristic curve exhibits p-type characteristics; when a negative bias voltage is applied to the drain, the transistor transfer characteristic curve exhibits n-type characteristics.

[0018] The present invention also provides a method for manufacturing a reconfigurable transistor based on a self-biased gate as described in any one of the above, comprising the following steps:

[0019] Pattern and deposit a bottom gate and a bottom self-biased gate on an insulating substrate through an electron beam lithography process and a thermal evaporation process;

[0020] Prepare a dielectric layer through an electron beam lithography process and an atomic layer deposition process;

[0021] Transfer a two-dimensional semiconductor material to the top of the dielectric layer at a fixed point;

[0022] Pattern and deposit a drain electrode and a source electrode through electron beam lithography and thermal evaporation, and connect the source electrode to the bottom self-biased gate.

[0023] Generally speaking, compared with the prior art through the above technical solutions conceived by the present invention, the following technical advantages are mainly possessed:

[0024] 1. For the reconfigurable transistor based on a self-biased gate provided by the present invention, the bottom gate and the self-biased gate are located below the dielectric layer, the channel two-dimensional material is located above the dielectric layer, and the drain electrode and the source electrode are built above the two-dimensional material; the self-biased gate passes through the dielectric layer and the channel two-dimensional material and is connected to the source. With such a setting, the doping effect on the channel can be achieved through the self-biased voltage between the self-biased gate and the channel two-dimensional semiconductor material. By changing the positive and negative of the drain bias voltage, the control of the channel carrier type can be realized, and a p-type or n-type transistor can be formed. The method provided by the present invention does not require chemical doping, a charge transfer layer or an additional electrostatic field, and provides a simple and effective new way for polarity control.

[0025] 2. The transistor of the present invention has reconfigurable characteristics. A single transistor can function as both a p-type transistor and an n-type transistor. When used in an integrated circuit, it can reduce the process complexity of circuit manufacturing, reduce the number of transistors, reduce power consumption, and can be applied to multifunctional devices.

[0026] 3. The transistor manufacturing process of the present invention is compatible with the existing CMOS process, which is beneficial for application in integrated circuits. Description of the Drawings

[0027] Figure 1 It is a schematic diagram of the device configuration of the reconfigurable transistor based on a self-biased gate in Embodiment 1 of the present invention;

[0028] Figure 2It is the optical microscope image of the reconfigurable transistor based on the self - biased gate in Embodiment 1 of the present invention;

[0029] Figure 3 It is the transfer characteristic curve of the reconfigurable transistor based on the self - biased gate in Embodiment 1 of the present invention;

[0030] Figure 4 It is the transfer characteristic curve of the reconfigurable transistor based on the self - biased gate under different bias voltages in Embodiment 1 of the present invention;

[0031] Figure 5 It is the schematic diagram of the preparation method of the reconfigurable transistor based on the self - biased gate in Embodiment 1 of the present invention.

[0032] In all the drawings, the same reference numerals are used to represent the same elements or structures, where:

[0033] 1 - insulating substrate; 2 - bottom gate; 3 - dielectric layer; 4 - two - dimensional semiconductor material; 5 - drain electrode; 6 - source electrode; 7 - bottom self - biased gate. Detailed implementation manners

[0034] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] The present invention provides a reconfigurable transistor based on a self - biased gate and its preparation method. The prepared transistor has reconfigurable characteristics. By changing the positive and negative of the drain bias voltage, the type of channel carriers can be regulated to form a p - type or n - type transistor. The method provided by the present invention does not require chemical doping, charge transfer layers or additional electrostatic fields, providing a simple and effective new way for polarity regulation.

[0036] Embodiment 1

[0037] As Figure 1 shown, the present invention provides a reconfigurable transistor based on a self - biased gate, where 1 is an insulating substrate, 2 is a bottom gate, 3 is a dielectric layer, 4 is a two - dimensional semiconductor material, 5 is a drain electrode, 6 is a source electrode, and 7 is a bottom self - biased gate.

[0038] Among them, the bottom gate 2 and the bottom self - biased gate 7 are arranged at intervals on the insulating substrate 1; the dielectric layer 3 is arranged on the bottom gate 2 and the bottom self - biased gate 7, and covers the gap between the bottom gate 2 and the bottom self - biased gate 7. The dielectric layer 3 completely covers the bottom gate 2, partially covers the bottom self - biased gate 7, and the uncovered part is located at the outer edge of the bottom self - biased gate 7.

[0039] The two - dimensional semiconductor material 4 is arranged on the dielectric layer 3, and the drain electrode 5 and the source electrode 6 are arranged at intervals at both ends of the two - dimensional semiconductor material 4, forming a channel in the middle.

[0040] The source electrode 6 passes through the two - dimensional semiconductor material 4 and the dielectric layer 3 and is connected to the part of the bottom self - biased gate 7 that is not covered by the dielectric layer 3.

[0041] When the device works, the drain 5, the source 6 and the bottom gate 2 form a three - terminal field - effect transistor device. When positive and negative bias voltages are applied to the drain - source electrodes, an opposite potential difference is generated between the self - biased gate 7 and the channel, thereby producing different doping effects on the channel and making the transistor exhibit different polarities.

[0042] As Figure 5 shown, the preparation method of the reconfigurable transistor based on the self - biased gate provided in this embodiment is as follows:

[0043] The bottom gate 2 and the bottom self - biased gate 7 are prepared on the insulating substrate 1 through electron - beam lithography patterning and thermal evaporation; the material of the bottom gate 2 is gold and the thickness is 10 nm; the material of the bottom self - biased gate 7 is gold and the thickness is 10 nm.

[0044] The dielectric layer 3 is prepared through electron - beam lithography patterning and atomic layer deposition; the material of the dielectric layer 3 is hafnium oxide and the thickness is 20 nm.

[0045] The two - dimensional semiconductor material 4 is transferred to the upper part of the dielectric layer 3 at a fixed point; the material of the two - dimensional semiconductor material 4 is tungsten diselenide and the thickness is 10 nm.

[0046] The source electrode 6 and the drain electrode 5 are prepared on the two - dimensional semiconductor material 4 through electron - beam lithography patterning and thermal evaporation, and the source electrode 6 is connected to the bottom self - biased gate 7. The material of the source electrode 6 is bismuth / gold, with a thickness of 10 / 40 nm; the material of the drain electrode 5 is bismuth / gold, with a thickness of 10 / 40 nm. The material of the part where the source electrode 6 is connected to the bottom self - biased gate 7 is bismuth / gold.

[0047] The optical microscope image of the reconfigurable transistor prepared in this embodiment is as Figure 2 shown. The transfer characteristic curve of its transistor performance is as Figure 3As shown, when a positive bias voltage is applied to the drain, the device exhibits p-type characteristics; when a negative bias voltage is applied to the drain, the device exhibits n-type characteristics, with reconfigurability, and the transistor switching ratios of both p-type and n-type are higher than 10 5 .

[0048] Test the transfer characteristics of the reconfigurable transistor in Test Example 1 under different bias voltages. The results are as Figure 4 shown. Under different positive bias voltages, the device exhibits p-type characteristics; under different negative bias voltages, the device exhibits n-type characteristics, indicating that the bias voltage direction has a significant regulatory effect on the polarity of the device.

[0049] In summary, in the present invention, a doping effect on the channel is generated through the self-bias voltage between the self-bias gate and the two-dimensional semiconductor of the channel. By changing the positive and negative of the drain bias voltage, the regulation of the channel carrier type can be realized to form a p-type or n-type transistor. The method provided by the present invention does not require chemical doping, a charge transfer layer or an additional electrostatic field, and provides a simple and effective new way for polarity regulation.

[0050] It is easy for those skilled in the art to understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A reconfigurable transistor based on a self-biased gate, characterized in that: It comprises an insulating substrate (1), a bottom gate (2), a dielectric layer (3), a two-dimensional semiconductor material (4), a drain electrode (5), a source electrode (6) and a bottom self-biased gate (7); The bottom gate (2) and the bottom self-bias gate (7) are arranged on the insulating substrate (1) at intervals; the dielectric layer (3) is arranged on the bottom gate (2) and the bottom self-bias gate (7) and covers the gap between the bottom gate (2) and the bottom self-bias gate (7); the dielectric layer (3) completely covers the bottom gate (2) and partially covers the bottom self-bias gate (7), and the uncovered portion is located at the outer edge of the bottom self-bias gate (7); The two-dimensional semiconductor material (4) is arranged on the dielectric layer (3), and the drain electrode (5) and the source electrode (6) are arranged at two ends of the two-dimensional semiconductor material (4) with a spacing, forming a channel in the middle; The source electrode (6) passes through the two-dimensional semiconductor material (4) and the dielectric layer (3) and is connected to the portion of the bottom self-biased gate (7) not covered by the dielectric layer (3).

2. The reconfigurable transistor based on self-biased gate according to claim 1, characterized in that: The two-dimensional semiconductor material (4) is a bipolar semiconductor material, including one or both of tungsten diselenide and black phosphorus; the thickness of the two-dimensional semiconductor material is 1-20 nm.

3. The reconfigurable transistor based on self-biased gate according to claim 1, characterized in that: The dielectric layer (3) is made of hafnium oxide, aluminum oxide, silicon oxide or boron nitride and has a thickness of 5-20 nm.

4. The reconfigurable transistor based on self-biased gate according to claim 1, characterized in that: The thickness of the bottom gate (2) and the bottom self-bias gate (7) are independently 5-10 nm.

5. The reconfigurable transistor based on self-biased gate according to claim 1, characterized in that: The thickness of the drain electrode (5) and the source electrode (6) are independently 5-10 nm.

6. The reconfigurable transistor based on self-biased gate according to claim 1, characterized in that: The material of the bottom gate (2) is any one or more of chromium, titanium, gold or platinum; The material of the bottom self-biased grid (7) is any one or more of chromium, titanium, gold or platinum.

7. The reconfigurable transistor based on self-biased gate according to claim 1, characterized in that: The material of the drain electrode (5) is any one or more of chromium, bismuth, indium or gold; the material of the source electrode (6) is any one or more of chromium, bismuth, indium or gold.

8. A method for preparing a reconfigurable transistor based on a self-biased gate according to any one of claims 1 to 7, characterized in that: The following steps are involved: Depositing a bottom gate (2) and a bottom self-bias gate (7) on an insulating substrate (1) by electron beam lithography patterning and thermal evaporation; The dielectric layer (3) is prepared by electron beam lithography patterning and atomic layer deposition process; Transferring the two-dimensional semiconductor material (4) onto the dielectric layer (3) in a targeted manner; The drain electrode (5) and the source electrode (6) are deposited by electron beam lithography patterning and thermal evaporation, and the source electrode (6) is connected to the bottom self-biased gate (7).

Images