Semiconductor device and manufacturing method thereof

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same, the semiconductor device comprising: a drift region having a first conductivity type; the well region is arranged close to the top of the drift region and has the second conduction type; a first trench gate; a second trench gate; the active regions are of the first conduction type, part of the active regions are arranged on the side face of the first trench gate and close to the first trench gate, and part of the active regions are arranged on the side face of the second trench gate and close to the second trench gate; wherein the thickness of the first gate dielectric layer is smaller than that of the second gate dielectric layer, and the doping concentration of the well region where the first trench gate is located and the doping concentration of the well region where the second trench gate is located are the same. According to the semiconductor device, the device with the first trench gate as the gate can reach a negative temperature coefficient region of a transfer characteristic curve first, and can reach a thermal stable state more quickly, so that the whole semiconductor device can reach the thermal stable state more quickly and has a larger safe working area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device, and also to a method for manufacturing the semiconductor device. Background Art

[0002] From the output characteristic curve of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), MOSFET has three main working areas: variable resistance area (ohm area), constant current area (saturation area), and pinch-off area. Figure 1 , when the device enters the saturation region, under the condition of constant Vgs (gate-source voltage), since the output current and voltage are already at their maximum, the device will bear a lot of power at this time. Safe operating area: SOA (Safe operating area) is used to evaluate the maximum voltage and maximum current of the device during operation. Neither should it exceed this limited range, otherwise the device will easily overheat and become unstable, which may cause serious damage to the device. However, for applications such as hot-swap, load switch, and discrete LDO (low-dropout linear regulator) adjustment tubes, MOSFET will work in the linear region for a long time or all the time, and the requirements for the safe operating area are higher. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device with a larger safe operating area.

[0004] A semiconductor device comprises: a drift region having a first conductivity type; a well region arranged near the top of the drift region and having a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; a first trench gate comprising a first gate dielectric layer located on the inner surface of a first trench, and a first gate electrode located in the first trench and surrounded by the first gate dielectric layer on all sides and at the bottom, wherein at least a portion of the first trench gate is located in the well region; a second trench gate comprising a second gate dielectric layer located on the inner surface of a second trench, and a second gate electrode located in the second trench and surrounded by the second gate dielectric layer on all sides and at the bottom, wherein at least a portion of the second trench gate is located in the well region; a plurality of active regions having the first conductivity type, wherein some of the active regions are arranged near the first trench gate on the side of the first trench gate, and some of the active regions are arranged near the second trench gate on the side of the second trench gate; wherein the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer, and the well region where the first trench gate is located and the well region where the second trench gate is located have the same doping concentration.

[0005] For the above semiconductor device, by providing a first trench gate with a relatively thin gate dielectric layer, the device with the first trench gate as the gate has a lower threshold voltage. Therefore, the device with the first trench gate as the gate will reach the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate as the gate will reach the thermal stable state faster. Therefore, the above semiconductor device as a whole will also reach the thermal stable state faster and has a larger safe operating area.

[0006] In one embodiment, the bottom of the first trench gate is separated from the drift region by a part of the well region.

[0007] In one embodiment, the depth of the second trench gate is greater than the depth of the well region, so that the bottom of the second trench gate reaches the drift region.

[0008] In one embodiment, the thickness of the first gate dielectric layer is 200 Å to 500 Å.

[0009] In one embodiment, the threshold voltage of the device with the first gate as the gate is not greater than 1.5 V.

[0010] In one embodiment, the thickness of the second gate dielectric layer is more than 1000 Å.

[0011] In one embodiment, the threshold voltage of the device with the second gate as the gate is 3 V or more.

[0012] In one embodiment, at least a part of the first trench gate is located between different second trench gates.

[0013] In one embodiment, the semiconductor device is a metal oxide semiconductor field effect transistor or a vertical double-diffused metal oxide semiconductor field effect transistor.

[0014] In one embodiment, the first conduction type is N-type and the second conduction type is P-type.

[0015] It is also necessary to provide a manufacturing method for a semiconductor device with a larger safe operating area.

[0016] A method for manufacturing a semiconductor device, comprising: forming a first trench gate and a second trench gate in a drift region of a first conductivity type; the first trench gate includes a first gate dielectric layer on an inner surface of a first trench, and a first gate electrode located in the first trench and surrounded by the first gate dielectric layer on all sides and at the bottom; the second trench gate includes a second gate dielectric layer on an inner surface of a second trench, and a second gate electrode located in the second trench and surrounded by the second gate dielectric layer on all sides and at the bottom; forming a well region of a second conductivity type at a position near the top of the drift region; the first conductivity type and the second conductivity type are opposite conductivity types; forming a plurality of active regions of the first conductivity type, with some of the active regions formed on sides of the first trench gate and close to the first trench gate, and some of the active regions formed on sides of the second trench gate and close to the second trench gate; wherein, a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer, doping concentrations of the well region where the first trench gate is located and the well region where the second trench gate is located are the same, at least a part of the first trench gate is located in the well region, and at least a part of the second trench gate is located in the well region.

[0017] In the above method for manufacturing a semiconductor device, by providing the first trench gate with a thinner gate dielectric layer, the device with the first trench gate as the gate electrode has a lower threshold voltage. Therefore, the device with the first trench gate as the gate electrode will reach the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate as the gate electrode will reach the thermal stable state faster. Therefore, the above semiconductor device as a whole will also reach the thermal stable state faster and has a larger safe operating area.

[0018] In one embodiment, in the step of forming the first trench gate and the second trench gate in the drift region of the first conductivity type, the first trench gates and the second trench gates are distributed in a mixed manner on the plane of the wafer.

[0019] In one embodiment, a depth of the first trench is less than a depth of the well region, so that a bottom of the first trench gate is separated from the drift region by a part of the well region. Description of the Drawings

[0020] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.

[0021] Figure 1 is a schematic diagram of the output characteristic curve of a MOSFET;

[0022] Figure 2It is a schematic diagram of the transfer characteristic curves of a MOSFET at 25°C and 175°C;

[0023] Figure 3 It is a schematic structural diagram of a semiconductor device in an embodiment of the present application;

[0024] Figure 4 It is a flowchart of a manufacturing method of a semiconductor device in an embodiment of the present application;

[0025] Figure 5 It is a flowchart of sub-steps of step S410 in an embodiment of the present application;

[0026] Figure 6a It is a schematic cross-sectional structure diagram of a device after step S412 is completed in an embodiment of the present application, Figure 6b It is a schematic cross-sectional structure diagram of a device after step S413 is completed in an embodiment of the present application, Figure 6c It is a schematic cross-sectional structure diagram of a device after step S415 is completed in an embodiment of the present application, Figure 6d It is a schematic cross-sectional structure diagram of a device after step S412 is completed in an embodiment of the present application;

[0027] Figure 7 It is the transfer characteristic curves of a semiconductor device in an embodiment of the present application and a comparative example. Detailed implementation manners

[0028] For ease of understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0030] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0031] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0034] The semiconductor field terms used herein are common technical terms for those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentrations, simply P+ type represents the P-type with a heavy doping concentration, P type represents the P-type with a medium doping concentration, P- type represents the P-type with a light doping concentration, N+ type represents the N-type with a heavy doping concentration, N type represents the N-type with a medium doping concentration, and N- type represents the N-type with a light doping concentration.

[0035] The safe operating area is mainly limited by five conditions, namely: on-resistance limit, package current limit, maximum power limit, thermal instability limit, and breakdown voltage limit. Among them, the thermal instability limit corresponds to the situation that when the device operates in the saturation region for a period of time, the generated heat causes the operating temperature of the device to rise, which will cause the device to be overheated and unstable. Here, a related concept called the zero temperature coefficient point (ZTC) is introduced. It is the intersection point of the transfer characteristic curves of the device at 25°C and 175°C. Refer to Figure 2 ... It can be simply understood that: when Vgs < Vgs(ZTC), the higher the temperature, the larger the drain current I D will be (i.e., positive temperature coefficient). When a local area of the chip becomes hotter than the adjacent areas, it will conduct more drain current, thus generating more heat. If appropriate limiting conditions are not set, it will lead to device failure (thermal runaway). When Vgs > Vgs(ZTC), the higher the temperature, the smaller the I D will be (i.e., negative temperature coefficient), which means the device enters a thermally stable state.

[0036] Therefore, the key to optimizing the thermal instability limit lies in the ZTC point. Making the transfer characteristic curves at 25°C and 175°C intersect when I D is very small or Vgs is very small can achieve the expansion of the safe operating area.

[0037] An exemplary VDMOS (Vertical Double-Diffused Metal Oxide Semiconductor Field-Effect Transistor) obtains a larger safe operating area by adjusting the concentration of P-type doping in the conductive channel under the gate in the cells of a partial area of the chip, so that these cells have a lower threshold voltage.

[0038] However, the solution of obtaining a larger safe operating area by adjusting the ion implantation dose of the P-type body region has the problem that the UIS (Unclamped Inductive Switching) capability of the chip becomes weaker. Taking the N-channel MOSFET as an example, the base resistance in the parasitic NPN triode of the low-threshold voltage cell will increase significantly, making this parasitic triode easier to turn on and easily causing device damage.

[0039] Figure 3 FIG. is a schematic structural diagram of a semiconductor device in an embodiment of the present application, including a drift region 110, a well region 122, a first trench gate 130, a second trench gate 140, and a plurality of active regions 124. The drift region 110 has a first conductivity type. The well region 122 is disposed near the top of the drift region 110 and has a second conductivity type. The first trench gate 130 includes a first gate dielectric layer 132 on the inner surface of the first trench, and a first gate electrode 134 located in the first trench and surrounded by the first gate dielectric layer 132 on all sides and at the bottom. At least a partial region of the first trench gate 130 is located in the well region 122. The second trench gate 140 includes a second gate dielectric layer 142 on the inner surface of the second trench, and a second gate electrode 144 located in the second trench and surrounded by the second gate dielectric layer 142 on all sides and at the bottom. At least a partial region of the second trench gate 140 is located in the well region 122. The active regions 124 have a first conductivity type, and some of the active regions 124 are disposed near the first trench gate 130 on the side of the first trench gate 130, and some of the active regions 124 are disposed near the second trench gate 140 on the side of the second trench gate 140. The thickness of the first gate dielectric layer 132 is less than the thickness of the second gate dielectric layer 134. The doping concentrations of the well regions 122 where the first trench gate 130 is located and the well regions 122 where the second trench gate 140 is located are the same. Since Figure 3 it is symmetric about the left and right, only one side of some structures is labeled. In Figure 3 the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Correspondingly, the drift region 110 is an N-region, the well region 122 is a P-well, and the active regions 124 are N+ regions. In other embodiments, the first conductivity type may also be P-type and the second conductivity type may be N-type.

[0040] For the above semiconductor device, by providing the first trench gate 130 with a relatively thin gate dielectric layer, the device (cell) with the first trench gate 130 as the gate has a lower threshold voltage. Therefore, the device with the first trench gate 130 as the gate will reach the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate 130 as the gate will reach the thermal stable state faster. Thus, the above semiconductor device as a whole will also reach the thermal stable state faster and has a larger safe operating area. Moreover, since the doping concentrations of the well regions 122 around the first trench gate 130 and the well regions 122 around the second trench gate 140 are the same, there is no problem that the base resistance of the parasitic triode NPN of the low-threshold voltage cell is larger, that is, the problem of low UIS ability of the low-threshold voltage cell is solved.

[0041] In an embodiment of the present application, the depth of the first trench gate 130 (i.e., the depth of the first trench) is less than the depth of the well region 122, so that the bottom of the first trench gate 130 is separated from the drift region 110 by a part of the well region 122. In this way, when the conductive channel is inverted, a JFET region is formed between the well region 122 at the bottom of the first trench gate 130 and the drift region 110, increasing the on-resistance of this region. And the resistance value of the JFET region will increase with the increase of temperature, which is equivalent to connecting a resistor with a resistance value increasing with the increase of temperature in series in this region, thereby introducing a "negative feedback mechanism" - that is, the higher the temperature, the greater the resistance, and the drain current I D becomes smaller. In this way, I D will be limited at high temperature, and the rising trend of the transfer characteristic curve of the device at 175 °C becomes gentle, and the ZTC point moves down.

[0042] In an embodiment of the present application, the depth of the second trench gate 140 (i.e., the depth of the second trench) is greater than the depth of the well region 122, so that the bottom of the second trench gate 140 reaches the drift region 110.

[0043] In an embodiment of the present application, the thickness of the first gate dielectric layer 132 is 200 Å to 500 Å. Thus, the threshold voltage of the device with the first gate 134 as the gate is limited to 1.5 V or lower.

[0044] In an embodiment of the present application, the thickness of the second gate dielectric layer 142 is more than 1000 Å; thus, the threshold voltage of the device with the second gate 144 as the gate is above 3 V.

[0045] The first gate dielectric layer 132 and the second gate dielectric layer 142 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the first gate dielectric layer 132 and the second gate dielectric layer 142 may include generally higher dielectric constant dielectric materials having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment of the present application, the first gate dielectric layer 132 and the second gate dielectric layer 142 are made of silicon dioxide.

[0046] In one embodiment of the present application, the first gate 134 and the second gate 144 are made of polysilicon material; in other embodiments, metals, metal nitrides, metal silicides, or similar compounds may also be used as the materials for the first gate 134 and the second gate 144.

[0047] In one embodiment of the present application, at least a part of the first trench gate 130 is located between different second trench gates 140. That is, several first trench gates 130 and several second trench gates 140 are mixed and distributed on the plane of the wafer. A second trench gate 140 is provided around each first trench gate 130, and a first trench gate 130 is also provided around each second trench gate 140. In Figure 3 the illustrated embodiment, two first trench gates 130 are provided between two second trench gates 140; in other embodiments, the number of the first trench gates 130, the depth of the first trench gates 130, the spacing between the first trench gates 130 and the adjacent second trench gates 140, and the spacing between two adjacent first trench gates 130 can all be optimized and adjusted. By adjusting parameters such as the depth and spacing of the first trench gates 130, the resistance in this area can be adjusted to achieve the best balance between the on-resistance and the safe operating area.

[0048] In one embodiment of the present application, part of the active region 124 is in direct contact with the first gate dielectric layer 132, and part of the active region 124 is in direct contact with the second gate dielectric layer 142.

[0049] In one embodiment of the present application, an USG (undoped silicon glass) layer 152 is further provided on the active region 124, the first trench gate 130, and the second trench gate 140. In one embodiment of the present application, a BPSG (boron phosphorus silicon glass) layer 154 is further provided on the USG layer 152. In one embodiment of the present application, the semiconductor device further includes a contact hole 162 that penetrates downward through the USG layer 152 and the BPSG layer 154. The contact hole 162 is filled with a conductive material, such as a tungsten plug, and the conductive material is in direct contact with the active region 124. A metal interconnect layer electrically connected to the conductive material is provided on the contact hole 162. InFigure 3 In the illustrated embodiment, the bottom of the contact hole 162 extends to the well region 122.

[0050] In one embodiment of the present application, the semiconductor device is a power device, such as a power MOSFET. The semiconductor device can also be a VDMOSFET, so that in Figure 3 the illustrated embodiment, the active region 124 is the source doping region of the device, and a drain of the VDMOSFET is further formed on the back surface of the drift region 110.

[0051] Figure 7 is the transfer characteristic curve of the semiconductor device of one embodiment of the present application and the comparative example. It can be seen that the ZTC point of the embodiment of the present application is lower, and when Vgs is larger, I D is smaller. Therefore, the semiconductor device of the embodiment of the present application has a larger safe operating area.

[0052] The present application correspondingly provides a manufacturing method of a semiconductor device. Figure 4 is a flowchart of the manufacturing method of the semiconductor device in one embodiment of the present application, including the following steps:

[0053] S410, forming a first trench gate and a second trench gate in a drift region of a first conductivity type.

[0054] The first trench gate 130 includes a first gate dielectric layer 132 located on the inner surface of the first trench, and a first gate electrode 134 located in the first trench 131 and surrounded by the first gate dielectric layer 132 on all sides and at the bottom. At least a part of the first trench gate 130 is located in the well region 122. The second trench gate 140 includes a second gate dielectric layer 142 located on the inner surface of the second trench, and a second gate electrode 144 located in the second trench and surrounded by the second gate dielectric layer 142 on all sides and at the bottom.

[0055] Figure 5 is a sub-step flowchart of step S410 in one embodiment of the present application, including the following steps:

[0056] S411, forming a second trench in the drift region.

[0057] In one embodiment of the present application, through photolithography and etching, a second trench 141 is formed in the wafer on which the drift region 110 is formed.

[0058] S412, forming a second gate dielectric layer on the inner surface of the second trench.

[0059] In one embodiment of the present application, a thick gate oxide is grown on the surface of the second trench 141 as the second gate dielectric layer 142, see Figure 6a。In an embodiment of the present application, the thickness of the second gate dielectric layer 142 is 1000 Å or more.

[0060] S413, Fill the second trench with gate material to form a second gate.

[0061] In an embodiment of the present application, step S413 forms the second gate 144 in the second trench 141 by depositing polysilicon. In an embodiment of the present application, after depositing polysilicon, CMP (chemical mechanical planarization) is used to remove excess polysilicon and other materials on the front side of the wafer to make the front side of the wafer flat, which is convenient for fabricating the low threshold voltage region. See Figure 6b 。

[0062] S414, Form a first trench in the drift region.

[0063] In an embodiment of the present application, a first trench 131 is formed in the drift region by photolithography and etching. The spacing W between two adjacent first trenches 131 can be optimized, and the number of first trenches 131 in each cell can also be optimized.

[0064] S415, Form a first gate dielectric layer on the inner surface of the first trench.

[0065] In an embodiment of the present application, a thin gate oxide is grown on the surface of the first trench 131 as the first gate dielectric layer 132. See Figure 6c 。In an embodiment of the present application, the thickness of the first gate dielectric layer 132 is 200 Å to 500 Å.

[0066] S416, Fill the first trench with gate material to form a first gate.

[0067] In an embodiment of the present application, step S416 forms the first gate 134 in the first trench 131 by depositing polysilicon. After completing step S416, step S410 ends.

[0068] S420, Form a well region of the second conductivity type at a position near the top of the drift region.

[0069] In one embodiment of the present application, a well region 122 of the second conductivity type is formed by photolithography and ion implantation (implanting ions of the second conductivity type). In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type may also be P-type and the second conductivity type may be N-type. At least a part of the first trench gate 130 is located in the well region 122, and at least a part of the second trench gate 140 is located in the well region 122. Since the well regions 122 around the first trench gate 130 and the second trench gate 140 are formed in the same step (i.e., step S420), the doping concentrations of the well regions 122 around the first trench gate 130 and the well regions 122 around the second trench gate 140 are the same (the dose of the ions of the second conductivity type implanted in step S420 is constant across the chip area).

[0070] S430, form a plurality of active regions of the first conductivity type.

[0071] In one embodiment of the present application, an active region 224 of the first conductivity type is formed by photolithography and ion implantation (implanting ions of the first conductivity type), see Figure 6d .

[0072] In the manufacturing method of the above semiconductor device, by setting the first trench gate 130 with a thinner gate dielectric layer, the device (cell) with the first trench gate 130 as the gate has a lower threshold voltage. Therefore, the device with the first trench gate 130 as the gate will reach the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate 130 as the gate will reach the thermal stable state faster. Therefore, the above semiconductor device as a whole will also reach the thermal stable state faster and has a larger safe operating area. And since the doping concentrations of the well regions 122 around the first trench gate 130 and the well regions 122 around the second trench gate 140 are the same, there is no problem that the base resistance of the parasitic triode NPN of the low-threshold voltage cell is larger, that is, the problem of low UIS ability of the low-threshold voltage cell is solved.

[0073] In one embodiment of the present application, the depth of the first trench 131 is less than the depth of the well region 122, so that the bottom of the first trench gate 130 and the drift region 110 are separated by a part of the well region 122. Thus, when the conductive channel is inverted, the well region 122 at the bottom of the first trench gate 130 and the drift region 110 will form a JFET region, increasing the on-resistance of this region. And the resistance value of the JFET region will increase with the increase of temperature, which is equivalent to connecting a resistor with a resistance value increasing with the increase of temperature in series in this region, thus introducing a "negative feedback mechanism" - that is, the higher the temperature, the greater the resistance, and the drain current I D is smaller. Thus I DIt will be restricted at high temperatures. The upward trend of the transfer characteristic curve of the device at 175 °C becomes gentle, and the ZTC point moves downward.

[0074] In one embodiment of the present application, the first trench gates 130 and the second trench gates 140 formed in step S410 are mixedly distributed on the plane of the wafer, that is, the second trench gates 140 are provided around each first trench gate 130, and the first trench gates 130 are also provided around each second trench gate 140.

[0075] In one embodiment of the present application, after step S430, it further includes the step of forming a USG layer 152 on the active region 124, the first trench gates 130 and the second trench gates 140. Further, a BPSG layer 154 can also be formed on the USG layer 152. Then, contact holes 162 are formed by lithography and etching to penetrate downward through the USG layer 152 and the BPSG layer 154. Then, a conductive material, such as a tungsten plug, is filled in the contact holes 162, and the conductive material is in direct contact with the active region 124. After filling the conductive material in the contact holes 162, a metal interconnection layer electrically connected to the conductive material can also be formed thereon, see Figure 3 . In Figure 3 the embodiment shown, the bottom of the contact hole 162 extends to the well region 122.

[0076] The manufacturing method of the semiconductor device of the present application and the semiconductor device are based on the same inventive concept. For the content not specifically described in the manufacturing method of the semiconductor device, reference can be made to the introduction of the semiconductor device above.

[0077] It should be understood that although the steps in the flowchart of the present application are sequentially shown according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0078] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0079] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0080] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized in that, comprising: a drift region having a first conductivity type; a well region disposed near the top of the drift region and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first trench gate including a first gate dielectric layer on an inner surface of a first trench and a first gate electrode located within the first trench and surrounded by the first gate dielectric layer on all sides and at the bottom, at least a part of the first trench gate being located in the well region; a second trench gate including a second gate dielectric layer on an inner surface of a second trench and a second gate electrode located within the second trench and surrounded by the second gate dielectric layer on all sides and at the bottom, at least a part of the second trench gate being located in the well region; a plurality of active regions having a first conductivity type, some of the active regions being disposed near the first trench gate on a side of the first trench gate, and some of the active regions being disposed near the second trench gate on a side of the second trench gate; wherein, a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer, and doping concentrations of the well regions where the first trench gate is located and the well regions where the second trench gate is located are the same.

2. The semiconductor device according to claim 1, characterized in that, a part of the well region separates between a bottom of the first trench gate and the drift region.

3. The semiconductor device according to claim 1, characterized in that, a depth of the second trench gate is greater than a depth of the well region, so that a bottom of the second trench gate reaches into the drift region.

4. The semiconductor device according to claim 1, characterized in that, the thickness of the first gate dielectric layer is from 200 Å to 500 Å; and / or a threshold voltage of a device with the first gate electrode as a gate electrode is not greater than 1.5 V.

5. The semiconductor device according to claim 1, characterized in that, the thickness of the second gate dielectric layer is more than 1000 Å; and / or a threshold voltage of a device with the second gate electrode as a gate electrode is above 3 V.

6. The semiconductor device according to claim 1, characterized in that, at least a part of the first trench gate is located between different second trench gates.

7. The semiconductor device according to claim 1, characterized in that, the semiconductor device is a metal oxide semiconductor field effect transistor or a vertical double-diffused metal oxide semiconductor field effect transistor.

8. A manufacturing method of a semiconductor device, comprising: forming a first trench gate and a second trench gate in a drift region of a first conductivity type; the first trench gate includes a first gate dielectric layer on an inner surface of a first trench and a first gate electrode located within the first trench and surrounded by the first gate dielectric layer on all sides and at the bottom; the second trench gate includes a second gate dielectric layer on an inner surface of a second trench and a second gate electrode located within the second trench and surrounded by the second gate dielectric layer on all sides and at the bottom; forming a well region of a second conductivity type at a position near the top of the drift region; the first conductivity type and the second conductivity type are opposite conductivity types; Form a plurality of active regions of a first conductivity type, with some of the active regions formed on the side surfaces of the first trench gate and close to the first trench gate, and some of the active regions formed on the side surfaces of the second trench gate and close to the second trench gate; Among them, the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer, the doping concentrations of the well regions where the first trench gate is located and the well regions where the second trench gate is located are the same, at least a part of the first trench gate is located in the well region, and at least a part of the second trench gate is located in the well region.

9. The manufacturing method of the semiconductor device according to claim 8, characterized in that, In the step of forming the first trench gate and the second trench gate in the drift region of the first conductivity type, the first trench gates and the second trench gates are mixedly distributed on the plane of the wafer.

10. The manufacturing method of the semiconductor device according to claim 8, characterized in that, The depth of the first trench is less than the depth of the well region, so that the bottom of the first trench gate is separated from the drift region by a part of the well region.

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