Semiconductor device

Abstract

The present disclosure relates to a semiconductor device comprising an "n" pair of pn junction structures, where n is an integer > = 2, where an i-th pair comprises two pn junction structures of an i-th type, where i = {1,..., n}, where the two pn junction structures of the i-th type are connected in anti-series, where the pn junction structures of the i-th type are arranged to have an i-th junction ramping coefficient mi. At least a first pair of the n pairs of pn junction structures is arranged to have a first junction ramp coefficient m1, wherein # imgabs0 # and m1lt; the first one of the n pairs of pn junction structures is arranged to have a first junction ramp coefficient m1, 0.50, and the second one of the n pairs of pn junction structures is arranged to have a second junction ramp coefficient m2, where the junction ramp coefficients m1, m2 of the first and second one of the # imgabs1 # n pairs of pn junction structures are adjusted to result in the generation of spurious third harmonic signals of a semiconductor device having a signal power level, the signal power level is at least 10 db lower than a reference signal power level for a spurious third harmonic signal obtained in a reference case where the first junction ramp coefficient and the second junction ramp coefficient m1, m2 are 0.25.

Description

[0001] Division Application Instructions

[0002] This application is a divisional application of a Chinese patent application with an application date of August 12, 2019, an application number of 201910741521.5, and a title of "Semiconductor Device". Technical Field

[0003] Embodiments relate to a semiconductor device having at least two pairs of anti - series - connected pn - junction structures (also denoted herein as diode structures) having an adjusted junction grading coefficient (also referred to as the diode power - law exponent) for providing at least reduced or minimized generation of spurious odd - order harmonics (e.g., third - harmonic).

[0004] Further embodiments relate to a semiconductor device having at least two anti - series - connected pn - junction structures with adjusted junction grading coefficients, wherein one of the two pn - junction structures includes a "composite" diode structure to adjust and obtain a desired TVS behavior (TVS = transient voltage suppressor) of the semiconductor device with respect to breakdown voltage, and to provide at least reduced or minimized generation of spurious odd - order harmonics (e.g., third - harmonic). Background Art

[0005] Discrete ESD protection devices (ESD = electrostatic discharge) and TVS devices (TVS = transient voltage suppressor) typically have non - linear electrical characteristics that result in harmonic distortion of RF signals (RF = radio frequency) present on signal lines, e.g., on PCB lines (PCB = printed circuit board) connected to ESD protection devices or TVS devices. This harmonic generation creates spurious and unwanted harmonic signals that can interfere with other functions or functional blocks of an electronic system if those functions or functional blocks use frequency bands that are integer multiples of the distorted RF signal.

[0006] For example, the third - harmonic (H3) frequencies in certain frequency bands within the range between 800 MHz and 900 MHz used in mobile telecommunications standards interfere with RF signals in the 2.4 GHz - WIFI band, i.e., in the frequency range between 2.412 and 2.472 GHz.

[0007] To avoid this unwanted interference between the exemplary frequency bands described above, electronic devices such as TVS devices should minimize their harmonic generation to a sufficiently low level.

[0008] In known embodiments, the generation of even harmonics is minimized, for example, by leveraging a strictly symmetric design and highly symmetric behavior of electronic devices for the positive and negative half-waves of an RF signal. By ensuring symmetry, even harmonics can be effectively suppressed. However, the generation of odd harmonics is not affected by or is sufficiently suppressed by this method.

[0009] For the minimum generation of odd harmonics, such as the third harmonic (h3), in the prior art, it has long been assumed that the low capacitance and flat capacitance versus voltage (CV) behavior of electronic devices result in low harmonic generation, including the third harmonic.

[0010] However, the applicant's current research has shown that, considering the comparison of harmonic generation of electronic devices with different capacitance values and CV characteristics, the above method for suppressing the generation of odd harmonics is insufficient.

[0011] Generally, there is a need in the art for a method of implementing a semiconductor device, such as for implementing a discrete ESD protection device or a TVS device, that has reduced or minimized generation of odd harmonics, such as the third harmonic.

[0012] Generally, there is a need in the art for a method of implementing a semiconductor device, such as for implementing a discrete ESD protection device or a TVS device, that also has a reduced or tuned breakdown voltage. SUMMARY OF THE INVENTION

[0013] According to one embodiment, a semiconductor device includes “n” pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i ∈ {1,…,n}, where the two pn junction structures of the i-th type are anti-series connected, and where the pn junction structure of the i-th type is arranged to have an i-th junction grading coefficient m i .

[0014] Where at least a first pair of the n pairs of pn junction structures is arranged to have a first junction grading coefficient m 1 , where and m 1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m 2 , where and where the junction grading coefficients m 1 、m 2is adjusted to result in the generation of a spurious third harmonic signal having a signal power level (PH3) that is at least 10 dB lower than the (e.g., simulated) reference signal power level (PH3) of the spurious third harmonic signal obtained for a (e.g., simulated) reference case in which the first junction grading coefficient and the second junction grading coefficient m 1 and m 2 are 0.25.

[0015] In a model of the common application of pn junction structures, the i-th junction grading coefficient m i is determined based on the voltage-dependent capacitance characteristic C i (V i ) of the depletion region of the i-th type of pn junction structure for a reverse bias voltage Vi applicable to the i-th type of pn junction structure, where:

[0016]

[0017] where C J0i represents the i-th zero-bias junction capacitance, and V Ji represents the i-th junction voltage potential.

[0018] For example, for this reference case, the spurious odd harmonic generation can be determined by simulation using a standard circuit simulation tool (such as the Advanced Design System (ADS) from Keysight Technologies), for example, through harmonic balance analysis commonly known in the art.

[0019] According to another embodiment, a semiconductor device includes “n” pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i ∈ {1, …, n}, where the two pn junction structures of the i-th type are anti-series connected, and where the pn junction structure of the i-th type is arranged to have an i-th junction grading coefficient m i .

[0020] where the first through the n-th junction grading coefficients m 1 through m n conform to the following elliptical equation within a tolerance of ±0.05:

[0021] where

[0022] where at least the first pair of the n pairs of pn junction structures is arranged to have a first junction grading coefficient m 1 , where and m 1 < 0.50, and the second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m 2 , where and wherein parameter a i is based on the zero - bias capacitance C J0i of the pn - junction structure of the i - th type Ji and the junction voltage potential V

[0023] A tolerance range of ±0.05 indicates the range for each grading coefficient. In the context of this article, in the case where the ellipse intersects or at least touches the volume defined by the tolerance range around a specific point (m 1 to m n ) in the n - dimensional space (coordinate system) of the grading coefficients, the grading coefficients m 1 to m n are considered to conform to the ellipse equation within this tolerance range. For illustrative purposes, in the two - dimensional case of two pairs of pn - junction structures with grading coefficients m 1 and m 2 , the volume defined by the tolerance range is a circle with a diameter of 0.10 and the specific point (m1, m2) in the middle. Thus, effectively, a range of width 0.10 around the ellipse is defined, within which the possible combinations of the grading coefficients m 1 to m n can be set.

[0024] wherein the i - th grading coefficient m i of the i - th type pn - junction structure, the zero - bias capacitance C J0i and the junction potential V Ji can also be described by the above - mentioned formula (A1).

[0025] Thus, an embodiment relates to a semiconductor device having at least two pairs of pn - junction structures connected in anti - series, wherein for each of at least two pairs, the semiconductor device with at least two pairs of pn - junction structures connected in anti - series has adjusted grading coefficients for providing at least reduced or minimized generation of spurious odd - order harmonics such as third - order harmonics.

[0026] According to another embodiment, a semiconductor device includes a compound pn - junction structure in a semiconductor substrate, wherein the compound pn - junction structure is arranged to have a predetermined first grading coefficient m 1 , where m 1 > 0.50, wherein the compound pn - junction structure includes a first partial pn - junction structure and a second partial pn - junction structure, wherein the first partial pn - junction structure is arranged to have a predetermined first - part grading coefficient m 11 , and wherein the second partial pn - junction structure is arranged to have a predetermined second - part grading coefficient m 12 , wherein the predetermined first - part grading coefficient m 11 is different from the predetermined second - part grading coefficient m 12 , where m11 ≠m 12 and wherein a predetermined first part junction grading coefficient and a second part junction grading coefficient m 11 、m 12 at least one of the junction grading coefficients is greater than 0.5, where m 11 and / or m 12 >0.5, and wherein a predetermined first junction grading coefficient m of the compound pn junction structure 1 is based on a predetermined combination of a first part junction grading coefficient and a second part junction grading coefficient m 11 、m 12 of the compound pn junction structure

[0027] Accordingly, embodiments relate to semiconductor devices having at least two pairs of anti - series - connected pn junction structures with adjusted junction grading coefficients, wherein at least one pair of the at least two pairs of pn junction structures is a pair of anti - series - connected compound pn junction structures (also denoted herein as "compound diode structures") to adjust and obtain the desired TVS behavior (TVS = transient voltage suppressor) of the semiconductor device with respect to breakdown voltage and to provide at least a reduced or minimized generation of spurious odd harmonics such as third harmonics. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Embodiments of the present concept are described herein with reference to the accompanying drawings, in which:

[0029] Figures 1a to 1d shows an exemplary schematic circuit diagram of a semiconductor device having n pairs of anti - series - connected pn junction structures according to an embodiment,

[0030] Figure 2 shows an exemplary circuit block diagram for testing the semiconductor device,

[0031] Figure 3a 、 Figure 3b shows a schematic power distribution of an RF signal according to an embodiment,

[0032] Figure 4a shows a graphical representation (curve graph of the function) of the cancellation line of the third - harmonic signal of the semiconductor device according to an embodiment as a function of a first junction grading coefficient and a second junction grading coefficient m 1 、m 2 of the semiconductor device,

[0033] Figure 4b shows Figure 4a an enlarged view (view) of

[0034] Figure 4c shows another graphical representation of a functional diagram that can optimally suppress the third - harmonic generation PH3 of the semiconductor device,

[0035] Figure 4d Shows an enlarged view (view) of the graphical representation of Figure 4c and

[0036] Figure 4e shows the parameter a of the ellipse where the third harmonic PH3 of the semiconductor device 100 can be optimally suppressed 1 、a 2 (= radius r 1 、r 2 ) of the graphical representation

[0037] Figure 4f shows the influence of the unequal values of the first junction voltage potential and the second junction voltage potential V J1 、V J2 and shows the graphical representation of the cancellation line of the third harmonic PH3 of the semiconductor device as a function of the first junction grading coefficient and the second junction grading coefficient m 1 、m 2

[0038] Figures 4g to 4j shows the spurious third harmonic PH3 of the simulation of the semiconductor device with equal first bias junction capacitance and second bias junction capacitance C J01 = C J02 at different input power levels of the fundamental frequency signal

[0039] Figure 5aa and Figure 5ab shows Figure 1a the schematic cross-sectional view of the semiconductor device

[0040] Figure 5b shows Figure 5aa and Figure 5ab the schematic simulation diagram of the exemplary doping distribution of the pn junction structure of the semiconductor device

[0041] Figure 6a shows the schematic cross-sectional view of the semiconductor device according to the embodiment

[0042] Figure 6b shows Figure 6a the schematic top view of the semiconductor device

[0043] Figure 7a 、 Figure 7b shows the exemplary schematic circuit diagram of the semiconductor device having n pairs of anti-series connected pn junction structures according to the embodiment

[0044] Figure 8a shows the schematic simulation diagram of the junction grading coefficient m Figure 5b resulting as a function of the doping concentration for different implantation doses based on the doping distribution of 1 ​

[0045] Figure 8b shows a schematic simulation diagram of the breakdown voltage resulting as a function of the doping concentration of different implantation doses as the doping profile for Figure 5b The

[0046] Figure 8c shows, as a function of the area ratio between the area of the first part pn - junction structure and the area of the second part pn - junction structure, the combined junction grading coefficient of the composite first - type pn - junction structure resulting from Figure 5b the two adjusted partial junction grading coefficients m 11 、m 12 for the two doping profiles shown.

[0047] Figure 9a shows a schematic cross - sectional view of another exemplary implementation of a semiconductor device.

[0048] Figure 9b shows Figure 9a a schematic simulation diagram of different exemplary doping profiles of the composite pn - junction structure of a semiconductor device for

[0049] Figure 9c shows a schematic top - view of a semiconductor device taken in a plane passing through Figure 9a the Figure 9c which shows the "active" areas of the first - part anode region and the second - part anode region of the first - type pn - junction structure, and

[0050] Figures 9d to 9f shows a schematic cross - sectional view of another exemplary implementation of a semiconductor device.

[0051] Before discussing the embodiments of the present invention in more detail with reference to the drawings, it is noted that in the drawings and the specification, the same elements and elements having the same functions and / or the same technical or physical effects are generally provided with the same reference numerals or are identified by the same names, such that the descriptions of these elements and their functions as illustrated in different embodiments are mutually interchangeable or can be applied to each other in different embodiments. Detailed Description

[0052] In the following description, embodiments of the present invention are discussed in detail. However, it should be recognized that the present invention provides many applicable concepts that can be embodied in a variety of semiconductor devices. The specific embodiments discussed merely illustrate specific ways of making and using the present invention and do not limit the scope of the present invention. In the following description of the embodiments, the same or similar elements having the same function have the same reference symbols or the same name associated therewith, and the description of such elements will not be repeated for each embodiment. Moreover, the features of the different embodiments described below can be combined with each other unless otherwise specifically mentioned.

[0053] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly" connected to another element, "connected" or "coupled", no intervening elements are present. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between", "adjacent" versus "directly adjacent", etc.).

[0054] As used herein, the abbreviations "CV" or "C(V)" represent capacitance with respect to voltage, respectively. The terms C(V) characteristic, C(V) property, and C(V) behavior may be used synonymously in this document.

[0055] Figures 1a to 1d Different schematic circuit diagrams of a semiconductor device 100 are shown. The semiconductor device 100 has "n" pairs 102, 104 (...) of anti-series connected pn-junction structures J1, J2, J3, J4 (...), which can be adjusted based on the concepts described below to include reduced, for example, strongly reduced, or even minimized generation of spurious odd harmonics such as third harmonics.

[0056] More specifically, the semiconductor device 100 includes "n" pairs 102, 104 (...) of pn-junction structures J1, J2 and J3, J4 (...), where n is an integer ≥ 2, where the i-th pair includes two pn-junction structures of the i-th type, where i ∈ {1,..., n}, and where the two pn-junction structures of the i-th type are anti-series connected. The pn-junction structures of the i-th type are arranged to have the i-th junction grading coefficient m i (m 1 , m 2 ...), the i-th zero-bias junction capacitance C J0i , and the i-th junction voltage potential V Ji , and having the following capacitance behavior C i (V i ) based on the reverse bias voltage V i ) for the pn-junction structures of the i-th type, where

[0057]

[0058] The C(V) characteristics described by the above equation are also valid for relatively small forward bias voltages. In other words, the expression is also valid for the range of applied voltages for which the reverse bias voltage is negative, i.e., the applied voltage is a forward bias voltage. In the present specification, the phrase "pn junction (or diode structure) having a grading coefficient m i " is used to indicate that the C(V) characteristics of the pn junction or diode structure can be described by the above equation having a grading coefficient or power law exponent m i .

[0059] According to an embodiment, at least a first pair 102 of n pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...) is arranged to have a first junction grading coefficient m 1 , where and a second pair 104 of n pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...) is arranged to have a second junction grading coefficient m 2 , where and where the pn junction structures J1, J2 of the first pair 102 are arranged to have a first junction grading coefficient m 1 , where m 1 < 0.50, and where the junction grading coefficients m 1 , m 2 of the first and second pairs 102, 104 (...) of n pairs of pn junction structures J1, J2 and J3, J4 (...) are adjusted to result in the generation of a spurious third harmonic signal having a signal power level PH3 of the semiconductor device 100, which signal power level PH3 is at least 10 dB lower, preferably at least 15 dB lower, and more preferably at least 20 dB lower than the (e.g., simulated) reference signal power level PH3 of the spurious third harmonic signal obtained for a reference case in which the first junction grading coefficient and the second junction grading coefficient m 1 , m 2 are 0.25, respectively. It may be preferred to keep m1 ≤ 0.48 from the aspect of facilitating the fabrication of the pn junction structure.

[0060] The second pair 104 of pn junction structures J3, J4 may be arranged to have a second junction grading coefficient m 2 , where m 2 > 0.50, preferably m 2 ≥ 0.52.

[0061] In the reference case, by setting the junction grading coefficients m 1 , m 2 , (...)(i.e., all junction grading coefficients m1 and m 2 and (…), these junction grading coefficients m 1 and m 2 and (…) have been adjusted previously and are set to a reference value of m deviating from 0.00 and 0.50 i = 0.25 to simulate and calculate the reference signal power level PH3’ of the spurious third - harmonic signal of the semiconductor device 100.

[0062] According to the embodiment defined above, when compared with, for example, the reference signal power level PH3’ of the spurious third - harmonic signal of the semiconductor device 100 obtained in a reference case where the junction grading coefficients m1, m2(…) of the n pairs 102, 104(…) of pn - junction structures J1, J2 and J3, J4 are set to the reference value 0.25, the junction grading coefficients m 1 and m 2 (…) of the pn - junction structures J1, J2 and J3, J4 of the n pairs 102, 104(…) are adjusted to provide at least a reduced signal power level PH3 of the spurious third - harmonic signal. For example, the following evaluation regarding Figure 2 will show that the simulation of the reference signal power level PH3’ of the semiconductor device 100 with the junction grading coefficient m 1 and m 2 set to the reference value 0.25, using a circuit simulation tool as described in more detail below, is related to the (theoretical) local maximum of the reference signal power level PH3’ of the spurious third - harmonic signal of the semiconductor device 100.

[0063] According to another embodiment, the semiconductor device 100 includes “n” pairs 102, 104(…) of pn - junction structures J1, J2 and J3, J4(…), where n is an integer ≥ 2, where the i - th pair includes two pn - junction structures of the i - th type, where i ∈ {1,…,n}, and the two pn - junction structures of the i - th type are anti - serially connected. The pn - junction structures of the i - th type are arranged to have the i - th junction grading coefficient m i , the i - th zero - bias junction capacitance C J0i , and the i - th junction voltage potential V Ji , and have the following capacitance behavior C i (V i ) based on the reverse - bias voltage V i where

[0064] and

[0065] where the first through the n - th junction grading coefficients m 1 through m n conform to the following elliptical equation within a tolerance of ±0.05:

[0066] wherein

[0067] at least a first pair of the n pairs of pn - junction structures is arranged to have a first junction grading coefficient m 1 , wherein wherein m 1 <0.50, and a second pair of the n pairs of pn - junction structures is arranged to have a second junction grading coefficient m 2 , wherein and wherein the first through nth parameters “a 1 through a n ” depend on the zero - bias capacitance C of the pn - junction structure J0i and the junction voltage potential V Ji . It may be preferable to maintain m1≤0.45 in terms of facilitating the fabrication of the pn - junction structure.

[0068] The second pair 104 of the pn - junction structures J3, J4 may be arranged to have a second junction grading coefficient m 2 , wherein m 2 ≥0.50, preferably m 2 ≥0.52.

[0069] As indicated above, the first through nth junction grading coefficients m 1 through m n are in accordance with the indicated (n - dimensional) elliptical equation within a tolerance range of ±0.05. For example, a tolerance range of ±0.05 (or ±0.03) may account for the inevitable semiconductor manufacturing tolerances of the semiconductor device 100. For example, a tolerance range of ±0.05 (or ±0.03) may also account for the (possible) difference between the locus of the theoretical optimal suppression of spurious third - harmonics and the locus of the actual (e.g., input - power - related) optimal suppression at different input power levels of the semiconductor device 100. This will be described in more detail below with reference to Figures 4g to 4j more specifically.

[0070] Hereinafter, with reference to Figures 1a to 1d a schematic circuit diagram depicting some possible implementations of the semiconductor device 100 according to the present concept is described.

[0071] As Figure 1a exemplarily shown, the semiconductor device 100 may include an anti - series connection of n = 2 pairs 102, 104 of pn - junction structures J1, J2, J3, J4, wherein the first pair of pn - junction structures 102 includes a first type of pn - junction structures J1, J2 having a first grading coefficient m 1 , a first junction voltage potential V J1 and a first zero - bias capacitance C J01 , and wherein the second pair of pn - junction structures 104 includes a second grading coefficient m2 , the second junction voltage potential V J2 and the second zero - bias capacitance C J02 of the second - type pn - junction structures J3, J4. As Figure 1a shown, the pn - junction structures J1, J2 of the first pair 102 and the pn - junction structures J3, J4 of the second pair 104 are connected in anti - series respectively, where (at least) two pairs 102, 104 of the pn - junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108.

[0072] Figure 1b shows another exemplary schematic circuit diagram of the semiconductor device 100 having two (n = 2) pairs 102, 104 of the junction structures J1, J2, J3, J4, where the first pair 102 includes pn - junction structures J1, J2 having a first grading coefficient m 1 , the first junction voltage potential V J1 and the first zero - bias capacitance C J01 of the first - type, and the second pair 104 includes pn - junction structures J3, J4 having a second grading coefficient m2, a second junction voltage potential V J2 and the second zero - bias capacitance C J02 of the second - type. As Figure 1b shown, the pn - junction structures J1, J2 of the first pair 102 are connected in anti - series and the pn - junction structures J3, J4 of the second pair 104 are connected in anti - series, where (at least) two pairs 102, 104 among the pn - junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108. When compared with the Figure 1a semiconductor device 100, as Figure 1b shown, the arrangement of the two pairs 102, 104 of the pn - junction structures J1, J2 and J3, J4 only differs by the reverse direction of the corresponding pn - junction structures J1 to J4.

[0073] Figure 1c shows another schematic circuit diagram of the semiconductor device 100 having N = 2 pairs 102, 104 on the pn - junction structures J1, J2, J3, J4, where in Figure 1c , the first pair 102 includes pn - junction structures J1, J2 having a first grading coefficient m 1 , the first junction voltage potential V J1 and the first zero - bias capacitance C J01 of the first - type, and the second pair 104 includes pn - junction structures J3, J4 having a second grading coefficient m 2 , the second junction voltage potential V J2 and the second zero - bias capacitance C J02 of the second - type. As Figure 1cAs shown, the pn - junction structures J1, J2 of the first pair 102 and the pn - junction structures J3, J4 of the second pair 104 are respectively connected in anti - series, where (at least) two pairs 102, 104 of the pn - junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108. When compared with the semiconductor device 100 of Figure 1a as Figure 1c shown, the arrangement of the pn - junction structures J1 to J4 of the two pairs 102, 104 only differs by the arrangement order of the corresponding pn - junction structures J1 to J4.

[0074] Figure 1d FIG. shows another schematic circuit diagram of a semiconductor device 100 having an anti - series connection of pn - junction structures J1, J2 and J3, J4 and J5, J6 with n = 3 pairs 102, 104, 106. As Figure 1d shown, for example, the first pair 102 includes two pn - junction structures J1, J2 of the first type having a first grading coefficient m 1 , a first junction voltage potential V J1 and a first zero - bias capacitance C J01 , the second pair 104 includes pn - junction structures J3, J4 of the second type having a second grading coefficient m 2 , a second junction voltage potential V J2 and a second zero - bias capacitance C J02 , and the third pair 106 includes pn - junction structures J5, J6 of the third type having a third grading coefficient m 3 , a third junction voltage potential V J3 and a third zero - bias capacitance C J03 . As Figure 1d shown, the pn - junction structures J1, J2 of the first pair 102, the pn - junction structures J3, J4 of the second pair 104 and the pn - junction structures J5, J6 of the third pair 104 are respectively connected in anti - series, where the pn - junction structures J1 to J6 of the three pairs 102, 104, 106 are connected between the first terminal 107 and the second terminal 108.

[0075] The above - described schematic circuit diagram of the semiconductor device 100 shows that the semiconductor device 100 may include multiple pairs 102, 104, 106 of pn - junction structures J1 to J6, where the two associated pn - junction structures of the corresponding pairs are respectively arranged or connected in anti - series between the first terminal 107 and the second terminal 108, and where the order of the corresponding pn - junction structures does not affect the final reduction of the third - harmonic generation of the semiconductor device, such that different pn - junction structures of n pairs can be arbitrarily arranged in anti - series between the first terminal 107 and the second terminal 108.

[0076] For example, for the reference case, spurious odd harmonic generation can be determined by simulation using standard circuit simulation tools such as the Advanced Design System (ADS) from Keysight Technologies, where, for example, harmonic balance analysis commonly known in the art can be employed. The simulation results can be compared with the measurement of spurious harmonic generation of the semiconductor device under test, and thus with the harmonic generation of the reference case, to determine the measured power level of the spurious third harmonic of the device under test relative to the power level of the spurious third harmonic determined by the simulation for the reference case. Model parameters for the simulation of the reference case, other than the scaling factors such as zero-bias junction capacitance and junction potential, can be obtained from the measurements of the device to be compared by methods commonly known in the art.

[0077] Figure 2 The block circuit diagram shows a possible circuit setup for the measurement or simulation of harmonic generation of a semiconductor device under test. Figure 2 A transmission line including two parts TL1 201 and TL2 202 is depicted, where a semiconductor device under test 200 (illustrated by way of example as a four-diode structure J1 to J4) is connected to ground in a shunt configuration. An RF signal is delivered by RF source PORT1 211 at a fundamental frequency f0 and is coupled into TL1 201 through circulator CIR1 203 at the depicted left end of transmission line TL1 201.

[0078] The RF signal is conducted to the semiconductor device under test 200 (J1 to J4), where harmonic signals at integer multiples of the fundamental frequency (overtones) are generated due to the non-linearity in the electrical properties of the semiconductor device under test 200. The generated harmonic signals are transmitted from the semiconductor device under test 200 via TL2 202 to terminal Term2 212 and via TL1 201, circulator CIR1 203, and transmission line TL3 204 to terminal Term3 213. By using a spectrum analyzer (not shown), the RF power distribution of the harmonic signals can be determined at the location of terminal Term2 212 or at the location of terminal Term3 213. By scanning the power of the transmitted RF signal at the fundamental frequency, the input power dependence of harmonic generation can be determined.

[0079] The determination sensitivity of the generated harmonic signals can be further increased by adding, for example, additional filters or duplexers (not shown) to filter out the signal at the fundamental frequency f0.

[0080] In Figure 3a and 3b the typical spectra of the generated RF signal and harmonic signals are schematically shown, respectively. Figure 3aShows the spectrum of the RF signal transmitted by RF source PORT1 211. This signal is transmitted to consist only of the fundamental frequency f0 (first harmonic, x = 1). Figure 3b Depicts the spectrum of the signal arriving at, for example, terminal Term2 212. Due to the following reasons, the signal power at the fundamental frequency is reduced compared to Figure 3a the incident signal shown in: (1) due to the impedance mismatch caused by the semiconductor device under test 200 in the shunt configuration, and (2) due to the partial conversion of the electrical signal at the fundamental frequency into overtones, shown here as the second to fourth harmonics for simplicity. The spectrum further shows that the signal in, for example, terminal Term2 212 also includes power contributions at integer multiples of the fundamental frequency, such as the second harmonic power Ph2 at 2 times f0 (2×f0, x = 2), the third harmonic power PH3 at 3 times f0 (3×f0, x = 3), and so on. Generally, the power contribution of the overtones decreases with the order of the harmonics.

[0081] The following evaluation provides a comprehensive explanation of the present concept in the form of the implementation and embodiment of the semiconductor device 100 with appropriately adjusted junction grading coefficients mi (m1, m2,...) as described in Figures 1a to 1d particular, the following discussion presented by the applicant regarding Figure 4a - to Figure 4j involves the technical and mathematical analysis in the field of semiconductor devices, for example, regarding the fields respectively based on discrete ESD protection devices and TVS devices, and involves the resulting technical findings and conclusions for appropriately adjusting the junction grading coefficient m of the n pn - junction structure of the semiconductor device 100 i .

[0082] Under the assumption that the "capacitance versus voltage C(V) characteristic" of the pn - junction structure (or simply the pn - junction) is the main contributor to the generation of odd - order harmonics of the semiconductor device 100, in the case of appropriately adjusting the C(V) characteristic of the individual pn - junction structure, the third - harmonic generation can be substantially completely eliminated or at least strongly reduced. The individual pn - junction structure can include at least two pairs 102, 104 (...) of back - to - back connected pn - junction structures J1, J2, J3, J4 (...).

[0083] More specifically, in the case of the connection or stacking of, for example, four back - to - back connected pn - junction structures J1 to J4 (i.e., two pairs of pn - junction structures), the third - harmonic generation can be eliminated or at least minimized by selecting a suitable combination of the C(V) behaviors of different pn - junction structures J1 to J4 in the four - pn - junction stack, for example, by according to the following shown for the junction grading coefficient m i and parameter a 1 、a 2The equations and formulas appropriately select the (first and second) pn junction grading coefficients m 1 、m 2 , which depend on the zero-bias capacitances C J01 、C J02 of the pn junction structures of the two pairs 102, 104 and the junction voltages V J1 、V J2 .

[0084] The C(V) behavior of the pn junction marked as "i" to represent the "i-th" type in this description can generally be described by the following expression:

[0085]

[0086] In many cases, this expression provides an accurate description of the C(V) characteristics of the pn junction structure. The parameters have the following meanings: C j0 is the capacitance at 0 V bias, V ji is the built-in voltage, and m i is the "junction grading coefficient". V represents the reverse bias across the i-th pn junction. As can be understood from expression (A1), the junction grading coefficient m i is a key parameter for controlling the C(V) behavior of the pn junction structure and thus the C(V) behavior of the semiconductor device 100. m i can be adjusted by the doping profile of the corresponding pn junction structures J1 to J4 (...).

[0087] Some examples of the grading coefficient m are:

[0088] - m = 0.5 represents the behavior of (1.) a step pn junction with uniform dopants ( = doping concentration) in the n-region and p-region, or (2.) a one-sided junction with a very abrupt pn junction between a highly doped region and a lower doped region with uniform doping. Implementing such an idealized junction with conventional semiconductor technology may be difficult or expensive.

[0089] - m = 0.33 represents the behavior of a linearly graded junction. In this case, the doping concentration around the junction varies linearly with depth. Due to the diffusion of the p-doped region and the n-doped region, this type of pn junction is very common in conventional semiconductor technology.

[0090] - In the case of m > 0.5, the term hyperabrupt junction is used. The hyperabrupt junction can be considered a one-sided junction where the lower doped region does not have a constant doping profile but has a doping concentration that decreases with the distance from the metallurgical junction.

[0091] In the following, a mathematical derivation of the optimal C(V) parameters for suppressing third harmonic generation in the semiconductor device 100 is outlined. The following derivation can adequately describe the C(V) characteristics for low input powers Pin of, for example, input RF signals not exceeding 20 dbm, but the C(V) characteristics may be less accurate for higher input powers.

[0092] In the following equations (1) to (38) and the related Figure 4a to 4J, the radius r i corresponds to the parameter a of the ellipse equation described so far i , that is, r i = a i . Generally within this document, the radius r as described and / or depicted herein i corresponds to the parameter a as described and / or depicted herein i , that is, r i = a i .

[0093] The capacitance of two different pn junctions with respect to the voltage behavior is represented by the following equations. These equations can be successfully used to describe the depletion capacitance behavior of pn junctions under reverse and small forward bias conditions within a wide range of doping profiles.

[0094]

[0095] where V is the applied reverse bias voltage, C J0i is the zero-bias junction capacitance, V Ji is the junction voltage or junction potential (equal to or close to the built-in voltage, sometimes referred to as the "effective built-in voltage"), and m i is the grading coefficient (also known as the "diode power-law exponent").

[0096] The capacitance-voltage behavior equation can be expanded into a Taylor series:

[0097] C 1 (V) = K 10 + K 11 V + K 12 V 2 + … (3)

[0098] C 2 (V) = K 20 + K 21 V + K 22 V 2 + … (4)

[0099] By integrating the C I (V) expression from 0V to a specific voltage V ij , the total charge Q ij. In the case of a series connection of 2 pairs of anti - series pn - junctions, the following will be applied to find the charge on each pn - junction, considering that in each pair of junctions, one junction is reverse - biased and one is forward - biased.

[0100]

[0101] Applying the integral of the capacitance - voltage relationship C(V) to the series expansion gives the following expression:

[0102]

[0103] In a series - connected capacitor configuration, the charge on all capacitors is equal:

[0104] Q 11 = Q 12 = Q 21 = Q 22 = Q (13)

[0105] By series inversion, the charge as a function of voltage (Equations 9 - 12) can be inverted to voltage as a function of charge.

[0106]

[0107]

[0108] The total voltage V across 2 pairs of anti - series - connected pn - junctions is

[0109] V = V 11 + V 12 + V 21 + V 22 (18)

[0110] By summing Equations 14 to 17, the total voltage V across the series - connected pn - junctions as a function of charge Q:

[0111]

[0112] By series inversion of Equation 19, the charge Q as a function of the total voltage V across the series - connected pn - junctions is as follows:

[0113]

[0114] The capacitance - voltage characteristics of the series - connected junctions can be calculated by differentiating the Q(V) expression (Equation

[0115] 20).

[0116]

[0117] We define the coefficients in this series of the C(V) behavior as follows:

[0118] C = κ 0 + κ 1 V + κ 2 V 2 +... (23)

[0119] The coefficient of the quadratic term κ 2 V 2 determines the generation of the third harmonic. This coefficient κ 2 is:

[0120]

[0121] Now, the coefficients K 10 、K 11 、K 12 、K 20 、K 21 、K 22 in the series expansion of an individual pn junction are replaced by the corresponding Taylor coefficients generated by the Taylor expansion of the C(V) behavior (Equations 1 and 2). After this replacement, the coefficient κ 2 of the quadratic term becomes:

[0122]

[0123] In the series expansion of the C(V) behavior, the quadratic term is responsible for the generation of the third harmonic. If the quadratic term is zero, the third harmonic will be completely eliminated.

[0124] κ 2 = 0 (26)

[0125] We can transform the expression Equation 25 for κ 2 = 0 into the following form that describes an ellipse in the m 1 、m 2 plane:

[0126]

[0127] where (m 0,1 , m 0,2 ) is the center point of the ellipse, and r 1 and r 2 are the radii in the m 1 and m 2 directions respectively

[0128] Equation 25 under the condition represented by Equation 26 is transformed into the form of Equation 27, and thus results in:

[0129]

[0130] Thus, we can infer that if the coefficient of variation m 1 and m 2 lies on the ellipse, the generation of third harmonics is eliminated, as described by the following equation, with a radius r 1 and r 2 :

[0131]

[0132]

[0133] According to equations 29 and 30, we can infer the shape of the ellipse on which the combination of the coefficients of variation m 1 and m 2 depends on the ratio of the zero-bias capacitance and the junction potentials of the two pairs of junctions. By adjusting the doping profile and / or the physical design (layout) of the pn junction, the zero-bias capacitance can be varied over a wide range. On the other hand, the range of variation of the junction potential is significantly smaller because this parameter is related to the built-in voltage of the pn junction. For silicon pn junctions, the typical range of variation of V J is from about 0.6 to 0.9 V. In cases where a certain breakdown voltage is required from the pn junction, the possibility of affecting V J is very limited and cannot be considered a useful parameter for designing device performance.

[0134] As described below, Figures 4a to 4j shows the influence of device parameters (i.e., the zero-bias junction capacitance C 1 to C n (here: C1 and C2) and the junction voltage potentials V J01 , C J02 and the junction voltage potentials V J1 , V J2 ) on the relationship between the first to nth (here: second) junction coefficients of variation m

[0135] Figure 4a shows a graphical representation (a plot of the function) of the cancellation line of the third harmonic signal PH3 of the semiconductor device 100 according to an embodiment as a function of the first junction coefficient of variation and the second junction coefficients of variation m1, m2.

[0136] Based on the above mathematical derivation of the optimal C(V) parameters, Figure 4a of the ellipse, where the combination of the coefficients of variation m 1 and m 2 lies on this ellipse, which indicates the cancellation of the third harmonic signal PH3 of the semiconductor device 100. Therefore, in this context, these ellipses are also referred to as cancellation lines. The shape of the ellipse depends on the zero-bias capacitance C J01, C J02 The ratio of and the junction voltage potentials V of the two pairs 102, 104 of pn - junction structures J1 to J4 of the semiconductor device 100 J1 , V J2 .

[0137] More specifically, Figure 4a Shows a combination of the junction grading coefficients m1, m2, where the third - harmonic PH3 generated by the semiconductor device 100 (e.g., having pn - junction structures J1, J2 and J3, J4 with two pairs 102, 104) is zero or at least close to zero, where the zero - bias capacitance C J01 , C J02 The ratio of determines the shape ( = eccentricity) of the ellipse by determining the parameter a1 and the parameter a2, as indicated by the above equations 29 and 30. As described above, the parameter a i Corresponds to the radius r of the above equations (1) to (31) i , and corresponds to the radius r as Figures 4a to 4j Shown i , i.e., r i = a i . Other parameters that have an impact on the parameters a 1 , a 2 (such as the first junction voltage potential and the second junction voltage potentials V J1 , V J2 ) are set to equal values, for example, during the calculation of the curve (functional diagram) of Figure 4a .

[0138] Figure 4b Shows Figure 4a An enlarged view (view) of Figure 4a and Figure 4b It can be seen that all ellipses have intersection points for (1.) m1 = m2 = 0; (2.) m1 = m2 = 0.5; (3.) m1 = 0 and m2 = 0.5; and (4.) m1 = 0.5 and m2 = 0, i.e., m i ∈{0.00, 0.50}

[0139] Figure 4c Shows another graphical representation of the functional diagram that theoretically completely suppresses the third - harmonic generation PH3 of the semiconductor device 100. More specifically, Figure 4c Shows the grading coefficient m of the pn - junction structures J3, J4 of the second pair 104 for which the third - harmonic generation PH3 is completely suppressed 2 , as a function of the ratio C R = C J01 / C J02 of the first zero - bias capacitance and the second zero - bias capacitance. The grading system m of the pn - junction structures J1, J2 of the first pair 102 1is a parameter of this curve graph (functional graph). During Figure 4c the calculation of these curves, the first junction voltage potential and the second junction voltage potential V J1 、V J2 are set to equal values, where V R =V J01 / V J02 =1.

[0140] Figure 4d shows an enlarged view (view) of the graphical representation of Figure 4c .

[0141] Figure 4e shows the parameters a 1 、a 2 (radius r 1 、r 2 ) of an ellipse in which the third harmonic PH3 generation of the semiconductor device 100 is at least theoretically completely suppressed, as a function of the ratio C R C J01 / C J02 . During the calculation of these curves, the first junction voltage potential and the second junction voltage potential V J1 、V J2 are set to equal values, where V R =V J01 / V J02 =1.

[0142] The relatively large dependence of the first parameter a R C J01 / C J02 of the ellipse from the ratio of the first bias capacitance and the second bias capacitance reflects the increasing eccentricity of the ellipse as shown in 1 (first radius R 1 ) with respect to the increasing ratio C Figure 4a of the first zero-bias capacitance and the second zero-bias capacitance, where C R C R =C J01 / C J02 .

[0143] Figure 4f shows the influence of unequal values of the first junction voltage potential and the second junction voltage potential V J1 、V J2 , i.e., for V R =V J01 / V J02 ≠1, as the first junction grading coefficient and the second junction grading coefficient m 1 、m 2Graphical representation of the cancellation line of the third harmonic PH3 of the semiconductor device 100 of the function. More specifically, Figure 4f shows the first junction voltage potential and the second junction voltage potential V J1 , V J2 for unequal values of the grading coefficients m 1 , m 2 The combination of the grading coefficients m 1 , m 2 results in complete suppression of the third harmonic PH3 generation of the semiconductor device 100. In Figure 4f In the case of, the first zero-bias capacitance and the second zero-bias capacitance C J01 , C J02 are set to equal values, where C J01 = C J02 . The junction voltage potential V J2 of the pn junction structures J3, J4 of the second pair 104 is set to a fixed value V J2 = 0.8.

[0144] Figures 4g to 4j shows the corresponding power level PH3 of the third harmonic of the semiconductor device 100 as a function of the first and second junction grading coefficients m 1 , m 2 , as a result of a simulation using the method explained, for example, with reference to Figure 2 and Figure 3. Figures 4g to 4j Also shown in is the theoretical cancellation line (= the locus of the theoretical optimum suppression of the third harmonic PH3 for low input power levels P IN ). More specifically, Figures 4g to 4j shows the different input power levels P IN ( Figure 4g P IN = -10dBm; Figure 4h P IN = 0dBm; and Figure 4i P IN = +10dBm) of the fundamental frequency RF signal with equal first zero-bias junction capacitance and second zero-bias junction capacitance C J01 = C J02 of the semiconductor device 100 in simulation (e.g., using the above circuit simulation tool). The theoretically optimum locus of PH3 suppression derived above (also referred to herein as the cancellation line) is represented by the curve "A" ("gray" curve). At lower input power levels P IN , the minimum third harmonic PH3 of the circuit simulation and the theoretical derivation (curve "A") match very closely, where for increasing input power levels P IN, the deviation of the minimum third harmonic PH3 from circuit simulation and from the theoretical optimum suppression (curve “A”) becomes somewhat more significant, but remains flat up to 20 dBm for the input powers studied.

[0145] It should be noted that Figures 4g to 4j the irregular features of the contours in

[0146] and the appearance of even discontinuous contour regions near the cancellation lines in the contour plot are due to the algorithm used to generate the contour plot from the simulation dataset, in which the simulation data exists only for a finite number of simulation m1, m2 combinations located on a regular rectangular grid. Figure 4j The variation of the optimum junction grading coefficient with input power can also be seen, Figure 4j showing the simulated PH3 power levels as a function of the junction grading coefficient m IN for different input powers P 2 (-10 dBm, 0 dBm, 10 dBm, and 20 dBm). The junction grading coefficient m 1 is held fixed at m 1 = 0.25, where C J01 = C J02 is further set. And the power levels are normalized to the local maximum at m 1 = m 2 = 0.25 (reference case) for better comparison of the results. From this, it can be understood that the suppression of the generation of spurious third harmonics can be optimized for a desired predetermined input power level. For this purpose, it may also be possible to deviate purposefully from curve “A”, which is analytically derived for small input power levels P IN and arrange the pn junction structure with the corresponding junction grading coefficient, which is designed to suppress the generation of spurious third harmonics relative to the reference case of the ideal amount for a predetermined input level P IN used by the circuit simulation tool from the results of the above simulations.

[0147] In addition, depending on the desired suppression level, it may only be necessary to reproduce the optimum junction grading coefficient with a certain accuracy. For example, if the power level of the spurious third harmonics is to be suppressed by 10 dB relative to the reference case, a deviation of ±0.05 for the junction grading coefficient m 2 may be acceptable. To achieve a higher level of suppression, a smaller deviation of ±0.03 or even ±0.02 may be required. Similar considerations apply to the junction grading coefficient m 1 or generally m i .

[0148] The relationship between the simulated PH3 values and the optimum values (curve “A”) for unequal zero - bias capacitances CJ0,1 , C J0,2 is also valid, which results in an increased eccentricity of the ellipse, as described with respect to Figure 4a .

[0149] In the following, the mathematical derivation of the optimal C(V) parameters for suppressing third - harmonic generation is extended to the back - to - back connected pn - junction structures J1, J2 and J3, J4 and J5, J6 of three (n = 3) pairs 102, 104, 106, and further generalized to n pairs.

[0150] By using the same steps as described above, we can determine the conditions for eliminating third - harmonic generation for 3 pairs of back - to - back connected pn - junctions. In this case, the quadratic coefficients of the series expansion of the C(V) behavior are as follows:

[0151]

[0152] This can be further simplified to:

[0153]

[0154] This is an ellipsoid of three dimensions with the following general form:

[0155]

[0156] where the center point m 0,i = 1 / 4, where i ∈ {1, …, n} and the radius

[0157]

[0158] Generalization for n pn - junction pairs: All combinations of m laid on the following n - dimensional ellipsoid result in the elimination of the third - harmonic, where i ∈ {1, …, n} i

[0159]

[0160] where the radius ri of the ellipsoid (where i ∈ {1, …, n}) is defined as

[0161]

[0162] In the following, different aspects of the inventive concept of the semiconductor device 100, as derivable from the above evaluation, are described in detail, where the semiconductor device 100 has n (at least two) pairs 102, 104 (…) of back - to - back connected pn - junction structures J1, J2, J3, J4 (…) and these pn - junction structures have an adjusted junction grading coefficient m 1 -m n ​, for providing at least reduced or minimized generation of spurious odd harmonics, e.g., for a predetermined input power level P IN of the third harmonic.

[0163] As derivable from the above evaluation of the semiconductor device 100 having the back-to-back connection of n pairs 102, 104 (...) with an adjusted junction grading coefficient m 1 -m n of the pn-junction structures J1, J2 and J3, J4 (...), each of the first to n parameters "a 1 to a n " is based on n zero-bias capacitances C J0,1 to C J0,n and the n junction voltage potentials V J1 to V Jn .

[0164] As derivable from the above evaluation of the semiconductor device 100, the first to n parameters "a 1 to a n " comply with the following equations:

[0165]

[0166] Based on the above evaluation of the semiconductor device 100 and with reference to Figures 4g to 4j , the graphical representation of the simulation of the corresponding power level PH3 of the third harmonic of the semiconductor device 100 as a function of the first junction grading coefficient and the second junction grading coefficients m 1 , m 2 and the theoretical cancellation line is shown together with the above general derivation. The values of the first to "n" junction grading coefficients m 1 to m n can be adjusted to produce a third-order intercept point IP3 of at least 50 dBm, 55 dBm or even 60 dBm. For example, at an input power of 10 dBm, a third-order intercept point IP3 of 50 dBm corresponds to a PH3 power level of -70 dBm. Wherein, one of the junction grading coefficients, e.g., m 2 , can be adjusted to m 2 <0.50, preferably adjusted to m2 ≤ 0.48, which is advantageous from a manufacturing aspect, as described above.

[0167] According to an embodiment of the semiconductor device 100, at least two of the first to n junction grading coefficients m 1 to m n are different. More specifically, the "n" pairs of pn-junctions include at least a first pair 102 and a second pair 104, the first pair 102 having a first type of pn-junction with a grading coefficient m 1, the second pair 104 has a second type pn junction, and the second type pn junction has a grading coefficient m 2 .

[0168] According to an embodiment of the semiconductor device 100, for Cj01 = Cj02 and Vj1 = Vj2, the first type pn junction structures J1, J2 are arranged to include a first junction grading coefficient m 1 = 0.59 ± 0.03, and wherein the second type pn junction structures J3, J4 are arranged to have a second junction grading coefficient m 2 , where m 2 = 0.33 ± 0.10. The latter may represent a nearly linearly graded junction.

[0169] Based on the above evaluation for some embodiments of the semiconductor device 100, where i ∈ {1, 2}, the parameters a 1 and a 2 (= radius r 1 , r 2 ) comply with the following equations:

[0170] and

[0171]

[0172] According to another embodiment, the pn junction structures J1, J2 and J3, J4 of the first type / pair 102 and the second type / pair 104 are arranged to have zero-bias capacitances C J0-1 , C J0-2 in a ratio of:

[0173]

[0174] According to another embodiment, the pn junction structure of the i-th type forms an i-th type diode structure having an anode region and a cathode region. In addition, the semiconductor device 100 may include a first connection terminal 107 and a second connection terminal 108, wherein the "n" pairs 102, 104 (...) pn junction structures J1 to J4 are connected between the first terminal 107 and the second terminal 108.

[0175] According to another embodiment, “n” pairs 102, 104 (...) of pn - junction structures J1 to J4 (...) are arranged in a stacked configuration in a semiconductor substrate. According to another embodiment, different doped semiconductor regions of the pn - junction structures extend vertically into the semiconductor substrate with respect to the main surface region of the semiconductor substrate, and wherein a major part of the region of the metallurgical pn - junction is a planar pn - junction extending parallel to the main surface region of the semiconductor substrate. According to another embodiment, two pn - junction structures of the i - th pair can be arranged together in a stacked configuration in the semiconductor substrate. According to another embodiment, one pn - junction structure of the two pn - junction structures of the first pair can be arranged in a stacked configuration in the semiconductor substrate having one pn - junction structure of the two pn - junction structures of the second pair. According to another embodiment, the stacked configuration can include an npn structure having a floating - base region in the semiconductor substrate.

[0176] Figure 5aa and Figure 5ab FIG. shows a schematic cross - sectional view of a semiconductor device 100 according to an embodiment, the embodiment having, for example, four anti - series - connected pn - junction structures J1, J2, J3, J4 according to an embodiment (see, for example, Figure 1a ), wherein the first stack or pair 102 includes pn - junction structures J1, J2 of a first type (i = 1), and wherein the second stack or pair 104 includes pn - junction structures J3, J4 of a second type (i = 2).

[0177] As Figure 5aa and Figure 5ab shown, the semiconductor device 100 includes a semiconductor substrate 120. The semiconductor substrate 120 has a first main - surface portion 120a and a second main - surface portion 120b on opposite main sides of the semiconductor substrate 120.

[0178] The following exemplary description of the different layers and regions of the semiconductor substrate 120 extends substantially from the second main - surface portion 120b of the semiconductor substrate 120 to the first main - surface portion 120. The different regions and structures in the semiconductor substrate 120 can be manufactured, for example, during a so - called front - end - of - the - line (FEOL) process stage.

[0179] The semiconductor substrate 120 can include a low - ohmic n - type substrate 120 - 1. A p - type semiconductor layer 120 - 2 is arranged on the n - type substrate 120 - 1. The p - type semiconductor layer 120 - 2 (e.g., a p - epitaxial layer 120 - 2) can be applied epitaxially on the n - type substrate 120 - 1. The p - type semiconductor layer 120 - 2 includes a buried p - type semiconductor layer 120 - 3 (p - buried layer 120 - 3). The buried p - type semiconductor layer 120 - 3 can be formed, for example, in the form of a blanket (maskless) implantation of p - type dopants in the semiconductor layer 120 - 2.

[0180] Another p-type layer 120-4 (e.g., p-epitaxial layer 120-4) is disposed on the p-type layer 120-2 having a buried p-type layer 120-3. The p-type semiconductor layer 120-4 may be applied epitaxially on the p-type layer 120-2. Alternatively, the layer 120-4 may also be implemented by an i-type (i.e., intrinsic or unintentionally doped) layer.

[0181] In the second epitaxial layer 120-4, a p-type well region 120-5 (p-well 120-5) may be disposed. The p-type well region 120-5 may be formed after performing LOCOS oxidation on the main surface region 120a of the p-type layer 120-4 of the semiconductor substrate 120 and by performing a blanket implantation step. Based on this method, a photoresist mask is not required on the surface region 120a of the p-type layer 120-4, but due to the LOCOS oxidation on the surface 120a, a self-aligned implantation process can be performed. The LOCOS process (LOCOS = local oxidation of silicon) is a microfabrication process in which silicon dioxide is formed in selected regions on a silicon wafer (i.e., semiconductor substrate 120), and the silicon wafer has a Si-SiO 2 interface at a point or plane lower than the rest of the silicon body surface region 120a. Of course, the p-well 102-5 may also be formed by using lithography methods well known in the art.

[0182] As Figure 5aa and Figure 5ab shown, pn junction structures J1, J3 and pn junction structures J2, J4 may be disposed in separate semiconductor regions 122, 124 of the semiconductor substrate 120, where the separate regions 122, 124 may be realized by means of so-called deep isolation trenches 130 that laterally confine and / or laterally surround the semiconductor regions 122, 124 having the pn junction structures J1, J3 and J2, J4. The deep isolation trenches 130 may be formed in the semiconductor substrate 120, for example, by means of an RIE process step (RIE = reactive ion etching), and the realized trenches may be lined with an oxide material 134 such as SiO 2 liner by means of a trench liner oxidation process, and filled with a semiconductor material 132 (e.g., polysilicon).

[0183] The semiconductor device 100 further includes a highly doped n-type contact region 120-7 in the form of an implantation region adjacent to the surface region of the p-type well 120-5. In some embodiments, the n-type contact region 120-7 may also be simply regarded as a shallow n-region 120-7 or an emitter region. The n-type contact region 120-7 may be formed by means of an n-contact implantation process step (e.g., by means of blanket implantation), which may be self-aligned by means of the (above-described) LOCOS process, such that a photoresist mask is not required.

[0184] As a further (e.g., final) process step of the front-end process for processing the semiconductor substrate 120, an oxide material 128 can be deposited on the first major surface region 120a of the semiconductor substrate 120. The semiconductor device 100 can also include a contact and metallization layer stack 140 (BEOL stack, BEOL = back-end-of-line) on the first major surface region 120a of the semiconductor substrate 120 for providing interconnects 110 (e.g., contact plugs or vias) and interconnect layers 107, 108 for the (multiple) semiconductor devices 100 and optionally another circuit element in the semiconductor substrate 120 (not shown in Figure 5aa and Figure 5ab . The contact structures and (structured) metallization layers of the metallization stack 140 can be formed by means of BEOL process steps. Finally, if multiple semiconductor devices 100 are fabricated in the semiconductor substrate 120 (such as a semiconductor wafer 120), the semiconductor devices 100 can be packaged and separated (diced). For example, a chip-level packaging process includes, for example, forming electrodes (or pads) as the top layer of the metallization stack 140 and a dicing process.

[0185] As Figure 5aa and Figure 5ab shown, the n-type contact region 120-7 (= cathode region) and the p-type well region 120-5 (= anode region) form first-type pn junction structures J1 and J2 in different semiconductor substrate regions 122 and 124, respectively. In addition, the buried p-type layer 120-3 (= anode region) and the n-type substrate 121 (= cathode region) form second-type pn junction structures J3 and J4 in separate semiconductor regions 122, 124 of the semiconductor substrate 120, respectively.

[0186] Figure 5b Shows Figure 5aa and Figure 5ab a schematic calculation diagram of an exemplary doping profile of the semiconductor device 100, where different doping concentrations in the p-type well 120-5 can be achieved by different implantation doses, which are indicated by "36" to "42". Figure 5b The curve of Figure 5aa and Figure 5ab also contains exemplary indications of the approximate extent of different layers and / or regions of the semiconductor substrate 120. The metallurgical junction between the n-type region 120-7 and the p-type region 120-5 falls within the falling slope of the p-type implantation profile of the region 120-5. In the case of a sufficiently steep slope of the n-type implantation in the n-type region 120-7, the C(V) properties of the pn junction formed by the regions 120-5 and 120-7 can exhibit hyperabrupt characteristics and thus can have a grading coefficient > 0.5.

[0187] Figure 6ashows a schematic cross-sectional view of semiconductor device 100 along a cut line A-B-C-D in a schematic top view of semiconductor device 100 passing through Figure 6b According to an embodiment, semiconductor device 100 has, for example, four pn junction structures J1, J2, J3, J4 connected in inverse series (see, for example, Figure 1a ). The pn junction structures J1, J3 (vertical device 1) may include a first npn structure having a first floating base region in semiconductor substrate 120, where the pn junction structures J2, J4 include a second npn structure having a second floating base region in semiconductor substrate 120. The floating base regions are respectively formed by p-type portions (e.g., by p-type regions 120-2 to 120-5) between n-type substrate 120 and n-type contact region 120-7.

[0188] As discussed with respect to Figures 5aa - 5b , for the first pair and the second pair 102, 104 of pn junction structures J1, J2 and J3, J4 connected in inverse series, the first type pn junction structures J1 and J2 may have (substantially) the same layout and doping profile and have a grading coefficient m 1 , where the second type pn junction structures J3 and J4 may also have (substantially) the same layout and doping profile and have a second junction grading coefficient m 2 .

[0189] According to an embodiment, for example, the semiconductor device forms a discrete ESD device (ESD = electrostatic discharge) having a TVS function.

[0190] According to other embodiments, semiconductor device 100 may have n (at least two) pairs of pn junction structures 102, 104 connected in inverse series having adjusted junction grading coefficients m 1 , m 2 …m n , where (at least) one pair of pn junction structures among the n pairs 102, 104 (…) of pn junction structures J1 to J4 (…) includes a “compound” diode structure to adjust and obtain a desired behavior with respect to the breakdown voltage of device 100 and to provide at least reduced or minimized generation of spurious odd harmonics (e.g., third harmonic). For example, device 100 may be used in a TVS (transient voltage suppressor) device.

[0191] Figure 7a shows a schematic view of semiconductor device 100 having n = 2 pairs 102, 104 of pn junction structures connected in inverse series, where (at least) one pair 102 of the pn junction structures of at least two pairs 102, 104 is arranged to have a junction type described herein as a compound pn junction structure (compound diode structure), and will be described in detail below with reference to Figure 7b .

[0192] Figure 7b Only the first pair 102 of the semiconductor device 100 shown in Figure 7a is shown. The first pair 102 is formed as a pair of two compound pn-junction structures 102-1 and 102-2. The first compound pn-junction structure 102-1 includes a first partial pn-junction structure J 11 and a second partial pn-junction structure J 12 , and the second compound pn-junction structure 102-2 includes a first partial pn-junction structure J 21 and a second partial pn-junction structure J 22 . That is to say, Figure 7a and 7b the first pair 102 is formed by a pair of compound pn-junction structures 102-1 and 102-2 connected in anti-series, and each of these compound pn-junction structures 102-1 and 102-2 has a first partial pn-junction structure J 11 , J 21 and a second partial pn-junction structure J 12 , J 22 in parallel connection. The first partial pn-junction structures J11 and J21 have a first partial junction grading coefficient m 11 , a first partial junction voltage potential V J11 and a first partial zero-bias capacitance C J011 , where the second partial pn-junction structures J 12 , J 22 have a second partial junction grading coefficient m 12 , a second partial junction voltage potential V J12 and a second partial zero-bias capacitance C J012 , where, for example, the second partial junction grading coefficient m 12 , the second partial junction voltage potential V J12 and the second partial zero-bias capacitance C J012 can be different from the first partial junction grading coefficient m 11 , the first partial junction voltage potential V J11 and the first partial zero-bias capacitance C J011 . Based on the combination of the first partial junction grading coefficient and the second partial junction grading coefficients m 11 , m 12 , the first effective junction grading coefficient m 1 of the corresponding compound pn-junction structures 102-1 and 102-2 is generated. That is to say, the compound pn-junction structures 102-1 and 102-2 behave as a pn-junction structure having an effective junction grading coefficient m 1 , an effective junction potential V J1 and an effective zero-bias junction capacitance C J01 . This effective behavior of the compound pn-junction structure as a simple pn-junction structure is in Figure 7bthrough the correspondence of the composite pn junction structure 102-1 with the pn junction structure J 1 and the correspondence of the composite pn junction structure 102-2 with the pn junction structure J 2 is indicated. Accordingly, in many cases, the voltage-dependent capacitance characteristics of the composite pn junction structure can be satisfactorily described or modeled by the above expression A1, taking m i as the effective (combined) junction grading coefficient and for the junction potential V Ji and the zero-bias junction capacitance C J0i similarly.

[0193] In other words, according to an embodiment, the semiconductor device 100 as shown in Figure 7a and Figure 7b includes a first parallel circuit 102-1 of a first part pn junction structure J 11 and a second part pn junction structure J 12 , and a second parallel circuit 102-2 of a first part pn junction structure J 21 and a second part pn junction structure J 22 , wherein the first parallel circuit and the second parallel circuit 102-1, 102-2 are anti-series connected. As shown in Figure 7a , the anti-series connected first parallel circuit and second parallel circuit 102-1, 102-2 form a first pair 102 of pn junction structures J1, J2 that are series connected to a second pair 104 of pn junction structures J3, J4.

[0194] That is to say, according to an embodiment of the semiconductor device 100, at least one pair 102 of n pairs 102, 104 (...) of pn junction structures J1 to J4 (...) can be arranged to form a composite pn junction structure 102 as shown in Figure 7b having a first part pn junction structure J 11 , J 21 and a second part pn junction structure J 12 , J 22 connected in parallel, wherein the first part pn junction structure J 11 , J 21 has a first part junction grading coefficient m 11 , and wherein the second part pn junction structure J 12 , J 22 has a second part junction grading coefficient m 12 , and the second part junction grading coefficient m 12 can be different from the first part junction grading coefficient m 11 in some embodiments. The resulting effective junction grading coefficient m 1 of the composite pn junction structure 120 is based on the first part junction grading coefficient and the second part junction grading coefficients m 11 , m 12combination

[0195] To provide another interpretation of the present concept in the form of the described implementations and embodiments of the semiconductor device 100 according to Figure 7a and 7b the following discussion regarding Figures 8a to 8c involves an exemplary technical analysis in the field of semiconductor devices, for example, in the fields of discrete ESD protection devices and TVS devices regarding the present applicant and the resulting technical findings and conclusions, respectively.

[0196] As Figure 7a shown, a semiconductor device 100 having a first pair (102) and a second pair (104) of pn - junction structures with a grading coefficient m 1 、m 2 can be implemented with a high degree of freedom. In particular, a pn - junction structure with a tuned breakdown voltage having a grading coefficient m≥0.5 can be implemented as a composite pn - junction structure and used for the semiconductor device 100 in some embodiments.

[0197] In conventional semiconductor technology, it is difficult to implement a hyper - abrupt junction with a low breakdown voltage below 25V or even below 16V or 12V and a controllable grading coefficient m≥0.5. Some embodiments provide a semiconductor device 100 having the desired properties, namely both a low breakdown voltage and an adjustable gradient coefficient of at least 0.5. This is due to the fact that the conventionally used processing steps in semiconductor technology (such as implantation and diffusion) result in a dopant distribution that shows some grading in a narrow region around the metallurgical junction. The space - charge region that determines the capacitance versus voltage behavior and the breakdown voltage of the pn - junction extends around the metallurgical junction. In the case of a low breakdown voltage, the doping concentration is high and the extension of the space - charge region is small. As the breakdown voltage increases, the doping concentration on one or both sides of the metallurgical junction decreases and the width of the space - charge region increases. Due to the inevitable grading near the metallurgical junction, a low - voltage breakdown junction will see a more or less graded distribution in practice rather than the desired abrupt or hyper - abrupt doping distribution. Therefore, it is difficult to achieve the combination of a low breakdown voltage and a grading coefficient m≥5 using semiconductor processes conventionally used in the mass production of semiconductor devices and circuits.

[0198] In summary, a higher doping level results in a less extended space - charge region (= depletion region) and thus a (lower) breakdown voltage V bd . Additionally, the resulting more linear graded - junction behavior results in a (smaller) gradient coefficient m.

[0199] (Relatively) high grading coefficient m≥0.5 requires a more (or super) abrupt doping profile. In the case of a lower doping level on one side of the metallurgical junction, the depletion layer will extend further into this lower doped region. Thus, the depletion layer is not limited to a narrow region around the metallurgical junction, as in the case of higher doping levels where the doping profile is typically shown as more or less linear grading. Since the depletion region extends beyond this grading region near the metallurgical junction in the case of lower doping levels, the C(V) characteristics of the lower doped junction can be more easily adapted to a grading coefficient m≥0.5. At the same time, the (relatively) low doping level results in a higher breakdown voltage V bd .

[0200] Therefore, it is difficult to achieve a combination of a low breakdown voltage and a grading coefficient m≥0.5 using conventional techniques.

[0201] To overcome this limitation, as Figure 7a and Figure 7b shown in the embodiments introduce the concept of obtaining a junction (pn junction structure) with desired properties (i.e., both a predetermined low breakdown voltage of not more than 25V and a predetermined grading coefficient equal to or higher than 0.5) by subdividing the junction into two regions, i.e., together subdividing the composite pn junction structure into partial pn junction structures. These two regions are:[[]]

[0202] (1) One active region with a higher well implantation dose, which results in a part of the pn junctions J 11 、J 21 having a low predetermined breakdown voltage and a grading coefficient m 11 <0.5, and

[0203] (2) Another active region with a lower well implantation dose, which results in a part of the pn junctions J 12 、J 22 having a breakdown voltage higher than the predetermined breakdown voltage and a grading coefficient m 12 >0.5.

[0205] The overall behavior of the composite pn junctions 102-1 and 102-2 shows respectively the breakdown voltage determined by the higher well doping and the capacitance with respect to the voltage characteristics' grading coefficient determined by the parallel connection in two branches of the first partial pn junction structure and the second partial pn junction structures J 11 、J 12 and J 21 、J 22 .

[0206] By adjusting (1) the first partial pn junction structure and the second partial pn junction structures J 11 、J 12 and J 21 、J 22The slow-varying coefficient m in the two regions 11 、m 12 (by well implantation dose and energy and by further diffusion steps) and by adjusting (2) the first partial pn junction structure and the second partial pn junction structure with different well implantations J 11 , J 12 and J 21 , J 22 The area ratio of the two regions is the effective ramp coefficient m of the composite junction structures 102-1 and 102-2. 1 can be adjusted to a target value close to a value that minimizes the generation of the third harmonic (h3). In some embodiments, for the pair 102 of composite junctions 102-1 and 102-2, J 11 and J 21 The zero bias capacitance (C J0 )(and respectively J 12 and J 22 ) can be arranged to be equal from the angle of forming a symmetrical device 100 to also suppress the generation of even (eg, second) harmonics. Similar considerations apply to the partial pn junction structure J 11 and J 21 (and respectively J 12 and J 22 ) junction voltage potential (V J0 ) and the area ratio of the partial pn junctions in each of the composite structures 102-1 and 102-2 forming the pair of composite pn junction structures 102. In the above concept, a pair of composite pn junctions 102-1 and 102-2 is realized, in which both the breakdown voltage and the net gradation coefficient can be controlled in a much larger parameter range through technical and physical design or layout adjustment.

[0207] Figure 8a The resulting junction grading coefficient m as a function of doping concentration for different implant doses is shown. 1 More specifically, for the region including regions 120-7 and 120-5 (see Figure 5aa and Figure 5ab 5 (described in more detail above), in Figure 8a The simulated capacitance-to-voltage characteristics of the pn junction between the highly n-doped shallow contact region and the p-doped well region are shown in FIG. 3 , where equal numbers (36-42) represent the corresponding doping profiles. It can be seen from the figure that m>0.5 can be obtained in the case of a low implantation dose for the p-well hyperabrupt junction.

[0208] Figure 8b Shown based on Figure 8a and Figure 5bSchematic simulation of the breakdown voltage generated as a function of doping concentration for different implant doses and doping profiles indicated by the same numbers in FIG. However, as mentioned above, the breakdown voltage of the junction with the lowest p-well dose and the highest grading coefficient tends to have a high breakdown voltage, such as Figure 8b In the case of this simulation example it can be seen that if the ramp coefficient for the minimum third harmonic generation is between 0.5 and 0.6, the junction will have a breakdown voltage of 40V or more without using a composite pn junction structure as explained above.

[0209] Figure 8c shows the partial junction ramp coefficient (J) based on two adjustments 11 or J 21 )m 11 and (J 12 or J 22 )m 12 , as the first partial pn junction structure and the second partial pn junction structure J of the composite pn junction structure 102-1 (102-2). 11 and J 12 (or J 21 and J 22 The combined junction grading coefficient m of the composite pn junction structure 102-1 (or 102-2) generated as a function of the area ratio between the active regions ) 1 In this case, the doping profiles of the first partial pn junction structure and the second partial pn junction structure correspond to Figure 5b 37 and 41 shown in (see also Figure 8a and Figure 8b As discussed above, the breakdown voltage of the junction with the lowest p-well dose and the highest grading coefficient tends to have a high breakdown voltage, such as Figure 8b The relative area contribution can be easily controlled by the physical design (layout) of the device.

[0210] More generally, the composite junction 102-1 described above can be described as being arranged as a type i pn junction structure 120-i. Thus, according to an embodiment, the first partial pn junction structure is arranged to have a first partial junction grading coefficient m i1 >0.5, and wherein the second part pn junction structure is arranged to have a second part junction grading coefficient m i2 <m i1 , for example m i1 Can be between 0.30 and 0.5.

[0211] According to an embodiment, the first partial pn junction structure and the second partial pn junction structure J 11 , J 21 and J 12 , J 22Disposed in a semiconductor substrate, wherein the combination depends proportionally on a first partial pn - junction structure and a second partial pn - junction structure J of a composite pn - junction structure 102 - 1 parallel to a first main - surface region of the semiconductor substrate 11 and J 12 of the active region and the area ratio between a first partial pn - junction structure and a second partial pn - junction structure J of a composite pn - junction structure 102 - 2 21 and J 22 According to an embodiment, the first partial pn - junction structure J of the first composite pn - junction structure 102 - 1 11 and the second partial pn - junction structure J 12 and the first partial pn - junction structure J of the second composite pn - junction structure 102 - 2 21 and the second partial pn - junction structure J 22 can be disposed together in a laterally isolated common region of the semiconductor substrate. According to an embodiment, the first partial pn - junction structure and the second partial pn - junction structure extend perpendicularly into the semiconductor substrate in a depth direction with respect to the first main - surface region of the semiconductor substrate.

[0212] Figure 9a and Figure 9d show schematic cross - sectional views of other exemplary implementations of a semiconductor device 100 including a pair of composite pn - junction structures. Figure 9b shows and is also in Figure 5b shown and now used for Figure 9a schematic simulation diagrams of different exemplary doping profiles of the semiconductor device. Figure 9c shows a schematic top - view of a semiconductor device through a composite - type pn - junction structure in a plane through Figure 9a for example, showing the "active" regions of a first partial anode region 120 - 5 and a second partial anode region 120 - 6 of a composite pn - junction structure J 1 and J 2 of the first and second parts.

[0213] In the drawings and the description, the same elements and elements having the same function and / or the same technical or physical effect have the same reference numerals or are identified by the same name. Thus, in Figure 9a and 9d the following description of the embodiments of the semiconductor device 100, when compared with the embodiments of the semiconductor device 100 in, for example Figures 5aa - 5b and Figures 6a - 6b the main focus is on the corresponding differences and adaptations between different implementations of the semiconductor device 100.

[0214] Figure 9a and 9dShows different schematic cross-sectional views of a semiconductor device 100 according to an embodiment having, for example, two pairs of pn-junction structures J1, J2 (= first pair 102) and J3, J4 (= second pair 104) connected in anti-series, wherein the first pair 102 includes composite pn-junction structures 102-1, 102-2, and wherein the second pair 104 includes pn-junction structures J3, J4 (see, for example, Figure 7a ), to adjust and obtain, for example, the desired TVS behavior (TVS = transient voltage suppressor) of the semiconductor device 100 with respect to its breakdown voltage and junction grading coefficient.

[0215] The first composite pn-junction structure 102-1 includes a first partial pn-junction structure J 11 having a first partial junction grading coefficient m 11 and a second partial pn-junction structure J 12 having a second partial junction grading coefficient m 12 . The second composite pn-junction structure 102-2 includes a third partial pn-junction structure J 11 also having a partial junction grading coefficient m 21 (likewise a structure substantially equal to J J0 with respect to the zero-bias capacitance C J0 and the junction potential V 11 ), and a partial pn-junction structure J 12 having a partial junction grading coefficient m 22 (likewise a structure substantially equal to J J0 with respect to the zero-bias capacitance C J0 and the junction potential V 12 ). The resulting junction grading coefficient m 1 of the first composite pn-junction structure and the second composite pn-junction structure 102-1, 102-2 is based on the combination of the first partial junction grading coefficient and the second partial junction grading coefficients m 11 , m 12 .

[0216] As Figure 9a shown, the first composite pn-junction structure 102-1 can be implemented by using two different implantation regions 120-5, 120-6 in the substrate region 122. Thus, the n-type contact region 120-7 in the substrate region 122 is embedded in the adjacent implantation regions 120-5, 120-6. The second composite pn-junction structure 102-2 can be implemented by using two different implantation regions 120-5, 120-6 in the substrate region 124. Thus, the additional n-type contact region 120-7 in the substrate region 124 is embedded in the additional adjacent implantation regions 120-5, 120-6.

[0217] As Figure 9a shown, the partial pn-junction structure J 11, J 12 can be arranged in the semiconductor region 122 of the semiconductor substrate 120 (as an adjacent partial pn-junction structure J 11 , J 12 ), where the partial pn-junction structure J 21 , J 22 can be arranged in another semiconductor region 124 of the semiconductor substrate 120 (as an adjacent partial pn-junction structure J 21 , J 22 ). The separated regions 122, 124 can be realized by means of so-called deep isolation trenches 130, which laterally limit and / or laterally surround the semiconductor regions 122, 124. Furthermore, a buried p-type layer 120-3 (= anode region) and a low-ohmic n-type substrate 121 (= cathode region) form second-type pn-junction structures J 3 and J 4 in the separated semiconductor regions 122, 124 of the semiconductor substrate 120, respectively.

[0218] Figure 9b Shows a schematic simulation diagram of different exemplary doping distributions for the semiconductor device 100 for Figure 9a . Different doping concentrations of the implantation regions 120-5, 120-6 in the p-type layer 120-4 can be achieved by using different implantation doses, and the different implantation doses are indicated by "36" to "42" in Figure 9b . The figure also contains an indication of the approximate extension of the different layers and / or regions of the semiconductor substrate 120. As Figure 9a shown, the first composite pn-junction structure 102-1 having a first partial pn-junction and a second partial pn-junction (diode) structure J11, J12 includes two p-type well regions 120-5, 120-6. The doping concentration distribution (A) of the p-well 120-5 results in, for example, a first partial junction grading coefficient m 11 . The doping concentration distribution (B) of the p-well 120-6, which can be lower than the doping concentration (A) of the p-well 120-5, results in a second partial junction grading coefficient m 12 , for example, where m 12 > m 11 . Based on the first partial junction grading coefficient and the second partial junction grading coefficients m 11 , m 12 , an effective net grading coefficient m 1 of the composite junction 102-1 can be achieved.

[0219] Due to the higher doping level resulting in a less extended space charge region (= depletion region), and thus resulting in a (lower) breakdown voltage V bd, the resulting more linear graded junction behavior leads to a (smaller) gradient coefficient m. A (higher) grading coefficient m requires a more (or super) abrupt doping profile. However, there are practical difficulties in creating an "ideal" abrupt profile. Thus, in order to form a pn junction structure with a grading coefficient m ≥ 0.50, a (wider) space charge region with a (lower) doping level may be necessary. The (lower) doping level results in a (higher) breakdown voltage V bd .

[0220] The above evaluation of the schematic simulation diagrams for different exemplary doping profiles correspondingly applies to the second composite pn junction structure 102-2 of the first pair of pn junction structures 102 and the resulting effective net grading coefficient m 1 .

[0221] Figure 9c shows Figure 9a A schematic top view of a possible layout of the semiconductor device 100, which shows the extension of the "active" regions of the first part anode region 120-5 (with a higher p-well doping injection) and the second part anode region 120-6 (with a lower p-well doping injection) of the composite type pn junction structures 102-1 and 102-2. An exemplary area ratio is 40% for the first part anode region 120-5 and 60% for the second part anode region 120-6.

[0222] By optimizing the layout, the ratio of the areas defined by the lower and higher dopant concentrations in the p-well regions 120-6, 120-5 can be adjusted to achieve a target (optimal) value of the junction grading coefficient m 1 > 0.5, for example m 1 ~ 0.55 while maintaining a breakdown voltage of no more than 25V.

[0223] As Figure 9d shown, the first pair of partial pn junction structures J 11 、J 12 can be arranged in the semiconductor region 122 of the semiconductor substrate 120, where the second pair of partial pn junction structures J 21 、J 22 can be arranged in another semiconductor region 124 of the semiconductor substrate 120. The separated regions 122, 124 can be realized by means of so-called deep isolation trenches 130, which laterally confine and / or laterally surround the semiconductor regions 122, 124.

[0224] As Figure 9dAs shown, a p-well region 120-5 (p-well 120-5) is disposed in the second epitaxial p-type layer 120-4 in the semiconductor regions 122 and 124, where the p-well 120-5 only partially surrounds a highly doped n-type contact region 120-7 in the p-type layer 120-4 of the semiconductor substrate 120. Thus, in the semiconductor region 122, the highly doped n-type contact region 120-7 and the second epitaxial p-type layer 120-4 form a first partial pn junction structure J 11 , where the p-well region 120-5 and the highly doped n-type contact region 120-7 form a second partial pn junction structure J 12 (as adjacent partial pn junction structures J 11 , J 12 ). Thus, in the semiconductor region 124, the highly doped n-type contact region 120-7 and the second epitaxial p-type layer 120-4 form a third partial pn junction structure J 21 , where the p-well region 120-5 and the highly doped n-type contact region 120-7 form a fourth partial pn junction structure J 22 (as adjacent partial pn junction structures J 21 , J 22 ). Thus, the first partial pn junction structure and the third partial pn junction structures J 12 , J 21 do not include, for example, a p-well region. As described above, the layer 120-4 can also be implemented by an i-type (i.e., intrinsic or unintentionally doped) layer.

[0225] Alternatively, the doping profile in the layer 120-4 can be adjusted by gradually adjusting the doping level during the epitaxial growth of the layer 120-4 to obtain a predetermined grading coefficient m 11 and J 21 in the partial pn junction structures J 12 . In other words, by controlling the gas flow of the dopant source gas during the epitaxial layer growth, a depth dependence of the doping level can be created in the epitaxial layer, and hyperabrupt junction behavior can be achieved in the partial pn junctions J 11 and J 21 .

[0226] In addition, the buried p-type layer 120-3 (= anode region) and the n-type substrate 121 (= cathode region) form second type pn junction structures J 3 and J 4 in the separated semiconductor regions 122, 124 of the semiconductor substrate 120, respectively.

[0227] The p-well region 120-5 (p-well 120-5) can be disposed in the second epitaxial p-type layer 120-4 by forming a desired doping profile (e.g., during epitaxial growth or by performing an implantation step) in the p-type semiconductor layer 120-4.

[0228] Figure 9e Shows the configuration of a composite pn junction structure 102-1 according to another embodiment. The composite pn junction structure 102-1 includes a pn junction between an n+ region 120-7 and a p-well region 120-5 and another adjacent voltage-dependent capacitance, which in this embodiment can be formed by an inversion charge layer 120-8 at the interface 135 between an oxide layer of a semiconductor material and a bulk or epitaxial layer 120-4. For example, the bulk semiconductor material or epitaxial layer 120-4 can be p-doped or intrinsic (i.e., unintentionally doped). One electrode (corresponding to the cathode) of the voltage-dependent capacitance is formed by the inversion charge layer 120-8, which is caused by the presence of fixed oxide charges 136 at or near the semiconductor / oxide interface 135. Immediately adjacent to the inversion charge layer 120-8, as indicated by the depletion region 120-9 in Figure 9e , the volume of the semiconductor material is depleted of mobile charges, and the undepleted semiconductor material below the depletion region forms the other electrode (corresponding to the anode) of the voltage-dependent capacitance. In Figure 9e , the depletion region is indicated by a dashed line 137 that schematically represents the boundary of the depletion layer.

[0229] In some embodiments, the doping profile of the p-well 120-5 near the edge and the semiconductor / oxide interface 135 is adjusted such that an inversion charge layer 120-8 also exists in this region, and an electrical connection is established between the n+ region 120-7 and the surrounding inversion charge layer 120-8.

[0230] The characteristics of the voltage-dependent capacitance formed by the electron inversion charge layer 120-8 can be modeled according to the above formula (A1), which defines the grading coefficient, zero-bias capacitance, and junction potential that are also used for such a voltage-dependent capacitance. In this regard, the voltage-dependent capacitance formed due to the presence of the inversion charge layer 120-8 as described above is also considered to be a partial pn junction structure J in the context of the composite pn junction structures 102-1, 102-2 11 , J 12 / J 21 , J 22 .

[0231] The effective grading coefficient of the composite pn junction structure 102-1 according to this embodiment is a combination of the grading coefficient of the pn junction and the grading coefficient of the voltage-dependent capacitance formed due to the presence of the electron inversion charge layer 120-8. The relative contributions of the two grading coefficients can be adjusted by (1) defining the doping profiles of the respective regions of the pn junction and the voltage-dependent capacitance 120-8, and (2) the relative areas of the pn junction and the voltage-dependent capacitance 120-8.

[0232] The voltage-dependent capacitor 120-8 can be surrounded by a channel stop region 120-10 that prevents regions outside the intended region for forming the voltage-dependent capacitor 120-8 from contributing to the voltage-dependent capacitor.

[0233] The breakdown voltage V of this structure bd is determined by the pn junction structure between the n+ region and the P-well region.

[0234] Figure 9f Another embodiment of the composite pn junction structure is shown. Figure 9e The voltage-dependent capacitor of the embodiment shown in Figure 9f is further extended in Figure 9e by an inversion layer 120-8 formed on the vertical sidewalls of the deep isolation trench structure 130. Other details are similar to those described with respect to

[0235] Aspects of the present invention may also include a method of manufacturing a semiconductor device that includes at least a first pair of pn junction structures of a first type and a second pair of pn junction structures of a second type. The method may include a design step of determining a first grading coefficient for the pn junction structures of the first type and a second grading coefficient for the pn junction structures of the second type, where the first grading coefficient is different from the second grading coefficient, and at least one of the first grading coefficient and the second grading coefficient is less than 0.50, where the grading coefficients are determined to suppress spurious third harmonics generated by the semiconductor device.

[0236] Exemplary embodiments may provide a semiconductor device including:

[0237] “n” pairs of pn junction structures, where n is an integer ≥ 2, where the i-th pair includes two pn junction structures of the i-th type, where i ∈ {1,…,n}, and where the two pn junction structures of the i-th type are anti-series connected,

[0238] where the pn junction structures of the i-th type are arranged to have an i-th junction grading coefficient m i .

[0239] where at least the first pair of the n pairs of pn junction structures is arranged to have a first junction grading coefficient m 1 , where and m 1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction grading coefficient m 2 , where

[0240] and

[0241] where the junction grading coefficients m of the first and second pairs of the n pairs of pn junction structures1 , m 2 is adjusted to cause generation of a spurious third - harmonic signal having a signal power level (PH3) that is at least 10 dB lower than a reference signal power level (PH3) of a spurious third - harmonic signal obtained for a reference case, where in the reference case, a first junction grading coefficient and a second junction grading coefficient m 1 , m 2 is 0.25.

[0242] According to an exemplary embodiment, the first through nth junction grading coefficients m 1 through m n conform to the following elliptical equation within a tolerance of ±0.05:

[0243] with

[0244] where the parameter a i is determined based on a zero - bias capacitance C J0i of the ith type of pn - junction structure and a junction voltage potential V Ji .

[0245] Another exemplary embodiment may provide a semiconductor device, comprising:

[0246] “n” pairs of pn - junction structures, where n is an integer ≥2, where the ith pair includes two pn - junction structures of the ith type, where i ∈ {1, …, n}, and where the two pn - junction structures of the ith type are anti - serially connected,

[0247] where the pn - junction structure of the ith type is arranged to have an ith junction grading coefficient m i

[0248] where the first through nth junction grading coefficients m 1 through m n conform to the following elliptical equation within a tolerance of ±0.05:

[0249] with

[0250] where at least a first pair of the n pairs of pn - junction structures is arranged to have a first junction grading coefficient m 1 , where and m 1 <0.50, and a second pair of the n pairs of pn - junction structures is arranged to have a second junction grading coefficient m 2 , where

[0251] where the parameter a iis the zero - bias capacitance C based on the pn - junction structure of the i - th type J0i and the junction voltage potential V Ji to be determined.

[0252] According to an exemplary embodiment, the first pair of the n pairs of pn - junction structures is arranged to have the first junction grading coefficient m 1 , where m 1 ≤0.48.

[0253] According to an exemplary embodiment, the second pair of the n pairs of pn - junction structures is arranged to have the second junction grading coefficient m 2 where m 2 >0.50.

[0254] According to an exemplary embodiment, each of the first to n - th parameters “a 1 to a n ” is based on n zero - bias capacitances C J0,1 -C J0,ni and based on n junction voltage potentials V J1 -V Jn to be determined.

[0255] According to an exemplary embodiment, the first to n - th parameters “a 1 to a n ” satisfy the following equation:

[0256]

[0257] According to an exemplary embodiment, the values of the first to “n - th” junction grading coefficients m 1 to m n are adjusted to produce a third - order intercept point IP3 of at least 50 dBm.

[0258] According to an exemplary embodiment, at least two of the first to n - th junction grading coefficients m 1 to m n are different.

[0259] According to an exemplary embodiment, for n = 2 and C j01 =C j02 , the first - type pn - junction structure is arranged to have a first junction grading coefficient m between 0.56 and 0.62 1 , and wherein the second - type pn - junction structure is arranged to have a second junction grading coefficient m between 0.23 and 0.43 2 .

[0260] According to an exemplary embodiment, for n = 2, the first - type and second - type pn - junction structures are arranged to have zero - bias capacitances C J0-1 , CJ0-2 Ratio:

[0261]

[0262] According to an exemplary embodiment, a pn - junction structure of the i - th type forms an i - th type diode structure having an anode region and a cathode region.

[0263] According to an exemplary embodiment, the semiconductor device may further include a first connection terminal and a second connection terminal, wherein "n" pairs of pn - junction structures are connected between the first terminal and the second terminal.

[0264] According to an exemplary embodiment, "n" pairs of pn - junction structures are arranged in a stacked configuration in a semiconductor substrate.

[0265] According to an exemplary embodiment, different doped semiconductor regions of the pn - junction structure extend vertically into the semiconductor substrate with respect to the main surface region of the semiconductor substrate, and wherein a major portion of the region of the metallurgical pn - junction is a planar pn - junction extending parallel to the main surface region of the semiconductor substrate.

[0266] According to an exemplary embodiment, two pn - junction structures of the i - th pair of pn - junction structures are arranged together in a stacked configuration in a semiconductor substrate.

[0267] According to an exemplary embodiment, one of the two pn - junction structures of the first pair of pn - junction structures in the n pairs of pn - junction structures is arranged in a stacked configuration in a semiconductor substrate having one of the two pn - junction structures of the second pair of pn - junction structures in the n pairs of pn - junction structures.

[0268] According to an exemplary embodiment, the stacked configuration includes an npn structure having a floating base region in the semiconductor substrate.

[0269] At least one pair of pn - junction structures in the n pairs of pn - junction structures is arranged as a pair of two composite pn - junction structures, and each of the two composite pn - junction structures in the pair of two composite pn - junction structures has a first partial pn - junction structure and a second partial pn - junction structure,

[0270] wherein the first partial pn - junction structure has a first partial junction grading coefficient m i1 , and wherein the second partial pn - junction structure has a second partial junction grading coefficient m different from the first partial junction grading coefficient m i1 i2 ,

[0271] wherein the junction grading coefficient m of the composite pn - junction structure i is based on a combination of the first partial junction grading coefficient and the second partial junction grading coefficients m i1 、m i2 .

[0272] According to an exemplary embodiment, a first part pn - junction structure and a second part pn - junction structure are disposed in a semiconductor substrate, wherein the combination is proportional to the area ratio between the active regions of the first part pn - junction structure and the second part pn - junction structure parallel to a first main surface region of the semiconductor substrate.

[0273] According to an exemplary embodiment, the first part pn - junction structure and the second part pn - junction structure of the first - type pn - junction structure and the first part pn - junction structure and the second part pn - junction structure of the second - type pn - junction structure are disposed together in a laterally isolated common region of the semiconductor substrate.

[0274] According to an exemplary embodiment, the first part pn - junction structure is arranged to have a first part junction grading coefficient m i1 > 0.50, and wherein the second part pn - junction structure is arranged to have a second part junction grading coefficient m between 0.30 and 0.5 i2 .

[0275] According to an exemplary embodiment, the first part pn - junction structure and the second part pn - junction structure extend perpendicularly into the semiconductor substrate in a depth direction with respect to a first main surface region of the semiconductor substrate.

[0276] Although some aspects have been described as features in the context of a device, it is clear that such a description can also be regarded as a description of corresponding features of a method. Although some aspects have been described as features in the context of a method, it is clear that such a description can also be considered as a description of corresponding features regarding the functions of a device.

[0277] In the foregoing detailed description, it can be seen that, for the purpose of simplifying the present disclosure, various features are combined in the examples. This method of the present disclosure should not be construed as reflecting an intention that the claimed examples require more features than those expressly recited in each claim. Rather, as reflected by the appended claims, the inventive subject matter may lie in less than all of the features in a single disclosed example. Accordingly, the appended claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. Although each claim may stand on its own as a separate example, it should be noted that although dependent claims may refer to a particular combination with one or more other claims in the claims, other examples may also include combinations of a dependent claim with the subject matter of each other dependent claim, or combinations of each feature with other dependent or independent claims. Such combinations are presented herein unless a particular combination is not intended. Furthermore, it is intended that the features of any other independent claim be included in the claims, even if this claim does not directly depend on an independent claim.

[0278] Although specific embodiments have been shown and described herein, those of ordinary skill in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Accordingly, the present invention is intended to be limited only by the claims and their equivalents.

[0279] List of Reference Signs

[0280] 32 - 42 Different injection doses

[0281] 100 Semiconductor device

[0282] 102 First pair of pn - junction structures

[0283] 102 - 1, 102 - 2 First and second parallel circuits / composite pn - junction structures

[0284] 104 Second pair of pn - junction structures

[0285] 106 Third pair of pn - junction structures

[0286] 107 First terminal

[0287] 108 Second terminal

[0288] 110 Interconnection

[0289] 120 Semiconductor substrate

[0290] 120a, 120b First and second main surface portions

[0291] 120 - 1 n - type substrate

[0292] 120 - 2 p - type semiconductor layer

[0293] 120 - 3 Buried p - type semiconductor layer

[0294] 120 - 4 p - type semiconductor layer

[0295] 120 - 5 p - type well region

[0296] 120 - 6 p - type well region

[0297] 120 - 7 n - type contact region

[0298] 120 - 8 Inversion charge layer

[0299] 120 - 9 Depletion region

[0300] 120 - 10 Channel stop region

[0301] 122 Isolated semiconductor regions

[0302] 124 Isolated semiconductor regions

[0303] 130 Deep isolation trenches

[0304] 132 Semiconductor fillers

[0305] 134 Liner oxides

[0306] 135 Semiconductor / oxide interfaces

[0307] 136 Fixed oxide charges

[0308] 137 Boundaries of depletion layers

[0309] a 1 ,a 2 Shape parameter of the ellipse (= radii r 1 、r 2 )

[0310] (A), (B) Higher and lower P-well doping concentrations

[0311] C J01 ,C J02 First and second zero-bias capacitances

[0312] C J011 ,C J012 First and second partial zero-bias capacitances

[0313] J1, J2 First-type pn-junction structures

[0314] J3, J4 Second-type pn-junction structures

[0315] J 11 ,J 21 First-type partial pn-junction structures

[0316] J 11 ,J 21 First-type partial pn-junction structures

[0317] m 1 ,m 2 First and second junction grading coefficients

[0318] m 11 ,m 12 Partial junction grading coefficients

[0319] S1, S2 First and second serial circuits

[0320] V bd Breakdown voltage

[0321] V J1 , V J2 The first and second junction voltage potentials

[0322] V J11 , V J12 The first and second partial junction voltage potentials

[0323] The signal power level of the PH3 stray third harmonic

Claims

1. A semiconductor device, comprising: n pairs of pn - junction structures, where n is an integer ≥ 2, and where the i - th pair includes two pn - junction structures of the i - th type, where i ∈ {1,…,n}, and where the two pn - junction structures of the i - th type are anti - serially connected, wherein the pn junction structure of the i-th type includes an i-th junction grading coefficient m i , and wherein at least a first pair of the n pairs of pn junction structures includes a first junction grading coefficient m 1 ≤ 0.48, and a second pair of the n pairs of pn junction structures includes a second junction grading coefficient m 2 ≥ 0.

52.

2. The semiconductor device according to claim 1, wherein the first junction grading coefficient m 1 to the n-th junction grading coefficient m n conforms to the following elliptic equation within a tolerance range of ±0.05: wherein where parameter a i is determined based on the zero - bias capacitance C J0i of the pn - junction structure of the i - th type Ji and the junction voltage potential V 3. The semiconductor device according to claim 1, wherein the first junction grading coefficient m 1 = 0.33 ± 0.1, and wherein the second junction grading coefficient m 2 = 0.59 ± 0.

03.

4. A semiconductor device, comprising: n pairs of pn - junction structures, where n is an integer ≥ 2, and where the i - th pair includes two pn - junction structures of the i - th type, where i ∈ {1,…,n}, and where the two pn - junction structures of the i - th type are anti - serially connected, wherein the pn junction structure of the i-th type includes an i-th junction grading coefficient m i . wherein the first junction grading coefficient m 1 to the nth junction grading coefficient m n conforms to the following elliptic equation: wherein and wherein at least a first pair of the n pairs of pn junction structures includes a first junction grading coefficient m 1 ≤0.48, and a second pair of the n pairs of pn junction structures includes a second junction grading coefficient m 2 ≥0.52, wherein the parameter a i is determined based on a zero-bias capacitance C J0i and a junction voltage potential V Ji of the pn junction structure of the i-th type.

5. The semiconductor device according to claim 4, wherein each of the first to nth parameters "a 1 to a n " is determined based on the n zero-bias capacitances C J0,1 -C J0,ni of the n pn-junction structures and based on the n junction voltage potentials V J1 -V Jn of the n pn-junction structures.

6. The semiconductor device according to claim 5, wherein the first to nth parameters "a 1 to a n " satisfy the following equation:

7. The semiconductor device according to claim 4, wherein at least two of the first junction grading coefficient m 1 to the nth junction grading coefficient m n are different.

8. The semiconductor device according to claim 4, wherein for n = 2 and C j01 = C j02 , the first type pn junction structure is arranged to have the first junction grading coefficient m between 0.23 and 0.43 1 , and wherein the second type pn junction structure is arranged to have the second junction grading coefficient m between 0.56 and 0.62 2 .

9. The semiconductor device according to claim 5, wherein for n = 1, the first type pn junction structure and the second type pn junction structure are arranged to have a zero-bias capacitance C J0-1 , C J0-2 in a ratio of:

10. The semiconductor device according to claim 4, wherein the pn - junction structures of the i - th type form an i - th type diode structure having an anode region and a cathode region.

11. The semiconductor device according to claim 4, further comprising a first connection terminal and a second connection terminal, wherein the n pairs of pn - junction structures are connected between the first connection terminal and the second connection terminal.

12. The semiconductor device according to claim 11, wherein the n pairs of pn - junction structures are arranged in a stacked configuration in a semiconductor substrate.

13. The semiconductor device according to claim 12, wherein the differently doped semiconductor regions of the pn - junction structures extend vertically into the semiconductor substrate with respect to the main surface region of the semiconductor substrate, and the planar metallurgical pn - junctions extend parallel to the main surface region of the semiconductor substrate.

14. The semiconductor device according to claim 13, wherein the two pn - junction structures of the i - th pair of pn - junction structures are arranged together in a stacked configuration in the semiconductor substrate.

15. The semiconductor device according to claim 14, wherein one of the two pn - junction structures of the first pair of pn - junction structures among the n pairs of pn - junction structures is arranged in a stacked configuration in the semiconductor substrate having one of the two pn - junction structures of the second pair of pn - junction structures among the n pairs of pn - junction structures.

16. The semiconductor device according to claim 14, wherein the stacked configuration includes an npn structure having a floating base region in the semiconductor substrate.

17. The semiconductor device according to claim 4, wherein at least one pair of the n pairs of pn - junction structures is arranged as a pair of two composite pn - junction structures, and each of the pair of two composite pn - junction structures has a first partial pn - junction structure and a second partial pn - junction structure. wherein the first part pn junction structure has a first part junction grading coefficient m i1 , and wherein the second part pn junction structure has a second part junction grading coefficient m different from the first part junction grading coefficient m i1 , and i2 , and wherein the grading coefficient m of the composite pn junction structure i is based on a combination of the grading coefficient m of the first part i1 and the grading coefficient m of the second part i2 thereof.

18. The semiconductor device according to claim 17, wherein the first partial pn - junction structure and the second partial pn - junction structure of the first - type pn - junction structure and the first partial pn - junction structure and the second partial pn - junction structure of the second - type pn - junction structure are arranged together in a laterally isolated common region of the semiconductor substrate.

19. The semiconductor device according to claim 17, wherein the first partial pn-junction structure is arranged to have a first partial junction grading coefficient m i1 > 0.50, and wherein the second partial pn-junction structure is arranged to have a second partial junction grading coefficient m between 0.30 and 0.5 i2 .

20. The semiconductor device according to claim 4, wherein the first junction grading coefficient m 1 = 0.33 ± 0.1, and wherein the second junction grading coefficient m 2 = 0.59 ± 0.03.

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