Insulating material with high dielectric constant, transistor and preparation method thereof

Abstract

The invention relates to an insulating material with a high dielectric constant, a transistor and a preparation method thereof. The preparation method comprises the following steps: growing a MoO3 thin layer on a SiO2 / Si substrate by adopting high-purity MoO3 powder and adopting a physical vapor deposition process: placing the MoO3 powder in an aluminum oxide boat; inversely arranging the substrate on an aluminum oxide boat, and then placing the aluminum oxide boat in a heating center of a single-temperature-zone tubular furnace; vacuumizing the tubular furnace, and heating to a target temperature under a vacuum condition; after the target temperature is reached, argon is introduced for heat preservation for a certain time; closing argon after heat preservation is finished, and naturally cooling along with the furnace to obtain a MoO3 thin layer standing on the substrate; the material has the characteristics of high dielectric constant, ultrathin equivalent oxide thickness and the like, the transistor is obtained through a polymer-free transfer method, the cleanliness of a device manufacturing contact surface is protected, the electrical property of the device is greatly improved, meanwhile, the structural stability of the material is kept, and the device shows an excellent transfer characteristic.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices, and particularly to a high dielectric constant insulating material, a transistor, and a preparation method thereof. Background Art

[0002] As the size of electronic devices continues to shrink, traditional silicon-based insulating materials are facing increasingly serious challenges. Especially in high-integration integrated circuits, as the thickness of the gate dielectric continues to decrease, problems such as gate leakage current, interface quality, and breakdown electric field strength of the material have become important factors restricting device performance. In order to meet the requirements of ultra-thin devices for material performance, the development of new insulating materials with high dielectric constant, low leakage, and good interface quality has become an urgent problem to be solved.

[0003] MoO 3 As a two-dimensional insulating material, with excellent electrical properties and structural stability, it has become a research hotspot in recent years. MoO 3 's high dielectric constant and low equivalent oxide thickness (EOT) make it a potential gate dielectric material, but there are still challenges in its growth process and interface performance. The high dielectric constant MoO 3 material and its preparation method proposed by the present invention can overcome the defects of existing materials and provide more stable and reliable material support for next-generation microelectronic devices. Summary of the Invention

[0004] The primary object of the present invention is to provide a high dielectric constant insulating material, a transistor, and a preparation method thereof. The insulating material MoO 3 has excellent electrical properties, especially outstanding performance in the application of gate dielectrics in low-power, high-integration electronic devices. The characteristics of this material include: high dielectric constant, ultra-thin equivalent oxide thickness (EOT), and relatively high breakdown electric field strength. When applied to a transistor, it can effectively reduce the leakage current and enhance the performance of the device.

[0005] The high dielectric constant insulating material MoO 3 provided by the present invention is prepared by a polymer-free mechanical pressing technique, which can efficiently grow MoO 3 with a layered structure on a substrate, ensuring its high dielectric constant and good electrical properties. The obtained MoO 3 material is combined with two-dimensional semiconductor material layers such as MoS 2 and WSe 2 to construct a field-effect transistor. The obtained MoS 2 / MoO 3 transistor exhibits excellent on-off ratio, extremely low subthreshold swing, and top-gate leakage current. The material provided by the present invention can be widely applied to MoO 3Fields such as electronic devices, MOSFETs, and CMOS technology.

[0006] On the one hand, the present invention provides a method for preparing an insulating material with a high dielectric constant, using high-purity (>99.9%) MoO 3 powder, and growing a MoO 2 thin layer on a SiO 3 / Si substrate by physical vapor deposition process:

[0007] Place the MoO 3 powder in an alumina boat;

[0008] Place the side of the substrate with the SiO 2 layer facing the alumina boat on the alumina boat, and then place the alumina boat at the heating center of a single-temperature zone tube furnace;

[0009] Vacuum the tube furnace and heat it to the target temperature under vacuum conditions;

[0010] After reaching the target temperature, introduce argon gas and keep it warm for a certain period of time;

[0011] After the heat preservation ends, close the argon gas and let it cool naturally in the furnace to obtain a MoO 3 thin layer standing upright on the substrate.

[0012] Further, in the step of heating to the target temperature under vacuum conditions, the heating rate is 35°C / min, and the target temperature is 740°C to 790°C.

[0013] Further, the argon gas flow rate is 80 - 100 sccm, and the heat preservation time is 0.25 - 0.4 hours.

[0014] On the one hand, the present invention provides an insulating material with a high dielectric constant. This insulating material is a MoO 3 thin layer with a layered structure, which is obtained by the above preparation method.

[0015] On the one hand, the present invention provides a method for preparing a transistor, including the following steps:

[0016] Obtain a two-dimensional semiconductor material thin-layer single-crystal tape by mechanical exfoliation process, use PDMS to adhere to the two-dimensional semiconductor material thin-layer single-crystal tape to get a two-dimensional semiconductor material thin layer / PDMS, and attach the side of the two-dimensional semiconductor material thin layer / PDMS with the two-dimensional semiconductor material thin layer to the surface of the SiO 2 layer of the SiO 2 / Si substrate, and tear off the PDMS layer on the SiO 2Obtain a thin layer of two-dimensional semiconductor material on a / Si substrate; the thin layer of two-dimensional semiconductor material obtained by this peeling method is larger, more uniform, and has less residual glue than the thin layer of two-dimensional semiconductor material directly peeled from the substrate using a single-crystal tape of two-dimensional semiconductor material.

[0017] Fabricate a first electrode and a second electrode at both ends of the thin layer of two-dimensional semiconductor material;

[0018] Take the substrate with the upright MoO 3 thin layer prepared above, and use a polymer-free transfer method to adhere the MoO 3 thin layer to PDMS to obtain MoO 3 / PDMS;

[0019] Turn the side of the MoO 3 / PDMS with the adhered MoO 3 towards the thin layer of two-dimensional semiconductor material, attach it to the thin layer of two-dimensional semiconductor material, and after tearing off the PDMS, obtain a MoO 3 thin layer on the thin layer of two-dimensional semiconductor material;

[0020] Adopt a PVA dry transfer process to transfer the third electrode onto the MoO 3 thin layer, then soak the substrate in deionized water, heat it at 60 - 70 °C for 4 hours, and then take it out and blow it dry.

[0021] Furthermore, the thin layer of two-dimensional semiconductor material is MoS 2 , WSe 2 or WS 2 .

[0022] Furthermore, the thickness of the MoO 3 thin layer is 1 - 100 nm.

[0023] Furthermore, the thickness of the thin layer of two-dimensional semiconductor material is 5 - 50 nm.

[0024] Furthermore, in the polymer-free transfer method, use PDMS to slowly approach the substrate with the upright MoO 3 thin layer, after adhering the MoO 3 thin layer to PDMS, slowly lift PDMS to obtain MoO 3 / PDMS.

[0025] Furthermore, the first electrode and the second electrode are Cr / Au electrodes, the thickness of the Cr layer is 2 - 10 nm, and the thickness of the Au layer is 30 - 80 nm.

[0026] Furthermore, the third electrode is an Au electrode with a thickness of 50 - 80 nm.

[0027] On the one hand, the present invention provides a transistor obtained by the above preparation method.

[0028] Compared with the prior art, the present invention has at least the following beneficial effects:

[0029] Through the PVD growth method, the present invention prepares molybdenum trioxide MoO with advantages such as a layered two-dimensional structure thin film, a high dielectric constant, and a large yield. 3 , and the grown MoO 3 grows upright on the SiO 2 / Si substrate. This material has a high dielectric constant, an ultra-thin equivalent oxide thickness (EOT), excellent interface quality, and a high breakdown electric field strength, and is suitable for use as a gate dielectric in the manufacture of two-dimensional electronic devices and field effect transistors. By transferring the MoO 3 material through a polymer-free transfer method, the cleanliness of the contact surface for device manufacturing is protected, its electrical properties are greatly improved, and the structural stability of the material is maintained. And through the polymer-free transfer method, MoO 3 can be successfully transferred to the target substrate. This transfer method is not limited to using molybdenum disulfide MoS 2 as the target substrate, and other two-dimensional materials such as WSe 2 , WS 2 , etc. can be used as transfer targets; and by combining the mechanical exfoliation process, the MoS 2 / MoO 3 transistor exhibits excellent transfer characteristics. In the range where the top gate voltage varies from -1.5V to 0V, it shows an excellent on-off ratio (10 7 ), an extremely low subthreshold swing (78 mV / dec), and a low top gate leakage current (10 -4 A / cm 2 ). The material preparation process of the present invention is simple, the technology is mature, the equipment is easy to obtain, and the cost is low, which is conducive to promoting the further development and application in the fields of transistors and low-dimensional electronic devices, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a SEM image of the MoO 3 material obtained by preparing an embodiment of the present invention.

[0031] Figure 2 is a schematic diagram of polymer-free transfer during the preparation process of an embodiment of the present invention.

[0032] Figure 3 is a schematic diagram of the device structure of the MoS 2 / MoO 3 transistor of an embodiment of the present invention.

[0033] Figure 4 During the preparation process of an embodiment of the present invention, the MoS 2 / MoO 3 transistor optical microscope image, and the inset therein is the AFM test image of the thin MoO 3 layer.

[0034] Figure 5 The MoS 2 / MoO 3 transistor data curve obtained by preparing an embodiment of the present invention, where Figure a is the transfer curve of the transistor under different bias voltages; Figure b is the comparison of gate leakage currents between different devices. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings of the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention. In the following embodiments, the experimental methods, unless otherwise specified, are all conventional methods; the reagents and materials, unless otherwise specified, can be obtained from public commercial channels.

[0036] In this specification, spatial relative terms such as "beneath", "below", "lower", "above", "upper", etc. are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device in addition to those shown in the figures.

[0037] In addition, terms such as "first", "second", etc. are used to describe each element, layer, region, section, etc., and are not intended to be limiting. The terms "having", "containing", "including", "comprising", etc. are open-ended terms, indicating the presence of the stated element or feature, but not excluding additional elements or features. Unless otherwise clearly stated in the context.

[0038] An embodiment of the present invention provides a method for preparing a high dielectric constant insulating material, including the following steps:

[0039] First, soak the SiO 2 / Si growth substrate in acetone solution, isopropyl alcohol solution, and deionized water respectively, and keep it for 4 minutes each time during the soaking process.

[0040] Next, use physical vapor deposition process to grow a MoO 2 thin layer on the SiO 3 layer of the Si substrate. Place high-purity (>99.9%) MoO 3 powder in the center of the alumina boat, and then the cleaned SiO2 The SiO₂ / Si substrate has a SiO₂ layer, and one side of the SiO₂ layer faces the alumina boat and covers the alumina boat. Subsequently, the alumina boat is pushed and placed at the heating center of the tube furnace, and the tube furnace is a single-temperature zone tube furnace. 2 Then, a vacuum pump is used to evacuate the entire tube furnace channel system to isolate air, and the vacuum is maintained while the temperature is continuously increased at a heating rate of 35 °C / min until the temperature reaches 740 - 790 °C. After reaching this temperature, argon gas is introduced with a gas flow rate of 80 - 100 sccm and maintained for 0.25 - 0.4 hours. After maintaining the temperature, the argon gas channel is closed and the system is naturally cooled to room temperature. A vertically grown MoO₃ thin layer is obtained on the SiO₂ / Si growth substrate, as shown in the SEM image of the MoO₃ material prepared as described.

[0041] Subsequently, a vacuum pump is used to evacuate the entire tube furnace channel system to isolate air, and the vacuum is maintained while the temperature is continuously increased at a heating rate of 35 °C / min until the temperature reaches 740 - 790 °C. After reaching this temperature, argon gas is introduced with a gas flow rate of 80 - 100 sccm and maintained for 0.25 - 0.4 hours. After maintaining the temperature, the argon gas channel is closed and the system is naturally cooled to room temperature. A vertically grown MoO₃ thin layer is obtained on the SiO₂ / Si growth substrate. 2 / Si growth substrate to obtain a vertically grown MoO₃ thin layer, such as the SEM image of the MoO₃ material prepared as shown. 3 As shown in Figure 1 the SEM image of the MoO₃ material prepared as described. The MoO₃ thin layer grown in the present invention is an insulating material, and controllable growth is achieved in a tube furnace using the PVD method. By adjusting the growth temperature and time, MoO₃ thin layers with different thicknesses and widths can be prepared. 3 This method can reliably, stably, and efficiently produce MoO₃ thin layers, which can improve the use value of the MoO₃ thin layers and provide excellent materials for the development of the electronic device field, thus paving the way for the development of the electronic device field. 3 The layered growth and the characteristics of growing upright on the substrate of the MoO₃ thin layer can be observed in the SEM test image of 3 As shown in 3 This method can reliably, stably, and efficiently produce MoO₃ thin layers, which can improve the use value of the MoO₃ thin layers and provide excellent materials for the development of the electronic device field, thus paving the way for the development of the electronic device field. 3 This method can reliably, stably, and efficiently produce MoO₃ thin layers, which can improve the use value of the MoO₃ thin layers and provide excellent materials for the development of the electronic device field, thus paving the way for the development of the electronic device field. Figure 1 As shown in the SEM test image of 3 the MoO₃ thin layer, the layered growth and the characteristics of growing upright on the substrate can be observed.

[0042] Figure 2 As shown in the figure, a polymer-free transfer method provided in an embodiment of the present invention is shown. In the figure, the MoO₃ grown upright on the SiO₂ / Si substrate is placed together with the substrate under the transfer platform. PDMS is slowly brought close to the substrate growing the MoO₃ thin layer. After the MoO₃ adheres to the PDMS, the PDMS is slowly lifted. Subsequently, the PDMS with the MoO₃ thin layer is attached to the target substrate to complete the transfer. 2 / Si substrate, the MoO₃ 3 adheres to the PDMS, and then the PDMS is slowly lifted. Subsequently, the PDMS with the MoO₃ thin layer is attached to the target substrate to complete the transfer. 3 adheres to the PDMS, and then the PDMS is slowly lifted. Subsequently, the PDMS with the MoO₃ thin layer is attached to the target substrate to complete the transfer. 3 adheres to the PDMS, and then the PDMS is slowly lifted. Subsequently, the PDMS with the MoO₃ thin layer is attached to the target substrate to complete the transfer. 3 adheres to the PDMS, and then the PDMS is slowly lifted. Subsequently, the PDMS with the MoO₃ thin layer is attached to the target substrate to complete the transfer.

[0043] Figure 3 As shown in 2 / MoO₃ 3 transistor device structure schematic diagram. The device of the present invention utilizes the MoS₂ thin layer and the MoO₃ thin layer, based on MoS₂ 2 and the MoO₃ thin layer, based on MoS₂ 3 and the MoO₃ thin layer, based on MoS₂ 2The characteristics of high mobility improve the switching characteristics and transfer characteristics of the transistor. By using the existing technology to evaporate the Cr / Au layer, the Figure 3 structure of the device diagram schematic is realized.

[0044] An embodiment of the present invention provides Figure 3 in which MoS 2 / MoO 3 a preparation method of a transistor, including the following steps:

[0045] Adopt the method of mechanical exfoliation, use tape to adhere to single-crystal MoS 2 to obtain a MoS 2 single-crystal tape, use PDMS to adhere to the MoS 2 single-crystal tape to obtain MoS 2 / PDMS. Cover the PDMS with the adhered MoS 2 on one side on the surface of the SiO 2 / Si substrate, gently press for 45 seconds, tear off the PDMS layer, and obtain a MoS 2 thin layer on the surface of the SiO 2 / Si substrate. Subsequently, select a thin layer of MoS with a thickness of 5-50 nm under an optical microscope 2 as the target layer.

[0046] Then, use the ultraviolet laser lithography process to etch the mesa of the first electrode and the second electrode. Place the substrate containing the thin layer of MoS 2 on the chuck of the spin coater. Set the spin coating rate to 4000 revolutions per second and the spin coating duration to 1 minute. Subsequently, place the substrate on the heating table and cure it at 100 °C for 1 minute, and use ultraviolet laser lithography to etch the mesa.

[0047] Subsequently, use the electron beam evaporation and thermal evaporation processes to evaporate a 10 nm Cr layer and a 35 nm Au layer. The evaporation rate is 0.01 nm / s. After the evaporation is completed, place it in acetone for ten minutes to dissolve the photoresist, thereby removing the excess Cr / Au layer, and form the first electrode and the second electrode at both ends of the thin layer of MoS 2 target layer.

[0048] Adopt the above polymer-free transfer method. Place the MoO 2 grown upright on the SiO 3 / Si substrate together with the substrate under the transfer platform. Use PDMS to slowly approach the substrate growing with the thin layer of MoO 3 . After the MoO 3 adheres to the PDMS, slowly lift it. Subsequently, attach the PDMS with the thin layer of MoO 3 to cover the above thin layer of MoS 2 target layer.

[0049] A 45-nm-thick Au layer was deposited on a silicon wafer by thermal evaporation at a deposition rate of 0.01 nm / s. Subsequently, the silicon wafer was immersed in acetone for ten minutes to remove the photoresist. As the photoresist was dissolved by acetone, the excess gold film would also fall off. Then it was rinsed with deionized water and finally the moisture on the surface of the silicon wafer was blown dry with a nitrogen gun.

[0050] Next, the PVA transfer method was adopted. The prepared Au electrode was placed under the transfer platform, and PVA dry transfer was used to transfer the Au electrode onto the above-mentioned thin layer of MoO 3 . This electrode was the third electrode. The device substrate was immersed in deionized water and placed on a heating table, heated at 60 - 70 °C for 4 hours. After that, the moisture on the surface was blown dry with a nitrogen gun. Thus, the MoS Figure 4 / MoO 2 / MoO 3 transistor as shown was obtained, where the first electrode and the second electrode were respectively arranged at both ends of the thin layer of MoS 2 , and the third electrode was arranged on the thin layer of MoO 3 .

[0051] Figure 5 Figure is the performance test diagram of the transistor obtained in the above embodiment. Among them, Figure a is the transfer curve of the prepared MoS 2 / MoO 3 transistor scanned at -2V - 2V. The thickness of its thin layer of MoO 3 is 9.31 nm. This curve shows that the transistor has good transfer characteristics. Under different bias voltages, the threshold voltage has no obvious shift. When the top gate voltage is 0V, the current reaches an approximately saturated state. When the top gate voltage is -1.5V, the off-state current of the transistor is as low as 10 -14 A, which indicates that the transistor has great potential in the field of low-power electronic devices. And the thickness of the thin layer of MoO 3 corresponds to an ultra-thin equivalent oxide thickness (EOT) of 0.31 nm, which provides an excellent material for future transistor scaling, can effectively scale the transistor and meet the commercial requirement level. Figure b is the comparison between the gate leakage currents of 6 MoS 2 / MoO 3 transistors prepared in the embodiments of the present invention. By comparing the different gate leakage currents, the transistors manufactured by the present invention have stable top gate leakage currents and strong stability. As shown in the figure, the top gate current sizes are almost unchanged after two months of comparison, and all reach the low-power device level required by IRDS.

[0052] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A method for preparing an insulating material with a high dielectric constant, characterized in that: Using high-purity MoO3 powder, a MoO3 thin layer is grown on a SiO2 / Si substrate using a physical vapor deposition process: The MoO3 powder is placed in an alumina boat; The substrate is placed on the alumina boat with the side of the substrate provided with the SiO2 layer facing the alumina boat, and then the alumina boat is placed in the heating center of a single temperature zone tube furnace; The tube furnace is evacuated and heated to a target temperature while maintaining the vacuum condition; After reaching the target temperature, introduce argon gas and keep it warm for a certain period of time; After the heat preservation is completed, the argon gas is turned off and the furnace is cooled naturally to obtain a MoO3 thin layer standing upright on the substrate.

2. The preparation method according to claim 1, characterized in that: In the step of heating to the target temperature under vacuum conditions, the heating rate is 35°C / min and the target temperature is 740°C to 790°C.

3. The preparation method according to claim 1 or 2, characterized in that: The argon gas flow rate is 80-100 sccm, and the insulation time is 0.25-0.4 hours.

4. An insulating material with a high dielectric constant, characterized in that: The insulating material is a MoO3 thin layer with a layered structure, which is obtained by the preparation method described in any one of claims 1 to 3 above.

5. A method for preparing a transistor, characterized in that: The following steps are involved: A two-dimensional semiconductor material thin layer single crystal tape is obtained by a mechanical stripping process, and a two-dimensional semiconductor material thin layer single crystal tape is adhered with PDMS to obtain a two-dimensional semiconductor material thin layer / PDMS, and a surface of the two-dimensional semiconductor material thin layer / PDMS adhered with the two-dimensional semiconductor material thin layer is attached to the surface of the SiO2 layer of the SiO2 / Si substrate, and the PDMS layer is torn off to obtain a two-dimensional semiconductor material thin layer on the SiO2 / Si substrate; Prepare a first electrode and a second electrode at both ends of the two-dimensional semiconductor material thin layer; Take the substrate with a vertical MoO3 thin layer prepared according to any one of claims 1 to 3, and use a polymer-free transfer method to adhere the MoO3 thin layer to PDMS to obtain MoO3 / PDMS; The MoO3 / PDMS is attached to the two-dimensional semiconductor material layer with the side thereof being adhered to the two-dimensional semiconductor material layer facing the two-dimensional semiconductor material layer, and the PDMS is removed to obtain a MoO3 thin layer on the two-dimensional semiconductor material thin layer; The third electrode was transferred onto the MoO3 thin layer by using a PVA dry transfer process, and then the substrate was immersed in deionized water, heated at 60-70° C. for 4 hours, and then taken out and blown dry.

6. The preparation method according to claim 5, characterized in that: The two-dimensional semiconductor material thin layer is MoS2 or WSe2, and its thickness is 5 to 50 nm.

7. The preparation method according to claim 5 or 6, characterized in that: The thickness of the MoO3 thin layer is 1 to 100 nm.

8. The preparation method according to claim 7, characterized in that: In the method without polymer transfer, PDMS is slowly brought close to the substrate with the upright MoO3 thin layer, and after the MoO3 thin layer is adhered to the PDMS, the PDMS is slowly lifted up to obtain MoO3 / PDMS.

9. The preparation method according to claim 6 or 8, characterized in that: The first electrode and the second electrode are Cr / Au electrodes, the thickness of the Cr layer is 2 to 10 nm, and the thickness of the Au layer is 30 to 80 nm; The third electrode is an Au electrode with a thickness of 50-80 nm.

10. A transistor, characterized in that: The method is obtained by the preparation method described in any one of claims 5 to 9.

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