Semiconductor structure and preparation method thereof
By alternately filling the semiconductor layer in the trench of the RC-IGBT structure to form a new PN junction, the problem of insufficient FRD free-current capability in traditional RC-IGBT is solved, and compatibility for large current applications is achieved.
Patent Information
- Application Number
- CN202311552500.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-20
- Publication Date
- 2025-05-30
AI Technical Summary
In the traditional inverter insulated gate bipolar transistor (RC-IGBT) structure, the FRD region sacrifices the area of the doped region due to the introduction of the trench structure, affecting the FRD's free-flow capability, making it difficult to compatible with high current application scenarios.
The first type semiconductor layer and the second type semiconductor layer are alternately filled in the trench of the semiconductor structure from bottom to top, and a new PN junction is formed without increasing the occupied area to improve the FRD free flow capability.
By providing alternately stacked semiconductor layers in the trench, the area loss introduced by the trench is avoided, a new PN junction region is formed, and the FRD free-flow capability is improved, so that the semiconductor structure can be compatible with application scenarios of high currents.
Smart Images
Figure CN120076399A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] The reverse conducting insulated gate bipolar transistor (RC-IGBT) is an important branch of the insulated gate bipolar transistor (IGBT). Usually, a conventional IGBT and a fast recovery diode (FRD) are packaged together for application.
[0003] The FRD mainly functions as a freewheeling diode during the switching process. In a traditional RC-IGBT structure, the introduction of a trench structure in the FRD region sacrifices the area of the doped region, which is equivalent to affecting the freewheeling ability of the FRD and is not conducive to the application scenario of the FRD compatible with high current. Summary of the Invention
[0004] Based on this, embodiments of this application provide a semiconductor structure and a method for manufacturing the same, which can improve the freewheeling ability without increasing the occupied area, so as to be compatible with the application scenario of high current.
[0005] According to some embodiments, one aspect of this application provides a semiconductor structure, including:
[0006] A first-type substrate; at least two second-type regions are spaced apart and distributed within the first side surface of the first-type substrate;
[0007] A first trench, located on the first side of the first-type substrate; the side wall of the first trench has an insulating dielectric layer, and the first trench is filled with a first-type semiconductor layer and a second-type semiconductor layer that are alternately stacked from bottom to top; wherein, the topmost second-type semiconductor layer is located between the two second-type regions.
[0008] In some embodiments, the ion doping concentration of the bottommost first-type semiconductor layer in the first trench is less than the ion doping concentration of the second-type region.
[0009] In some embodiments, a second-type buried layer is provided below the first trench; the second-type buried layer is in contact with the bottommost first-type semiconductor layer in the first trench.
[0010] In some embodiments, the first-type substrate includes an adjacent fast recovery diode region and an insulated gate bipolar transistor region, and the first trench is located in the fast recovery diode region;
[0011] The semiconductor structure further includes:
[0012] A trench gate is located on the first side of the insulated gate bipolar transistor region and between two adjacent second-type regions; the trench gate includes a first-type gate electrode and a gate dielectric layer located between the first-type gate electrode and the first-type substrate.
[0013] In some embodiments, the ion doping concentration of the first-type semiconductor layer at the bottommost layer in the first trench is less than the ion doping concentration of the second-type region, and the ion doping concentration of the second-type region is less than the ion doping concentration of the first-type gate electrode.
[0014] According to some embodiments, on the other hand, the present application provides a method for manufacturing a semiconductor structure, including:
[0015] Providing a first-type substrate; at least two second-type regions spaced apart are formed in the first-side surface of the first-type substrate;
[0016] Forming a first trench on the first side of the first-type substrate;
[0017] Forming an insulating dielectric layer on the sidewalls of the first trench, and alternately forming a first-type semiconductor layer and a second-type semiconductor layer from bottom to top in the first trench; wherein, the topmost second-type semiconductor layer is formed between the two second-type regions.
[0018] In some embodiments, the forming of the insulating dielectric layer on the sidewalls of the first trench includes:
[0019] Forming an insulating dielectric material layer on the sidewalls and the bottom of the first trench;
[0020] Performing anisotropic etching on the insulating dielectric material layer to remove the insulating dielectric material layer located at the bottom of the first trench, and retaining the insulating dielectric material layer located on the sidewalls of the first trench as the insulating dielectric layer.
[0021] In some embodiments, the alternately forming a first-type semiconductor layer and a second-type semiconductor layer from bottom to top in the first trench includes:
[0022] Filling a first-type semiconductor material layer in the first trench;
[0023] Performing second-type ion implantation on the first-type semiconductor material layer to form the second-type semiconductor layer extending from the top to the bottom of the first-type semiconductor material layer, and maintaining the first-type semiconductor material layer filled at the bottom of the first trench as the first-type semiconductor layer.
[0024] In some embodiments, each of the second-type regions is formed synchronously when performing the second-type ion implantation on the first-type semiconductor material layer.
[0025] In some embodiments, the first-type substrate includes an adjacent fast-recovery diode region and an insulated gate bipolar transistor region, and the first trench is formed in the fast-recovery diode region;
[0026] The method for manufacturing the semiconductor structure further includes:
[0027] Forming a second trench between two adjacent second-type regions on the first side of the insulated gate bipolar transistor region;
[0028] Forming a gate dielectric layer on the sidewall and bottom of the second trench, and filling a first-type gate in the second trench; the gate dielectric layer and the first-type gate together form a trench gate.
[0029] The semiconductor structure and the method for manufacturing the same provided by the present application may / at least have the following unexpected advantages:
[0030] In the embodiment of the present application, a first-type semiconductor layer and a second-type semiconductor layer are alternately stacked from bottom to top in the first trench, and the topmost second-type semiconductor layer is located between two second-type regions. Compared with the related art in which only a single type of semiconductor material is filled in the trench, by providing a second-type semiconductor layer in the first trench in the embodiment of the present application, it is possible to avoid sacrificing the area of the second-type region in the first-type substrate due to the introduction of the first trench. Without increasing the occupied area and without compromising the breakdown voltage characteristics, etc., a new PN junction is formed between the first-type semiconductor layer and the second-type semiconductor layer in the first trench, thereby improving the freewheeling ability of the FRD part of the semiconductor structure and enabling the semiconductor structure to be compatible with high-current application scenarios. Description of the Drawings
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0032] Figure 1 It is a cross-sectional structure schematic diagram of a semiconductor structure provided by some embodiments of the present application; Figure 1 It is also a cross-sectional structure schematic diagram of the structure obtained after forming a first-type cathode region, a second-type collector region, and a back metal layer in the method for manufacturing a semiconductor structure provided by some embodiments of the present application;
[0033] Figure 2 It is a cross-sectional structure schematic diagram of a semiconductor structure provided by other embodiments of the present application;
[0034] Figure 3 Schematic flow chart of a method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0035] Figure 4 Schematic flow chart of step S300 in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0036] Figure 5 Schematic flow chart of step S300 in the method for fabricating a semiconductor structure provided by some other embodiments of the present application;
[0037] Figure 6 Schematic flow chart of the method for fabricating a semiconductor structure provided by some other embodiments of the present application;
[0038] Figure 7 Schematic cross-sectional structure diagram of the structure obtained after providing a first-type substrate in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0039] Figure 8 Schematic cross-sectional structure diagram of the structure obtained after forming a trench gate in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0040] Figure 9 Schematic cross-sectional structure diagram of the structure obtained after forming a first trench in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0041] Figure 10 Schematic cross-sectional structure diagram of the structure obtained after removing the insulating dielectric material layer located at the bottom of the first trench in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0042] Figure 11 Schematic cross-sectional structure diagram of the structure obtained after filling a first-type semiconductor material layer in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0043] Figure 12 Schematic cross-sectional structure diagram of the structure obtained after forming a second-type semiconductor layer and a first-type semiconductor layer in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0044] Figure 13 Schematic cross-sectional structure diagram of the structure obtained after forming a first-type emitter region in the method for fabricating a semiconductor structure provided by some embodiments of the present application;
[0045] Figure 14 Schematic cross-sectional structure diagram of the structure obtained after forming a second-type transistor contact region, an interlayer insulating layer, and a front metal layer in the method for fabricating a semiconductor structure provided by some embodiments of the present application.
[0046] Description of reference numerals:
[0047] 10. First-type substrate; 11. Second-type region; 12. Diode contact region; 210. First-type cathode region; 211. First trench; 212. Insulating dielectric layer; 212'. Insulating dielectric material layer; 213a. First-type semiconductor layer; 213a'. First-type semiconductor material layer; 213b. Second-type semiconductor layer; 214. Second-type buried layer; 220. Second-type collector region; 221. First-type gate; 222. Gate dielectric layer; 222'. Gate dielectric material layer; 223. Second-type transistor contact region; 224. First-type emitter region; 225. Interlayer insulating layer; 30. Front metal layer; 40. Back metal layer. DETAILED DESCRIPTION
[0048] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0050] It should be understood that when an element or layer is referred to as "adjacent...", it can be directly adjacent to other elements or layers, or there can be intervening elements or layers. It should be understood that although the terms first and second can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part; for example, the first type can be referred to as the second type, and similarly, the second type can be referred to as the first type.
[0051] Spatial relationship terms such as “... below” can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawing is flipped, the element or feature described as “... below” will be oriented “above” other elements or features. Therefore, the exemplary term “... below” can include both upper and lower orientations. In addition, the device can also include other orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.
[0052] As used herein, the singular forms “a”, “an” and “the” may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms “comprising” and / or “including” are used in this specification, the presence of the described features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, as used herein, the term “and / or” includes any and all combinations of the related listed items.
[0053] Fast Recovery Diodes (FRD for short) mainly play a freewheeling role during the switching process. In the traditional Reverse Conducting Insulated Gate Bipolar Transistor (RC-IGBT for short) structure, the area of the doped region is sacrificed due to the introduction of trench structures in the FRD region, which is equivalent to affecting the freewheeling ability of the FRD and is not conducive to the application scenarios of the FRD compatible with large currents.
[0054] Based on this, the embodiments of the present application provide a semiconductor structure and a preparation method thereof, which can improve the freewheeling ability without increasing the occupied area, so as to be compatible with the application scenarios of large currents. Its detailed content will be elaborated in the subsequent embodiments.
[0055] According to some embodiments, on the one hand, the present application provides a semiconductor structure.
[0056] Please refer to Figure 1 , in some embodiments, the semiconductor structure may include a first-type substrate 10, and at least two second-type regions 11 spaced apart are provided in the first side surface of the first-type substrate 10. As an example, the first-type substrate 10 may include a fast recovery diode region, as shown by the FRD region in the figure.
[0057] A first trench 211 is formed on the first side of the first-type substrate 10. As an example, the first trench 211 may be located in the fast recovery diode region.
[0058] The sidewall of the first trench 211 has an insulating dielectric layer 212, and the first trench 211 is filled with a first-type semiconductor layer 213a and a second-type semiconductor layer 213b that are alternately stacked from bottom to top; wherein, the topmost second-type semiconductor layer 213b is located between two second-type regions 11.
[0059] In the semiconductor structure provided in the above embodiment, the first trench 211 is filled with a first-type semiconductor layer 213a and a second-type semiconductor layer 213b that are alternately stacked from bottom to top, and the topmost second-type semiconductor layer 213b is located between two second-type regions 11. Compared with the related art in which only a single type of semiconductor material is filled in the trench, by providing the second-type semiconductor layer 213b in the first trench 211 in the above embodiment, it is possible to avoid sacrificing the area of the second-type region 11 in the first-type substrate 10 due to the introduction of the first trench 211. Without increasing the occupied area and without damaging the breakdown voltage characteristics, etc., a new PN junction is formed by the first-type semiconductor layer 213a and the second-type semiconductor layer 213b in the first trench 211, increasing the area of the PN junction region, thereby improving the freewheeling ability of the FRD part of the semiconductor structure and enabling the semiconductor structure to be compatible with high-current application scenarios.
[0060] It should be noted that the first type and the second type are different doping types; for example, the first type can be P-type and the second type can be N-type, or the first type can be N-type and the second type can be P-type. In the embodiments of the present application, an example is given with the first type being N-type and the second type being P-type.
[0061] It can be understood that the number of layers of the first-type semiconductor layer 213a and the second-type semiconductor layer 213b filled in the first trench 211 can be set according to the working application requirements in the actual embodiments. In the embodiments of the present application, an example is given with one layer of the first-type semiconductor layer 213a and one layer of the second-type semiconductor layer 213b being sequentially filled in the first trench 211.
[0062] In some embodiments, the ion doping concentration of the bottommost first-type semiconductor layer 213a in the first trench 211 can be less than the ion doping concentration of the second-type region 11.
[0063] Please refer to Figure 2 , in some embodiments, a second-type buried layer 214 can be provided below the first trench 211; specifically, the second-type buried layer 214 can be in contact with the bottommost first-type semiconductor layer 213a in the first trench 211.
[0064] In the semiconductor structure provided in the above embodiments, the equivalent length of the first trench 211 can be adjusted by introducing a second-type buried layer 214 below the first trench 211, so as to further adjust the freewheeling ability of the FRD part of the semiconductor structure according to the working requirements in the actual embodiments.
[0065] As an example, the first-type substrate 10 may further include an insulated gate bipolar transistor region, such as Figure 1 shown in the IGBT region, and the insulated gate bipolar transistor region is disposed adjacent to the fast recovery diode region.
[0066] In some embodiments, the semiconductor structure may further include a trench gate. The trench gate is located on the first side of the insulated gate bipolar transistor region and between two adjacent second-type regions 11.
[0067] Please continue to refer to Figure 1 , the trench gate may include a first-type gate 221 and a gate dielectric layer 222 located between the first-type gate 221 and the first-type substrate 10.
[0068] In some embodiments, the ion doping concentration of the bottommost first-type semiconductor layer 213a in the first trench 211 is less than the ion doping concentration of the second-type region 11, and the ion doping concentration of the second-type region 11 is less than the ion doping concentration of the first-type gate 221.
[0069] As an example, as Figure 1 shown, the second-type region 11 in the FRD region can be used as the anode region of the FRD in subsequent processes, and a diode contact region 12 may also be provided above the second-type region 11 in the FRD region.
[0070] As an example, as Figure 1 shown, the second-type region 11 in the IGBT region can be used as the base region of the IGBT in subsequent processes. A second-type transistor contact region 223 and a first-type emitter region 224 may also be provided above the second-type region 11 in the IGBT region. Among them, the first-type emitter region 224 is located on both sides of the trench gate, and the second-type transistor contact region 223 is located between adjacent first-type emitter regions 224.
[0071] As an example, as Figure 1 shown, the semiconductor structure may further include a front metal layer 30, which is located on the first side surface of the first-type substrate 10 and can be used as a front lead electrode. Exemplarily, the front metal layer 30 in the FRD region can be used as the anode lead electrode of the FRD in subsequent processes.
[0072] As an example, as Figure 1As shown, the semiconductor structure may further include an interlayer insulating layer 225 disposed between the trench gate and the front metal layer 30 to electrically isolate the trench gate from the front metal layer 30.
[0073] As an example, in the second side surface of the first-type substrate 10, a first-type cathode region 210 located in the FRD region may be provided, as shown by the N+ region in Figure 1 ; a second-type collector region 220 located in the IGBT region may also be provided, as shown by the P+ region in Figure 1 .
[0074] As an example, as shown in Figure 1 , the semiconductor structure may further include a back metal layer 40 located on the second side surface of the first-type substrate 10 and may be used as a back extraction electrode. Exemplarily, a part of the back metal layer 40 in contact with the first-type cathode region 210 may be used as the cathode extraction electrode of the FRD in subsequent processes, and a part of the back metal layer 40 in contact with the second-type collector region 220 may be used as the collector extraction electrode of the IGBT in subsequent processes.
[0075] As shown in Figure 1 , in some embodiments of the present application, the semiconductor structure in the FRD region may be, from top to bottom in sequence: the front metal layer 30 - the diode contact region 12 - the second-type semiconductor layer 213b - the first-type semiconductor layer 213a - the first-type substrate 10 - the first-type cathode region 210 - the back metal layer 40.
[0076] According to some embodiments, on the other hand, the present application provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure provided in the foregoing some embodiments.
[0077] It can be understood that the methods for manufacturing the semiconductor structure in the embodiments of the present application can all be used to manufacture the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structure embodiments can be mutually replaced and supplemented without conflict, so that those skilled in the art can learn the technical content of the present application.
[0078] Please refer to Figure 3 , in some embodiments, the method for manufacturing the semiconductor structure may include the following steps:
[0079] S100: Provide a first-type substrate; at least two spaced-apart second-type regions are formed in the first side surface of the first-type substrate.
[0080] S200: Form a first trench on the first side of the first-type substrate.
[0081] S300: Form an insulating dielectric layer on the sidewalls of the first trench, and alternately form a first-type semiconductor layer and a second-type semiconductor layer from bottom to top within the first trench; wherein, the topmost second-type semiconductor layer is formed between two second-type regions.
[0082] In the manufacturing method provided in the above embodiment, a first-type semiconductor layer and a second-type semiconductor layer are alternately formed from bottom to top within the first trench, and the topmost second-type semiconductor layer is located between two second-type regions. Compared with the related art where only a single type of semiconductor material is filled in the trench, the manufacturing method provided in the above embodiment can avoid sacrificing the area of the second-type region in the first-type substrate due to the introduction of the first trench. On the premise of not increasing the occupied area and not damaging the breakdown voltage characteristics, etc., a new PN junction is formed between the first-type semiconductor layer and the second-type semiconductor layer within the first trench, thereby enhancing the freewheeling ability of the FRD part of the semiconductor structure and enabling the semiconductor structure to be compatible with high-current application scenarios.
[0083] In addition, the technological process of the above manufacturing method is simple and easy to implement, and can save the manufacturing cost of the semiconductor structure.
[0084] Please refer to Figure 4 , in some embodiments, forming an insulating dielectric layer on the sidewalls of the first trench in step S300 may specifically include the following steps:
[0085] S311: Form an insulating dielectric material layer on the sidewalls and bottom of the first trench.
[0086] S312: Perform anisotropic etching on the insulating dielectric material layer to remove the insulating dielectric material layer located at the bottom of the first trench, and retain the insulating dielectric material layer located on the sidewalls of the first trench as the insulating dielectric layer.
[0087] Please refer to Figure 5 , in some embodiments, alternately forming a first-type semiconductor layer and a second-type semiconductor layer from bottom to top within the first trench in step S300 may specifically include the following steps:
[0088] S321: Fill a first-type semiconductor material layer within the first trench.
[0089] S322: Perform second-type ion implantation on the first-type semiconductor material layer to form a second-type semiconductor layer extending from the top to the bottom of the first-type semiconductor material layer, and maintain the first-type semiconductor material layer filled at the bottom of the first trench as the first-type semiconductor layer.
[0090] Please refer to Figure 6, in some embodiments, the first-type substrate includes an adjacent fast-recovery diode region and an insulated gate bipolar transistor region, and the first trench is formed in the fast-recovery diode region; the method for manufacturing the semiconductor structure may further include the following steps:
[0091] S400: Form a second trench between two adjacent second-type regions on the first side of the insulated gate bipolar transistor region.
[0092] S500: Form a gate dielectric layer on the sidewall and bottom of the second trench, and fill the first-type gate in the second trench; the gate dielectric layer and the first-type gate together form a trench gate.
[0093] It should be understood that although Figures 3 to 6 the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figures 3 to 6 at least a part of the steps in
[0094] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of the steps or stages in other steps or other steps.
[0094] To more clearly illustrate the manufacturing method in the above-mentioned some embodiments, the following will be combined with Figures 7 to 14 to understand some embodiments of the present application. It should be noted that the first type and the second type are different doping types; for example, the first type can be P-type and the second type can be N-type, or the first type can be N-type and the second type can be P-type. In the embodiments of the present application, the first type is N-type and the second type is P-type for exemplary illustration.
[0095] In step S100, as Figure 7 shown, provide a first-type substrate 10; at least two second-type regions 11 are formed in the first side surface of the first-type substrate 10 and are spaced apart from each other.
[0096] Among them, the first-type substrate 10 can be, for example, an N-type substrate (N Substrate), and the second-type region 11 can be, for example, a P-type region.
[0097] As an example, the first-type substrate 10 may include an adjacent fast-recovery diode region (as shown by the FRD region in Figure 7 ) and an insulated gate bipolar transistor region (as shown by the IGBT region in Figure 7 ).
[0098] Exemplarily, the first-type substrate 10 may include a first-type buffer layer and a first-type low-doped (e.g., N-) breakdown voltage layer stacked in sequence from bottom to top.
[0099] It can be understood that there is no order restriction on steps S200 - S300 and steps S400 - S500, that is, either of the two can be executed first, or they can be executed simultaneously, which is also allowed.
[0100] The following takes the execution of steps S400 - S500 before steps S200 - S300 as an example for illustration.
[0101] In step S400, a second trench is formed between two adjacent second-type regions 11 on the first side of the insulated gate bipolar transistor region.
[0102] In step S500, as Figure 8 shown, a gate dielectric layer 222 is formed on the sidewalls and bottom of the second trench, and a first-type gate 221 is filled in the second trench; the gate dielectric layer 222 and the first-type gate 221 together form a trench gate.
[0103] As an example, the following steps can be used to form the gate dielectric layer 222 on the sidewalls and bottom of the second trench, specifically including: forming a gate dielectric material layer 222' that covers the sidewalls and bottom of the second trench and the first-side surface of the first-type substrate 10; then, removing the gate dielectric material layer 222' formed on the first-side surface of the first-type substrate 10, and retaining the gate dielectric material layer 222' formed on the sidewalls and bottom of the second trench as the gate dielectric layer 222.
[0104] Exemplarily, the material of the gate dielectric layer 222 may include but is not limited to an oxide layer.
[0105] Exemplarily, the material of the first-type gate 221 may be, for example, a first-type high-concentration doped (N+) material; for example, the material of the first-type gate 221 may include first-type high-concentration doped polysilicon (N+ Poly).
[0106] In step S200, as Figure 9 shown, a first trench 211 is formed on the first side of the first-type substrate 10.
[0107] In step S300, as Figures 9 to 12 shown, an insulating dielectric layer 212 is formed on the sidewalls of the first trench 211, and a first-type semiconductor layer 213a and a second-type semiconductor layer 213b are alternately formed in the first trench 211 from bottom to top; among them, the topmost second-type semiconductor layer 213b is formed between two second-type regions 11.
[0108] Exemplarily, the material of the insulating dielectric layer 212 may include but is not limited to an oxide layer.
[0109] In some embodiments, an insulating dielectric layer 212 is formed on the sidewalls of the first trench 211 in step S300, which can be specifically embodied as steps S311 to S312 as follows.
[0110] In step S311, as Figure 9 shown, an insulating dielectric material layer 212' is formed on the sidewalls and bottom of the first trench 211.
[0111] As an example, the insulating dielectric material layer 212' can be formed synchronously with the gate dielectric material layer 222'. In this way, it is beneficial to simplify the process flow, thereby improving the production efficiency of the manufacturing method.
[0112] In step S312, as Figure 10 shown, the insulating dielectric material layer 212' is anisotropically etched to remove the insulating dielectric material layer 212' located at the bottom of the first trench 211, and the insulating dielectric material layer 212' located on the sidewalls of the first trench 211 is retained as the insulating dielectric layer 212.
[0113] The anisotropic etching in step S312 above refers to a specific etching process, which can show less etching of the insulating dielectric material layer 212' on the sidewalls of the first trench 211 and more focus on removing the insulating dielectric material layer 212' at the bottom when processing the first trench 211. The anisotropic etching will not overly damage the insulating dielectric material layer 212' on the sidewalls. Therefore, using anisotropic etching to process the insulating dielectric material layer 212' is beneficial to the precise preparation of vertical structures (such as the first-type semiconductor layer and the second-type semiconductor layer filled in subsequent processes), making its preparation process more precise and controllable.
[0114] In some embodiments, in step S300, a first-type semiconductor layer 213a and a second-type semiconductor layer 213b are alternately formed from bottom to top in the first trench 211, which can be specifically embodied as steps S321 to S322 as follows:
[0115] In step S321, as Figure 11 shown, a first-type semiconductor material layer 213a' is filled in the first trench 211.
[0116] As an example, the first-type semiconductor material layer 213a' can be, for example, an N-type semiconductor material layer; exemplarily, the doping concentration of the first-type semiconductor material layer 213a' can be less than 1E19 cm -3 ; for example, the doping concentration of the first-type semiconductor material layer 213a' can be 1E12 cm -3 ~1E19 cm -3 .
[0117] As an example, the material of the first-type semiconductor material layer 213a' may include, but is not limited to, single-crystalline silicon or polycrystalline silicon; for example, the material of the first-type semiconductor material layer 213a' may be, for example, N-type doped single-crystalline silicon or N-type doped polycrystalline silicon.
[0118] In step S322, as Figure 12 shown, a second-type ion implantation is performed on the first-type semiconductor material layer 213a' to form a second-type semiconductor layer 213b extending from the top to the bottom of the first-type semiconductor material layer 213a', and the first-type semiconductor material layer 213a' filled at the bottom of the first trench 211 is maintained as the first-type semiconductor layer 213a.
[0119] It should be noted that in the above step S322, maintaining the first-type semiconductor material layer 213a' filled at the bottom of the first trench 211 means that the first-type semiconductor material layer 213a' filled at the bottom of the first trench 211 is not affected by the second-type ion implantation.
[0120] It can be understood that in the above step S322, the second-type ion implantation concentration is greater than the doping concentration of the first-type semiconductor material layer 213a' in step S321. As an example, the second-type ion implantation concentration in the above step S322 is also less than the doping concentration of the first-type gate 221.
[0121] As an example, the first-type semiconductor layer 213a may be, for example, an N-type semiconductor layer, and the second-type semiconductor layer 213b may be, for example, a P-type semiconductor layer.
[0122] Exemplarily, the step of removing the gate dielectric material layer 222' formed on the first side surface of the first-type substrate 10 may be performed before the second-type ion implantation on the first-type semiconductor material layer 213a'.
[0123] As an example, the second-type regions 11 located within the first side surface of the first-type substrate 10 may be formed synchronously with the second-type ion implantation process in step S322 and with the second-type semiconductor layer 213b.
[0124] In some embodiments, each second-type region 11 is formed synchronously when the second-type ion implantation is performed on the first-type semiconductor material layer.
[0125] In some embodiments, after the first-type semiconductor layer 213a and the second-type semiconductor layer 213b are formed in step S300, as Figure 13 shown, the method for manufacturing the semiconductor structure may further include the following step: forming first-type emitter regions 224 on both sides of the trench gate.
[0126] It should be noted that the first-type emitter region 224 is located on the top surface of the second-type region 11 in the IGBT region.
[0127] As an example, the first-type emitter region 224 can be, for example, a first-type highly doped (N+) emitter region. The process steps for forming the first-type emitter region 224 in the above steps can include: forming a first-type emitter ion implantation window on the top surface of the second-type region 11 in the IGBT region, implanting first-type doping ions into the first-type emitter ion implantation window, and forming the first-type emitter region 224 after pushing the well.
[0128] In some embodiments, after forming the first-type emitter regions 224 on both sides of the trench gate, as Figure 14 shown, the method for preparing the semiconductor structure may further include process steps such as forming a second-type transistor contact region 223, an interlayer insulating layer 225, and a front metal layer 30, etc. The process thereof can be understood by referring to the process for forming the corresponding structure in the related art.
[0129] In some embodiments, as Figure 1 shown, the method for preparing the semiconductor structure may further include process steps such as forming a first-type cathode region 210, a second-type collector region 220, and a back metal layer 40, etc. The process thereof can be understood by referring to the process for forming the corresponding structure in the related art.
[0130] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.
[0131] The above-described embodiments only represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A semiconductor structure, characterized in that, it includes: a first-type substrate; at least two second-type regions are distributed at intervals within the first-side surface of the first-type substrate; a first trench, located on the first side of the first-type substrate; the sidewall of the first trench has an insulating dielectric layer, and the first trench is filled with a first-type semiconductor layer and a second-type semiconductor layer that are alternately stacked from bottom to top; wherein, the topmost second-type semiconductor layer is located between the two second-type regions.
2. The semiconductor structure according to claim 1, characterized in that, the ion doping concentration of the bottommost first-type semiconductor layer in the first trench is less than the ion doping concentration of the second-type region.
3. The semiconductor structure according to claim 1, characterized in that, a second-type buried layer is provided below the first trench; the second-type buried layer is in contact with the bottommost first-type semiconductor layer in the first trench.
4. The semiconductor structure according to claim 1, characterized in that, the first-type substrate includes an adjacent fast-recovery diode region and an insulated-gate bipolar transistor region, and the first trench is located in the fast-recovery diode region; the semiconductor structure further includes: a trench gate, located on the first side of the insulated-gate bipolar transistor region and between two adjacent second-type regions; the trench gate includes a first-type gate electrode and a gate dielectric layer located between the first-type gate electrode and the first-type substrate.
5. The semiconductor structure according to claim 4, characterized in that, the ion doping concentration of the bottommost first-type semiconductor layer in the first trench is less than the ion doping concentration of the second-type region, and the ion doping concentration of the second-type region is less than the ion doping concentration of the first-type gate electrode.
6. A method for manufacturing a semiconductor structure, characterized in that, it includes: providing a first-type substrate; at least two second-type regions are formed at intervals within the first-side surface of the first-type substrate; forming a first trench on the first side of the first-type substrate; forming an insulating dielectric layer on the sidewall of the first trench, and alternately forming a first-type semiconductor layer and a second-type semiconductor layer from bottom to top within the first trench; wherein, the topmost second-type semiconductor layer is formed between the two second-type regions.
7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, the forming an insulating dielectric layer on the sidewall of the first trench includes: forming an insulating dielectric material layer on the sidewall and bottom of the first trench; performing anisotropic etching on the insulating dielectric material layer to remove the insulating dielectric material layer located at the bottom of the first trench, and retaining the insulating dielectric material layer located on the sidewall of the first trench as the insulating dielectric layer.
8. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, the alternately forming a first-type semiconductor layer and a second-type semiconductor layer from bottom to top within the first trench includes: filling a first-type semiconductor material layer within the first trench; Performing a second-type ion implantation on the first-type semiconductor material layer to form the second-type semiconductor layer extending from the top to the bottom of the first-type semiconductor material layer, and maintaining the first-type semiconductor material layer filled at the bottom of the first trench as the first-type semiconductor layer.
9. The method for manufacturing a semiconductor structure according to claim 8, wherein, each of the second-type regions is formed synchronously when the second-type ion implantation is performed on the first-type semiconductor material layer.
10. The method for manufacturing a semiconductor structure according to claim 6, wherein, the first-type substrate includes an adjacent fast-recovery diode region and an insulated gate bipolar transistor region, and the first trench is formed in the fast-recovery diode region; the method for manufacturing the semiconductor structure further includes: forming a second trench between two adjacent second-type regions on the first side of the insulated gate bipolar transistor region; forming a gate dielectric layer on the sidewall and bottom of the second trench, and filling a first-type gate in the second trench; the gate dielectric layer and the first-type gate together form a trench gate.