Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a first region and a second region adjacent to the first region; the fin part protrudes from the top of the substrate in the first region and the second region; the first gate structure is positioned on one side of the fin part in the first region and covers the side wall of the fin part; the second gate structure is located on the other side of the fin part in the first region and covers the side wall of the fin part, and the top of the first gate structure is flush with the top of the second gate structure; the third gate structure is located at the top of the substrate in the second region and stretches across part of the top and part of the side wall of the fin part, and the top of the third gate structure is flush with the top of the first gate structure and the top of the second gate structure. The voltage values of the first gate structure and the second gate structure are controlled to be different, so that the current values of conductive communication in the first region are different, and the adjustable range value of the current value of the conductive channel is expanded.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes are continuously reduced following Moore's law. To adapt to the reduction of process nodes, it is necessary to continuously shorten the channel length of MOSFET field effect transistors. However, as the device channel length is shortened, the distance between the source and drain of the device is also shortened. Therefore, the gate's control ability over the channel becomes worse, making the subthreshold leakage phenomenon, namely the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better meet the requirements of proportional reduction of device size, non-planar MOS transistors have emerged, such as gate-all-around (GAA) transistors or fin field effect transistors (FinFET). In FinFETs, the gate can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET devices, the gate has a stronger control ability over the channel and can well suppress the short-channel effect. Moreover, compared with other devices, FinFETs have better compatibility with existing integrated circuit manufacturing. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improving the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present invention provide a semiconductor structure, including: a substrate, the substrate includes a first region and a second region adjacent thereto; fins, protruding from the top of the substrate in the first region and the second region; a first gate structure, located on one side of the fins in the first region and covering the sidewalls of the fins; a second gate structure, located on the other side of the fins in the first region and covering the sidewalls of the fins, the top of the first gate structure is flush with the top of the second gate structure; a third gate structure, located on the top of the substrate in the second region and straddling a part of the top and a part of the sidewalls of the fins, the top of the third gate structure is flush with the top of the first gate structure and the second gate structure.

[0006] Optionally, the number of fins in the first region is one or more; when the number of fins in the first region is multiple, adjacent fins share the first gate structure; or, adjacent fins share the second gate structure, or, adjacent fins share the first gate structure and adjacent fins share the second gate structure.

[0007] Optionally, the semiconductor structure further includes: a hard mask layer located on top of the fins in the first region; the top of the hard mask layer is flush with the tops of the first gate structure, the second gate structure, and the third gate structure.

[0008] Optionally, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0009] Optionally, the thickness of the hard mask layer is from 1 nanometer to 20 nanometers.

[0010] Optionally, the first gate structure includes a first work function layer having a first thickness, and the second gate structure includes a second work function layer having a second thickness.

[0011] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region adjacent thereto, fins protrude from the top of the substrate in the first region and the second region; in the first region, a first gate structure covering the sidewalls of the fins is formed on the top of the substrate on one side of the fins, and a second gate structure covering the sidewalls of the fins is formed on the top of the substrate on the other side of the fins, the top of the first gate structure is flush with the top of the second gate structure; in the second region, a third gate structure spanning part of the top and part of the sidewalls of the fins is formed on the top of the substrate, the top of the third gate structure is flush with the tops of the first gate structure and the second gate structure.

[0012] Optionally, in the step of providing the substrate, the number of fins in the first region is one or more; when the number of fins in the first region is multiple, in the step of forming the first gate structure and the second gate structure, adjacent fins share the same first gate structure; or, adjacent fins share the second gate structure; or, adjacent fins share the same first gate structure and adjacent fins share the same second gate structure.

[0013] Optionally, in the step of providing the substrate, a hard mask layer is further formed on the top of the fins; before forming the first gate structure, the second gate structure, and the third gate structure, it further includes: removing the hard mask layer in the second region; in the step of forming the first gate structure and the second gate structure, the top of the hard mask layer in the first region is used as the stop position.

[0014] Optionally, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0015] Optionally, the thickness of the hard mask layer is from 1 nanometer to 20 nanometers.

[0016] Optionally, the step of removing the hard mask layer in the second region includes: forming a mask layer covering the fins on top of the substrate in the first region, with the mask layer exposing the hard mask layer in the second region; using the mask layer as a mask to pattern the hard mask layer in the second region and remove the hard mask layer in the second region; and removing the mask layer.

[0017] Optionally, the process of removing the hard mask layer in the second region includes a dry etching process.

[0018] Optionally, the first gate structure and the second gate structure in the first region and the third gate structure in the second region are formed in the same step.

[0019] Optionally, the steps of forming the first gate structure, the second gate structure, and the third gate structure include: forming a dummy gate structure spanning the fins on top of the substrates in the first region and the second region; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure; removing the dummy gate structure and forming a first gate opening in the interlayer dielectric layer; forming a first gate material layer in the first gate opening; removing the first gate material layer on one side of the fin in the first region and forming a second gate opening in the remaining first gate material layer; forming a second gate material layer in the second gate opening; using the top of the fin as a stop position to planarize the first gate material layer and the second gate material layer above the top of the fin, taking the remaining second gate material layer in the first region as the first gate structure, taking the remaining first gate material layer in the first region as the second gate structure, and taking the remaining first gate material layer in the second region as the third gate structure.

[0020] Optionally, the process of removing the first gate material layer between adjacent fins in the first region includes a dry etching process.

[0021] Optionally, in the steps of forming the first gate structure and the second gate structure, the first gate structure includes a first work function layer with a first thickness, and the second gate structure includes a second work function layer with a second thickness.

[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0023] An embodiment of the present invention provides a method for forming a semiconductor structure. In a first region, a first gate structure covering the sidewalls of a fin is formed on top of a substrate on one side of the fin, and a second gate structure covering the sidewalls of the fin is formed on top of the substrate on the other side of the fin. The top of the first gate structure is flush with the top of the second gate structure. In a second region, a third gate structure spanning part of the top and part of the sidewall of the fin is formed on top of the substrate, and the top of the third gate structure is flush with the tops of the first gate structure and the second gate structure. That is, a first gate structure is formed on one side of the fin in the first region, and a second gate structure is formed on the other side of the fin. That is to say, a dual-gate structure is formed in the first region to control conductive communication. In the first region, by controlling the voltage values of the first gate structure and the second gate structure to be different, the current value of conductive communication in the first region is made different, thereby further expanding the adjustable range value of the current value of the conductive channel in the first region, and further improving the performance of the semiconductor structure. Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram corresponding to the semiconductor structure of the present invention.

[0025] Figures 2 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed Embodiment

[0026] Currently, the gate structure surrounding the conductive channel is a single-gate structure. After applying a working voltage to the single-gate structure, the threshold opening voltages surrounding the conductive channel are all the same, which makes the current values passing through the conductive channel all the same value, thereby making the adjustable range value of the current value of the conductive channel in the semiconductor structure too small, thus affecting the performance of the semiconductor structure.

[0027] To solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region adjacent thereto, and fins protrude from the top of the substrate in the first region and the second region; in the first region, a first gate structure covering the sidewalls of the fin is formed on top of the substrate on one side of the fin, and a second gate structure covering the sidewalls of the fin is formed on top of the substrate on the other side of the fin, and the top of the first gate structure is flush with the top of the second gate structure; in the second region, a third gate structure spanning part of the top and part of the sidewall of the fin is formed on top of the substrate, and the top of the third gate structure is flush with the tops of the first gate structure and the second gate structure.

[0028] An embodiment of the present invention provides a method for forming a semiconductor structure. In a first region, a first gate structure covering the sidewalls of a fin is formed on top of a substrate on one side of the fin, and a second gate structure covering the sidewalls of the fin is formed on top of the substrate on the other side of the fin. The top of the first gate structure is flush with the top of the second gate structure. In a second region, a third gate structure spanning across a part of the top and a part of the sidewalls of the fin is formed on top of the substrate. The top of the third gate structure is flush with the tops of the first gate structure and the second gate structure. That is, a first gate structure is formed on one side of the fin in the first region, and a second gate structure is formed on the other side of the fin. In other words, a dual-gate structure is formed in the first region to control conductive communication. In the first region, by controlling different voltage values of the first gate structure and the second gate structure, the current value of the conductive communication in the first region is made different, thereby further expanding the adjustable range value of the current value of the conductive channel in the first region, and further improving the performance of the semiconductor structure.

[0029] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0030] Figure 1 It is a schematic structural diagram corresponding to the semiconductor structure of the present invention.

[0031] The semiconductor structure includes: a substrate 200, the substrate 200 includes a first region 200A and a second region 200B adjacent thereto; a fin 201, protruding from the top of the substrate 200 in the first region 200A and the second region 200B; a first gate structure 230, located on one side of the fin 201 in the first region 200A and covering the sidewalls of the fin 201; a second gate structure 231, located on the other side of the fin 201 in the first region 200A and covering the sidewalls of the fin 201, the top of the first gate structure is flush with the top of the second gate structure; a third gate structure 232, located on the top of the substrate 200 in the second region 200B and spanning across a part of the top and a part of the sidewalls of the fin 201, the top of the third gate structure 232 is flush with the tops of the first gate structure 230 and the second gate structure 231.

[0032] It should be noted that by disposing a first gate structure 230 on one side of the fin 201 in the first region 200A and a second gate structure 231 on the other side of the fin 201 in the first region 200A, that is, a first gate structure 230 is formed on one side of the fin 201 in the first region 200A, and a second gate structure 231 is formed on the other side of the fin 201. That is to say, a dual-gate structure is formed in the first region 200A to control conductive communication. In the first region 200A, by controlling the voltage values of the first gate structure 230 and the second gate structure 231 to be different, the current value of conductive communication in the first region 200A is made different, thereby further expanding the adjustable range value of the conductive channel current value in the first region 200A, and further improving the performance of the semiconductor structure.

[0033] The substrate 200 provides a process platform for the formation method of the semiconductor structure.

[0034] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate 200 may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate 200 can also be other types of substrates 200 such as a silicon-on-insulator substrate 200 or a germanium-on-insulator substrate 200.

[0035] As an example, the substrate 200 includes a first region 200A and a second region 200B adjacent thereto. The first region 200A is used as a region for subsequently forming a dual-gate structure, and the second region 200B is used as a region for subsequently forming a single-gate structure.

[0036] The fin 201 is used to provide a conductive channel during device operation.

[0037] In this embodiment, the material of the fin 201 is the same as the material of the substrate 200, and the material of the fin 201 is silicon.

[0038] In this embodiment, the number of fins 201 in the first region 200A is one or more. As an example, Figure 1 two fins 201 are shown in the first region 200A in

[0039] In this embodiment, the semiconductor structure further includes: a hard mask layer 202, located on top of the fin 201.

[0040] Specifically, in the process of forming a semiconductor structure, the hard mask layer 202 is used as an etching mask for forming the fin 201. At the same time, during the process of forming the first gate structure 230, the second gate structure 231, and the third gate structure 232, the top of the hard mask layer 202 can be used as a stopping position, making the tops of the first gate structure 230, the second gate structure 231, and the third gate structure 232 flush, improving the flatness of the top surfaces of the first gate structure 230, the second gate structure 231, and the third gate structure 232. Moreover, by controlling the thickness of the hard mask layer 202, the purpose of controlling the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 can be achieved, making the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 reach the target heights.

[0041] In this embodiment, the material of the hard mask layer 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0042] Specifically, silicon oxide, silicon nitride, and silicon oxynitride materials are commonly used materials for the hard mask layer 202, with characteristics such as low process cost. At the same time, there is a high selectivity ratio (etching selectivity ratio and polishing selectivity ratio) between the materials of silicon oxide, silicon nitride, and silicon oxynitride and the materials selected for the fin 201, as well as the materials selected for the first gate structure 230, the second gate structure 231, and the third gate structure 232. In the process of forming a semiconductor structure, the hard mask layer 202 can function as an etching mask, and the top of the hard mask layer 202 can be used as a stopping position, reducing the probability of damage to other film layers (such as the fin 201), thereby improving the performance of the semiconductor structure.

[0043] It should be noted that the thickness of the hard mask layer 202 should not be too large or too small. If the thickness of the hard mask layer 202 is too small, during the formation process of the semiconductor structure, when patterning the fin 201 using the hard mask layer 202 as a mask, it is likely to cause a decrease in the protection effect of the hard mask layer 202 on the top of the fin 201, increasing the probability of damage to the fin 201. At the same time, during the formation of the first gate structure 230, the second gate structure 231, and the third gate structure 232, due to the too small thickness of the hard mask layer 202, the top of the hard mask layer 202 fails to play a stopping role, resulting in a low flatness of the top surfaces of the first gate structure 230, the second gate structure 231, and the third gate structure 232, and the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 not reaching the target height, thus affecting the performance of the semiconductor structure. If the thickness of the hard mask layer 202 is too large, in the subsequent processes of the semiconductor structure, it increases the process difficulty of removing the hard mask layer 202. At the same time, it is also likely to make the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 too large, which is not conducive to further reducing the overall height of the semiconductor structure. Therefore, in this embodiment, the thickness of the hard mask layer 202 is 1 nanometer to 20 nanometers.

[0044] In this embodiment, the top of the hard mask layer 202 is flush with the tops of the first gate structure 230, the second gate structure 231, and the third gate structure 232.

[0045] Specifically, during the formation of the first gate structure 230, the second gate structure 231, and the third gate structure 232, the top of the hard mask layer 202 can be used as a stopping position, making the tops of the first gate structure 230, the second gate structure 231, and the third gate structure 232 flush, resulting in a relatively high flatness of the top surfaces of the first gate structure 230, the second gate structure 231, and the third gate structure 232. At the same time, the top of the third gate structure 232 is flush with the tops of the first gate structure 230 and the second gate structure 231, making the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 consistent, improving the uniformity of the heights of the devices in the first region 200A and the devices in the second region 200B.

[0046] In this embodiment, the semiconductor structure further includes: an isolation structure 205, located on the substrate 200 exposed by the fin 201, and the isolation structure 205 covers a part of the sidewalls of the fin 201.

[0047] The isolation structure 205 is used for electrically isolating adjacent devices.

[0048] The material of the isolation structure 205 is an insulating material, and the material of the isolation structure 205 can be silicon oxide, silicon nitride, or silicon oxynitride. As an example, the material of the isolation structure 205 is silicon oxide.

[0049] The first gate structure 230 and the second gate structure 231 are used to control the opening and closing of the conductive channel when the semiconductor structure is operating.

[0050] In this embodiment, when the number of fins 201 in the first region 200A is multiple, adjacent fins 201 share the first gate structure 230; alternatively, adjacent fins 201 share the second gate structure 231, or adjacent fins 201 share the first gate structure 230 and adjacent fins 201 share the second gate structure 231.

[0051] Specifically, adjacent fins 201 sharing the first gate structure 230 and adjacent fins 201 sharing the second gate structure 231 can reduce the area occupied by the semiconductor structure.

[0052] As an example, Figure 2 The first region 200A shows two fins 201. A first gate structure 230 is provided on the top of the substrate 200 between adjacent fins 201, and a second gate structure 231 is formed on the top of the substrate 200 on the side where adjacent fins 201 face away from each other. Adjacent fins 201 share the first gate structure 230.

[0053] It should be noted that in the first region 200A, a first gate structure 230 is provided on one side of the fin 201, and a second gate structure 231 is provided on the other side of the fin 201. That is to say, a dual-gate structure is formed in the first region 200A to control the conductive communication. In the first region 200A, by controlling the voltage values of the first gate structure 230 and the second gate structure 231 to be different, the current value of the conductive communication in the first region 200A is made different, thereby further expanding the adjustable range value of the current value of the conductive channel in the first region 200A, and further improving the performance of the semiconductor structure.

[0054] It should also be noted that by making the top of the third gate structure 232 flush with the tops of the first gate structure 230 and the second gate structure 231, the top surface flatness of the first gate structure 230, the second gate structure 231, and the third gate structure 232 is relatively high, providing a better process basis for subsequent semiconductor manufacturing processes (such as forming an interconnect structure electrically connected to the gate structure). At the same time, the top of the third gate structure 232 being flush with the tops of the first gate structure 230 and the second gate structure 231 makes the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 consistent, improving the uniformity of the heights of the devices in the first region 200A and the heights of the devices in the second region 200B.

[0055] In the process of forming the semiconductor structure, the first gate structure 230 and the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B are formed in the same step.

[0056] Specifically, the first gate structure 230 and the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B being formed in the same step can reduce the process steps, lower the process cost, and improve the process efficiency. At the same time, forming the first gate structure 230, the second gate structure 231, and the third gate structure 232 in the same step enables the top of the hard mask layer 202 to only undergo a planarization process once, reducing the probability of excessive consumption of the hard mask layer 202 and enabling the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 to be as close as possible to the target height, thereby improving the performance of the semiconductor structure.

[0057] In this embodiment, the first gate structure 230 includes a first work function layer (not shown in the figure) having a first thickness, and the second gate structure 231 includes a second work function layer (not shown in the figure) having a second thickness.

[0058] Specifically, a first gate structure 230 is formed on one side of the fin 201 in the first region 200A, and a second gate structure 231 is formed on the other side of the fin 201. The first gate structure 230 includes a first work function layer having a first thickness, and the second gate structure 231 includes a second work function layer having a second thickness, enabling different threshold opening voltages on both sides of the same conductive channel, thereby facilitating the adjustment of the voltage of the semiconductor structure, introducing an additional gain stage between the input and output, adjusting the gain characteristics of the voltage, and at the same time, having a relatively high input impedance, which can better adapt to different signal sources, and in high-frequency applications, having a higher frequency response and lower losses.

[0059] It should be noted that, as an example, in the formation process of the semiconductor structure, the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B are both formed by the same gate material layer. Therefore, the thicknesses of the work functions of the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B are consistent, so that the threshold turn-on voltage of the third gate structure 232 is the same as that of the second gate structure 231.

[0060] In other embodiments, the second gate structure 231 and the third gate structure 232 may also be formed in different steps, and the thicknesses of the work functions of the second gate structure 231 and the third gate structure 232 are different.

[0061] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer (not shown in the figure), located on top of the substrate 200 and covering the sidewalls of the first gate structure 230, the sidewalls of the second gate structure 231, and the sidewalls of the third gate structure 232.

[0062] The interlayer dielectric layer is used to electrically isolate adjacent devices.

[0063] Among them, the material of the interlayer dielectric layer is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer is silicon oxide.

[0064] Correspondingly, the embodiment of the present invention further provides a method for forming a semiconductor structure, wherein Figures 2 to 7 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present invention.

[0065] Refer to Figures 2 to 3 , provide a substrate 100, the substrate 100 includes a first region 100A and a second region 100B adjacent thereto, and fins 101 protrude on top of the substrate 100 in the first region 100A and the second region 100B.

[0066] The substrate 100 provides a process platform for the subsequent method of forming the semiconductor structure.

[0067] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0068] The fins 101 are used to provide a conductive channel during device operation.

[0069] In this embodiment, the material of the fin 101 is the same as that of the substrate 100, and the material of the fin 101 is silicon.

[0070] In this embodiment, the number of fins 101 located in the first region 100A is one or more. As an example, Figure 2 the first region 100A in [reference] shows two fins 101.

[0071] As an example, the substrate 100 includes a first region 100A and a second region 100B adjacent thereto. The first region 100A is used as the region for forming a subsequent dual-gate structure, and the second region 100B is used as the region for forming a subsequent single-gate structure.

[0072] In this embodiment, a hard mask layer 102 is further formed on the top of the fin 101.

[0073] The hard mask layer 102 is used as an etching mask for forming the fin 101. At the same time, during the subsequent formation of the first gate structure, the second gate structure, and the third gate structure, the top of the hard mask layer 102 can be used as a stopping position, so that the tops of the first gate structure, the second gate structure, and the third gate structure are flush, improving the flatness of the top surfaces of the first gate structure, the second gate structure, and the third gate structure. Moreover, by controlling the thickness of the hard mask layer 102, the purpose of controlling the heights of the first gate structure, the second gate structure, and the third gate structure can be achieved, so that the heights of the first gate structure, the second gate structure, and the third gate structure reach the target heights.

[0074] In this embodiment, the material of the hard mask layer 102 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0075] Specifically, the materials of silicon oxide, silicon nitride, and silicon oxynitride are commonly used materials for the hard mask layer 102, which have the characteristics of low process cost, etc. At the same time, there is a high selectivity (etching selectivity and polishing selectivity) between the materials of silicon oxide, silicon nitride, and silicon oxynitride and the materials selected for the fin 101, as well as the materials selected for the first gate structure, the second gate structure, and the third gate structure. Thus, the hard mask layer 102 can act as an etching mask, and the top of the hard mask layer 102 can be used as a stopping position, reducing the probability of damage to other film layers (such as the fin 101), and thereby improving the performance of the semiconductor structure.

[0076] It should be noted that the thickness of the hard mask layer 102 should not be too large or too small. If the thickness of the hard mask layer 102 is too small, during the process of forming the fin 101 with the hard mask layer 102 as a mask in the patterning process, it is likely to cause a decrease in the protection effect of the hard mask layer 102 on the top of the fin 101, increasing the probability of damage to the fin 101. At the same time, during the subsequent process of forming the first gate structure, the second gate structure, and the third gate structure, due to the too small thickness of the hard mask layer 102, the top of the hard mask layer 102 fails to play a stopping role, resulting in a low flatness of the top surfaces of the first gate structure, the second gate structure, and the third gate structure, and the heights of the first gate structure, the second gate structure, and the third gate structure not reaching the target height, thus affecting the performance of the semiconductor structure. If the thickness of the hard mask layer 102 is too large, in the subsequent processes of the semiconductor structure, it increases the process difficulty of removing the hard mask layer 102. At the same time, it is also likely to make the heights of the first gate structure, the second gate structure, and the third gate structure too large, which is not conducive to further reducing the overall height of the semiconductor structure. Therefore, in this embodiment, the thickness of the hard mask layer 102 is 1 nanometer to 20 nanometers.

[0077] In this embodiment, the steps of forming the fin 101 and the hard mask layer 102 include: forming a fin material layer on the top of the substrate 100; forming a hard mask material layer on the top of the fin material layer; forming a patterned photoresist layer on the top of the hard mask material layer; using the patterned photoresist layer as a mask to pattern the hard mask material layer, and using the remaining hard mask material layer as the hard mask layer 102; using the hard mask layer 102 as a mask to pattern the fin material layer to form the fin 101 protruding from the substrate 100.

[0078] As an example, the process of patterning the fin material layer with the hard mask layer 102 as a mask includes a dry etching process.

[0079] It should be noted that in this embodiment, after forming the fin 101, the method for forming the semiconductor structure further includes: forming an isolation structure 105 on the substrate 100 of the fin 101, and the isolation structure 105 covers a part of the sidewalls of the fin 101.

[0080] The isolation structure 105 is used for electrically isolating adjacent devices.

[0081] The material of the isolation structure 105 is an insulating material, and the material of the isolation structure 105 can be silicon oxide, silicon nitride, or silicon oxynitride. As an example, the material of the isolation structure 105 is silicon oxide.

[0082] Reference Figure 4 , before subsequently forming the first gate structure, the second gate structure, and the third gate structure, it further includes: removing the hard mask layer 102 in the second region 100B.

[0083] Specifically, the hard mask layer 102 of the second region 100B is removed to expose the top of the fin 101 in the second region 100B, which is beneficial for forming a third gate structure covering a part of the top and part of the sidewalls of the fin 101 in the second region 100B later, so that both the top and the sidewalls of the fin 101 can serve as conductive channels, thereby improving the mobility and migration amount of carriers in the conductive channel.

[0084] In this embodiment, the steps of removing the hard mask layer 102 of the second region 100B include: forming a mask layer 108 covering the fin 101 on the top of the substrate 100 in the first region 100A, and the mask layer 108 exposes the hard mask layer 102 of the second region 100B; using the mask layer 108 as a mask to pattern the hard mask layer 102 of the second region 100B and remove the hard mask layer 102 of the second region 100B.

[0085] Specifically, the mask layer 108 plays a protective role for the fin 101 and the hard mask layer 102 in the first region 100A, reducing the probability of damaging the hard mask layer 102 in the first region 100A during the process of removing the hard mask layer 102 of the second region 100B.

[0086] In this embodiment, the process of removing the hard mask layer 102 of the second region 100B includes a dry etching process.

[0087] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate. By using the dry etching process to remove the hard mask layer 102 of the second region 100B, the hard mask layer 102 in the second region 100B can be removed cleanly. At the same time, the probability of damaging the sidewalls of the fin 101 is also reduced, and the sidewall morphology quality in the second region 100B is improved.

[0088] In this embodiment, the mask layer 108 includes an organic material layer (not shown in the figure), an anti-reflection coating (not shown in the figure) located on the organic material layer, and a photoresist layer (not shown in the figure) located on the anti-reflection coating.

[0089] The material of the organic material layer includes an organic material. In this embodiment, the material of the organic material layer is spin-on carbon (SOC).

[0090] In other embodiments, the material of the organic material layer may also be other organic materials, such as one or more of ODL (organic dielectric layer) materials, DUO (Deep UV Light Absorbing Oxide) materials, and APF (Advanced Patterning Film) materials.

[0091] The material of the anti-reflection coating includes BARC (bottom anti-reflective coating) material. As an example, the BARC material is Si-ARC (silicon-containing anti-reflective coating) material.

[0092] In other embodiments, the mask layer may also include only a photoresist layer.

[0093] It should be noted that after removing the hard mask layer 102 of the second region 100B, it further includes removing the mask layer 108.

[0094] The process of removing the mask layer 108 includes a wet etching process or an ashing process.

[0095] Refer to Figures 5 to 7 , in the first region 100A, a first gate structure 130 covering the sidewalls of the fin 101 is formed on top of the substrate 100 on one side of the fin 101, and a second gate structure 131 covering the sidewalls of the fin 101 is formed on top of the substrate 100 on the other side of the fin 101. The top of the second gate structure 131 is flush with the top of the second gate structure 131; in the second region 100B, a third gate structure 132 spanning part of the top and part of the sidewalls of the fin 101 is formed on top of the substrate 100. The top of the third gate structure 132 is flush with the tops of the first gate structure 130 and the second gate structure 131.

[0096] It should be noted that in the first region 100A, on top of the substrate 100 on one side of the fin 101, a first gate structure 130 covering the sidewall of the fin 101 is formed, and on top of the substrate 100 on the other side of the fin 101, a second gate structure 131 covering the sidewall of the fin 101 is formed. The top of the second gate structure 131 is flush with the top of the second gate structure 131. That is, in the first region 100A, a first gate structure 130 is formed on one side of the fin 101, and a second gate structure 131 is formed on the other side of the fin 101. That is to say, a dual-gate structure is formed in the first region 100A to control the conductive communication. In the first region 100A, by controlling the voltage values of the first gate structure 130 and the second gate structure 131 to be different, the current value of the conductive communication in the first region 100A is made different, thereby further expanding the adjustable range value of the conductive channel current value in the first region 100A, and further improving the performance of the semiconductor structure.

[0097] It should also be noted that by making the top of the third gate structure 132 flush with the tops of the first gate structure 130 and the second gate structure 131, the top surface flatness of the first gate structure 130, the second gate structure 131, and the third gate structure 132 is relatively high, providing a good process foundation for subsequent semiconductor manufacturing processes (such as forming an interconnect structure electrically connected to the gate structure). At the same time, the top of the third gate structure 132 is flush with the tops of the first gate structure 130 and the second gate structure 131, making the heights of the first gate structure 130, the second gate structure 131, and the third gate structure 132 consistent, and improving the uniformity of the heights of the devices in the first region 100A and the devices in the second region 100B.

[0098] The first gate structure 130 and the second gate structure 131 are used to control the opening and closing of the conductive channel when the semiconductor structure is working.

[0099] In this embodiment, when the number of fins 101 in the first region 100A is multiple, in the steps of forming the first gate structure and the second gate structure, adjacent fins 101 share the first gate structure 130; or, adjacent fins 101 share the second gate structure 131, or, adjacent fins 101 share the first gate structure 130 and adjacent fins 101 share the second gate structure 131.

[0100] Specifically, adjacent fins 101 sharing the first gate structure 130 and adjacent fins 101 sharing the second gate structure 131 can reduce the area occupied by the semiconductor structure.

[0101] As an example, Figure 7In the first region 100A, two fin portions 101 are shown. A first gate structure 130 is formed on the top of the substrate 100 between adjacent fin portions 101. A second gate structure 131 is formed on the top of the substrate 100 on the side of the substrate 100 where adjacent fin portions 101 face away from each other. Adjacent fin portions 101 share the first gate structure 130.

[0102] In this embodiment, the first gate structure 130 and the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are formed in the same step.

[0103] Specifically, the first gate structure 130 and the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are formed in the same step, which can reduce the process steps, lower the process cost, and improve the process efficiency. At the same time, forming the first gate structure 130, the second gate structure 131, and the third gate structure 132 in the same step enables the top of the hard mask layer 102 to only undergo a planarization process once, reducing the probability of excessive consumption of the hard mask layer 102 and enabling the heights of the first gate structure 130, the second gate structure 131, and the third gate structure 132 to approach the target height as much as possible, thereby improving the performance of the semiconductor structure.

[0104] In other embodiments, the first gate structure and the second gate structure in the first region and the third gate structure in the second region may also be formed in different steps.

[0105] In this embodiment, in the step of forming the first gate structure 130 and the second gate structure 131, the top of the hard mask layer 102 in the first region 100A is used as the stop position.

[0106] Specifically, using the top of the hard mask layer 102 in the first region 100A as the stop position makes the top of the third gate structure 132 flush with the tops of the first gate structure 130 and the second gate structure 131, resulting in a high flatness of the top surfaces of the first gate structure 130, the second gate structure 131, and the third gate structure 132, providing a good process basis for subsequent semiconductor manufacturing processes (such as forming an interconnect structure electrically connected to the gate structure). At the same time, the top of the third gate structure 132 being flush with the tops of the first gate structure 130 and the second gate structure 131 makes the heights of the first gate structure 130, the second gate structure 131, and the third gate structure 132 consistent, improving the uniformity of the heights of the devices in the first region 100A and the devices in the second region 100B.

[0107] In this embodiment, the steps of forming the first gate structure 130, the second gate structure 131, and the third gate structure 132 include: forming a dummy gate structure 110 across the fin 101 on top of the substrate 100 in the first region 100A and the second region 100B; forming an interlayer dielectric layer (not shown in the figure) on the substrate 100 exposed by the dummy gate structure 110; removing the dummy gate structure 110 and forming a first gate opening (not shown in the figure) in the interlayer dielectric layer; forming a first gate material layer 121 in the first gate opening; removing the first gate material layer 121 on one side of the fin 101 in the first region 100A and forming a second gate opening (not shown in the figure) in the remaining first gate material layer 121; forming a second gate material layer 120 in the second gate opening; using the top of the fin 101 as a stop position, planarizing the first gate material layer 121 and the second gate material layer 120 above the top of the fin 101, taking the remaining second gate material layer 120 in the first region 100A as the first gate structure 130, taking the remaining first gate material layer 121 in the first region 100A as the second gate structure 131, and taking the remaining first gate material layer 121 in the second region 100B as the third gate structure 132.

[0108] Specifically, the dummy gate structure 110 provides a spatial position for forming the first gate structure 130, the second gate structure 131, and the third gate structure 132.

[0109] As an example, the material of the dummy gate structure 110 includes polysilicon.

[0110] The interlayer dielectric layer is used for electrically isolating adjacent devices.

[0111] Among them, the material of the interlayer dielectric layer is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer is silicon oxide.

[0112] In this embodiment, the process of removing the first gate material layer 121 between adjacent fins 101 in the first region 100A includes a dry etching process.

[0113] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than the lateral etching rate. By using the dry etching process to remove the first gate material layer 121 between adjacent fins 101 in the first region 100A, the topography quality of the sidewall of the second gate opening can be improved, which is beneficial to depositing the first gate structure 130 in the second gate opening subsequently, reducing the probability of voids appearing between the first gate structure 130 and the fin 101, and thus improving the performance of the semiconductor structure.

[0114] In this embodiment, in the steps of forming the first gate structure 130 and the second gate structure 131, the first gate structure 130 includes a first work function layer (not shown in the figure) having a first thickness, and the second gate structure 131 includes a second work function layer (not shown in the figure) having a second thickness.

[0115] Specifically, a first gate structure 130 is formed on one side of the fin 101 in the first region 100A, and a second gate structure 131 is formed on the other side of the fin 101. The first gate structure 130 includes a first work function layer having a first thickness, and the second gate structure 131 includes a second work function layer having a second thickness, so that different threshold opening voltages are provided on both sides of the same conductive channel, thereby facilitating the adjustment of the voltage of the semiconductor structure, introducing an additional gain stage between the input and the output, adjusting the gain characteristics of the voltage. At the same time, it has a high input impedance, can better adapt to different signal sources, and in high-frequency applications, has a higher frequency response and lower losses.

[0116] It should be noted that, as an example, both the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are formed by the second gate material layer 120. Therefore, the thicknesses of the work functions of the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are the same, so that the threshold opening voltage of the third gate structure 132 is the same as that of the second gate structure 131.

[0117] In other embodiments, the second gate structure and the third gate structure may also be formed in different steps, and the thicknesses of the work functions of the second gate structure and the third gate structure are different.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate including a first region and a second region adjacent thereto; a fin protruding from the top of the substrate in the first region and the second region; a first gate structure located on one side of the fin in the first region and covering the sidewall of the fin; a second gate structure located on the other side of the fin in the first region and covering the sidewall of the fin, the top of the first gate structure being flush with the top of the second gate structure; a third gate structure located on the top of the substrate in the second region and spanning a part of the top and a part of the sidewall of the fin, the top of the third gate structure being flush with the tops of the first gate structure and the second gate structure.

2. The semiconductor structure according to claim 1, characterized in that, the number of fins in the first region is one or more; when the number of fins in the first region is multiple, adjacent fins share the first gate structure; or, adjacent fins share the second gate structure, or, adjacent fins share the first gate structure and adjacent fins share the second gate structure.

3. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further comprises: a hard mask layer located on the top of the fin in the first region; the top of the hard mask layer is flush with the tops of the first gate structure, the second gate structure, and the third gate structure.

4. The semiconductor structure according to claim 3, characterized in that, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

5. The semiconductor structure according to claim 3, characterized in that, the thickness of the hard mask layer is 1 nanometer to 20 nanometers.

6. The semiconductor structure according to claim 1, characterized in that, the first gate structure includes a first work function layer having a first thickness, and the second gate structure includes a second work function layer having a second thickness.

7. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate including a first region and a second region adjacent thereto, with fins protruding from the top of the substrate in the first region and the second region; in the first region, forming a first gate structure covering the sidewall of the fin on the top of the substrate on one side of the fin, and forming a second gate structure covering the sidewall of the fin on the top of the substrate on the other side of the fin, the top of the first gate structure being flush with the top of the second gate structure; in the second region, forming a third gate structure spanning a part of the top and a part of the sidewall of the fin on the top of the substrate, the top of the third gate structure being flush with the tops of the first gate structure and the second gate structure.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, in the step of providing the substrate, the number of fins in the first region is one or more; When the number of fins in the first region is multiple, in the steps of forming the first gate structure and the second gate structure, adjacent fins share the same first gate structure; or, adjacent fins share the second gate structure; or, adjacent fins share the same first gate structure and adjacent fins share the same second gate structure.

9. The method for forming a semiconductor structure according to claim 7, wherein, in the step of providing the substrate, a hard mask layer is further formed on the top of the fins; before forming the first gate structure, the second gate structure and the third gate structure, it further includes: removing the hard mask layer in the second region; in the steps of forming the first gate structure and the second gate structure, the top of the hard mask layer in the first region is used as a stop position.

10. The method for forming a semiconductor structure according to claim 9, wherein, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

11. The method for forming a semiconductor structure according to claim 9, wherein, the thickness of the hard mask layer is 1 nanometer to 20 nanometers.

12. The method for forming a semiconductor structure according to claim 9, wherein, the step of removing the hard mask layer in the second region includes: forming a mask layer covering the fins on the top of the substrate in the first region, the mask layer exposing the hard mask layer in the second region; using the mask layer as a mask to pattern the hard mask layer in the second region and remove the hard mask layer in the second region; removing the mask layer.

13. The method for forming a semiconductor structure according to claim 9, wherein, the process of removing the hard mask layer in the second region includes a dry etching process.

14. The method for forming a semiconductor structure according to claim 7, wherein, the first gate structure and the second gate structure in the first region and the third gate structure in the second region are formed in the same step.

15. The method for forming a semiconductor structure according to claim 7, wherein, the steps of forming the first gate structure, the second gate structure and the third gate structure include: forming a dummy gate structure across the fins on the top of the substrates in the first region and the second region; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure; removing the dummy gate structure and forming a first gate opening in the interlayer dielectric layer; forming a first gate material layer in the first gate opening; removing the first gate material layer on one side of the fins in the first region and forming a second gate opening in the remaining first gate material layer; forming a second gate material layer in the second gate opening; using the top of the fins as a stop position to planarize the first gate material layer and the second gate material layer higher than the top of the fins, taking the remaining second gate material layer in the first region as the first gate structure, taking the remaining first gate material layer in the first region as the second gate structure, and taking the remaining first gate material layer in the second region as the third gate structure.

16. The method for forming a semiconductor structure as described in claim 15, wherein, the process of removing the first gate material layer between adjacent fins in the first region includes a dry etching process.

17. The method for forming a semiconductor structure as described in claim 7, wherein, in the steps of forming the first gate structure and the second gate structure, the first gate structure includes a first work function layer having a first thickness, and the second gate structure includes a second work function layer having a second thickness.

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