Semiconductor device

Abstract

Disclosed is a semiconductor device including: first and second upper power lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern; a second semiconductor pattern spaced apart from the first semiconductor pattern in the second direction; a third semiconductor pattern spaced apart from the second semiconductor pattern in the second direction; a fourth semiconductor pattern spaced apart from the first semiconductor pattern in the first direction; and a fifth semiconductor pattern spaced apart from the third semiconductor pattern in the first direction. The first semiconductor pattern, the second semiconductor pattern, the third semiconductor pattern, the fourth semiconductor pattern, and the fifth semiconductor pattern are between the first upper power line and the second upper power line. The second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0168393, filed with the Korean Intellectual Property Office on November 28, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including an upper source / drain pattern and a lower source / drain pattern. Background art

[0004] Semiconductor devices include integrated circuits that include metal - oxide - semiconductor field - effect transistors (MOSFETs). As the size and design rules of semiconductor devices are gradually reduced, the size of MOSFETs is also increasingly shrinking. The shrinking of MOSFETs may deteriorate the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices that have excellent performance while overcoming the limitations caused by the high integration of semiconductor devices. Summary of the invention

[0005] Some example embodiments of the present inventive concept provide a semiconductor device having improved electrical characteristics and increased reliability.

[0006] According to some example embodiments of the present inventive concept, a semiconductor device may include: a first upper power line and a second upper power line extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern; a second semiconductor pattern spaced apart from the first semiconductor pattern in the second direction; a third semiconductor pattern spaced apart from the second semiconductor pattern in the second direction; a fourth semiconductor pattern spaced apart from the first semiconductor pattern in the first direction; and a fifth semiconductor pattern spaced apart from the third semiconductor pattern in the first direction. The first semiconductor pattern, the second semiconductor pattern, the third semiconductor pattern, the fourth semiconductor pattern, and the fifth semiconductor pattern are between the first upper power line and the second upper power line. The second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern. The distance between the first semiconductor pattern and the third semiconductor pattern is greater than the distance between the fourth semiconductor pattern and the fifth semiconductor pattern.

[0007] According to some example embodiments of the inventive concept, a semiconductor device may include: a first semiconductor pattern; a second semiconductor pattern and a third semiconductor pattern overlapping the first semiconductor pattern in a first direction; a fourth semiconductor pattern overlapping the first semiconductor pattern in a second direction intersecting the first direction; and a fifth semiconductor pattern overlapping the third semiconductor pattern in the second direction. The second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern. Each of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern has a width in the first direction less than that of each of the fourth semiconductor pattern and the fifth semiconductor pattern in the first direction.

[0008] According to some example embodiments of the inventive concept, a semiconductor device may include: a first source / drain structure; a first semiconductor pattern contacting the first source / drain structure; a first gate electrode overlapping the first semiconductor pattern; a second source / drain structure spaced apart from the first source / drain structure in a first direction; a second semiconductor pattern contacting the second source / drain structure; a second gate electrode overlapping the second semiconductor pattern; a third source / drain structure spaced apart from the second source / drain structure in the first direction; a third semiconductor pattern contacting the third source / drain structure; a third gate electrode overlapping the third semiconductor pattern; a fourth source / drain structure spaced apart from the first source / drain structure in a second direction intersecting the first direction; a fourth semiconductor pattern contacting the fourth source / drain structure; a fourth gate electrode overlapping the fourth semiconductor pattern; a fifth source / drain structure spaced apart from the third source / drain structure in the second direction; a fifth semiconductor pattern contacting the fifth source / drain structure; a fifth gate electrode overlapping the fifth semiconductor pattern; a first gate isolation layer between the first gate electrode and the second gate electrode; a second gate isolation layer between the second gate electrode and the third gate electrode; and a third gate isolation layer between the fourth gate electrode and the fifth gate electrode. Each of the first source / drain structure, the second source / drain structure, the third source / drain structure, the fourth source / drain structure, and the fifth source / drain structure includes an upper source / drain pattern and a lower source / drain pattern. The third gate isolation layer is between the first gate isolation layer and the second gate isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A conceptual diagram showing a logic cell of a semiconductor device according to some example embodiments is shown.

[0010] Figure 2A A plan view showing a semiconductor device according to some example embodiments is shown.

[0011] Figure 2B A cross-sectional view taken along line A1 - A1' is shown. Figure 2A of

[0012] Figure 2CShows a cross-sectional view taken along Figure 2A the line B1 - B1'.

[0013] Figure 2D Shows a cross-sectional view taken along Figure 2A the line C1 - C1'.

[0014] Figure 2E Shows a cross-sectional view taken along Figure 2A the line D1 - D1'.

[0015] Figure 2F Shows a cross-sectional view taken along Figure 2A the line E1 - E1'.

[0016] Figure 3A Shows a plan view showing a semiconductor device according to some example embodiments.

[0017] Figure 3B Shows a cross-sectional view taken along Figure 3A the line A2 - A2'.

[0018] Figure 4 Shows a cross-sectional view showing a semiconductor device according to some example embodiments. Detailed Description

[0019] Figure 1 Shows a conceptual diagram of a logic unit of a semiconductor device according to some example embodiments.

[0020] Referring to Figure 1 , a single-height cell SHC can be provided, and the single-height cell SHC includes three-dimensional devices such as stacked transistors. For example, a first power line POR1 and a second power line POR2 can be provided on the substrate 10. The single-height cell SHC can be defined between the first power line POR1 and the second power line POR2.

[0021] The single-height cell SHC can include a first active region AR1 as a bottom layer and a second active region AR2 as a top layer. In some example embodiments, the NMOSFETs of the first active region AR1 can be provided on the substrate 10, and the PMOSFETs of the second active region AR2 can be stacked on the NMOSFETs of the first active region AR1. In some example embodiments, the PMOSFETs of the first active region AR1 can be provided on the substrate 10, and the NMOSFETs of the second active region AR2 can be stacked on the PMOSFETs of the first active region AR1.

[0022] Since the first active region AR1 and the second active region AR2 are vertically stacked, each of the first active region AR1 and the second active region AR2 can have a relatively small width W in the first direction D1, and the single-height cell SHC can have a relatively small length H in the first direction D1.

[0023] Figure 2A A plan view showing a first active region AR1 and a second active region AR2 of a semiconductor device according to some example embodiments is shown. Figure 1 of the semiconductor device. Figure 2B A cross-sectional view taken along line A1-A1' of is shown. Figure 2A is shown. Figure 2C A cross-sectional view taken along line B1-B1' of is shown. Figure 2A is shown. Figure 2D A cross-sectional view taken along line C1-C1' of is shown. Figure 2A is shown. Figure 2E A cross-sectional view taken along line D1-D1' of is shown. Figure 2A is shown. Figure 2F A cross-sectional view taken along line E1-E1' of is shown. Figure 2A is shown.

[0024] Referring to Figures 2A to 2F , the semiconductor device may include a first lower dielectric layer 110. The first lower dielectric layer 110 may include a dielectric material.

[0025] Referring to Figures 2B to 2F a cross-sectional view of, layers including a lower active contact LAC, a lower electrode LE, a lower source / drain pattern LSD, a lower via LV, a second lower dielectric layer 120, and a first interlayer dielectric layer 130 may constitute Figure 1 the first active region AR1 of. Layers including an upper active contact UAC, an upper electrode UE, an upper source / drain pattern USD, an upper via UV, a second upper dielectric layer 170, and a second interlayer dielectric layer 140 may constitute Figure 1 the second active region AR2 of.

[0026] The first lower dielectric layer 110 may be provided therein with a first lower power line LP1, a second lower power line LP2, a third lower power line LP3, a fourth lower power line LP4, and a lower signal line LS. The second lower power line LP2 and the third lower power line LP3 may be provided between the first lower power line LP1 and the fourth lower power line LP4. The first lower power line LP1, the second lower power line LP2, the third lower power line LP3, the fourth lower power line LP4, and the lower signal line LS may include a conductive material.

[0027] The first lower power line LP1, the second lower power line LP2, the third lower power line LP3, and the fourth lower power line LP4, as well as the lower signal line LS, may be alternately arranged along a first direction D1. The first lower power line LP1, the second lower power line LP2, the third lower power line LP3, the fourth lower power line LP4, and the lower signal line LS may extend along a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other.

[0028] A lower signal line LS may be disposed between two adjacent ones of the lower power lines LP1, LP2, LP3, and LP4, and the two adjacent lower power lines are adjacent to each other in the first direction D1. For example, a lower signal line LS may be disposed between the first lower power line LP1 and the second lower power line LP2. In some example embodiments, a plurality of lower signal lines LS may be disposed between two adjacent ones of the lower power lines LP1, LP2, LP3, and LP4, and the two adjacent lower power lines are adjacent to each other in the first direction D1.

[0029] The second lower dielectric layer 120 may be disposed on the first lower dielectric layer 110. The second lower dielectric layer 120 may include a dielectric material.

[0030] The substrate 100 may be disposed on the second lower dielectric layer 120. The substrate 100 may be a semiconductor substrate, a dielectric substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the substrate 100 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium-phosphide (GaP), or gallium-arsenide (GaAs). However, the example embodiments are not limited thereto.

[0031] The substrate 100 may include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, a fourth active pattern AP4, and a fifth active pattern AP5. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, the fourth active pattern AP4, and the fifth active pattern AP5 may be defined by trenches TR on the substrate 100. Each of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, the fourth active pattern AP4, and the fifth active pattern AP5 may be an upper portion of the substrate 100 that protrudes in a third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0032] The first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 may overlap with each other in the first direction D1. In this specification, the phrase "A and B overlap with each other in the X direction" may mean that there is at least one straight line extending in the X direction and spanning both A and B. The fourth active pattern AP4 and the fifth active pattern AP5 may overlap with each other in the first direction D1. The first active pattern AP1 and the fourth active pattern AP4 may overlap with each other in the second direction D2. The third active pattern AP3 and the fifth active pattern AP5 may overlap with each other in the second direction D2.

[0033] The first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 may be spaced apart from each other in the first direction D1. The second active pattern AP2 may be disposed between the first active pattern AP1 and the third active pattern AP3. The fourth active pattern AP4 and the fifth active pattern AP5 may be spaced apart from each other in the first direction D1. The first active pattern AP1 and the fourth active pattern AP4 may be spaced apart from each other in the second direction D2. The third active pattern AP3 and the fifth active pattern AP5 may be spaced apart from each other in the second direction D2.

[0034] The width of each of the first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 in the first direction D1 may be less than the width of each of the fourth active pattern AP4 and the fifth active pattern AP5 in the first direction D1. For example, the width of each of the fourth active pattern AP4 and the fifth active pattern AP5 in the first direction D1 may be about 1.5 times to about 3 times the width of each of the first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 in the first direction D1.

[0035] The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a dielectric material. For example, the device isolation layer ST may include an oxide.

[0036] A first channel structure CH1 that may overlap with the first active pattern AP1 in the third direction D3, a second channel structure CH2 that may overlap with the second active pattern AP2 in the third direction D3, a third channel structure CH3 that may overlap with the third active pattern AP3 in the third direction D3, a fourth channel structure CH4 that may overlap with the fourth active pattern AP4 in the third direction D3, and a fifth channel structure CH5 that may overlap with the fifth active pattern AP5 in the third direction D3. A plurality of first channel structures CH1 that overlap with the first active pattern AP1 in the third direction D3 may be spaced apart from each other in the second direction D2.

[0037] The first channel structure CH1 may include a first semiconductor pattern SP1 overlapping with each other in a third direction D3. The second channel structure CH2 may include a second semiconductor pattern SP2 overlapping with each other in a third direction D3. The third channel structure CH3 may include a third semiconductor pattern SP3 overlapping with each other in a third direction D3. The fourth channel structure CH4 may include a fourth semiconductor pattern SP4 overlapping with each other in a third direction D3. The fifth channel structure CH5 may include a fifth semiconductor pattern SP5 overlapping with each other in a third direction D3.

[0038] In some example embodiments, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the fourth semiconductor pattern SP4, and the fifth semiconductor pattern SP5 may include silicon (Si). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the fourth semiconductor pattern SP4, and the fifth semiconductor pattern SP5 may include crystalline silicon. In some example embodiments, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the fourth semiconductor pattern SP4, and the fifth semiconductor pattern SP5 may include silicon-germanium (SiGe). However, the example embodiments are not limited thereto.

[0039] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may overlap with each other in a first direction D1. The fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 may overlap with each other in a first direction D1. The first semiconductor pattern SP1 and the fourth semiconductor pattern SP4 may overlap with each other in a second direction D2. The third semiconductor pattern SP3 and the fifth semiconductor pattern SP5 may overlap with each other in a second direction D2.

[0040] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a first direction D1. The second semiconductor pattern SP2 may be between the first semiconductor pattern SP1 and the third semiconductor pattern SP3. The fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 may be spaced apart from each other in a first direction D1. The first semiconductor pattern SP1 and the fourth semiconductor pattern SP4 may be spaced apart from each other in a second direction D2. The third semiconductor pattern SP3 and the fifth semiconductor pattern SP5 may be spaced apart from each other in a second direction D2.

[0041] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may have a width in the first direction D1 that is less than the width of each of the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 in the first direction D1. The width W1 of the first semiconductor pattern SP1 in the first direction D1 may be less than the width W2 of the fourth semiconductor pattern SP4 in the first direction D1. For example, the width W2 of the fourth semiconductor pattern SP4 in the first direction D1 may be about 1.5 times to about 3 times the width W1 of the first semiconductor pattern SP1 in the first direction D1. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may have the same width in the first direction D1. The fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 may have the same width in the first direction D1.

[0042] The distance L1 in the first direction D1 between the first semiconductor pattern SP1 and the third semiconductor pattern SP3 may be greater than the distance L2 in the first direction D1 between the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5.

[0043] A first gate electrode GE1 overlapping the first active pattern AP1 in the third direction D3, a second gate electrode GE2 overlapping the second active pattern AP2 in the third direction D3, a third gate electrode GE3 overlapping the third active pattern AP3 in the third direction D3, a fourth gate electrode GE4 overlapping the fourth active pattern AP4 in the third direction D3, and a fifth gate electrode GE5 overlapping the fifth active pattern AP5 in the third direction D3 may be provided. The plurality of first gate electrodes GE1 overlapping the first active pattern AP1 in the third direction D3 may be spaced apart from each other in the second direction D2. The gate electrodes GE1, GE2, GE3, GE4, or GE5 may overlap the semiconductor patterns SP1, SP2, SP3, SP4, or SP5 in the third direction D3. The gate electrodes GE1, GE2, GE3, GE4, or GE5 may include a portion between the semiconductor patterns SP1, SP2, SP3, SP4, or SP5 overlapping each other in the third direction D3.

[0044] Each of the gate electrodes GE1, GE2, GE3, GE4, and GE5 may include an upper electrode UE and a lower electrode LE. The upper electrode UE may be provided on the lower electrode LE. The upper electrode UE and the lower electrode LE may include different conductive materials.

[0045] The first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 may overlap with each other in the first direction D1. The fourth gate electrode GE4 and the fifth gate electrode GE5 may overlap with each other in the first direction D1. The first gate electrode GE1 and the fourth gate electrode GE4 may overlap with each other in the second direction D2. The first gate electrode GE1 and the fourth gate electrode GE4 may overlap with each other in the second direction D2.

[0046] The width of each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 in the first direction D1 may be less than the width of each of the fourth gate electrode GE4 and the fifth gate electrode GE5 in the first direction D1. For example, the width of each of the fourth gate electrode GE4 and the fifth gate electrode GE5 in the first direction D1 may be about 1.5 times to about 3 times the width of each of the first gate electrode GE1, the second gate electrode GE2, and the third gate electrode GE3 in the first direction D1.

[0047] A gate dielectric layer GI may be provided. The gate dielectric layer GI may separate the gate electrodes GE1, GE2, GE3, GE4, or GE5 from the semiconductor patterns SP1, SP2, SP3, SP4, or SP5. The gate dielectric layer GI may cover the top surface, bottom surface, and sidewalls of the semiconductor patterns SP1, SP2, SP3, SP4, or SP5. The gate dielectric layer GI may include a dielectric material. For example, the gate dielectric layer GI may include an oxide.

[0048] A gate spacer GS may be provided. A pair of gate spacers may be provided on opposite sidewalls of the gate electrodes GE1, GE2, GE3, GE4, or GE5. The gate spacer GS may extend in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrodes GE1, GE2, GE3, GE4, or GE5. The gate spacer GS may include a dielectric material.

[0049] A gate capping pattern GP may be provided. The gate capping pattern GP may be provided on the gate electrodes GE1, GE2, GE3, GE4, or GE5. The gate capping pattern GP may extend in the first direction D1. The top surface of the gate capping pattern GP may be coplanar with the top surface of the gate spacer GS. The gate capping pattern GP may include a dielectric material. For example, the gate capping pattern GP may include a nitride.

[0050] A gate isolation layer GD may be provided. The gate isolation layer GD may be provided between the gate electrodes GE1, GE2, GE3, GE4, and GE5 adjacent to each other in the first direction D1. The gate isolation layer GD may separate the gate electrodes GE1, GE2, GE3, GE4, and GE5 adjacent to each other in the first direction D1 from each other. The gate isolation layer GD may include a dielectric material.

[0051] The gate isolation layer GD may include a first gate isolation layer GD1 between the first gate electrode GE1 and the second gate electrode GE2, a second gate isolation layer GD2 between the second gate electrode GE2 and the third gate electrode GE3, and a third gate isolation layer GD3 between the fourth gate electrode GE4 and the fifth gate electrode GE5.

[0052] The third gate isolation layer GD3 may be disposed between the first gate isolation layer GD1 and the second gate isolation layer GD2. The distance between the third gate isolation layer GD3 and the first gate isolation layer GD1 or the second gate isolation layer GD2 in the first direction D1 may be less than the distance between the first gate isolation layer GD1 and the second gate isolation layer GD2 in the first direction D1.

[0053] The first gate isolation layer GD1 may overlap with the fourth active pattern AP4, the fourth semiconductor pattern SP4, the fourth gate electrode GE4, and the fourth source / drain structure SS4 in the second direction D2, which will be discussed below. The second gate isolation layer GD2 may overlap with the fifth active pattern AP5, the fifth semiconductor pattern SP5, the fifth gate electrode GE5, and the fifth source / drain structure SS5 in the second direction D2, which will be discussed below. The third gate isolation layer GD3 may overlap with the second active pattern AP2, the second semiconductor pattern SP2, the second gate electrode GE2, and the second source / drain structure SS2 in the second direction D2, which will be discussed below.

[0054] A first source / drain structure SS1 that may overlap with the first active pattern AP1 in the third direction D3, a second source / drain structure SS2 that may overlap with the second active pattern AP2 in the third direction D3, a third source / drain structure SS3 that may overlap with the third active pattern AP3 in the third direction D3, a fourth source / drain structure SS4 that may overlap with the fourth active pattern AP4 in the third direction D3, and a fifth source / drain structure SS5 that may overlap with the fifth active pattern AP5 in the third direction D3. The plurality of first source / drain structures SS1 that overlap with the first active pattern AP1 in the third direction D3 may be spaced apart from each other in the second direction D2. The source / drain structures SS1, SS2, SS3, SS4, or SS5 may be disposed between corresponding semiconductor patterns among the semiconductor patterns SP1, SP2, SP3, SP4, and SP5 that are adjacent to each other in the second direction D2. The source / drain structures SS1, SS2, SS3, SS4, or SS5 may contact the corresponding semiconductor patterns among the semiconductor patterns SP1, SP2, SP3, SP4, and SP5.

[0055] Each of the source / drain structures SS1, SS2, SS3, SS4, and SS5 may include a lower source / drain pattern LSD and an upper source / drain pattern USD. The lower source / drain pattern LSD and the upper source / drain pattern USD included in one of the source / drain structures SS1, SS2, SS3, SS4, and SS5 may overlap each other in a third direction D3. The lower source / drain pattern LSD and the upper source / drain pattern USD may be epitaxial patterns formed by a selective epitaxial growth process. The lower source / drain pattern LSD and the upper source / drain pattern USD may include a semiconductor material. In some example embodiments, the lower source / drain pattern LSD may have p-type conductivity, and the upper source / drain pattern USD may have n-type conductivity. In some example embodiments, the lower source / drain pattern LSD may have n-type conductivity, and the upper source / drain pattern USD may have p-type conductivity.

[0056] The first source / drain structure SS1, the second source / drain structure SS2, and the third source / drain structure SS3 may overlap each other in a first direction D1. The fourth source / drain structure SS4 and the fifth source / drain structure SS5 may overlap each other in a first direction D1. The first source / drain structure SS1 and the fourth source / drain structure SS4 may overlap each other in a second direction D2. The third source / drain structure SS3 and the fifth source / drain structure SS5 may overlap each other in a second direction D2.

[0057] The width of each of the upper source / drain patterns USD of the first source / drain structure SS1, the second source / drain structure SS2, and the third source / drain structure SS3 in the first direction D1 may be less than the width of each of the upper source / drain patterns USD of the fourth source / drain structure SS4 and the fifth source / drain structure SS5 in the first direction D1. For example, the width of each of the upper source / drain patterns USD of the fourth source / drain structure SS4 and the fifth source / drain structure SS5 in the first direction D1 may be about 1.5 times to about 3 times the width of each of the upper source / drain patterns USD of the first source / drain structure SS1, the second source / drain structure SS2, and the third source / drain structure SS3 in the first direction D1.

[0058] The width of each of the lower source / drain patterns LSD of the first source / drain structure SS1, the second source / drain structure SS2, and the third source / drain structure SS3 in the first direction D1 may be less than the width of each of the lower source / drain patterns LSD of the fourth source / drain structure SS4 and the fifth source / drain structure SS5 in the first direction D1. For example, the width of each of the lower source / drain patterns LSD of the fourth source / drain structure SS4 and the fifth source / drain structure SS5 in the first direction D1 may be about 1.5 times to about 3 times the width of each of the lower source / drain patterns LSD of the first source / drain structure SS1, the second source / drain structure SS2, and the third source / drain structure SS3 in the first direction D1.

[0059] The lower active contact LAC may be provided. The lower active contact LAC may penetrate the substrate 100 to contact the lower portion of the lower source / drain pattern LSD. The lower via LV may be provided. The lower via LV may penetrate the second lower dielectric layer 120 to contact the lower active contact LAC. The lower source / drain pattern LSD may be electrically connected to the lower power lines LP1, LP2, LP3, or LP4 or the lower signal line LS through the lower active contact LAC and the lower via LV. The lower active contact LAC and the lower via LV may include a conductive material.

[0060] At least one of the lower active contacts LAC may be electrically connected to the plurality of lower power lines LP1, LP2, LP3, and LP4. For example, the lower active contact LAC contacting the fourth source / drain structure SS4 may be electrically connected to the first lower power line LP1 and the second lower power line LP2 through two lower vias LV.

[0061] The lower gate contact LGC may be provided. The lower gate contact LGC may penetrate the second lower dielectric layer 120 and the substrate 100 to contact the lower portion of the lower electrode LE. The lower electrode LE may be electrically connected to the lower signal line LS through the lower gate contact LGC. The lower gate contact LGC may include a conductive material. In some example embodiments, the lower gate contact LGC may include a plurality of contacts overlapping each other in the third direction D3.

[0062] The first interlayer dielectric layer 130 may be provided on the lower source / drain pattern LSD. The second interlayer dielectric layer 140 may be provided on the first interlayer dielectric layer 130. A part of the first interlayer dielectric layer 130 may be interposed between the upper source / drain pattern USD and the lower source / drain pattern LSD. The first interlayer dielectric layer 130 and the second interlayer dielectric layer 140 may include a dielectric material.

[0063] The diffusion barrier dielectric layer 150 may be provided between the first active pattern AP1 and the fourth active pattern AP4 and between the third active pattern AP3 and the fifth active pattern AP5. The diffusion barrier dielectric layer 150 may be provided on the device isolation layer ST. The diffusion barrier dielectric layer 150 may define a double diffusion barrier region. The diffusion barrier dielectric layer 150 may include a dielectric material.

[0064] The first upper dielectric layer 160 may be provided on the second interlayer dielectric layer 140. The second upper dielectric layer 170 may be provided on the first upper dielectric layer 160. The third upper dielectric layer 180 may be provided on the second upper dielectric layer 170. The first upper dielectric layer 160, the second upper dielectric layer 170, and the third upper dielectric layer 180 may include a dielectric material.

[0065] An upper active contact UAC can be provided. The upper active contact UAC can penetrate the first upper dielectric layer 160 and the second interlayer dielectric layer 140 to contact the upper part of the upper source / drain pattern USD. An upper via UV can be provided. The upper via UV can penetrate the second upper dielectric layer 170 to contact the upper active contact UAC. The upper source / drain pattern USD can be electrically connected to the upper power lines UP1, UP2, UP3, or UP4 or the upper signal line US through the upper active contact UAC and the upper via UV, which will be discussed below. The upper active contact UAC and the upper via UV can include a conductive material.

[0066] An upper gate contact UGC can be provided. The upper gate contact UGC can penetrate the gate capping pattern GP, the first upper dielectric layer 160, and the second upper dielectric layer 170 to contact the upper part of the upper electrode UE. The upper electrode UE can be electrically connected to the upper signal line US through the upper gate contact UGC, which will be discussed below. The upper gate contact UGC can include a conductive material. In some example embodiments, the upper gate contact UGC can include a plurality of contacts overlapping each other in the third direction D3.

[0067] The third upper dielectric layer 180 can be provided with a first upper power line UP1, a second upper power line UP2, a third upper power line UP3, a fourth upper power line UP4, and an upper signal line US therein. The second upper power line UP2 and the third upper power line UP3 can be provided between the first upper power line UP1 and the fourth upper power line UP4. The first upper power line UP1, the second upper power line UP2, the third upper power line UP3, the fourth upper power line UP4, and the upper signal line US can include a conductive material.

[0068] The first upper power line UP1, the second upper power line UP2, the third upper power line UP3, the fourth upper power line UP4, and the upper signal line US can extend along the second direction D2. A plurality of upper signal lines US can be provided between two of the upper power lines UP1, UP2, UP3, and UP4, and the two upper power lines are adjacent to each other in the first direction D1. For example, three upper signal lines US can be provided between the first upper power line UP1 and the second upper power line UP2. In some example embodiments, the upper power lines UP1, UP2, UP3, and UP4 can be Vss lines, and the lower power lines LP1, LP2, LP3, and LP4 can be Vdd lines. In some example embodiments, the upper power lines UP1, UP2, UP3, and UP4 can be Vdd lines, and the lower power lines LP1, LP2, LP3, and LP4 can be Vss lines.

[0069] At least one of the upper active contacts UAC can be electrically connected to a plurality of upper power lines UP1, UP2, UP3, and UP4. For example, the upper active contact UAC contacting the fourth source / drain structure SS4 can be electrically connected to the first upper power line UP1 and the second upper power line UP2 through two upper vias UV.

[0070] The spacing between the upper power lines UP1, UP2, UP3, and UP4 in the first direction D1 can be the same as the spacing between the lower power lines LP1, LP2, LP3, and LP4 in the first direction D1. The first upper power line UP1 can overlap with the first lower power line LP1 in the third direction D3. The second upper power line UP2 can overlap with the second lower power line LP2 in the third direction D3. The third upper power line UP3 can overlap with the third lower power line LP3 in the third direction D3. The fourth upper power line UP4 can overlap with the fourth lower power line LP4 in the third direction D3.

[0071] The first gate isolation layer GD1 can overlap with the second lower power line LP2 and the second upper power line UP2 in the third direction D3. The second gate isolation layer GD2 can overlap with the third lower power line LP3 and the third upper power line UP3 in the third direction D3. The third gate isolation layer GD3 can overlap with the lower signal line LS and the upper signal line US in the third direction D3. The third gate isolation layer GD3 can be disposed between the second lower power line LP2 and the third lower power line LP3 and between the second upper power line UP2 and the third upper power line UP3.

[0072] The second upper power line UP2 and the second lower power line LP2 can overlap with the fourth active pattern AP4, the fourth semiconductor pattern SP4, the fourth gate electrode GE4, and the fourth source / drain structure SS4 in the third direction D3. The third upper power line UP3 and the third lower power line LP3 can overlap with the fifth active pattern AP5, the fifth semiconductor pattern SP5, the fifth gate electrode GE5, and the fifth source / drain structure SS5 in the third direction D3.

[0073] The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can not overlap with any of the upper power lines UP1, UP2, UP3, and UP4 and the lower power lines LP1, LP2, LP3, and LP4 in the third direction D3.

[0074] The first semiconductor pattern SP1 may have a first sidewall S1 adjacent to the first upper power line UP1 and a second sidewall S2 opposite to the first sidewall S1. The fourth semiconductor pattern SP4 may have a first sidewall S3 adjacent to the first upper power line UP1 and a second sidewall S4 opposite to the first sidewall S3. In some example embodiments, the first sidewall S1 of the first semiconductor pattern SP1 and the first sidewall S3 of the fourth semiconductor pattern SP4 may be disposed on a straight line extending along the second direction D2. The distance between the third upper power line UP3 and the second sidewall S2 of the first semiconductor pattern SP1 in the first direction D1 may be greater than the distance between the third upper power line UP3 and the second sidewall S2 of the fourth semiconductor pattern SP4 in the first direction D1.

[0075] The third semiconductor pattern SP3 may have a first sidewall S5 adjacent to the fourth upper power line UP4 and a second sidewall S6 opposite to the first sidewall S5. The fifth semiconductor pattern SP5 may have a first sidewall S7 adjacent to the fourth upper power line UP4 and a second sidewall S8 opposite to the first sidewall S7. In some example embodiments, the first sidewall S5 of the third semiconductor pattern SP3 and the first sidewall S7 of the fifth semiconductor pattern SP5 may be disposed on a straight line extending along the second direction D2. The distance between the second upper power line UP2 and the second sidewall S6 of the third semiconductor pattern SP3 in the first direction D1 may be greater than the distance between the second upper power line UP2 and the second sidewall S8 of the fifth semiconductor pattern SP5 in the first direction D1.

[0076] The first upper power line UP1 may include a first portion UP11 adjacent to the first semiconductor pattern SP1 and a second portion UP12 adjacent to the fourth semiconductor pattern SP4. In some example embodiments, the distance between the first sidewall S1 of the first semiconductor pattern SP1 and the first portion UP11 of the first upper power line UP1 in the first direction D1 may be the same as the distance between the first sidewall S3 of the fourth semiconductor pattern SP4 and the second portion UP12 of the first upper power line UP1 in the first direction D1.

[0077] A center line CT1 of the first portion UP11 included in the first upper power line UP1 and a center line CT2 of the second portion UP12 included in the first upper power line UP1 may be defined. The first upper power line UP1 may be configured such that the center line CT1 of the first portion UP11 and the center line CT2 of the second portion UP12 may be disposed on a straight line extending along the second direction D2.

[0078] In some example embodiments, the distance in the first direction D1 between the first sidewall S1 of the first semiconductor pattern SP1 and the centerline CT1 of the first portion UP11 included in the first upper power line UP1 may be the same as the distance in the first direction D1 between the first sidewall S3 of the fourth semiconductor pattern SP4 and the centerline CT2 of the second portion UP12 included in the first upper power line UP1.

[0079] The fourth upper power line UP4 may include a first portion UP41 adjacent to the third semiconductor pattern SP3 and a second portion UP42 adjacent to the fifth semiconductor pattern SP5. In some example embodiments, the distance in the first direction D1 between the first sidewall S5 of the third semiconductor pattern SP3 and the first portion UP41 of the fourth upper power line UP4 may be the same as the distance in the first direction D1 between the first sidewall S7 of the fifth semiconductor pattern SP5 and the second portion UP42 of the fourth upper power line UP4.

[0080] The centerline CT3 of the first portion UP41 included in the fourth upper power line UP4 and the centerline CT4 of the second portion UP42 included in the fourth upper power line UP4 may be defined. The fourth upper power line UP4 may be configured such that the centerline CT3 of the first portion UP41 and the centerline CT4 of the second portion UP42 may be disposed on a straight line extending along the second direction D2.

[0081] In some example embodiments, the distance in the first direction D1 between the first sidewall S5 of the third semiconductor pattern SP3 and the centerline CT3 of the first portion UP41 included in the fourth upper power line UP4 may be the same as the distance in the first direction D1 between the first sidewall S7 of the fifth semiconductor pattern SP5 and the centerline CT4 of the second portion UP42 included in the fourth upper power line UP4.

[0082] The first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, the fourth semiconductor pattern SP4, and the fifth semiconductor pattern SP5 may be disposed between the first upper power line UP1 and the fourth upper power line UP4 and between the first lower power line LP1 and the fourth lower power line LP4.

[0083] The distances in the first direction D1 between the upper power lines UP1, UP2, UP3, and UP4 may be greater than the widths in the first direction D1 of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the distance L3 in the first direction D1 between the second upper power line UP2 and the third upper power line UP3 may be greater than the width W1 in the first direction D1 of the first semiconductor pattern SP1.

[0084] The distance between the upper power lines UP1, UP2, UP3, and UP4 in the first direction D1 can be greater than the width of each of the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 in the first direction D1. For example, the distance L3 between the second upper power line UP2 and the third upper power line UP3 in the first direction D1 can be greater than the width W2 of the fourth semiconductor pattern SP4 in the first direction D1.

[0085] The length of the unit defined by the fourth semiconductor pattern SP4, the fourth source / drain structure SS4, the fourth gate electrode GE4, and the fourth active pattern AP4 in the first direction D1 can be about 1.5 times the length of the unit defined by the first semiconductor pattern SP1, the first source / drain structure SS1, the first source / drain structure SS1, the first gate electrode GE1, and the first active pattern AP1 in the first direction D1.

[0086] In a semiconductor device according to some example embodiments, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 having widths different from those of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can share one or more of the upper wires UP1, UP2, UP3, and UP4 and one or more of the lower wires LP1, LP2, LP3, and LP4. Thus, the number of the upper wires UP1, UP2, UP3, and UP4 and the number of the lower wires LP1, LP2, LP3, and LP4 can be minimized, and thereby, the semiconductor device can be simplified in terms of structure and manufacturing process. In addition, the number of fill units in the semiconductor device can be minimized.

[0087] In a semiconductor device according to some example embodiments, the lengths of the three units defined by the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 having relatively small widths can be the same as the lengths of the two units defined by the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 having relatively large widths. Thus, the transistor frequency caused by the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 can be improved, the area occupied by the units defined by the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 can be minimized, and the density of the semiconductor patterns in the units defined by the fourth semiconductor pattern SP4 and the fifth semiconductor pattern SP5 can be maximized.

[0088] In a semiconductor device according to some example embodiments, at least one of the upper active contacts UAC can be electrically connected to the upper power lines UP1, UP2, UP3, and UP4 through a plurality of upper vias UV. Thus, the loss caused by the resistance of the upper vias UV can be minimized.

[0089] In a semiconductor device according to some example embodiments, at least one of the lower active contacts LAC may be electrically connected to a plurality of lower power lines LP1, LP2, LP3, and LP4 through a plurality of lower vias LV, and thus, losses due to the resistance of the lower vias LV may be minimized.

[0090] Figure 3A A plan view showing a semiconductor device according to some example embodiments is illustrated. Figure 3B A cross-sectional view taken along line Figure 3A A2 - A2' is illustrated. In addition to the following description, Figure 3A and Figure 3B the semiconductor device may be similar to Figures 2A to 2F the semiconductor device.

[0091] Referring to Figure 3A and Figure 3B , the semiconductor device may include a first active pattern AP1a, a second active pattern AP2a, a third active pattern AP3a, a fourth active pattern AP4a, and a fifth active pattern AP5a.

[0092] A first connecting active pattern CAP1a may be provided to connect the first active pattern AP1a and the fourth active pattern AP4a to each other, and a second connecting active pattern CAP2a may be provided to connect the third active pattern AP3a and the fifth active pattern AP5a to each other.

[0093] The first active pattern AP1a, the first connecting active pattern CAP1a, and the fourth active pattern AP4a may be connected without a boundary to form a single integral structure. The first active pattern AP1a, the first connecting active pattern CAP1a, and the fourth active pattern AP4a may have top surfaces coplanar with each other. The width of the first connecting active pattern CAP1a in the first direction D1 may increase in the direction from the first active pattern AP1a toward the fourth active pattern AP4a.

[0094] The first active pattern AP1a may have a first sidewall S1a adjacent to the first upper power line UP1 and a second sidewall S2a opposite to the first sidewall S1a. The fourth active pattern AP4a may have a first sidewall S3a adjacent to the first upper power line UP1 and a second sidewall S4a opposite to the first sidewall S3a. The first connecting active pattern CAP1a may have a first sidewall S5a adjacent to the first upper power line UP1 and a second sidewall S6a connecting the second sidewall S2a of the first active pattern AP1a to the second sidewall S4a of the fourth active pattern AP4a.

[0095] The first sidewall S1a of the first active pattern AP1a, the first sidewall S3a of the fourth active pattern AP4a, and the first sidewall S5a of the first connecting active pattern CAP1a may be coplanar with each other. The first sidewall S1a of the first active pattern AP1a, the first sidewall S3a of the fourth active pattern AP4a, and the first sidewall S5a of the first connecting active pattern CAP1a may be parallel to the second direction D2.

[0096] The second sidewall S6a of the first connecting active pattern CAP1a may be parallel to the fourth direction D4. The fourth direction D4 may intersect the first direction D1, the second direction D2, and the third direction D3. For example, the fourth direction D4 may be a horizontal direction that intersects the first direction D1 and the second direction D2 and is perpendicular to the third direction D3.

[0097] The third active pattern AP3a, the second connecting active pattern CAP2a, and the fifth active pattern AP5a may be connected without boundaries to form a single integral structure. The width of the second connecting active pattern CAP2a in the first direction D1 may increase in the direction from the third active pattern AP3a toward the fifth active pattern AP5a.

[0098] The second connecting active pattern CAP2a may have a first sidewall S7a adjacent to the fourth upper power line UP4 and a second sidewall S8a opposite to the first sidewall S7a. The second sidewall S8a of the second connecting active pattern CAP2a may be parallel to the fifth direction D5. The fifth direction D5 may intersect the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4. For example, the fifth direction D5 may be a horizontal direction that intersects the first direction D1, the second direction D2, and the fourth direction D4 and is perpendicular to the third direction D3.

[0099] The semiconductor device may include a separation dielectric layer 190. The separation dielectric layer 190 may contact the first connecting active pattern CAP1a. The separation dielectric layer 190 may penetrate the dummy gate electrode DG between the first source / drain structure SS1 and the fourth source / drain structure SS4. The separation dielectric layer 190 may define a single diffusion interruption region. The separation dielectric layer 190 may include a dielectric material.

[0100] Figure 4 A cross-sectional view showing a semiconductor device according to some example embodiments is shown. In addition to the following description, Figure 4 the semiconductor device may be similar to Figures 2A to 2F the semiconductor device.

[0101] Referring to Figure 4, a filling dielectric layer FL may be disposed on the second lower dielectric layer 120. The filling dielectric layers FL may be spaced apart from each other across the device isolation layer ST. The lower active contact LAC may penetrate the filling dielectric layer FL in a third direction D3. The first source / drain structure SS1 and the fourth source / drain structure SS4, and the first gate electrode GE1 and the fourth gate electrode GE4 may overlap the filling dielectric layer FL in the third direction D3. The filling dielectric layer FL may include a dielectric material.

[0102] The source / drain structure SS1 or SS4 may be formed on the active pattern, the active pattern may be removed, and then the filling dielectric layer FL may be formed in the empty space where the active pattern has been removed.

[0103] In a semiconductor device according to some example embodiments of the inventive concept, the number of upper wires and the number of lower wires may be minimized, so that the semiconductor device may be simplified in terms of structure and manufacturing process. In addition, the number of filling units in the semiconductor device may be minimized.

[0104] In a semiconductor device according to some example embodiments of the inventive concept, cells defined by semiconductor patterns having a relatively small width and cells defined by semiconductor patterns having a relatively large width may be arranged at a ratio of about 3:2, and thus, transistor frequency may be improved, the area occupied by the cells may be minimized, and the density of the semiconductor patterns may be maximized.

[0105] When the terms “about” or “substantially” are used in conjunction with a numerical value in this specification, it means that the associated numerical value includes a tolerance of ±10% around the stated value. When a range is specified, the range includes all values therebetween, such as increments of 0.1%.

[0106] Although the present invention has been described in connection with some example embodiments of the inventive concept shown in the drawings, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the spirit and basic features of the inventive concept. Accordingly, the example embodiments disclosed above should be considered illustrative rather than restrictive. In addition, the example embodiments discussed above may be combined with each other.

Claims

1. A semiconductor device, comprising: a first upper power line and a second upper power line extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a first semiconductor pattern; a second semiconductor pattern spaced apart from the first semiconductor pattern in the second direction; a third semiconductor pattern spaced apart from the second semiconductor pattern in the second direction; a fourth semiconductor pattern spaced apart from the first semiconductor pattern in the first direction; as well as a fifth semiconductor pattern spaced apart from the third semiconductor pattern in the first direction, wherein the first semiconductor pattern, the second semiconductor pattern, the third semiconductor pattern, the fourth semiconductor pattern, and the fifth semiconductor pattern are between the first upper power line and the second upper power line, wherein the second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern, and The distance between the first semiconductor pattern and the third semiconductor pattern is greater than the distance between the fourth semiconductor pattern and the fifth semiconductor pattern.

2. The semiconductor device according to claim 1, wherein A width of each of the first, second, and third semiconductor patterns in the second direction is smaller than a width of each of the fourth and fifth semiconductor patterns in the second direction.

3. The semiconductor device according to claim 2, wherein: A width of each of the fourth and fifth semiconductor patterns in the second direction is 1.5 to 3 times greater than a width of each of the first, second, and third semiconductor patterns in the second direction.

4. The semiconductor device according to claim 1, further comprising: A third upper power line and a fourth upper power line are between the first upper power line and the second upper power line, wherein the third upper power line overlaps with the fourth semiconductor pattern, and Wherein, the fourth upper power line overlaps with the fifth semiconductor pattern.

5. The semiconductor device according to claim 4, wherein: Each of the third upper power line and the fourth upper power line does not overlap any one of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern.

6. The semiconductor device according to claim 4, wherein: A width of each of the first, second, and third semiconductor patterns in the second direction is smaller than a distance between the third upper power line and the fourth upper power line in the second direction.

7. The semiconductor device according to claim 4, wherein: A width of each of the fourth semiconductor pattern and the fifth semiconductor pattern in the second direction is greater than a distance between the third upper power line and the fourth upper power line in the second direction.

8. A semiconductor device comprising: a first semiconductor pattern; a second semiconductor pattern and a third semiconductor pattern overlapping the first semiconductor pattern in a first direction; a fourth semiconductor pattern, overlapping the first semiconductor pattern in a second direction, the second direction intersecting the first direction; as well as a fifth semiconductor pattern overlapping the third semiconductor pattern in the second direction, wherein the second semiconductor pattern is between the first semiconductor pattern and the third semiconductor pattern, and A width of each of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern in the first direction is smaller than a width of each of the fourth semiconductor pattern and the fifth semiconductor pattern in the first direction.

9. The semiconductor device according to claim 8, further comprising: a first source / drain structure contacting the first semiconductor pattern; a second source / drain structure contacting the second semiconductor pattern; a third source / drain structure contacting the third semiconductor pattern; a fourth source / drain structure contacting the fourth semiconductor pattern; as well as a fifth source / drain structure contacting the fifth semiconductor pattern, wherein each of the first source / drain structure, the second source / drain structure, the third source / drain structure, the fourth source / drain structure, and the fifth source / drain structure comprises an upper source / drain pattern and a lower source / drain pattern, wherein the lower source / drain pattern overlaps with the upper source / drain pattern in a third direction, and Wherein, the third direction intersects with the first direction and the second direction.

10. The semiconductor device according to claim 9, wherein A width of each of the first source / drain structure, the second source / drain structure, and the third source / drain structure in the first direction is smaller than a width of each of the fourth source / drain structure and the fifth source / drain structure in the first direction.

11. The semiconductor device according to claim 9, further comprising: a first upper power line and a second upper power line extending along the second direction; An upper active contact portion contacting the upper source / drain pattern of the fourth source / drain structure; a first upper via connecting the upper active contact to the first upper power line; as well as A second upper via connects the upper active contact to the second upper power line.

12. The semiconductor device according to claim 9, further comprising: a first lower electric force line and a second lower electric force line extending along the second direction; a lower active contact portion contacting the lower source / drain pattern of the fourth source / drain structure; a first lower via connecting the lower active contact to the first lower power line; as well as A second lower via connects the lower active contact to the second lower power line.

13. The semiconductor device according to claim 8, further comprising: an upper electrode and a lower electrode overlapping the first semiconductor pattern; an upper gate contact portion, contacting the upper electrode; A lower gate contact portion, contacting the lower electrode; an upper signal line contacting the upper gate contact portion; as well as A lower signal line contacts the lower gate contact portion.

14. The semiconductor device according to claim 13, wherein: The upper electrode and the lower electrode include conductive materials different from each other.

15. The semiconductor device according to claim 8, further comprising: a first gate electrode overlapping the first semiconductor pattern in a third direction; a second gate electrode overlapping the second semiconductor pattern in the third direction; a third gate electrode overlapping the third semiconductor pattern in the third direction; a fourth gate electrode overlapping the fourth semiconductor pattern in the third direction; as well as a fifth gate electrode overlapping the fifth semiconductor pattern in the third direction, wherein the third direction intersects the first direction and the second direction, and The width of each of the first gate electrode, the second gate electrode and the third gate electrode in the first direction is smaller than the width of each of the fourth gate electrode and the fifth gate electrode in the first direction.

16. A semiconductor device comprising: a first source / drain structure; a first semiconductor pattern contacting the first source / drain structure; a first gate electrode overlapping the first semiconductor pattern; a second source / drain structure spaced apart from the first source / drain structure in a first direction; a second semiconductor pattern contacting the second source / drain structure; a second gate electrode overlapping the second semiconductor pattern; a third source / drain structure, spaced apart from the second source / drain structure in the first direction; a third semiconductor pattern, contacting the third source / drain structure; a third gate electrode, overlapping the third semiconductor pattern; a fourth source / drain structure, spaced apart from the first source / drain structure in a second direction, the second direction intersecting the first direction; a fourth semiconductor pattern, contacting the fourth source / drain structure; a fourth gate electrode, overlapping the fourth semiconductor pattern; a fifth source / drain structure spaced apart from the third source / drain structure in the second direction; a fifth semiconductor pattern contacting the fifth source / drain structure; a fifth gate electrode, overlapping the fifth semiconductor pattern; a first gate separation layer between the first gate electrode and the second gate electrode; a second gate separation layer between the second gate electrode and the third gate electrode; as well as a third gate separation layer, between the fourth gate electrode and the fifth gate electrode, wherein each of the first source / drain structure, the second source / drain structure, the third source / drain structure, the fourth source / drain structure, and the fifth source / drain structure comprises an upper source / drain pattern and a lower source / drain pattern, and Wherein, the third gate separation layer is between the first gate separation layer and the second gate separation layer.

17. The semiconductor device according to claim 16, further comprising: a first upper power line overlapping the first gate separation layer; as well as a second upper electric field line, overlapping the second gate separation layer, The third gate separation layer is between the first upper power line and the second upper power line.

18. The semiconductor device according to claim 17, further comprising: a first lower electric field line overlapping the first gate separation layer; as well as a second lower electric field line, overlapping the second gate separation layer, The third gate separation layer is between the first lower power line and the second lower power line.

19. The semiconductor device according to claim 18, further comprising: an upper signal line between the first upper power line and the second upper power line; as well as a lower signal line between the first lower power line and the second lower power line, The number of the upper signal lines between the first upper power line and the second upper power line is greater than the number of the lower signal lines between the first lower power line and the second lower power line.

20. The semiconductor device according to claim 17, further comprising: a third upper power line and a fourth upper power line spaced apart from each other in the first direction across the first upper power line and the second upper power line, The third upper power line includes a first portion adjacent to the first semiconductor pattern and a second portion adjacent to the fourth semiconductor pattern, and Wherein, a center line of the first portion of the third upper power line and a center line of the second portion of the third upper power line are on a straight line.

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