Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, the solar cell comprises a crystalline silicon substrate, the back surface of the crystalline silicon substrate comprises P-type doped regions and N-type doped regions which are alternately arranged, the P-type doped regions correspond to P-type doped layers, the N-type doped regions correspond to N-type doped layers, isolation channels are arranged between the adjacent P-type doped regions and N-type doped regions, and the P-type doped regions and the N-type doped regions are arranged on the back surface of the crystalline silicon substrate. The side wall, adjacent to the P-type doped region, of the isolation channel is provided with a first boss structure, and the face, away from the side wall, of the first boss structure is provided with at least one second boss structure. The first boss structure and the second boss structure can reduce the hot spot temperature of the photovoltaic module.

Description

Technical Field

[0001] This application relates to the field of solar cells, and particularly to a solar cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts solar energy into electrical energy, and has the advantages of being clean and pollution-free, and has been widely used in the power generation industry.

[0003] Among them, a BC solar cell is a solar cell with no metal grid lines on the front side, and the metal grid lines of the P / N regions are distributed in a finger-like pattern on the back side of the cell. Although the BC solar cell has a high photoelectric conversion efficiency, it is limited by the risk of hot spots after the cell is fabricated into a module, which is likely to cause a decrease in the power of the module. Summary of the Invention

[0004] In order to solve the above technical problems, this application discloses a solar cell and a photovoltaic module to reduce the risk of hot spots at the photovoltaic module end of the BC solar cell.

[0005] In a first aspect, this application provides a solar cell, including: a crystalline silicon substrate, the back side of the crystalline silicon substrate includes alternately arranged P-type doped regions and N-type doped regions, the P-type doped regions correspond to P-type doped layers, the N-type doped regions correspond to N-type doped layers, and an isolation channel is provided between adjacent P-type doped regions and N-type doped regions; wherein: the side wall of the isolation channel adjacent to the P-type doped region has a first boss structure, and at least one second boss structure is provided on a surface of the first boss structure facing away from the side wall.

[0006] In some embodiments of this application, a plurality of the second boss structures are distributed along the extending direction of the isolation channel.

[0007] In some embodiments of this application, the number of the first boss structures is at least one, within a target length L3 along the extending direction of the isolation channel, there are N second boss structures, the sum of the lengths of the N second boss structures is L2, 0.01 ≤ L2 / L3 ≤ 0.8, and N ≥ 1.

[0008] In some embodiments of this application, along the extending direction of the side wall, the width of the first boss structure is W1, the width of the second boss structure is W2, and 1.05 ≤ W1 / W2 ≤ 2.

[0009] In some embodiments of this application, the widest width of the second boss structure is Wmax, and 0.5 μm ≤ Wmax ≤ 5 μm.

[0010] In some embodiments of the present application, the surface of the isolation channel has a first matte structure, the height difference between the second boss structure and the P-type doped layer is H1, the height difference between the second boss structure and the first matte structure is H2, 0.3μm ≤ H1 ≤ 3μm, and / or, 2μm ≤ H2 ≤ 8μm.

[0011] In some embodiments of the present application, 0.2 ≤ H1 / H2 ≤ 1.

[0012] In some embodiments of the present application, the side wall of the isolation channel adjacent to the P-type doped region further has a reflective support arm.

[0013] In a second aspect, the present application provides a photovoltaic module, which includes the solar cell as described in the first aspect.

[0014] Compared with the prior art, the present application has at least the following beneficial effects: The present application provides a solar cell and a photovoltaic module. The solar cell includes a crystalline silicon substrate. The back surface of the crystalline silicon substrate includes alternately arranged P-type doped regions and N-type doped regions. The P-type doped regions correspond to P-type doped layers, and the N-type doped regions correspond to N-type doped layers. An isolation channel is provided between adjacent P-type doped regions and N-type doped regions. The side wall of the isolation channel adjacent to the P-type doped region has a first boss structure, and at least one second boss structure is provided on the side of the first boss structure facing away from the side wall, so that the solar cell forms a dispersed leakage current region in the second boss structure containing the N-type doped conductive type and the P-type doped layer, thereby reducing the hot spot temperature of the photovoltaic module. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 It is a schematic structural diagram of a crystalline silicon substrate according to an embodiment of the present application; Figure 2 It is a schematic structural diagram of a solar cell according to an embodiment of the present application; Figure 3 It is a scanning electron microscope (SEM) image of the back surface of a solar cell according to an embodiment of the present application; Figure 4 It is a schematic structural diagram of a semi-finished solar cell according to another embodiment of the present application; Figure 5 It is an SEM image of the back surface of a solar cell according to another embodiment of the present application; Figure 6 It is a schematic diagram when observed along the positive projection direction of the second boss structure relative to the side wall; Figure 7 It is a schematic diagram of the structure of a semi-finished solar cell according to another embodiment of the present application; Figure 8 It is a schematic diagram of the structure of a solar cell according to another embodiment of the present application; Figure 9 It is a schematic diagram of the structure of a semi-finished solar cell after the first coating treatment of the present application; Figure 10 It is a schematic diagram of the structure of a semi-finished solar cell after the first patterning treatment of the present application; Figure 11 It is a schematic diagram of the structure of a semi-finished solar cell after the second coating treatment of the present application; Figure 12 It is a schematic diagram of the structure of a semi-finished solar cell after the second patterning treatment of the present application; Figure 13 It is a schematic diagram of the flow direction of the texturing solution of the present application; Figure 14 It is a schematic diagram of the structure of a semi-finished solar cell after texturing of the present application.

[0017] Explanation of reference numerals: crystalline silicon substrate - 1, P-type doping layer - 2, N-type doping layer - 3, isolation channel - 4, first boss structure - 5, second boss structure - 6, first tunneling oxide layer - 7, second tunneling oxide layer - 8, side wall - 9, first textured structure - 10, first passivation layer - 11, first antireflection layer - 12, second passivation layer - 13, second antireflection layer - 14, electrode grid line - 15, reflective support arm - 16, first masking oxide layer - 21, second masking oxide layer - 22, second textured structure - 23, first patterned area - 31, second patterned area - 32, etching blind area - 312. Detailed implementation manners

[0018] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0019] In this application, the orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", "vertical", "horizontal", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe this application and its embodiments, and are not used to limit that the indicated device, element or component must have a specific orientation, or be constructed and operated in a specific orientation.

[0020] Moreover, in addition to being used to represent the orientation or positional relationship, some of the above terms may also be used to represent other meanings. For example, the term "upper" may also be used to represent a certain attachment relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this application can be understood according to specific circumstances.

[0021] In addition, the terms "mounted", "arranged", "provided with", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there can be internal communication between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] In addition, terms such as "first", "second", etc. are mainly used to distinguish different devices, elements or components (the specific types and structures may be the same or different), and are not used to indicate or imply the relative importance and quantity of the indicated devices, elements or components. Unless otherwise specified, the meaning of "a plurality" is two or more.

[0023] Next, the technical solutions of this application will be further described in conjunction with embodiments and drawings.

[0024] In this application, as Figure 1 shown, the extension direction along the main gate electrode is defined as the x-direction, the extension direction along the sub-gate electrode is defined as the y-direction, that is, the extension direction along the isolation channel is the y-direction, and the height direction of the crystalline silicon substrate 1 is defined as the z-direction.

[0025] This application provides a solar cell. Figure 2 It is a schematic structural diagram of a solar cell according to an implementation scheme of this application, as Figure 2As shown, the solar cell includes a crystalline silicon substrate 1. The back surface of the crystalline silicon substrate 1 includes alternately arranged P-type doped regions and N-type doped regions. The P-type doped regions correspond to P-type doped layers 2, and the N-type doped regions correspond to N-type doped layers 3. An isolation channel 4 is provided between adjacent P-type doped regions and N-type doped regions. Among them: The side wall 9 of the isolation channel 4 adjacent to the P-type doped region has a first boss structure 5. At least one second boss structure 6 is provided on the surface of the first boss structure 5 facing away from the side wall 9. The first boss structure and the second boss structure have electrical conductivity. In addition, a first tunneling oxide layer 7 is provided on the back surface of the crystalline silicon substrate 1 in the P-type doped region, and the P-type doped layer 2 is provided on the surface of the first tunneling oxide layer 7; a second tunneling oxide layer 8 is sequentially provided on the back surface of the crystalline silicon substrate 1 in the N-type doped region, and the N-type doped layer 3 is provided on the surface of the second tunneling oxide layer 8. Among them, the second boss structure 6 includes a doped layer of N-type conductive type.

[0026] In this application, the first boss structure 5 and at least one second boss structure 6 can disperse the leakage current in the hot spot effect. This is because: When the second boss structure 6 forms a connection path with the P-type doped layer 2 in a local area of the side wall 9, and when the photovoltaic module appears conditions that can cause the hot spot effect, the N-type doped layer in the second boss structure 6 just forms a leakage conduction structure with the P-type doped layer 2. Therefore, the effect of reducing the hot spot temperature of the photovoltaic module can be achieved.

[0027] The material of the first tunneling oxide layer and / or the second tunneling oxide layer of the present application may include various dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polysilicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the first tunneling oxide layer and / or the second tunneling oxide layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation performance, can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate, and is a film with excellent durability for subsequent high-temperature processes. In order to better provide interface passivation for the substrate, the thickness of the first tunneling oxide layer and / or the second tunneling oxide layer may be 0.1 nm to 5 nm. For example, the thickness of the first tunneling oxide layer and / or the second tunneling oxide layer may be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc. However, the present application is not limited thereto, and the thickness of the first tunneling oxide layer and / or the second tunneling oxide layer may have various values. The first tunneling oxide layer and / or the second tunneling oxide layer, as a kind of barrier for electrons and holes, can combine with the polysilicon layer to prevent minority carriers from passing through. The first tunneling oxide layer and / or the second tunneling oxide layer may also have the function of pinhole channels, enabling the carriers in the solar cell to move freely, generating selective passage for majority carriers through heavily doped polysilicon, which is beneficial to reducing the recombination loss of minority carriers. In addition, the first tunneling oxide layer and / or the second tunneling oxide layer can be used as a diffusion barrier to prevent the dopant in the doped polysilicon layer from diffusing into the semiconductor substrate.

[0028] The thickness of the crystalline silicon substrate of the present application is 100 μm to 200 μm, and the present application does not make specific limitations.

[0029] In some embodiments of the present application, as shown in the regions indicated by the dotted boxes in Figure 3 , a plurality of second boss structures 6 are distributed along the extension direction of the sub-grid electrode, and this direction is the y direction. In the present application, a plurality of second boss structures 6 may be arranged at intervals along the y direction on the side of the first boss structure 5 facing away from the sidewall 9. Thus, when a connection path is formed between the second boss structure 6 and the P-type doping layer 2 in a local region of the sidewall 9, and when the conditions for the hot spot effect of the photovoltaic module occur, the N-type doping layer in the second boss structure 6 just forms a leakage conduction structure with the P-type doping layer 2. In addition, along the y direction, the first boss structures 5 may be continuously distributed on the surface of the sidewall 9.

[0030] In some embodiments of the present application, the number of the first boss structures is at least one. Referring to Figure 4 , a plurality of first boss structures 5 and a plurality of second boss structures 6 are provided on the sidewall 9. Within the target length L3 along the extension direction of the sub-grid electrode, that is, within the target length L3 along the y direction, there are N second boss structures 6, and the length of the first second boss structure is L21 , the length of the second second boss structure is L2 2 , and so on, the length of the (N - 1)th second boss structure is L2 （N-1） , the length of the Nth second boss structure is L2 N , then the sum of the lengths of these N second boss structures is L2, where 0.01 ≤ L2 / L3 ≤ 0.8, N ≥ 1. By adjusting L2 / L3 within the above range, it is beneficial to achieve a uniform leakage current distribution. When there is an occlusion in the photovoltaic module that causes the hot spot effect, it is possible to evenly disperse the heat generated by the hot spot, and thus no local heat concentration phenomenon occurs, reducing the thermal stress caused by heat concentration and the reliability risk of related components; in addition, the hot spot temperature of the photovoltaic module can also be reduced. The value of L3 in this application can be, for example, 1μm, 2μm, 5μm or 20μm. In this application, the target length L3 refers to the length of the crystalline silicon substrate of the solar cell along the y direction within the field of view in the SEM image of the solar cell.

[0031] In some embodiments of the present application, referring to Figure 5 , along the extension direction of the side wall 9, the width of the first boss structure is W1, and the width of the second boss structure is W2, 1.05 ≤ W1 / W2 ≤ 2.0. For example, W1 / W2 is 1.05, 1.2, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.0. By controlling W1 / W2 within the above range, a leakage current conduction structure is formed between the second boss structure 6 containing N-type doping atoms and the P-type doping layer 2 in the direction away from the crystalline silicon substrate 1, thereby forming a leakage current region with an appropriate area range, and the conversion efficiency of the solar cell will not be reduced due to an overly large leakage current dispersion region, nor will the technical effect of effectively reducing the hot spot temperature of the photovoltaic module not be achieved due to an overly small leakage current dispersion region.

[0032] In some embodiments of the present application, referring to Figure 6 , when observing along the direction of the orthogonal projection of the second boss structure with respect to the side wall 9, the widest width of the second boss structure 6 is Wmax, 0.5μm ≤ Wmax ≤ 5μm. For example, Wmax is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm or 5μm. In this application, the widest width of the second boss structure refers to the dimension of the widest part of the second boss structure when observing along the direction of the projection of the second boss structure with respect to the side wall perpendicular to it.

[0033] In some embodiments of the present application, referring to Figure 7, the surface of the isolation trench 4 has a first matte structure 10. The height difference between the second boss structure 6 and the P-type doped layer is H1, and the height difference between the second boss structure 6 and the first matte structure 10 is H2, where 0.3μm ≤ H1 ≤ 3μm and 2μm ≤ H2 ≤ 8μm. For example, H1 is 0.3μm, 0.5μm, 1μm, 1.5μm, 2μm, or 3μm; H2 is 2μm, 4μm, 5μm, 6μm, or 8μm. In this application, the height difference between the second boss structure and the P-type doped layer means: along the z direction, selecting a cross-sectional view of any isolation trench, the distance between the center of the second boss structure and the bottom of the P-type doped layer; the height difference between the second boss structure and the first matte structure means: along the z direction, the distance between the center of the second boss structure and the bottom of the first matte structure. It should be noted that the center of the second boss refers to: referring to Figure 7 , the center point of the second boss structure along the extending direction of the sidewall 9. When H1 and H2 are too small, a larger conduction region is formed between the second boss structure and the P-type doped region, and the solar cell is prone to leakage regions; when H1 and H2 are too large, it indicates that the action time of the alkali treatment in the first patterning process is longer, resulting in the complete reaction of the first mask oxide layer, and it cannot provide mask protection for the layer structure covered by the first mask oxide layer. Or, when the action time of the alkali treatment in the first patterning process is longer, the depth of corrosion of the crystalline silicon substrate is too deep, which is not conducive to improving the overall mechanical strength of the solar cell wafer, increasing the defect rate in the subsequent process, especially increasing the fragmentation rate of the solar cell wafer. By controlling H1 and H2 within the above ranges, a leakage current region is formed between the second boss structure 6 of the N-type doped conductive type and the P-type doped layer 2 in the solar cell, thereby reducing the hot spot temperature of the photovoltaic module; secondly, sufficient mask protection can also be reserved for the layer structure covered by the first mask oxide layer; moreover, controlling the action duration of the alkali treatment in the first patterning process can avoid the over-deep corrosion depth of the crystalline silicon substrate, thereby reducing the process defect rate of the solar cell.

[0034] In some embodiments of the present application, 0.2 ≤ H1 / H2 ≤ 1. For example, H1 / H2 is 0.2, 0.3, 0.4, 0.5, 0.6, 0.8, or 1. By controlling H1 / H2 within the above range, it is beneficial to form an isolation trench with a good insulation isolation effect and improve the light utilization rate on the back of the solar cell.

[0035] In some embodiments of the present application, referring to Figure 8 , the sidewall 9 of the isolation trench 4 adjacent to the P-type doped region further has a reflective arm 16. The reflective arm is used to reflect the light emitted from the isolation trench back into the crystalline silicon substrate, thereby improving the light utilization rate of the solar cell.

[0036] In some embodiments of the present application, reference is made to Figure 8 , on the back surface of the crystalline silicon substrate 1, a first passivation layer 11 and a first antireflection layer 12 are sequentially provided. The front surface of the crystalline silicon substrate 1 has a second textured structure 23. On the front surface of the crystalline silicon substrate 1, a second passivation layer 13 and a second antireflection layer 14 are sequentially provided. In addition, electrode grid lines 15 are respectively provided in the P-type doping region and the N-type doping region.

[0037] In the present application, the preparation process of the solar cell may be as follows: First coating treatment: Provide a polished crystalline silicon substrate, and use low-pressure chemical vapor deposition (LPCVD) to sequentially deposit a first tunneling oxide layer and a first intrinsic amorphous silicon layer on the back surface of the crystalline silicon substrate. The thickness of the first tunneling oxide layer is 0.5 nm to 3 nm, and the thickness of the first intrinsic amorphous silicon layer is 100 nm to 300 nm; then the first intrinsic amorphous silicon layer is doped by thermal diffusion. For example, 3 is used as the doping source to obtain a P-type doping layer with a thickness of 200 nm to 400 nm, and a first mask oxide layer with a thickness of 20 nm to 60 nm is formed on the surface of the P-type doping layer. The semi-finished structure of the solar cell obtained after the first coating treatment is as Figure 9 shown. On the back surface of the crystalline silicon substrate 1 are sequentially the first tunneling oxide layer 7, the P-type doping layer 2, and the first mask oxide layer 21. The CVD process of the present application includes but is not limited to processes such as low-pressure chemical vapor deposition (LPCVP) and plasma-enhanced chemical vapor deposition (PECVD).

[0038] First patterning treatment: Perform a first patterning treatment on the semi-finished solar cell after the first coating treatment to remove part of the first mask oxide layer 21; then use an alkali solution to perform an alkali wet treatment on the semi-finished solar cell to form Figure 10 the first patterned region 31 as shown, and form a reflective arm, which can be considered as the part of the P-type doping layer that is not etched away by the alkali solution. The first patterned region 31 is used to form an N-type doping region and an isolation channel in subsequent processes, and the regions on both sides of the first patterned region are used to form a P-type doping region in subsequent processes. Among them, the first patterning treatment can adopt a laser etching method, or dry etching or wet etching under the action of a mask template, and there is no special limitation in the present application. The alkali solution can be a sodium hydroxide (NaOH) solution or a potassium hydroxide (KOH) solution, the concentration of the alkali solution is 8 wt% to 12 wt%, the process temperature is 80 °C to 90 °C, and the process time is 100 s to 200 s. The laser-related parameters of the present application can be: according to the pulse width of the laser, at least one of nanosecond, picosecond, and femtosecond, and according to the wavelength emitted by the laser, the laser is any one of infrared, visible light, and ultraviolet.

[0039] Second coating process: By using the CVD method, a second tunneling oxide layer and a second intrinsic amorphous silicon layer are sequentially deposited on the patterned area and the non-patterned area on the back of the semi-finished solar cell after the first patterning process. The thickness of the second tunneling oxide layer is 0.5 nm to 3 nm, and the thickness of the second intrinsic amorphous silicon layer is 100 nm to 300 nm. Then, the second intrinsic amorphous silicon layer is doped by means of thermal diffusion. For example, using PH 3 as the doping source, an N-type doped layer with a thickness of 200 nm to 400 nm is obtained, and a second mask oxide layer with a thickness of 20 nm to 60 nm is formed on the surface of the N-type doped layer. The structure of the semi-finished solar cell obtained after the second coating process is as shown in Figure 11 . On the back of the crystalline silicon substrate 1 are, in sequence, the second tunneling oxide layer 8, the N-type doped layer 3, and the second mask oxide layer 22.

[0040] Second patterning process: The semi-finished solar cell is subjected to a second patterning process to remove part of the second mask oxide layer 22, forming the second patterned area 32 as shown in Figure 12 .

[0041] The second patterning process can adopt the laser etching method, or dry etching or wet etching under the action of a mask template. There is no special limitation in this application. The laser-related parameters in this application can be: according to the pulse width of the laser, at least one of nanosecond, picosecond, and femtosecond, and according to the wavelength emitted by the laser, the laser is any one of infrared, visible light, and ultraviolet.

[0042] Texturing: The front of the semi-finished solar cell after the second patterning process is subjected to acid polishing to remove the wrap-around coating, and then the front of the semi-finished solar cell is textured. At the same time, the N-type doped layer 3, the second tunneling oxide layer 8, and the crystalline silicon substrate in the second patterned area 32 on the back are etched using a texturing chemical solution. The process temperature is 65 °C to 80 °C, and the process time is 400 s to 700 s. Since after the first patterning process, when observing along the y direction, the first patterned area 31 with an inverted trapezoidal cross-section is formed, and after the second patterning process, the second patterned area 32 is formed. Affected by the above-mentioned patterned areas, the texturing chemical solution flows along Figure 13Etch the back of the semi-finished solar cell in the direction of the arrow shown, and form an etch blind area 312 within the first patterned area 31; meanwhile, the second mask oxide layer 22 of the first patterned area 31 will protect the second tunneling oxide layer 8 and the N-type doped layer 3 below it, so that the texturing solution flows into the crystalline silicon substrate from the second patterned area 32 for etching. When the etch depth ratio is too low (for example, lower than 0.5), on the one hand, it will cause incomplete etching in the first patterning process and become a recombination center, and on the other hand, it will cause over-etching phenomena in the P-type doped and N-type doped regions during the texturing process and reduce the thickness of the cell in the isolation channel region, affecting the comprehensive performance of the device; when the etch depth ratio is too high (for example, higher than 0.8), the wetting reaction of the texturing solution to the etched area is insufficient, which will cause the areas of the first boss structure and the second boss structure to be too large, and even directly connect to the P-type doped region to form a continuous leakage structure, greatly reducing the conversion efficiency of the solar cell. By controlling the etch depth ratio to be 0.5 - 0.8, the first boss structure and the second boss structure of the present application are formed. Among them, the first boss structure is formed based on the crystalline silicon substrate after being etched, and the second boss structure is formed based on the N-type doped layer after being etched.

[0043] In the present application, the etch depth ratio is expressed as: H3 / H4. Among them, refer to Figure 7 , H3 is the height difference between the highest point of the P-type doped region and the highest point of the N-type doped region; H4 is the height difference between the highest point of the N-type doped region and the lowest point of the isolation channel region.

[0044] The texturing solution of the present application includes an alkali, lignin, an antifoaming agent, and a wetting agent. Among them, the content of the alkali in the texturing solution is 0.8 wt% - 2 wt%, the content of lignin in the texturing solution is 0.001 wt% - 0.03 wt%, the content of the antifoaming agent in the texturing solution is 0.001 wt% - 0.03 wt%, and the content of the wetting agent in the texturing solution is 0.001 wt% - 0.03 wt%. The alkali includes at least one of NaOH and KOH. By controlling the content of the wetting agent within the above range, the surface tension between the texturing solution and the crystalline silicon substrate can be reduced, and the surface contact effect of the texturing solution on the narrow space formed by the isolation channel 4 can be promoted, especially the narrow space formed below the positive projection of the reflective arm 16 and the reflective arm 16, which is not conducive to the exchange of macromolecular substances in the solution, and is beneficial to the formation of the first boss structure and the second boss structure of the present application. Among them, the above wetting agent includes, but is not limited to, non-ionic wetting agents, anionic wetting agents, or cationic wetting agents. For example, it includes at least one of polyoxyethylene, polyoxypropylene, sodium sulfate, sodium phosphate, dodecyl trimethyl ammonium chloride, and sodium dodecyl sulfonate.

[0045] After texturing, refer to Figure 14, on the back surface of the semi-finished solar cell, a first boss structure 5 and a second boss structure 6 are formed on the surface of the side wall 9 adjacent to the P-type doping region in the isolation trench 4, and a first textured structure 10 is formed on the surface of the crystalline silicon substrate in the isolation trench 4; on the front surface of the semi-finished solar cell, a second textured structure is formed on the surface of the crystalline silicon substrate.

[0046] Preparation of the functional layer and the electrode grid lines: By using the CVD method, an aluminum oxide layer is deposited on the front and back surfaces of the textured semi-finished solar cell as a passivation layer, and then a silicon nitride layer and / or a silicon oxynitride layer and / or a silicon oxide layer are deposited on the surface of the passivation layer on the front and back surfaces respectively as an antireflection layer. Among them, referring to Figure 8 , the thickness of the first passivation layer 11 is 3 nm to 8 nm, and the thickness of the first antireflection layer 12 is 60 nm to 90 nm; the thickness of the second passivation layer 13 is 3 nm to 8 nm, and the thickness of the second antireflection layer 14 is 80 nm to 110 nm; On the back surface of the semi-finished solar cell with the functional layer, the electrode paste is coated on the antireflection layer by screen printing, and then sintered, referring to Figure 8 , to form the electrode grid lines 15.

[0047] The present application does not particularly limit the method for regulating the sizes of the first boss structure and the second boss structure, as long as the purpose of the present application can be achieved. Exemplarily, in the above-mentioned texturing process, the sizes of the first boss structure (such as length and / or width) and the second boss structure (such as width) can be controlled by controlling the etching depth ratio and / or the content of the wetting agent in the texturing solution.

[0048] The present application provides a photovoltaic module, and the photovoltaic module includes the solar cell described in any of the above embodiments.

[0049] The present application also provides a photovoltaic module, and the photovoltaic module is used to convert the received light energy into electrical energy and transmit it to an external load. The photovoltaic module includes: at least one battery string, which is formed by connecting a plurality of the above-mentioned solar cells; an encapsulation adhesive film, which is used to cover the surface of the battery string; and a cover plate, which is used to cover the surface of the encapsulation adhesive film facing away from the battery string.

[0050] For the photovoltaic module of the present application, since the solar cell therein has a smaller risk of leakage current, the risk of hot spots in the photovoltaic module is accordingly reduced.

[0051] Examples The following further describes the solar cell and the photovoltaic module of the present application in combination with more specific examples.

[0052] Example 1 <The first coating treatment> Provide a polished crystalline silicon substrate (with a thickness of 120 μm). Using the LPCVD method, a first tunneling oxide layer and a first intrinsic amorphous silicon layer are sequentially deposited on the back surface of the crystalline silicon substrate. Then, by means of thermal diffusion, using BCl 3 as a doping source to dope the first intrinsic amorphous silicon layer, a P-type doped layer is obtained, and a first masking oxide layer is formed on the surface of the P-type doped layer. The main component of the first masking oxide layer is silicon oxide. The structure of the solar cell semi-finished product obtained after the first coating treatment is as Figure 9 shown.

[0053] <First patterning process> Adopt the laser etching method to perform the first patterning process on the solar cell semi-finished product after the first coating treatment to remove part of the first masking oxide layer; then use an alkaline solution to perform wet alkaline treatment on the solar cell semi-finished product. The structure of the solar cell semi-finished product obtained after the first patterning process is as Figure 10 shown.

[0054] <Second coating treatment> Using the CVD method, a second tunneling oxide layer and a second intrinsic amorphous silicon layer are sequentially deposited on the patterned area and the non-patterned area on the back surface of the solar cell semi-finished product after the first patterning process. Then, by means of thermal diffusion, using PH 3 as a doping source to dope the second intrinsic amorphous silicon layer, an N-type doped layer is obtained, and a second masking oxide layer is formed on the surface of the N-type doped layer. The main component of the second masking oxide layer is silicon oxide. The structure of the solar cell semi-finished product obtained after the second coating treatment is as Figure 11 shown.

[0055] <Second patterning process> Perform the second patterning process on the solar cell semi-finished product to remove part of the second masking oxide layer and form a second patterned area. The structure of the solar cell semi-finished product obtained after the second patterning process is as Figure 12 shown.

[0056] <Texturing> Perform acid polishing on the front surface of the solar cell semi-finished product after the second patterning process to remove the overplating layer, and then perform texturing treatment on the front surface of the solar cell semi-finished product. At the same time, use the texturing solution to etch the N-type doped layer, the second tunneling oxide layer and the crystalline silicon substrate in the second patterned area on the back surface, and control the etching depth ratio to be 0.75. Thus, on the back surface of the solar cell semi-finished product, a first boss structure 5 and a second boss structure 6, and a reflective support arm 16 are formed on the side wall surface adjacent to the P-type doped area in the isolation trench, and a first textured surface structure is formed on the surface of the crystalline silicon substrate in the isolation trench 4; on the front surface of the solar cell semi-finished product, a second textured surface structure is formed on the surface of the crystalline silicon substrate. The structure of the solar cell semi-finished product obtained after texturing is asFigure 14 As shown. In the texturing solution, the content of NaOH is 0.9 wt%, the content of lignin is 0.005 wt%, the content of defoamer is 0.003 wt%, the content of wetting agent is 0.003 wt%, and the wetting agent is sodium dodecyl sulfonate.

[0057] <Preparation of Functional Layer and Electrode Grid Lines> Using ALD, an aluminum oxide layer is deposited on the front and back of the semi-finished solar cell after texturing as a passivation layer, and then a silicon nitride layer is deposited on the surface of the passivation layer on the front and back respectively as an antireflection layer; on the back of the semi-finished solar cell with a functional layer, the electrode paste is applied to the P-type doping region and the N-type doping region by screen printing, and then sintered to form electrode grid lines, obtaining a solar cell. The structure of the solar cell is as Figure 8 shown.

[0058] The above has introduced a solar cell and a photovoltaic module disclosed in the present application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and the core invention point of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A solar cell, characterized in that: include: A crystalline silicon substrate, wherein the back side of the crystalline silicon substrate comprises alternately arranged P-type doping regions and N-type doping regions, wherein the P-type doping regions correspond to the P-type doping layers, and the N-type doping regions correspond to the N-type doping layers, and an isolation channel is provided between adjacent P-type doping regions and N-type doping regions; in: The side wall of the isolation channel adjacent to the P-type doping region has a first boss structure, and at least one second boss structure is arranged on a side of the first boss structure facing away from the side wall.

2. The solar cell according to claim 1, characterized in that: A plurality of the second boss structures are distributed along an extending direction of the isolation trench.

3. The solar cell according to claim 1, characterized in that: The number of the first boss structure is at least one, and within the target length L3 along the extension direction of the isolation channel, there are N second boss structures, the sum of the lengths of the N second boss structures is L2, 0.01≤L2 / L3≤0.8, N≥1.

4. The solar cell according to claim 1, characterized in that: Along the extension direction of the side wall, the width of the first boss structure is W1, the width of the second boss structure is W2, and 1.05≤W1 / W2≤2.

5. The solar cell according to claim 1, characterized in that: The widest width of the second boss structure is Wmax, and 0.5 μm≤Wmax≤5 μm.

6. The solar cell according to claim 1, characterized in that: The surface of the isolation channel has a first velvet structure, the height difference between the second boss structure and the P-type doping layer is H1, the height difference between the second boss structure and the first velvet structure is H2, 0.3μm≤H1≤3μm, and / or, 2μm≤H2≤8μm.

7. The solar cell according to claim 6, characterized in that: 0.2≤H1 / H2≤1.

8. The solar cell according to claim 1, characterized in that: The side wall of the isolation channel adjacent to the P-type doping region also has a reflective arm.

9. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to any one of claims 1 to 8.

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