Double-lineation interconnection type solar cell structure and preparation method thereof

Abstract

The invention discloses a double-lineation interconnection type solar cell structure and a preparation method thereof. The preparation method comprises the following steps: 1) selecting a substrate and forming a first electrode layer; (2) forming a P1 scribing line; 3) depositing a semiconductor device layer; 4) depositing a second electrode layer; 5) forming a P2 scribing line; and 6) forming a grid line network. On one hand, on the basis of processing of two etching processes, the width of a dead zone can be reduced so as to increase the effective power generation area of the assembly, reduce transverse resistance and improve the carrier collection efficiency, the number of the etching lines is reduced, the process is simplified, and the production efficiency is improved; on the other hand, based on the formed grid line structure, the thickness of the TCO layer is effectively reduced by about 30%-70%, the light absorption loss of the window layer is effectively reduced, the overall efficiency of the cell is improved, meanwhile, the material consumption of the TCO layer is greatly reduced, and the cost is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of solar cells, and particularly relates to a double-scribed interconnected solar cell structure, and also relates to a preparation method of the double-scribed interconnected solar cell structure. Background Art

[0002] At present, for large-area thin-film solar cell modules, three scribing and interconnecting processes are basically required to meet the actual use requirements. Briefly speaking, generally, for thin-film solar cell modules, after the large-area cells are divided into several sub-cell units by laser scribing, they are then interconnected. The specific process (combined Figure 1 as shown) is as follows: First, the first electrode layer 2' on the substrate 1' is scribed into several small sections to form P1 scribing; then the semiconductor device layer 3' (generally including P / N type functional layers, an intrinsic absorption layer, N / P type functional layers) is deposited; then, on one side of the P1 scribing at a distance as small as possible, the semiconductor device layer 3' is scribed in parallel the same number of times to form P2 scribing; finally, after the second electrode layer 4' is deposited, on one side of the P2 scribing at a distance as small as possible, the device layer is scribed in parallel the same number of times to form P3 scribing. In this way, the entire large-area cell forms a series structure of several sub-cells. However, this scribing and segmentation interconnection method has the following problems: 1) For each sub-cell, an area that does not generate electricity is formed between the P1 scribing and the P3 scribing, which is also called a dead zone. Among them, the device area between P2 and P3 is in a short-circuit state and belongs to an invalid area after being blocked by P3. Therefore, the existence of this dead zone directly reduces the effective power generation area, reduces the number of photo-generated carriers, resulting in a decrease in the short-circuit current (Isc). At the same time, lattice defects or impurities near the dead zone form recombination centers, accelerating the recombination of electron-hole pairs and reducing the open-circuit voltage (Voc) and fill factor (FF); 2) The second electrode layer generally uses a transparent conductive oxide layer (abbreviated as TCO layer), and its conductivity is 1-2 orders of magnitude lower than that of metals. In particular, the lateral transfer resistance is relatively large, resulting in a relatively large series resistance of the module. Under a large-current design, the internal loss wind field of the module is high. In other words, generally, in order to achieve better carrier collection efficiency and lower transfer resistance, it is necessary to minimize the section width to obtain a smaller output current. Then, it is necessary to significantly increase the thickness of the TCO layer (the conductivity is proportional to the TCO thickness). In this way, not only does it significantly increase the number of scribed lines, increase the difficulty of equipment manufacturing and process control, but also limits the output characteristics of the module to a large voltage and a small current; moreover, it prolongs the TCO process time, increases the material consumption, increases the cost, and at the same time, the increase in the TCO layer thickness increases the light absorption accordingly, resulting in an increase in light absorption loss and a loss of the battery output power. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a brand-new double-scribed interconnected solar cell structure.

[0004] Meanwhile, the present invention also relates to a preparation method of a double-scribed interconnected solar cell structure.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A preparation method of a double-scribed interconnected solar cell structure, which includes the following steps: 1) Select a substrate and deposit a first electrode layer on the substrate; 2) Scratch a P1 scribing line on the first electrode layer, and the scratching depth is the thickness of the first electrode layer; 3) Deposit a semiconductor device layer on the first electrode layer and the substrate, wherein the semiconductor device layer fills the scribed area, and the surface of the semiconductor device layer is flat; 4) Deposit a second electrode layer on the surface of the semiconductor device layer; 5) Taking the P1 scribing line as a parallel reference, form a P2 scribing line that is recessed from the second electrode layer to the first electrode layer near the P1 scribing line, and the scribing depth is the sum of the thicknesses of the second electrode layer and the semiconductor device layer; 6) Form metal strips and grid lines on the P2 scribing line and the second electrode layer respectively, wherein the metal strips and the grid lines constitute a surface grid line network, the metal strips are located in the scribing grooves of the P2 scribing line, and the metal strips are respectively attached to the side edges of the scribing grooves and the adjacent grid lines from the same side, and the other side of the metal strip is separated from the other side of the scribing groove to form a spacer area.

[0006] Preferably, in step 1), the substrate material is an inorganic non-metal, a metal or a polymer, wherein the inorganic non-metal includes rigid glass and flexible glass; the metal includes stainless steel, aluminum alloy and titanium; the polymer includes polyethylene terephthalate, polyethylene naphthalate, polyimide, parylene and polycarbonate. In short, the substrate material includes but is not limited to inorganic non-metals, metals or polymers, such as rigid glass, ultra-thin flexible glass for inorganic non-metals; stainless steel (SS), aluminum alloy (Al), titanium (Ti) for metals; polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), parylene, polycarbonate (PC), etc. for polymers.

[0007] According to a specific implementation and preferred aspect of the present invention, in step 1), the material of the first electrode layer is a transparent conductive oxide; the deposition method of the first electrode layer includes any one or a combination of at least two of vacuum evaporation, magnetron sputtering, reactive plasma deposition, and chemical vapor deposition; the thickness of the first electrode layer is 10-1000 nm.

[0008] Preferably, the material of the first electrode layer is any one or a combination of at least two of fluorine-doped tin oxide, indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, indium tungsten oxide, tin titanium indium oxide, boron-doped zinc oxide, and indium cerium oxide; and / or, the material of the first electrode layer is a metal oxide, and the conductive metal in the metal oxide includes one or a combination of at least two of copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese. In short, the material of the first electrode layer can be a transparent conductive oxide (TCO) including but not limited to any one or a combination of at least two of FTO (fluorine-doped tin oxide), ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), IWO (indium tungsten oxide), ITIO (tin titanium indium oxide), BZO (boron-doped zinc oxide), or ICO (indium cerium oxide), or can be a conductive metal including but not limited to any one or a combination of at least two of high-conductivity metals and alloys such as copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese.

[0009] According to another specific implementation and preferred aspect of the present invention, in step 2), a nanosecond infrared or picosecond infrared or nanosecond ultraviolet or picosecond ultraviolet laser is used to scribe the P1 scribed lines, where the number of P1 scribed lines is any integer greater than 1, and the number of P2 scribed lines matches the number of P1 scribed lines and is set in one-to-one correspondence; the width of the P1 scribed lines is 20-50 μm; the wavelength of the infrared laser is 1064 ± 106.4 nm, the wavelength of the green laser is 532 ± 53.2 nm, and the wavelength of the ultraviolet laser is 355 ± 35.5 nm.

[0010] According to another specific implementation and preferred aspect of the present invention, in step 3), the semiconductor device layer includes a P / N type functional layer, an intrinsic absorption layer, and an N / P type functional layer, and is formed in sequence; the semiconductor device layer is a combination of one or at least two of amorphous silicon, perovskite, copper indium gallium selenide, cadmium telluride, and gallium arsenide.

[0011] According to another specific implementation and preferred aspect of the present invention, in step 4), the material of the second electrode layer is a transparent conductive oxide; the deposition method of the second electrode layer includes any one or a combination of at least two of vacuum evaporation, magnetron sputtering, reactive plasma deposition, and chemical vapor deposition; the thickness of the first electrode layer is 10-1000 nm.

[0012] Preferably, the material of the second electrode layer is any one or a combination of at least two of fluorine-doped tin oxide, indium tin oxide, indium zinc oxide, aluminum-doped zinc oxide, indium tungsten oxide, tin titanium indium oxide, boron-doped zinc oxide, and indium cerium oxide; and / or, the material of the second electrode layer is a metal oxide, and the conductive metal in the metal oxide includes one or a combination of at least two of copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese.

[0013] According to another specific implementation and preferred aspect of the present invention, in step 5), a mechanical scribing or nanosecond infrared or picosecond infrared or nanosecond green or picosecond green or nanosecond ultraviolet or picosecond ultraviolet laser is used to scribe the P2 scribing line, and the width of the P2 scribing line is 20 - 50 μm, where the infrared laser wavelength is 1064 ± 106.4 nm, the green laser wavelength is 532 ± 53.2 nm, and the ultraviolet laser wavelength is 355 ± 35.5 nm.

[0014] In short, the second electrode layer material can be a transparent conductive oxide (TCO) including but not limited to any one or a combination of at least two of FTO (tin-doped fluorine oxide), ITO (indium tin oxide), IZO (indium zinc oxide), AZO (aluminum-doped zinc oxide), IWO (tungsten-doped indium oxide), ITIO (indium tin oxide doped with titanium), BZO (boron-doped zinc oxide), or ICO (cerium-doped indium oxide), or it can be a conductive metal including but not limited to any one or a combination of at least two of high-conductivity metals and alloys such as copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, manganese. The deposition method of the second electrode layer includes but not limited to any one or a combination of at least two of vacuum evaporation, magnetron sputtering, reactive plasma deposition, and chemical vapor deposition. The thickness of the second electrode layer is 10 - 1000 nm.

[0015] According to another specific implementation and preferred aspect of the present invention, in step 6), the width of each gate line is 0.01 - 8 mm; the height is 0.01 - 14 μm.

[0016] Preferably, the gate lines that fit the metal strip are flush with the top surface of the metal strip to form an interconnection contact surface, and the top surfaces of the remaining gate lines are flush to form a conductive contact surface, where there is a height difference between the interconnection contact surface and the conductive contact surface. Here, not only are the interconnection contact surface and the conductive contact surface relatively separated, but also the area of the interconnection contact surface is further increased based on the fit.

[0017] In some specific embodiments, the height difference is 5% - 70% of the width of the P2 scribeline; the width of the interconnect contact surface is 20 - 50 μm; the metal strip is L-shaped, and the width of the bottom side of the L-shape is equal to the width of the interconnect contact surface. The technical objectives of such a design are as follows: 1) To reduce the contact resistance and improve the carrier transport efficiency, that is, the optimized contact area can reduce the resistance of the carrier transport path, thereby reducing the series resistance (Rs) and increasing the fill factor (FF); 2) To reduce the recombination loss and increase the open-circuit voltage (Voc), that is, to improve the carrier collection efficiency; 3) To optimize the component packaging process and reduce costs, that is, the interconnect design simplifies the packaging process, enables automated operation through coplanar connection, reduces the complexity of the solder ribbon series connection, and at the same time reduces the performance loss caused by deformation. In addition, it can also reduce the grid line shielding loss; 4) To enhance the light absorption and current output, that is, the design without electrode shielding on the front maximizes the absorption of incident light, effectively reduces the light absorption loss of the window layer, and improves the overall efficiency of the battery; In addition, the metal strip is deposited on the first electrode layer, and the deposition method includes evaporation coating or magnetron sputtering using a mask plate. The material of the metal strip is any one or a combination of at least two of copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese; the forming method of the grid line is any one of screen printing, vacuum evaporation, magnetron sputtering, and electroplating.

[0018] Another technical solution of the present invention is: a double-scribeline interconnect type solar cell structure, which includes a substrate, a first electrode layer, a semiconductor device layer for photoelectric conversion, and a second electrode layer. A P1 scribeline is formed on the first electrode layer, the semiconductor device layer fills the P1 scribeline, and a P2 scribeline is formed near the P1 scribeline in the semiconductor device layer. The P2 scribeline is scribed from the second electrode layer to the first electrode layer, and the scribing depth is the sum of the thicknesses of the second electrode layer and the semiconductor device layer; the double-scribeline interconnect type solar cell structure further includes grid lines formed on the second electrode layer and metal strips formed in the P2 scribeline. The grid lines and the metal strips constitute a grid line network, and each metal strip is attached to the adjacent grid line and formed on one side of the scribing groove formed by the P2 scribeline. The other side of the metal strip is separated from the other side of the scribing groove to form a spacer region.

[0019] Preferably, the grid lines in contact with the metal strip are flush with the top surface of the metal strip to form an interconnected contact surface, and the top surfaces of the remaining grid lines are flush to form a conductive contact surface, where there is a height difference between the interconnected contact surface and the conductive contact surface, and the height difference is 5%-70% of the width of the P2 scribeline; and / or, the width of the interconnected contact surface is 20-50 μm; and / or, the metal strip is L-shaped, where the width of the bottom side of the L shape is equal to the width of the interconnected contact surface. The technical purpose of such a design is as follows: 1) Reduce the contact resistance and improve the carrier transport efficiency, that is, the optimized contact area can reduce the resistance of the carrier transport path, thereby reducing the series resistance (Rs) and increasing the fill factor (FF); 2) Reduce the recombination loss and increase the open-circuit voltage (Voc), that is, improve the carrier collection efficiency; 3) Optimize the component packaging process and reduce costs, that is, the interconnected design simplifies the packaging process, can achieve automated operation through coplanar connection, reduces the complexity of the solder ribbon series connection, and at the same time reduces the performance loss caused by deformation. In addition, it can also reduce the grid line shadowing loss; 4) Enhance light absorption and current output, that is, the design without electrode occlusion on the front maximizes the absorption of incident light, effectively reduces the light absorption loss of the window layer, and improves the overall efficiency of the battery.

[0020] Due to the implementation of the above technical solutions, the present invention has the following advantages compared with the prior art: In existing interconnected solar cell modules, for the non - generating area, also known as the dead zone, between the P1 scribeline and the P3 scribeline of each sub - cell, among which the device area between P2 and P3, after being blocked by P3, is in a short - circuit state and belongs to the ineffective area. Therefore, the existence of this dead zone directly reduces the effective power - generating area, decreases the number of photo - generated carriers, resulting in a decrease in the short - circuit current (Isc). At the same time, lattice defects or impurities near the dead zone form recombination centers, accelerating the recombination of electron - hole pairs, reducing the open - circuit voltage (Voc) and the fill factor (FF). In addition, the second electrode layer generally uses a transparent conductive oxide layer (abbreviation: TCO layer), whose conductivity is 1 - 2 orders of magnitude lower than that of metals. Especially, the relatively large lateral transfer resistance causes a relatively large series resistance of the module. Under the design of large current, the internal loss wind field of the module is high. In other words, generally, in order to achieve better carrier collection efficiency and lower transfer resistance, it is necessary to minimize the junction width to obtain a smaller output current, that is, it is necessary to significantly increase the thickness of the TCO layer (the conductivity is in a proportional relationship with the TCO thickness). In this way, not only does it significantly increase the number of scribelines, increasing the difficulty of equipment manufacturing and process control, but also limits the output characteristics of the module to a large voltage and a small current. Moreover, it prolongs the TCO manufacturing time, increases material consumption, raises costs, and at the same time, the increase in the TCO layer thickness correspondingly increases the light absorption, resulting in an increase in light absorption loss and causing a loss in the battery output power and other deficiencies. However, the present invention conducts an overall design on the preparation method of the double - scribeline interconnected solar cell structure, ingeniously solving the deficiencies and defects of the prior art. After adopting the preparation method of the double - scribeline interconnected solar cell structure, a substrate is selected, and a first electrode layer is deposited on the substrate; then a P1 scribeline is scribed on the first electrode layer, and the scribing depth is the thickness of the first electrode layer; then a semiconductor device layer is deposited on the first electrode layer and the substrate, where the semiconductor device layer fills the scribed area, and the surface of the semiconductor device layer is flat; then a second electrode layer is deposited on the surface of the semiconductor device layer; then, taking the P1 scribeline as a parallel reference, a P2 scribeline that is recessed from the second electrode layer to the first electrode layer is formed near the P1 scribeline, and the scribing depth is the sum of the thicknesses of the second electrode layer and the semiconductor device layer; finally, metal strips and grid lines are respectively formed on the P2 scribeline and the second electrode layer, where the metal strips and the grid lines constitute the surface grid line network. The metal strips are located in the scribing grooves of the P2 scribeline, and the metal strips respectively adhere to the side edges of the scribing grooves and the adjacent grid lines from the same side. The other side of the metal strip is separated from the other side of the scribing groove to form a spacer area. Therefore, on the one hand, based on the processing of two scribing processes, the present invention can not only reduce the width of the dead zone, increase the effective power - generating area of the module, reduce the lateral resistance, and improve the carrier collection efficiency, but also reduce the number of scribelines, simplify the process, and improve the production efficiency;On the other hand, based on the formed gate line structure, it not only effectively thins the thickness of the TCO layer by about 30% - 70%, but also effectively reduces the light absorption loss of the window layer, improves the overall efficiency of the battery, and at the same time greatly saves the material consumption of the TCO layer and reduces the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the interconnection structure of a solar cell module in the background art; Figure 2 is a front view schematic diagram of a double - scribed interconnection type solar cell structure in Embodiment 1; Figure 3 is Figure 2 a top view schematic diagram of; Wherein: 1, 1′ are substrates; 2, 2′ are first electrode layers; 3, 3′ are semiconductor device layers; 4, 4′ are second electrode layers; 5 are gate lines; 6 are metal strips; q is a spacer; Ⅰ′ is a groove; Ⅱ′ is a scribed groove. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] In order to make the above - mentioned objects, features, and advantages of the present invention more obvious and understandable, the present invention will be described in detail below in conjunction with the drawings and specific embodiments. Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0023] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.

[0024] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0025] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over", and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath", and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is less than that of the second feature.

[0027] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "up", "down", "left", "right", and similar expressions used herein are only for the purpose of illustration and do not represent the only implementation.

[0028] Example 1: As Figure 2 and Figure 3 shown, the double - ruled - interconnected type solar cell structure involved in this embodiment includes a substrate 1, a first electrode layer 2, a semiconductor device layer 3 for photoelectric conversion, and a second electrode layer 4, grid lines 5 formed on the second electrode layer 4, and metal strips 6 formed within the P2 ruling. Among them, the grid lines 5 and the metal strips 6 constitute a grid line network (briefly, the grid line network is the current collection network formed by the grid line system).

[0029] Specifically, P1 rulings are formed on the first electrode layer 2, the semiconductor device layer 3 fills the P1 rulings, and P2 rulings are formed near the P1 rulings on the semiconductor device layer 3. The P2 rulings are scribed from the second electrode layer 4 towards the first electrode layer 2, and the scribing depth is the sum of the thicknesses of the second electrode layer 4 and the semiconductor device layer 3; each metal strip 6 is attached to the adjacent grid line 5 and is formed on one side of the scribing groove formed by the P2 ruling, and the other side of the metal strip 6 is separated from the other side of the scribing groove to form a spacer q.

[0030] In some specific embodiments, the grid lines 5 that are in contact with the metal strip 6 are flush with the top surface of the metal strip 6 to form an interconnected contact surface, and the top surfaces of the remaining grid lines 5 are flush to form a conductive contact surface. There is a height difference between the interconnected contact surface and the conductive contact surface, and the height difference is 5% - 70% of the width of the P2 scribed line. The width of the interconnected contact surface is 20 - 50 μm. The metal strip 6 is L-shaped, and the width of the bottom side of the L-shape is equal to the width of the interconnected contact surface. The width of each grid line 5 is 0.01 - 8 mm; the height is 0.01 - 14 μm. In this example, the technical purpose of such a design is as follows: 1) Reduce the contact resistance and improve the carrier transport efficiency, that is, the optimized contact area can reduce the resistance of the carrier transport path, thereby reducing the series resistance (Rs) and increasing the fill factor (FF); 2) Reduce the recombination loss and increase the open-circuit voltage (Voc), that is, improve the carrier collection efficiency; 3) Optimize the component packaging process and reduce costs, that is, the interconnected design simplifies the packaging process, can achieve automated operation through coplanar connection, reduces the complexity of the solder ribbon series connection, and at the same time reduces the performance loss caused by deformation. In addition, it can also reduce the grid line shielding loss; 4) Enhance the light absorption and current output, that is, the design without electrode shielding on the front maximizes the absorption of incident light, effectively reduces the light absorption loss of the window layer, and improves the overall efficiency of the battery.

[0031] At the same time, taking the perovskite thin-film solar cell module as an example, its size is 1200*600 mm, the number of sub-cells: 93, and the preparation method includes the following steps: 1) Select the substrate 1, and deposit and form the first electrode layer 2 on the substrate 1. The material of the substrate 1 is inorganic non-metal (such as flexible glass), the first electrode layer 2 is an FTO electrode layer, and it is formed on the flexible glass by the deposition method; 2) Use laser scribing to form P1 scribed lines on the first electrode layer 2, and the scribing depth is the thickness of the first electrode layer 2. At the same time, the width of the P1 scribed line is 30 μm; 3) Deposit the semiconductor device layer 3 on the first electrode layer 2 and the substrate 1. The semiconductor device layer 3 fills the scribed area, and the surface of the semiconductor device layer 3 is flat; 4) Deposit the second electrode layer 4 on the surface of the semiconductor device layer 3 by magnetron sputtering. The second electrode layer 4 is a composite electrode layer; 5) Taking the P1 scribed line as a parallel reference, laser scribe to form P2 scribed lines that are recessed from the second electrode layer 4 to the first electrode layer 2 near the P1 scribed line. The scribing depth is the sum of the thicknesses of the second electrode layer 4 and the semiconductor device 3 layer. At the same time, the width of the P2 scribed line is 50 μm, and the distance between the P1 scribed line and the P2 scribed line is 15 μm. Therefore, the dead zone width is 30 μm + 15 μm + 50 μm = 95 μm (less than 100 μm); 6) A metal strip 6 and a grid line 5 are respectively formed on the P2 scribing line and the second electrode layer 4. The metal strip 6 and the grid line 5 form a surface grid line network. The metal strip 6 is located in the scribing groove of the P2 scribing line, and the metal strip 6 is respectively attached to the scribing groove and the side edge of the adjacent grid line 5 from the same side. The other side of the metal strip 6 is separated from the other side of the scribing groove to form a spacing area q. The metal strip 6 is L-shaped. The distance between the bottom of the L-shape and the other side of the scribing groove is 10 μm, and the distance between the vertical part of the L-shape and the other side of the scribing groove is 15 μm. The grid line 5 attached to the metal strip 6 is flush with the top surface of the metal strip 6 to form an interconnected contact surface, and the top surfaces of the remaining grid lines 5 are flush to form a conductive contact surface. There is a height difference between the interconnected contact surface and the conductive contact surface, and the height difference is 25 μm. The width of the bottom edge of the L-shape is equal to the width of the interconnected contact surface, and the width is 35 μm.

[0032] In some specific embodiments, the metal strip 6 is formed into an interconnected structure by using a mask vacuum thermal evaporation copper grid line, and the grid lines are formed by screen printing. At the same time, the width of each grid line is 10 μm and the height is 5 μm.

[0033] Example 2: The double-scribing interconnected type solar cell structure involved in this example is basically the same as that of Example 1, except for the dimensional changes in the preparation method.

[0034] Taking a perovskite thin film solar cell module as an example, its size is 1200*600 mm, the number of sub-cells is 93, and the preparation method includes the following steps: 1) Select a substrate 1 and deposit a first electrode layer 2 on the substrate 1. The material of the substrate 1 is an inorganic non-metal (such as flexible glass), the first electrode layer 2 is an FTO electrode layer, and it is formed on the flexible glass by a deposition method. 2) Use laser scribing on the first electrode layer 2 to form a P1 scribing line, and the scribing depth is the thickness of the first electrode layer 2. At the same time, the width of the P1 scribing line is 25 μm. 3) Deposit a semiconductor device layer 3 on the first electrode layer 2 and the substrate 1. The semiconductor device layer 3 fills the scribing area, and the surface of the semiconductor device layer 3 is flat. 4) Deposit a second electrode layer 4 on the surface of the semiconductor device layer 3 by vacuum evaporation. The second electrode layer 4 is a composite electrode layer. 5) Taking the P1 scribing line as a parallel reference, laser scribe a P2 scribing line that is recessed from the second electrode layer 4 to the first electrode layer 2 near the P1 scribing line. The scribing depth is the sum of the thicknesses of the second electrode layer 4 and the semiconductor device 3 layer. At the same time, the width of the P2 scribing line is 45 μm, and the distance between the P1 scribing line and the P2 scribing line is 10 μm. Therefore, the dead zone width is 25 μm + 10 μm + 45 μm = 80 μm (less than 100 μm). 6) A metal strip 6 and a grid line 5 are respectively formed on the P2 scribing line and the second electrode layer 4. The metal strip 6 is formed into an interconnection structure by using a mask vacuum thermal evaporation copper grid line. The line is formed by screen printing. At the same time, the width of each grid line is 10 μm; the height is 2 μm. The distance between the bottom of the L-shaped part and the other side of the scribing groove is 8 μm, and the distance between the vertical part of the L-shaped part and the other side of the scribing groove is 10 μm; there is a height difference between the interconnection contact surface and the conductive contact surface, and the height difference is 18 μm. The bottom width of the L-shaped part is equal to the width of the interconnection contact surface, and the width is 37 μm.

[0035] Comparative Example 1: As Figure 1 shown, the interconnection structure of the thin-film solar cell module involved in this comparative example includes a substrate 1′, a first electrode layer 2′, a semiconductor device layer 3′, and a second electrode layer 4′. The first electrode layer 1′ is scribed into several small sections to form P1 scribing lines; then, the device layer is scribed parallelly the same number of times at a distance as small as possible on one side of the P1 scribing line to form P2 scribing lines; finally, after depositing the second electrode layer 4′, the semiconductor device layer 3′ is scribed parallelly the same number of times at a distance as small as possible on one side of the P2 scribing line to form P3 scribing lines. Therefore, the dead zone width is the maximum distance between the P1 scribing line and the P3 scribing line.

[0036] Taking the perovskite thin-film solar cell module as an example, its size is 1200*600 mm, the number of sub-cells: 93, and the preparation method includes the following steps: 1) Select a substrate 1′ and deposit a first electrode layer 2′ on the substrate 1′. The material of the substrate 1′ is inorganic non-metal (such as flexible glass), and the first electrode layer 2′ is an FTO electrode layer, and is formed on the flexible glass by a deposition method; 2) Scribe P1 scribing lines on the first electrode layer 2′. The scribed thickness is equal to the thickness of the first electrode layer 2′, and the width of the formed laser scribing is 40 μm; 3) Deposit a semiconductor device layer 3′ on the first electrode layer 2′ and the substrate 1′. The semiconductor device layer 3′ fills the scribed area, and the surface of the semiconductor device layer 3′ is flat; 4) Taking the P1 scribing line as a parallel reference, laser scribe P2 scribing lines that are recessed from the P / N type functional layer to the first electrode layer 2′ near the P1 scribing line. The scribed depth is the thickness of the semiconductor device layer 3′. At the same time, the distance between the P1 scribing line and the P2 scribing line is 20 μm, and the width of the P2 scribing line is 50 μm; 5) Deposit a second electrode layer 4′. The second electrode layer 4′ is partially formed on the semiconductor device layer 3′, partially formed on the inner wall of the groove of the P2 scribing line, and the remaining part is formed on the first electrode layer 2′. The second electrode layer 4′ located in the P2 scribing line forms a groove Ⅰ′, and the width of the groove Ⅰ′ is 25 μm. At the same time, the second electrode layer 4′ is a composite electrode layer; 6) Using the P2 scribed line as a parallel reference, a P3 scribed line that is recessed from the second electrode layer 4' towards the first electrode layer 2' is laser scribed near the P2 scribed line. The thickness of the P3 scribed line is the sum of the thicknesses of the second electrode layer 4' and the semiconductor device layer 3'. The width of the groove Ⅱ' formed by the P3 scribed line is 30 μm, and the spacing distance between the P2 scribed line and the P3 scribed line is 50 μm. That is, the width of the dead zone is 40 μm + 20 μm + 50 μm + 50 μm + 30 μm = 190 μm.

[0037] In summary, for the interconnection structures of the solar cell modules in the examples and comparative examples, an IV tester is used to test the photovoltaic conversion efficiency of the cells and related electrical performance parameters under standard illumination power under a simulated solar light source. The specific test results are shown in Table 1.

[0038]

[0039] Based on the data analysis in Table 1, it can be seen that based on the width of the dead zone being less than 100 μm, a double scribing process is adopted to significantly improve the open-circuit voltage, short-circuit current, fill factor, output power, and conversion efficiency of the entire solar cell module.

[0040] In summary, the present application has the following technical advantages: 1) Based on the processing of two scribing processes, not only can the width of the dead zone be reduced to increase the effective power generation area of the module, reduce the lateral resistance, and improve the carrier collection efficiency, but also the number of scribed lines can be reduced, the process can be simplified, and the production efficiency can be improved; 2) Based on the formed grid line structure, not only can the thickness of the TCO layer be effectively reduced by about 30% - 70%, but also the light absorption loss of the window layer can be effectively reduced, the overall efficiency of the cell can be improved, and at the same time, the material consumption of the TCO layer can be greatly saved, and the cost can be reduced; 3) Reduce the contact resistance and improve the carrier transport efficiency. That is, the optimized contact area can reduce the resistance of the carrier transport path, thereby reducing the series resistance (Rs) and improving the fill factor (FF); 4) Reduce the recombination loss and increase the open-circuit voltage (Voc). That is, improve the carrier collection efficiency; 5) Optimize the module packaging process and reduce costs. That is, the interconnection design simplifies the packaging process, can achieve automated operation through coplanar connection, reduces the complexity of solder ribbon series connection, and at the same time reduces the performance loss caused by deformation. In addition, it can also reduce the grid line shadowing loss; 6) Enhance light absorption and current output. That is, the design without electrode occlusion on the front maximizes the absorption of incident light, effectively reduces the light absorption loss of the window layer, and improves the overall efficiency of the cell.

[0041] The above has described the present invention in detail, aiming to enable those skilled in the art to understand the content of the present invention and implement it. However, it should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for preparing a double-line interconnection type solar cell structure, characterized in that: It includes the following steps: 1) Selecting a substrate and depositing a first electrode layer on the substrate; 2) Scribing the first electrode layer to form a P1 scribe line, and the depth of the scribe line is equal to the thickness of the first electrode layer; 3) depositing a semiconductor device layer on the first electrode layer and the substrate, wherein the semiconductor device layer fills the scribed area and the surface of the semiconductor device layer is flat; 4) depositing a second electrode layer on the surface of the semiconductor device layer; 5) Taking the P1 scribe line as a parallel reference, a P2 scribe line is formed near the P1 scribe line, which is recessed from the second electrode layer to the first electrode layer, and the depth of the scribe line is the sum of the thickness of the second electrode layer and the semiconductor device layer; 6) Metal strips and gate lines are formed on the P2 scribe line and the second electrode layer, respectively, wherein the metal strips and gate lines constitute a surface gate line network, the metal strips are located in the scribe grooves of the P2 scribe line, and the metal strips adhere to the side edges of the scribe grooves and adjacent gate lines from the same side, and the other side of the metal strips is separated from the other side of the scribe grooves to form a spacing area.

2. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 1), the substrate material is inorganic non-metal, metal or polymer, wherein the inorganic non-metal includes rigid glass and flexible glass; and / or, the metal includes stainless steel, aluminum alloy and titanium; and / or, the polymer includes polyethylene terephthalate, polyethylene naphthalate, polyimide, polyparaxylene and polycarbonate.

3. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 1), the material of the first electrode layer is a transparent conductive oxide; and / or the deposition method of the first electrode layer includes any one of vacuum evaporation, magnetron sputtering, reactive plasma deposition, and chemical vapor deposition, or a combination of at least two thereof; and / or the thickness of the first electrode layer is 10-1000 nm.

4. The method for preparing a double-line interconnection type solar cell structure according to claim 3, characterized in that: The material of the first electrode layer is any one of fluorine-doped tin oxide, tin-doped indium oxide, zinc-doped indium oxide, aluminum-doped zinc oxide, indium oxide doped with tungsten, titanium-tin-doped indium oxide, boron-doped zinc oxide, and cerium-doped indium oxide, or a combination of at least two of them; and / or the material of the first electrode layer is a metal oxide, and the conductive metal in the metal oxide includes one of copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese, or a combination of at least two of them.

5. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 2), nanosecond infrared or picosecond infrared or nanosecond ultraviolet or picosecond ultraviolet laser is used to scribe P1 lines, wherein the number of P1 lines is any integer greater than 1, and the number of P2 lines matches the number of P1 lines and is arranged one-to-one.

6. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: The width of the P1 line is 20-50 μm; and / or the infrared laser wavelength is 1064±106.4 nm, the green laser wavelength is 532±53.2 nm, and the ultraviolet laser wavelength is 355±35.5 nm.

7. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 3), the semiconductor device layer includes a P / N type functional layer, an intrinsic absorption layer, and an N / P type functional layer, and they are formed in sequence; and / or, the semiconductor device layer is amorphous silicon, perovskite, copper indium gallium selenide, cadmium telluride, gallium arsenide, or a combination of at least two.

8. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 4), the material of the second electrode layer is a transparent conductive oxide; and / or the deposition method of the second electrode layer includes any one of vacuum evaporation, magnetron sputtering, reactive plasma deposition, and chemical vapor deposition, or a combination of at least two thereof; and / or the thickness of the first electrode layer is 10-1000 nm.

9. The method for preparing a double-line interconnection type solar cell structure according to claim 8, characterized in that: The material of the second electrode layer is any one of fluorine-doped tin oxide, tin-doped indium oxide, zinc-doped indium oxide, aluminum-doped zinc oxide, indium oxide doped with tungsten, titanium-tin-doped indium oxide, boron-doped zinc oxide, and cerium-doped indium oxide, or a combination of at least two of them; and / or the material of the second electrode layer is a metal oxide, and the conductive metal in the metal oxide includes one of copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese, or a combination of at least two of them.

10. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 5), mechanical scribing or nanosecond infrared or picosecond infrared or nanosecond green light or picosecond green light or nanosecond ultraviolet or picosecond ultraviolet laser scribing is used to scribe the P2 line, and the width of the P2 line is 20-50 μm, wherein the infrared laser wavelength is 1064±106.4 nm, the green laser wavelength is 532±53.2 nm, and the ultraviolet laser wavelength is 355±35.5 nm.

11. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 6), the width of each gate line is 0.01-8 mm and the height is 0.01-14 μm.

12. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: In step 6), the gate lines attached to the metal strips are flush with the top surface of the metal strips to form an interconnection contact surface, and the top surfaces of the remaining gate lines are flush with each other to form a conductive contact surface, wherein there is a height difference between the interconnection contact surface and the conductive contact surface.

13. The method for preparing a double-line interconnection type solar cell structure according to claim 12, characterized in that: The height difference is 5%-70% of the P2 line width; and / or, the width of the interconnection contact surface is 20-50 μm; and / or, the metal strip is L-shaped, wherein the bottom width of the L-shape is equal to the width of the interconnection contact surface.

14. The method for preparing a double-line interconnection type solar cell structure according to claim 1, characterized in that: The metal strips are deposited on the first electrode layer, and the deposition method includes evaporation or magnetron sputtering using a mask, wherein the material of the metal strips is any one of copper, silver, gold, iron, aluminum, tungsten, molybdenum, chromium, nickel, tantalum, vanadium, titanium, and manganese, or a combination of at least two thereof; the grid lines are formed by any one of screen printing, vacuum evaporation, magnetron sputtering, and electroplating.

15. A double-line interconnected solar cell structure, comprising a substrate, a first electrode layer, a semiconductor device layer for photoelectric conversion, and a second electrode layer, wherein a P1 line is formed on the first electrode layer, the semiconductor device layer fills the P1 line, and a P2 line is formed near the P1 line on the semiconductor device layer, characterized in that: The double-line interconnected solar cell structure is made by the preparation method of the double-line interconnected solar cell structure according to any one of claims 1 to 14, wherein the P2 line is scribed from the second electrode layer to the first electrode layer, and the scribe depth is the sum of the thicknesses of the second electrode layer and the semiconductor device layer; the double-line interconnected solar cell structure also includes a grid line formed on the second electrode layer and a metal strip formed in the P2 line, wherein the grid line and the metal strip constitute a grid line network, and each metal strip is attached to a neighboring grid line and formed on one side of the scribe groove formed by the P2 line, and the other side of the metal strip is separated from the other side of the scribe groove to form a spacing area.

16. The double-line interconnection type solar cell structure according to claim 15, characterized in that: The grid lines bonded to the metal strip are flush with the top surface of the metal strip to form an interconnect contact surface, and the top surfaces of the remaining grid lines are flush to form a conductive contact surface, wherein there is a height difference between the interconnect contact surface and the conductive contact surface, and the height difference is 5%-70% of the P2 line width; and / or, the width of the interconnect contact surface is 20-50μm; and / or, the metal strip is L-shaped, wherein the bottom width of the L-shape is equal to the width of the interconnect contact surface.

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