Image sensor and manufacturing method thereof
By forming multiple overlapping N-type source-drain doping regions in the semiconductor substrate of the image sensor, and using phosphorus ions to adsorb metal pollution, the problem of unclear photos in the dark field is solved, and the number of white pixel points is significantly reduced.
Patent Information
- Application Number
- CN202311588752.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-25
- Publication Date
- 2025-05-30
AI Technical Summary
In the dark field, the image sensor has unclear photos due to the abnormal distribution of white pixel points, and the prior art is difficult to effectively solve this problem.
By forming a plurality of N-type source-drain doped regions in the semiconductor substrate, including a first phosphorus ion doped region, an arsenic ion doped region and a second phosphorus ion doped region, the metal contamination caused by the high dose of arsenic ion doping implant is adsorbed in the overlapping region.
The white pixel points caused by metal contamination are significantly reduced, improving the image sensor's photo clarity in dark fields.
Smart Images
Figure CN120076434A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of imaging, and particularly to an image sensor and a manufacturing method thereof. Background Art
[0002] In a light-shielded environment, the photos taken by an image sensor should theoretically be completely black images. However, due to reasons such as damage to the silicon in the photoelectric conversion region and metal ion contamination, abnormal white pixels often appear, and these white pixels will cause the photos in the dark field to be unclear. The white pixels caused by different reasons usually have different brightnesses, and the brightness test results of the white pixels can be represented by a histogram. The horizontal axis represents the brightness of the pixels. In the dark field, the brightness of all pixels should theoretically be the same, but usually there will be several abnormally distributed peaks. Figure 1 is a histogram of the distribution of white pixels in a traditional image sensor in the dark field. It is generally considered that the ones with relatively low brightness are caused by damage to the silicon during the etching or filling of shallow trench isolation (STI), such as Figure 1 peak0.5 and peak1 in, and the larger ones are caused by metal contamination introduced by doping heavy atoms arsenic during the process of forming N-type source / drain doping regions in the semiconductor substrate, such as Figure 1 peak2 in. Summary of the Invention
[0003] In view of this, the present invention provides a manufacturing method of an image sensor, including: providing a semiconductor substrate; forming a plurality of N-type source / drain doping regions in the semiconductor substrate; wherein, forming a plurality of N-type source / drain doping regions in the semiconductor substrate includes: forming a plurality of first phosphorus ion doping regions in the semiconductor substrate; corresponding to the plurality of first phosphorus ion doping regions, forming a plurality of arsenic ion doping regions in the semiconductor substrate; corresponding to the plurality of arsenic ion doping regions, forming a plurality of second phosphorus ion doping regions in the semiconductor substrate; wherein, there is an overlapping region between the corresponding first phosphorus ion doping region and the arsenic ion doping region, and there is an overlapping region between the corresponding arsenic ion doping region and the second phosphorus ion doping region.
[0004] Optionally, the doping ion concentration of the second phosphorus ion doping region is higher than that of the first phosphorus ion doping region.
[0005] Optionally, the doping ion concentration of the first phosphorus ion doping region is 1E13 atoms / cm², and the doping ion concentration of the second phosphorus ion doping region is 1E14 atoms / cm².
[0006] Optionally, the ion implantation energy for forming the second phosphorus ion doping region is lower than that for forming the first phosphorus ion doping region.
[0007] Optionally, the ion implantation energy for forming the second phosphorus ion doped region is lower than the ion implantation energy for forming the arsenic ion doped region.
[0008] Optionally, there are corresponding arsenic ion doped regions and second phosphorus ion doped regions one by one, wherein the second phosphorus ion doped regions surround the arsenic ion doped regions.
[0009] Optionally, the ion implantation energy for forming the first phosphorus ion doped region is 35 KeV, the ion implantation energy for forming the arsenic ion doped region is 20 KeV, and the ion implantation energy for forming the second phosphorus ion doped region is 5 - 20 KeV.
[0010] Optionally, before forming multiple N-type source / drain doped regions in the semiconductor substrate, it further includes: forming a first photolithography pattern on the semiconductor substrate using a photolithography process; wherein each N-type source / drain doped region among the multiple N-type source / drain doped regions is formed based on the first photolithography pattern.
[0011] Optionally, after forming multiple N-type source / drain doped regions in the semiconductor substrate, it further includes: annealing treatment.
[0012] The present invention also provides an image sensor formed by using the manufacturing method of the above image sensor.
[0013] Compared with the prior art, the present invention has at least the following prominent advantages:
[0014] By improving the NMOS source / drain doping process, the present invention adds another phosphorus ion doping after the existing first phosphorus ion doping and second arsenic ion doping to adsorb the metal contamination brought by the high-dose arsenic ion doping injection, improve the abnormal white pixel points, and further solve the problem of unclear photos of the image sensor in the dark field. Description of the Drawings
[0015] Figure 1 is a histogram of the white dot distribution of a traditional image sensor in the dark field;
[0016] Figure 2 is a process flow chart of the preparation of an image sensor provided by an embodiment of the present invention;
[0017] Figure 3 is a partial cross-sectional schematic diagram of a semiconductor substrate provided by an embodiment of the present invention;
[0018] Figure 4 is a partial cross-sectional schematic diagram of the semiconductor substrate after the first phosphorus ion doping provided by an embodiment of the present invention;
[0019] Figure 5 is a partial cross-sectional schematic diagram of the semiconductor substrate after the arsenic ion doping provided by an embodiment of the present invention;
[0020] Figure 6 It is a partial cross-sectional view of a semiconductor substrate after the second phosphorus ion doping provided by an embodiment of the present invention;
[0021] Figure 7 It is a test result graph of the number of white pixels caused by metal contamination obtained by wafer testing for a traditional image sensor and the image sensor provided by the present invention respectively;
[0022] Figure 8 It is another partial cross-sectional view of a semiconductor substrate after the second phosphorus ion doping provided by an embodiment of the present invention;
[0023] Figure 9 It is a partial cross-sectional view of a semiconductor substrate using a lithography process provided by an embodiment of the present invention.
[0024] Description of component labels
[0025] 10 Semiconductor substrate
[0026] 101 Photoelectric conversion region
[0027] 102 Gate structure
[0028] 103 Sidewall
[0029] 210 First phosphorus ion doping region
[0030] 220 Arsenic ion doping region
[0031] 230 Second phosphorus ion doping region
[0032] 1001 First lithography pattern Detailed implementation manners
[0033] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0034] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be locally enlarged out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0035] For ease of description, spatial relationship terms such as "below", "beneath", "lower", "under", "above", "on" etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation in addition to the orientations depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.
[0036] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0037] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0038] In the process of forming the N-type source / drain doping region, both VA group elements phosphorus and arsenic are very important ion implantation elements. Ion implantation is a process of changing the physical or chemical properties of a material by ionizing atoms of a certain element into charged ions, accelerating them in an electric field, and injecting them into the surface layer of the material after obtaining high kinetic energy. Different ions with different charge-to-mass ratios will have different deflection angles after being accelerated by the same electric field, so that unwanted ions can be separated, and highly pure target ions can be obtained. The charge-to-mass ratio of arsenic is very close to that of tungsten, resulting in the introduction of tungsten elements when heavy atoms arsenic are ion implanted in the N-type source / drain doping region. Tungsten elements are exactly the reason for Figure 1 the high Peak2 in the white pixel histogram of the traditional image sensor shown. The inventors found that introducing the gettering characteristics of phosphorus elements into the N-type source / drain doping process of the image sensor can reduce the number of white pixels. Therefore, the present invention aims at the pixel region heavily doped with arsenic ions in the N-type source / drain doping process, and improves the abnormal white pixels by sequentially adding an additional phosphorus ion implantation after one phosphorus ion implantation and one arsenic ion implantation.
[0039] Based on the above analysis, the embodiments of the present invention provide a process flow diagram for manufacturing an image sensor, as Figure 2 shown. The manufacturing method of this image sensor includes:
[0040] S10: Provide a semiconductor substrate;
[0041] S20: Form a plurality of N-type source / drain doping regions in the semiconductor substrate;
[0042] Among them, forming a plurality of N-type source / drain doping regions in the semiconductor substrate specifically includes the following steps:
[0043] S201: Form a plurality of first phosphorus ion doping regions in the semiconductor substrate;
[0044] S202: Corresponding to the plurality of first phosphorus ion doping regions, form a plurality of arsenic ion doping regions in the semiconductor substrate;
[0045] S203: Corresponding to the plurality of arsenic ion doping regions, form a plurality of second phosphorus ion doping regions in the semiconductor substrate; wherein, there is an overlapping region between the corresponding first phosphorus ion doping region and the arsenic ion doping region, and there is an overlapping region between the corresponding arsenic ion doping region and the second phosphorus ion doping region.
[0046] Refer to Figures 3 to 6 and Figure 8 and Figure 9 which is schematically a structural diagram of each step presented in the preparation of the above image sensor in this embodiment. The following will be combined with Figures 2 to 9 to illustrate the preparation of the above image sensor.
[0047] First, refer to Figure 2 and Figure 3 , perform step S10 to provide a semiconductor substrate 10. Among them, in some embodiments, the semiconductor substrate 10 can be a single crystal silicon, single crystal germanium or single crystal germanium-silicon substrate. In other embodiments, the semiconductor substrate 10 can also be a semiconductor substrate formed by doping P-type ions in the above single crystal silicon, single crystal germanium or single crystal germanium-silicon substrate. However, it is not limited thereto, and the material, size and thickness of the semiconductor substrate 10 are not overly limited here.
[0048] Perform ion implantation on the semiconductor substrate 10 to form a photoelectric conversion region 101 in the semiconductor substrate 10, and deposit and etch polysilicon on the semiconductor substrate 10 to form various gate structures 102. Among them, the gate structure 102 can include one or a combination of a transfer gate, a reset gate, a source follower gate and a row selection gate. At the same time, in order to prevent the source / drain doping regions of high-energy ion implantation from being too close to the channel, resulting in an overly short channel or even source / drain connection, sidewalls 103 are formed on both sides of the gate structure 102.
[0049] Next, refer to Figure 2 and Figures 4 to 6 , perform step S20 to form a plurality of N-type source / drain doping regions in the semiconductor substrate. Among them, step S20 consists of multiple processes, such as Figure 4As shown, in the first process S201, multiple first phosphorus ion doped regions 210 are formed in the semiconductor substrate 10; that is, the semiconductor substrate 10 is implanted with arsenic ions at a high dose to form the first phosphorus ion doped regions 210;
[0050] As Figure 5 shown, in the second process S202, corresponding to the multiple first phosphorus ion doped regions 210, multiple arsenic ion doped regions 220 are formed in the semiconductor substrate 10. Among them, there is an overlapping region between the corresponding first phosphorus ion doped region 210 and arsenic ion doped region 220; that is, the first formed first phosphorus ion doped regions 210 are implanted with arsenic ions at a high dose to form the arsenic ion doped regions 220, which can better adjust the valence band of the formed NMOS source-drain doped regions.
[0051] Furthermore, as Figure 6 shown, in the third process S203, corresponding to the multiple arsenic ion doped regions 220, multiple second phosphorus ion doped regions 230 are formed in the semiconductor substrate 10; that is, the formed arsenic ion doped regions 220 are implanted with phosphorus ions at a high dose to form the second phosphorus ion doped regions 230; among them, there is an overlapping region between the corresponding second phosphorus ion doped region 230 and arsenic ion doped region 220. It should be explained that since the overlapping region between the arsenic ion doped region 220 and the second phosphorus ion doped region 230 can achieve the technical effect of adsorbing metal contamination, the overlapping region between the corresponding second phosphorus ion doped region 230 and arsenic ion doped region 220 can be partially overlapped or completely overlapped, which is set according to actual requirements and is not limited here.
[0052] Figure 7 Figure 14 is a test result diagram of the number of white pixels caused by metal contamination obtained by wafer testing for a traditional image sensor and the image sensor provided by the present invention respectively. Among them, ① is the traditional image sensor, ② is the image sensor provided by the present invention, and the doping concentrations of the arsenic ion doped regions of the two image sensors are the same. The horizontal axis is the number of white pixels caused by metal contamination (i.e., Figure 1 peak2 in FIG. 14), and the vertical axis is the probability percentage; it can be seen from the test result diagram that for the image sensor provided by the present invention with an additional phosphorus ion doping compared to the traditional image sensor, although the doping concentrations of the arsenic ion doped regions are the same, the number of white pixels caused by metal contamination is reduced by about 40%. Thus, it can be seen that adding an additional second phosphorus ion doping is effective for adsorbing metal contamination.
[0053] In the prior art, during the process of forming the NMOS source / drain doping region by first lightly doping with phosphorus ions and then heavily doping with arsenic ions, tungsten element contamination is introduced, resulting in white pixel points. However, in the present invention, the NMOS source / drain doping process is improved by adding an additional phosphorus ion doping after the existing first phosphorus ion doping and the second arsenic ion doping. The phosphorus ions are used to adsorb the tungsten contamination brought by the high-dose arsenic ion doping injection, thereby improving the white pixel points.
[0054] In some embodiments, the doping ion concentration of the second phosphorus ion doping region 230 is higher than that of the first phosphorus ion doping region 210. That is, compared with the first phosphorus ion doping, the concentration of the second phosphorus ion doping is higher. Theoretically, the higher the concentration of the second phosphorus ion doping, the better the effect of adsorbing tungsten metal contamination. However, if the concentration of the second phosphorus ion doping is too high, it will cause the VT (threshold voltage) of the NMOS to fluctuate and exceed the threshold of the device design, resulting in poor NMOS performance. Therefore, the concentration of the second phosphorus ion doping can be only one order of magnitude higher than that of the second phosphorus ion doping. Optionally, the doping ion concentration of the first phosphorus ion doping region 210 is 1E13 atoms / cm², and the doping ion concentration of the second phosphorus ion doping region 230 is 1E14 atoms / cm². Further optionally, the concentration range of the arsenic ion doping is 2E15 atoms / cm² to 3.6E15 atoms / cm². Since the second phosphorus ion doping is introduced, by replacing a part of the arsenic ion doping with phosphorus ion doping, the arsenic ion doping concentration in the NMOS source / drain doping process can be reduced, further reducing the tungsten metal contamination.
[0055] In other embodiments, the ion implantation energy for forming the second phosphorus ion doping region 230 is lower than the ion implantation energy for forming the first phosphorus ion doping region 210. Optionally, the ion implantation energy of the first phosphorus ion doping region is 35 KeV, and the ion implantation energy for forming the second phosphorus ion doping region is 5 - 20 KeV. It can be understood that the ion implantation energy represents the doping depth. As Figure 6 shown, that is, the depth of the second phosphorus ion doping is shallower than that of the first phosphorus ion doping, thereby avoiding the influence of the second phosphorus ion doping on the channel effect.
[0056] In some embodiments, the ion implantation energy for forming the second phosphorus ion doping region 230 is lower than the ion implantation energy for forming the arsenic ion doping region 220. Optionally, the ion implantation energy for forming the arsenic ion doping region is 20 KeV, and the ion implantation energy for forming the second phosphorus ion doping region is 5 - 20 KeV. At the same ion implantation energy, the doping depth of the phosphorus ions is greater than that of the arsenic ions. Therefore, the ion implantation energy of the second phosphorus ion doping needs to be less than that of the arsenic ion doping. Optionally, as Figure 8As shown, for the one-to-one corresponding arsenic ion doping region 220 and the second phosphorus ion doping region 230, the second phosphorus ion doping region 230 surrounds the arsenic ion doping region 220, that is, the doping depth of the second phosphorus ion doping exceeds the doping depth of the arsenic ion doping, which can adsorb the metal contamination generated by the arsenic ion doping as much as possible.
[0057] As Figure 9 shown, before forming multiple N-type source / drain doping regions in the semiconductor substrate 10, it further includes: forming a first photolithography pattern 1001 on the semiconductor substrate using a photolithography process; wherein, each of the multiple N-type source / drain doping regions is formed based on the first photolithography pattern 1001. That is, the first phosphorus ion doping region, the arsenic ion doping region, and the second phosphorus ion doping region are all formed through the same photolithography pattern, saving costs.
[0058] After forming multiple N-type source / drain doping regions in the semiconductor substrate, it further includes: annealing treatment. After the semiconductor substrate undergoes the first phosphorus ion doping, arsenic ion doping, and the second phosphorus ion doping, rapid thermal annealing (RTP) is used in a hydrogen environment at 900 - 990 °C, and the annealing time is about 20 s. The purpose is to repair the crystal damage on the silicon surface caused by ion implantation and activate the implanted impurities.
[0059] The present invention further includes an image sensor formed by using the above method for manufacturing an image sensor. The image sensor of the present invention improves the NMOS source / drain doping process. After the existing first phosphorus ion doping and the second arsenic ion doping, an additional phosphorus ion doping is added to adsorb the tungsten contamination brought by the high-dose arsenic ion doping injection, improve abnormal white pixel points, and further solve the problem of unclear photos of the image sensor in the dark field.
[0060] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.
Claims
1. A method for manufacturing an image sensor, characterized in that, comprising: providing a semiconductor substrate; forming a plurality of N-type source / drain doping regions in the semiconductor substrate; wherein, forming a plurality of N-type source / drain doping regions in the semiconductor substrate includes: forming a plurality of first phosphorus ion doping regions in the semiconductor substrate; corresponding to the plurality of first phosphorus ion doping regions, forming a plurality of arsenic ion doping regions in the semiconductor substrate; corresponding to the plurality of arsenic ion doping regions, forming a plurality of second phosphorus ion doping regions in the semiconductor substrate; wherein, there is an overlapping region between the corresponding first phosphorus ion doping region and the arsenic ion doping region, and there is an overlapping region between the corresponding arsenic ion doping region and the second phosphorus ion doping region.
2. The method for manufacturing an image sensor according to claim 1, characterized in that, the doping ion concentration of the second phosphorus ion doping region is higher than that of the first phosphorus ion doping region.
3. The method for manufacturing an image sensor according to claim 2, characterized in that, the doping ion concentration of the first phosphorus ion doping region is 1E13 atoms / cm², and the doping ion concentration of the second phosphorus ion doping region is 1E14 atoms / cm².
4. The method for manufacturing an image sensor according to claim 1, characterized in that, the ion implantation energy for forming the second phosphorus ion doping region is lower than the ion implantation energy for forming the first phosphorus ion doping region.
5. The method for manufacturing an image sensor according to claim 1, characterized in that, the ion implantation energy for forming the second phosphorus ion doping region is lower than the ion implantation energy for forming the arsenic ion doping region.
6. The method for manufacturing an image sensor according to claim 5, characterized in that, for each corresponding arsenic ion doping region and the second phosphorus ion doping region, wherein the second phosphorus ion doping region surrounds the arsenic ion doping region.
7. The method for manufacturing an image sensor according to claim 1, characterized in that, the ion implantation energy for forming the first phosphorus ion doping region is 35 KeV, the ion implantation energy for forming the arsenic ion doping region is 20 KeV, and the ion implantation energy for forming the second phosphorus ion doping region is 5 - 20 KeV.
8. The method for manufacturing an image sensor according to claim 1, characterized in that, before forming a plurality of N-type source / drain doping regions in the semiconductor substrate, further comprising; forming a first photolithography pattern on the semiconductor substrate using a photolithography process; wherein, each N-type source / drain doping region in the plurality of N-type source / drain doping regions is formed based on the first photolithography pattern.
9. The method for manufacturing an image sensor according to claim 1, characterized in that, after forming a plurality of N-type source / drain doping regions in the semiconductor substrate, further comprising: annealing treatment.
10. An image sensor, characterized in that, is formed by using the method for manufacturing an image sensor according to any one of claims 1 - 9.