Light detection pixel using vertical and planar gates

Abstract

Various embodiments described herein relate to systems, devices, products, and methods for light detection. In various embodiments, a pixel for detecting light is provided. The pixel may include a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate; and a first planar gate and a second planar gate disposed on the substrate. The first planar gate and the second planar gate may be configured to direct the one or more charge carriers from the transfer region to the first sensing node or the second sensing node.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to light detection, and more particularly to light detection pixels. Background Art

[0002] Light detection pixels are used in various technologies, such as in three-dimensional (3D) and two-dimensional (2D) imaging systems. New developments in technologies using light detection pixels require pixels to have improved performance. The applicant has recognized many technical challenges and difficulties associated with light detection pixels. Through the applied efforts, ingenuity, and innovation, the applicant has solved problems associated with light detection pixels by developing the solutions implemented in the present disclosure, which will be described in detail below. Summary of the Invention

[0003] Various embodiments described herein relate to systems, devices, products, and methods for light detection. In various embodiments, a pixel for detecting light is provided. In various embodiments, the pixel includes: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a transfer region of the substrate; and a first planar gate and a second planar gate disposed on the substrate, wherein the first planar gate and the second planar gate are configured to direct the one or more carriers from the transfer region to a first sensing node or a second sensing node.

[0004] In various embodiments, the pixel includes: a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first vertical gate control signal; a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second vertical gate control signal; a first planar gate input electrically coupled to the first planar gate and configured to receive a first planar gate control signal; and a second planar gate input electrically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first planar vertical gate and the second planar vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first planar gate control signal and the second planar gate control signal.

[0005] In various embodiments, the first vertical gate and the second vertical gate are configured to be activated using a first vertical gate control signal and a second vertical gate control signal, and to direct the one or more carriers to a transfer region when activated; the first planar gate is configured to be activated using a first planar gate control signal and to direct the one or more carriers to a first sensing node when activated; and the second planar gate is configured to be activated using a second planar gate control signal and to direct the one or more carriers to a second sensing node when activated.

[0006] In various embodiments, the first vertical gate and the second vertical gate are configured to be activated concurrently; the first planar gate is configured to be activated when the second planar gate is deactivated; and the second planar gate is configured to be activated when the first planar gate is deactivated. In various embodiments, the first vertical gate control signal and the second vertical gate control signal are DC voltages, and the first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

[0007] In various embodiments, a pixel includes: a third vertical gate disposed within a substrate; a fourth vertical gate disposed within the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to a transfer region; a third vertical gate input electrically coupled to the third vertical gate and configured to receive a DC third gate control signal; a fourth vertical gate input electrically coupled to the fourth vertical gate and configured to receive a DC fourth vertical gate control signal; a third planar gate disposed on the substrate and configured to direct the one or more carriers to a third sensing node when the third planar gate is activated; a fourth planar gate disposed on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sensing node when the fourth planar gate is activated; a third planar gate input electrically coupled to the third planar gate and configured to receive a third planar gate control signal; and a fourth planar gate input electrically coupled to the fourth planar gate and configured to receive a fourth planar gate control signal, wherein the first planar gate control signal, the second planar gate control signal, the third planar gate control signal, and the fourth planar gate control signal include periodic waveforms and are spaced apart from each other by a 90° phase shift.

[0008] In various embodiments, a pixel includes: a first deep insulating trench located on a first side of the substrate; and a second deep insulating trench located on a second side of the substrate, wherein the first deep insulating trench and the second deep insulating trench are configured to create a pinned potential at the substrate to deplete the substrate.

[0009] In various embodiments, the first planar gate and the second planar gate are configured to be alternately activated using a first planar gate control signal and a second planar gate control signal, where at a given time, the first planar gate control signal is the complement of the second planar gate control signal; the first vertical gate and the second vertical gate are configured to be activated using a first vertical gate control signal and a second vertical gate control signal; and the pixel is configured to determine indirect time-of-flight (iToF).

[0010] In various embodiments, the first vertical gate and the second vertical gate are configured to be deactivated simultaneously, and the first planar gate and the second planar gate are configured to be deactivated simultaneously for a first time period; the first vertical gate and the second vertical gate are configured to be activated, and the first planar gate or the second planar gate is configured to be activated for a second time period; and the pixel is configured to provide two-dimensional imaging.

[0011] In various embodiments, a pixel is provided. The pixel may include: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, where the first vertical gate and the second vertical gate are configured to direct the one or more carriers toward the first vertical gate and the second vertical gate; a first planar gate input electrically coupled to the first planar gate and configured to receive a first planar gate control signal; and a second planar gate input electrically coupled to the second planar gate and configured to receive a second planar gate control signal, where the first planar gate and the second planar gate are configured to direct the one or more carriers to a first capacitor or a second capacitor using a first gate control signal and a second gate control signal.

[0012] In various embodiments, the first planar gate is configured to be activated using a first gate control signal and, when activated, direct the one or more carriers to a first capacitor; and the second planar gate is configured to be activated using a second planar gate control signal and, when activated, direct the one or more carriers to a second capacitor, where the first planar gate and the second planar gate, and the first vertical gate and the second vertical gate are disposed near the same surface of the substrate.

[0013] In various embodiments, when the second planar gate is activated, the first planar gate is deactivated; when the first planar gate is activated, the second planar gate is deactivated; and the first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

[0014] Various embodiments of the present disclosure provide a method. The method may include: deploying a first vertical gate and a second vertical gate inside a substrate, wherein the first vertical gate and the second vertical gate are configured to direct one or more carriers to a transfer region of the substrate, wherein the one or more carriers are generated inside the substrate in response to an incident light beam; and deploying a first planar gate and a second planar gate on the substrate, wherein the first planar gate and the second planar gate are configured to direct the one or more carriers from the transfer region to a first sensing node or a second sensing node.

[0015] The method may include: configuring a first vertical gate input terminal to receive a first vertical gate control signal, wherein the first vertical gate input terminal is electrically coupled to the first vertical gate; configuring a second vertical gate input terminal to receive a second vertical gate control signal, wherein the second vertical gate input terminal is electrically coupled to the second vertical gate; configuring a first planar gate input terminal to receive a first planar gate control signal, wherein the first planar gate input terminal is electrically coupled to the first planar gate; configuring a second planar gate input terminal to receive a second planar gate control signal, wherein the second planar gate input terminal is electrically coupled to the second planar gate, wherein the first planar gate and the second planar gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first planar gate control signal and the second planar gate control signal.

[0016] In various embodiments, the method includes: configuring the first vertical gate and the second vertical gate to be activated using the first vertical gate control signal and the second vertical gate control signal, wherein when the first vertical gate and the second vertical gate are activated, the first vertical gate and the second vertical gate direct the one or more carriers to the transfer region; configuring the first planar gate to be activated using the first planar gate control signal and directing the one or more carriers to the first sensing node when the first planar gate is activated; and configuring the second planar gate to be activated using the second planar gate control signal and directing the one or more carriers to the second sensing node when the second planar gate is activated.

[0017] In various embodiments, the method includes: configuring the first planar gate to be deactivated when the second planar gate is activated; configuring the second planar gate to be deactivated when the first planar gate is activated. In various embodiments, the method includes: deploying a first deep insulating trench on a first side of the substrate; and deploying a second deep insulating trench on a second side of the substrate, wherein the first deep insulating trench and the second deep insulating trench are configured to create a pinning potential at the substrate to deplete the substrate.

[0018] In various embodiments, the method includes: activating a first vertical gate using a first vertical gate control signal, where the first vertical gate control signal is a DC voltage; and activating a second vertical gate using a second vertical gate control signal, where the second vertical gate control signal is a DC voltage.

[0019] In various embodiments, the method includes: electrically coupling a first sensing node to a first supplementary capacitor; electrically coupling a second sensing node to a second supplementary capacitor; and configuring the first supplementary capacitor and the second supplementary capacitor to determine an indirect time-of-flight or a two-dimensional density image using a first charge value of the first supplementary capacitor and a second charge value of the second supplementary capacitor.

[0020] In various embodiments, the method includes: deploying a third vertical gate inside a substrate; deploying a fourth vertical gate inside the substrate, where the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to guide the one or more carriers to a transfer region of the substrate; deploying a third planar gate on the substrate, where the third planar gate is configured to guide the one or more carriers to a third sensing node when the third planar gate is activated; deploying a fourth planar gate on the substrate, where the fourth planar gate is configured to guide the one or more carriers to a fourth sensing node when the fourth planar gate is activated; electrically coupling a third planar gate input terminal to the third planar gate to receive a third planar gate control signal; and electrically coupling a fourth planar gate input terminal to the fourth planar gate to receive a fourth planar gate control signal, where the first planar gate control signal, the second planar gate control signal, the third planar gate control signal, and the fourth planar gate control signal include periodic waveforms and are spaced apart from each other by a 90° phase shift.

[0021] The above summary of the invention is only used to outline some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it should be recognized that the above embodiments are only examples and should not be construed as limiting the scope or spirit of the present disclosure in any way. It should also be recognized that the scope of the present disclosure covers many potential embodiments in addition to the embodiments summarized here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Some example embodiments of the present disclosure have been generally described above, and now reference will be made to the accompanying drawings, which are not necessarily drawn to scale, where:

[0023] Figure 1 is a schematic diagram illustrating an iToF determination system.

[0024] Figure 2 is a schematic diagram illustrating a pixel.

[0025] Figure 3A FIG. is a schematic diagram of pixels according to various embodiments of the present disclosure.

[0026] Figure 3B FIG. is a schematic diagram of pixels according to various embodiments of the present disclosure.

[0027] Figure 3C FIG. is a schematic diagram of pixels according to various embodiments of the present disclosure.

[0028] Figure 4 FIG. is a schematic diagram of the operation of pixels according to various embodiments of the present disclosure.

[0029] Figure 5 FIG. is a schematic diagram of pixels according to various embodiments of the present disclosure.

[0030] Figure 6 FIG. is a flowchart of a method according to various embodiments of the present disclosure.

[0031] Figure 7 FIG. is a flowchart of a method according to various embodiments of the present disclosure.

[0032] Figure 8 FIG. illustrates an example computing device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. In fact, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals always denote like elements.

[0034] The phrases "in one embodiment", "according to an embodiment", "in some embodiments", "in various embodiments", etc., generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0035] The word "example" or "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0036] If the specification states that a component or feature “can,” “is able to,” “may,” “should,” “would,” “preferably,” “has the potential to,” “generally,” “optionally,” “for example,” “often,” or “might” (or other similar language) is included or has a characteristic, then that particular component or feature need not be included or have that characteristic. In some embodiments, such a component or feature may optionally be included or may be excluded.

[0037] The terms “electrically coupled,” “communicate with,” “electronically communicate with,” or “connected” in this disclosure refer to two or more elements or components being connected by wired means and / or wireless means such that signals, voltage / current, data, and / or information can be sent to and / or received from these elements or components.

[0038] Various embodiments of this disclosure are directed to improved systems, devices, products, and methods for optical detection, such as by using an improved optical detection system. In various embodiments, the optical detection system can be used in 3D imaging, such as using indirect time-of-flight (iToF) measurements.

[0039] In 3D imaging, the distance to an object can be determined. One method of measuring the distance to an object is time-of-flight (ToF) measurement. In a ToF system, the time it takes for a measurement beam to travel from a transmitter to an object and back to a detector is measured. Using the speed of light and the propagation time, the distance to the object can be measured.

[0040] In an indirect time-of-flight (iToF) system, the phase shift of the received beam relative to the transmitted beam is used to indirectly measure the distance to an object.

[0041] Now referring Figure 1 , a schematic diagram illustrating an indirect time-of-flight (iToF) measurement system 100 is provided. The iToF measurement system 100 includes a transmitter 102 configured to emit a beam 104 having, for example, a sine wave 106. In an example, the transmitted beam 104 can be an intensity-modulated continuous wave. The transmitted beam can be reflected from an object 108. The reflected beam 110 will be detected by a pixel 112. In various embodiments, the pixel 112 is an optical detection pixel.

[0042] To determine the phase shift between the reflected beam and the transmitted beam, the pixel 112 can reconstruct its sine wave after detecting the reflected beam 110.

[0043] To reconstruct the sine wave, the pixel 112 samples the detected beam. When the beam is received by the pixel 112, the pixel generates electron-hole pairs (e) and holes (h). The carriers are sampled using switches S1 and S2 and directed to corresponding sensing nodes SN1 or SN2 for detection.

[0044] The carriers detected at the sensing nodes SN1 and SN2 charge the corresponding capacitors. For example, the sensing node SN1 charges the first capacitor 122, and the sensing node SN2 charges the second capacitor 124. The controller 114 can compare the charges stored at the capacitors to reconstruct the phase value of the reflected light beam.

[0045] The sensing nodes SN1 and SN2 may be floating nodes, and the voltage of the sensing nodes may need to be reset after each detection cycle to prepare for another charge acquisition and measurement. Switches 116 and 118 may use a reset signal to reset the voltage to V DC .

[0046] In some examples, the emitted light beam may be in a near infrared (NIR) wavelength range of 800nm-1100nm, for example 940nm. In some examples, the emitted light beam may be in a short wave infrared (SWIR) wavelength range of 1100nm-3000nm. Therefore, suitable materials in the pixel 112 may be used to detect light beams in the corresponding wavelength range. For example, silicon has good absorption in the NIR wavelength range and can be used in pixels 112 for iToF and other imaging systems. Other materials (such as Ge, InGaAs) may be used in the SWIR wavelength range.

[0047] Reference now Figure 2 , a schematic diagram illustrating a pixel 200 according to various embodiments that have been used is provided. The pixel 200 may include a substrate 202. In various embodiments, the substrate 202 is a silicon substrate. The pixel 200 includes a PN junction 208 located at the center of the pixel between a first planar gate 204 and a second planar gate 206. The PN junction 208 may be created, for example, by an N well 210. The N well 210 may be an N implant region located approximately at the center of the pixel 200.

[0048] When the light beam is incident on the substrate 202, carriers are generated in the substrate 202. The PN junction 208 creates an electrostatic potential gradient that transfers the carriers to the top of the pixel. By switching between activation of the first planar gate 204 and the second planar gate 206, the charge is driven to the first sense node 212 or the second sense node 214. The first and second planar nodes can be controlled using an AC signal V AC is activated.

[0049] The first and second sensing nodes can be electrically coupled to an N+ region of the semiconductor. The N+ region can have a high concentration of N-type impurity dopants. In an example, the N+ region can reduce the contact resistance with the sensing node. For example, the N+ region can be an N fuse diffusion made of arsenic or phosphorus doping.

[0050] Now referring to Figure 3A FIG. [FIG. number not provided in the original, assuming it's a reference figure number], there is provided a schematic diagram showing pixels 300 in accordance with various embodiments of the present disclosure. In various embodiments, pixel 300 includes a substrate 302. Substrate 302 may be configured to generate one or more carriers in response to an incident light beam (e.g., reflected light beam 110). In various embodiments, pixel 300 includes a transparent layer 322 at the surface of substrate 302, at which surface the substrate is configured to absorb the incident light beam. Transparent layer 322 may include any of an anti-reflection layer, a lens, a microlens array, etc.

[0051] In various embodiments, pixel 300 includes a first vertical gate 334 and a second vertical gate 336 disposed within substrate 302. The first and second vertical gates may be configured to direct one or more carriers generated in response to the incident light beam to a higher region of the substrate, such as an integration zone 308. In various embodiments, the higher region may refer to a region away from the surface of the substrate that receives the incident light beam. In various embodiments, the first and second vertical gates are configured to direct one or more carriers to a transfer region 309 of the substrate. Transfer region 309 may be higher than integration zone 308.

[0052] In various embodiments, pixel 300 includes a first planar gate 304 and a second planar gate 306. In various embodiments, first planar gate 304 and second planar gate 306 are disposed on substrate 302. First planar gate 304 and second planar gate 306 may be fabricated by depositing layers of silicon oxide and a conductive material (such as doped polysilicon or a metal such as Al, W, Ag, etc.).

[0053] In an example embodiment, when operating in the NIR wavelength range, the height of the substrate may be between 5 - 12 microns. In an example embodiment, the depth of the first vertical gate 334 and the second vertical gate 336 may be between 0.3 and 2 microns, e.g., 1 micron. In an example embodiment, if a material other than silicon with higher absorbency is used, then the height of the substrate may be smaller. In various embodiments, the height of the general vertical gate may be between about 5% and 30% of the substrate height.

[0054] In various embodiments, the first and second vertical gates and the first and second planar gates are used for the efficient transfer of carriers from substrate 302 to a first sensing node 310 and a second sensing node 312.

[0055] In various embodiments, pixel 300 includes a first vertical gate input 344 electrically coupled to a first vertical gate and configured to receive a first vertical gate signal. Pixel 300 may include a second vertical gate input 346 electrically coupled to a second vertical gate and configured to receive a second vertical gate signal. In various embodiments, the first and second vertical gates are configured to be activated using the first and second vertical gate signals and, when activated, direct one or more carriers to a transfer region. In various embodiments, the first and second vertical gates may be activated concurrently. The first and second vertical gate control signals are DC voltages. In various embodiments, the same DC voltage may be applied to all vertical gates.

[0056] In various embodiments, the first planar gate 304 and the second planar gate 306 are activated using a first planar gate control signal applied to the first planar gate input 314 and a second planar gate control signal applied to the second planar gate input 316. In various embodiments, the first and second vertical gates are configured to direct one or more carriers to the first sensing node 310 or the second sensing node 312 using the first and second planar gate control signals.

[0057] For example, by activating the vertical gate, one or more carriers may be directed to the transfer region 309. In various embodiments, due to the appropriate doping profile of the substrate and the potential applied to the deep insulating trenches 324 and 326, a potential in region 309 may also be generated, as further described below. By alternately activating the first and second planar gates, a potential is created in the substrate 302 and the one or more carriers are directed from the transfer region 309 to the corresponding sensing node. For example, when the first planar gate 304 is activated, carriers are directed in the direction towards the first planar gate and are directed to the first sensing node. When the second planar gate 306 is activated, carriers are directed in the direction towards the second planar gate and are directed to the second sensing node.

[0058] In an example embodiment, pixel 300 directs carriers to the corresponding sensing node without a P-N junction created by a deep N implantation (e.g., as described with respect to pixel 200). By not requiring an N well, various embodiments provide a reduction in process variations for fabricating the pixel while increasing the transfer efficiency of carriers to the sensing node. Reducing process variations for fabricating the pixel may reduce mismatches and / or inconsistencies between individual pixels in a pixel array or matrix.

[0059] In various embodiments, when the second planar gate is activated, the first planar gate is deactivated, and when the first planar gate is activated, the second planar gate is deactivated. The planar gates can be activated using, for example, a periodic signal generated by a voltage and / or current source 320. The voltage source 320 can generate a first planar gate control signal and a second planar gate control signal. The first and second planar gate control signals can have a periodic waveform and can be complementary to each other. For example, at a given time, the first planar gate control signal applied to the input of the first planar gate can have a high value, while the second planar gate control signal applied to the input of the second planar gate will have a low value.

[0060] In an example embodiment, compared to pixel 200, pixel 300 provides a more homogeneous electrostatic potential in the substrate, having a gradient towards the vertical gate and then towards the corresponding sensing node when the corresponding planar gate is activated.

[0061] In various embodiments, the first and second sensing nodes are floating junctions, and the signals they generate will vary as carriers are directed to each sensing node. This can be because each sensing node has an inherent capacitance, and when carriers are transferred to the corresponding sensing node, the charge of the inherent capacitance and its corresponding voltage can change. In various embodiments, the inherent capacitance of each sensing node is supplemented, for example, by using supplementary capacitance that can be provided by an external capacitor. In various embodiments, when pixel 300 is used as an iToF pixel, the charge accumulated on each sensing node and / or on a supplementary capacitor electrically coupled in parallel with the sensing node is measured for iToF determination, as described, for example, in Figure 1 as described.

[0062] In various embodiments, by switching between activations of the planar gates, the pixel alternates between charge collection at the first and second sensing nodes. By doing so over a period of time, the controller 114 can integrate the first charge collection on the first sensing node and the second charge collection on the second sensing node. Using the integrated value, a reconstruction of the phase shift suffered when the light beam is reflected from an object and received by the pixel is determined.

[0063] In various embodiments, by faster alternation between charge collections at different sensing nodes, pixel 300 can provide a more accurate measurement of the phase shift of the reflected signal for iToF determination. In an example embodiment, compared to pixel 200, for example, pixel 300 enables the planar gates to be activated and deactivated at a higher frequency, and thus enables faster alternation between charge collections at the first and second sensing nodes to achieve a more accurate iToF measurement.

[0064] In various embodiments, by etching deep vertical gates in the substrate in the pixel 300, a higher driving potential is created in the substrate volume and carriers are guided to the transfer region. Subsequently, the carriers are then more efficiently guided to the sensing node with a lower amplitude requirement for the planar gate control signal.

[0065] In various embodiments, the pixel 300 includes a first deep insulating trench 324 and a second deep insulating trench 326. The deep insulating trenches can extend as deep as the substrate. In various embodiments, the substrate can be completely surrounded by a plurality of deep insulating trenches.

[0066] In various embodiments, the first deep insulating trench 324 and the second deep insulating trench 326 create a pinning potential at the substrate to deplete the substrate. In various embodiments, a DC voltage signal can be applied to the deep insulating trenches to create the pinning potential. For example, a first deep insulating trench DC bias voltage can be applied to the first deep insulating trench 324, and a second deep insulating trench DC bias voltage can be applied to the second deep insulating trench 326.

[0067] In an example embodiment, using the vertical gate and the deep insulating trenches, a uniform electrostatic field can be generated in the substrate from bottom to top to guide the carriers to the transfer region, and then using the planar gate, the carriers can be guided in the correct direction to the corresponding sensing node near the top according to which planar gate is activated.

[0068] In various embodiments, a lateral gradient of the electrostatic field is created by the deep insulating trenches to deplete the substrate body, and a vertical gradient of the electrostatic field that is upward and reaches the sensing node corresponding to the vertical gate activated at a given time is created by the vertical gate.

[0069] In various embodiments, the deep insulating trenches and the vertical gates utilize a dielectric liner (e.g., SiO 2 or HK material, HfO 2 , Al 2 O 3 etc.), and then are made by filling with a conductive material (e.g., doped polysilicon or a metal such as Al, W, Ag, etc.). In various embodiments, the substrate is made of silicon, Ge, InGaAs, etc., as described above.

[0070] In various embodiments, different arrangements for the vertical gate and the planar gate can be possible. Now referring to Figure 3A , a schematic diagram is provided showing the arrangement of various components of the pixel 300 according to various embodiments of the present disclosure from a top view. In an embodiment, the first and second vertical gates, the first and second planar gates, the first and second sensing nodes, and their corresponding N+ regions can be approximately deployed on a straight line 352. Figure 3BFIG. is a schematic diagram showing another arrangement in pixel 350 according to various embodiments of the present disclosure. For example, the first and second vertical gates may be approximately deployed on a first straight line 354, while the first and second planar gates, the first and second sensing nodes, and their corresponding N+ regions may be approximately deployed on a second straight line 356. The first and second lines may be approximately perpendicular to each other.

[0071] Now referring to Figure 4 , a schematic diagram is provided showing example operations of pixel 300 according to various embodiments of the present disclosure in three-dimensional (3D) imaging or iToF measurement and in two-dimensional (2D) imaging. As Figure 4 shown, line 402 is a schematic diagram of the electrostatic potential level in pixel 300 according to various embodiments.

[0072] In various embodiments, pixel 300 may operate in 3D imaging or iToF mode. When in iToF mode, the first and second vertical gates of the pixel are configured to be activated to direct carriers to the transfer region. In various embodiments, the first and second planar gates of the pixel may be configured to be alternately activated using a first planar gate control signal and a second planar gate control signal. In various embodiments, at a given time, the first planar control signal is the complement of the second planar control signal.

[0073] In various embodiments, when the first planar gate is deactivated, it creates a low gate that acts as a potential barrier between the carriers in the transfer region (e.g., Figure 3A transfer region 309 in) of the substrate and the first sensing node. In iToF mode, when the first planar gate is deactivated, the second planar gate may be activated, as shown, for example, in Figure 4 . When the second planar gate is activated, it creates a high gate that acts as a potential gradient for directing carriers to the second sensing node. By alternately activating and deactivating the first and / or second planar gates, when operating in iToF mode, pixel 300 alternately directs charge to the corresponding first or second sensing node.

[0074] In an example embodiment, by not using a P-N junction or an N-well in the integration region, the activation and / or deactivation of the first and second planar gates in pixel 300 can be performed at a higher frequency and with a lower amplitude. Therefore, the measurement accuracy can be increased, and the power consumption of the pixel can be reduced.

[0075] In various embodiments, pixel 300 may operate in 2D imaging, such as using light intensity acquisition. When operating in 2D imaging, the first vertical gate and the two planar gates may be configured to be deactivated simultaneously for a first time period, which may be referred to as the integration time. During the integration time, carriers generated in response to the incident light beam may accumulate in the integration region of the substrate. In various embodiments, the barrier created during the integration time may be a stronger barrier than the barrier created during the iToF mode to allow for greater charge accumulation for 2D imaging.

[0076] In various embodiments, then for a second time period, the first and second vertical gates and either the first planar gate or the second planar gate may be activated, which second time period may be referred to as the readout time. During the readout time, an intensity signal for the pixel is generated, which intensity signal may represent a 2D image pixel. In various embodiments, the vertical gates are activated and deactivated using first and second vertical gate control signals, and the planar gates are activated and deactivated using first and second planar gate control signals.

[0077] During the readout time, either of the first or second vertical carriers may be activated. When the vertical gate is activated, it creates a high gate that acts as a potential gradient to direct the integrated carriers to the corresponding sensing node for readout of the 2D image captured in the pixel.

[0078] In an example embodiment, by not using a P-N junction or an N-well in the integration region, greater carrier integration may be achieved in the integration region. Using vertically implanted gates in the pixel may allow for providing gates with low bias, thereby creating a significantly low gate barrier, which allows for storing a significant amount of carriers in the body of the pixel.

[0079] Thus, in an example embodiment, by simply changing the bias conditions of the vertical and planar gates using vertical and planar gate control signals, the pixel may operate in 3D or 2D imaging modes.

[0080] Now referring Figure 5 , there is provided a schematic top view of a pixel 500 illustrating various embodiments in accordance with the present disclosure. In various embodiments, pixel 500 includes a first vertical gate 524, a second vertical gate 526, a third vertical gate 528, and a fourth vertical gate 530 disposed inside a substrate 502. In various embodiments, the vertical gates are implanted in the substrate 502. The vertical gates may be deep trenches disposed within the substrate 502. In various embodiments, the vertical gates are configured to direct carriers to the transfer region of the substrate 502.

[0081] In various embodiments, the cross-section of the vertical gate can have various shapes. For example, one or more vertical gates can have an L-shaped cross-section. The L-shaped cross-section can provide a strong and / or homogeneous electrostatic field in the substrate to direct carriers to the transfer region. In various embodiments, the cross-section of the vertical gate can have any other geometric shape, such as square, rectangular, trapezoidal, circular, elliptical, etc. and / or any combination thereof.

[0082] In various embodiments, pixel 500 includes a first planar gate 504, a second planar gate 506, a third planar gate 508, and a fourth planar gate 510 disposed on substrate 502. In various embodiments, the first, second, third, and fourth planar gates are configured to direct one or more carriers from the transfer region to a first sensing node 514, a second sensing node 516, a third sensing node 518, or a fourth sensing node 520. In various embodiments, each planar gate is configured to transfer carriers to a corresponding sensing node. For example, the first planar gate can be configured to direct carriers to the first sensing node, the second planar gate can be configured to direct carriers to the second sensing node, the third planar gate can be configured to direct carriers to the third sensing node, and the fourth planar gate can be configured to direct carriers to the fourth sensing node. In various embodiments, the first planar gate can be disposed near the first sensing node, the second planar gate can be disposed near the second sensing node, the third planar gate can be disposed near the third sensing node, and the fourth planar gate can be disposed near the fourth sensing node. In various embodiments, each sensing node can be disposed on a corresponding N+ region and / or electrically coupled to the corresponding N+ region.

[0083] In various embodiments, the vertical gates, planar gates, and sensing nodes can be arranged in the substrate 502 in various ways. For example, the vertical gates and planar gates (or sensing nodes) can be generally arranged on a square shape 540. In other examples, the vertical gates and planar gates (or sensing nodes) can be arranged on various other shapes, such as circular, elliptical, rectangular, etc. In an example embodiment, by arranging the vertical gates and planar gates (or sensing nodes) as described herein, the transfer efficiency of carriers from the substrate to the corresponding sensing nodes is increased.

[0084] In various embodiments, the planar gates may have various cross-sectional shapes. For example, at least one or all of the first, second, third, or fourth planar gates may have various cross-sectional shapes around the corresponding sensing nodes and may completely or partially surround the corresponding sensing nodes. In various embodiments, at least one or all of the planar gates may partially surround the sensing nodes, for example, by having a C cross-sectional shape, an F cross-sectional shape, or an h cross-sectional shape. In various embodiments, at least one or all of the planar gates may completely surround the corresponding sensing nodes, for example, by having a circular (e.g., O) cross-sectional shape or a b cross-sectional shape that surrounds the corresponding sensing node. In various embodiments, when more than one planar gate corresponds to a sensing node, the planar gates that completely or partially surround the sensing node may be concentric or eccentric with respect to each other.

[0085] In various embodiments, each vertical gate is electrically coupled to a vertical gate input terminal and is configured to receive a vertical gate control signal. The vertical gate control signal may be a DC voltage.

[0086] In various embodiments, each planar gate is electrically coupled to a planar gate input terminal and is configured to receive a corresponding planar gate control signal. Each planar gate control signal may include a periodic waveform to periodically enable and disable the corresponding planar gate. In various embodiments, when four planar gates and corresponding four sensing nodes are used, the planar gate control signals may be offset from each other by 90°. In an example embodiment, doing so provides a finer granularity for transferring carriers to the corresponding sensing nodes. Thus, pixel 500 may provide, for example, 4-tap sampling per period of the incident reflected light beam to achieve a more accurate iToF determination.

[0087] In various embodiments, a pixel may include more than four vertical, planar, and / or sensing nodes and may be arranged in various forms, for example, in a similar manner as described above. When more sensing nodes are used, higher-tap sampling per period may be performed in the iToF determination.

[0088] In various embodiments, a pixel may include two or more planar gates for each sensing node. For example, two or more planar gates corresponding to a sensing node may be deployed near the sensing node and guide carriers from the transfer region to the corresponding sensing node. For example, when the first and / or second planar gate control signals are used to activate the first and / or second planar gates, carriers are guided to the first sensing node. And, for example, when the third and / or fourth planar gate control signals are used to activate the third and / or fourth planar gates, carriers are guided to the second sensing node. In various embodiments, all vertical gates may be activated to guide carriers to the transfer region.

[0089] In various embodiments, pixel 500 may include one or more deep insulating trenches located on each side of the substrate. The deep insulating trenches may be configured to create a pinned potential at the substrate to deplete the substrate.

[0090] In an example embodiment, the vertical gate provided herein may have a higher driving capability throughout the volume of the pixel substrate than a planar gate. This may reduce the amplitude requirement for the signal applied to the planar gate, since the vertical gate first guides the carriers to a transfer region closer to the planar gate. Thus, a small voltage for the planar gate control signal may be sufficient to provide the transfer of carriers to the corresponding sensing node. Accordingly, the efficiency of the pixel may be increased by requiring a lower amplitude for the planar gate control signal.

[0091] In an example embodiment, using the vertical gate and its higher driving capability may enable an increase in the volume of the substrate without degrading the frequency performance of the pixel. For example, due to the uniform and strong electric field gradient generated by the vertical gate and the resulting strong driving force on the carriers, using the vertical gate increases the quantum efficiency (QE) of the pixel by increasing the thickness of the volume of the substrate silicon without degrading the performance. In an example embodiment, QE may represent the ratio of the total carriers measured by the sensing node of the pixel to the total incident photons on the pixel. In an example embodiment, using the vertical gate and the planar gate as described herein may also maintain a high demodulation contrast (DMC) in the pixel. DMC may indicate an estimate of the rate at which the pixel collects and / or detects photons at the operating frequency.

[0092] Now referring Figure 6 FIG. 600 is a schematic diagram illustrating a method 600 according to various embodiments of the present disclosure. In various embodiments, method 600 may be used to fabricate and / or prepare a light detection pixel, such as pixel 300 described above.

[0093] In various embodiments, at step 602, method 600 deploys a first vertical gate and a second vertical gate inside a substrate (e.g., substrate 302). In various embodiments, the first and second vertical gates are configured to guide one or more carriers generated in the substrate to a transfer region of the substrate. The one or more carriers may be generated inside the substrate in response to an incident light beam.

[0094] In various embodiments, at step 604, method 600 deploys a first planar gate and a second planar gate on the substrate. The first and second planar gates may be configured to guide one or more carriers from the transfer region to a first sensing node or a second sensing node.

[0095] In various embodiments, at step 606, method 600 configures a first vertical gate input to receive a first vertical gate control signal. The first vertical gate input may be electrically coupled to a first vertical gate. In various embodiments, at step 608, method 600 configures a second vertical gate input to receive a second vertical gate control signal. The second vertical gate input may be electrically coupled to a second vertical gate. In various embodiments, the first and second vertical gate control signals may be DC voltages.

[0096] In various embodiments, at step 610, method 600 configures a first planar gate input to receive a first planar gate control signal. The first planar gate input may be electrically coupled to a first planar gate. In various embodiments, at step 612, method 600 may configure a second planar gate input to receive a second planar gate control signal. The second planar gate input may be electrically coupled to a second planar gate. In various embodiments, the first and second planar gates are configured to direct one or more carriers to a first sensing node or a second sensing node using the first and second planar gate control signals.

[0097] In various embodiments, the first and second planar gates are configured to direct one or more carriers to a first capacitor or a second capacitor using the first and second planar gate control signals. In an example embodiment, the first and second sensing nodes have an inherent capacitance and are the first and second capacitors. In various embodiments, the capacitance of the first and second sensing nodes is supplemented by supplementary capacitors. For example, capacitor 122 may be a first supplementary capacitor electrically coupled to the first sensing node, and capacitor 124 may be a second supplementary capacitor electrically coupled to the second sensing node, as Figure 1 shown. In an example embodiment, the supplementary capacitors may be external capacitors.

[0098] Now referring Figure 7 , a schematic diagram illustrating method 700 according to various embodiments of the present disclosure is provided. In various embodiments, method 700 may be used to fabricate and / or prepare a light detection pixel, such as pixel 300 described above.

[0099] In various embodiments, at step 702, method 700 configures the first and second vertical gates to be activated using the first and second vertical gate control signals. When the first and second vertical gates are activated, the first and second vertical gates may direct one or more carriers to a transfer region. In various embodiments, at step 704, method 700 configures the first planar gate to be activated using the first planar gate control signal, and when the first planar gate is activated, directs one or more carriers to the first sensing node.

[0100] In various embodiments, at step 706, method 700 configures a second planar gate to be activated using a second planar gate control signal and guides one or more carriers to a second sense node when the second planar gate is activated.

[0101] In various embodiments, at step 708, method 700 configures a first planar gate to be deactivated when the second planar gate is activated. In various embodiments, at step 710, method 700 configures the second planar gate to be deactivated when the first planar gate is activated.

[0102] In various embodiments, a method may deploy a first deep insulating trench on a first side of a substrate and a second deep insulating trench on a second side of the substrate. The first and second deep insulating trenches may be configured to create a pinned potential at the substrate to deplete the substrate.

[0103] In various embodiments, a method may activate a first vertical gate using a first vertical gate control signal. In various embodiments, the method may activate a second vertical gate using a second vertical gate control signal. The first and second vertical gate control signals may be DC voltages.

[0104] In various embodiments, a method may electrically couple a first sense node to a first supplementary capacitor and a second sense node to a second supplementary capacitor. In various embodiments, the method uses a first charge value of the first supplementary capacitor and a second charge value of the second supplementary capacitor to determine an indirect time-of-flight or a two-dimensional density image.

[0105] In various embodiments, a method may deploy a third vertical gate inside a substrate. The method may deploy a fourth vertical gate inside the substrate. The first, second, third, and fourth vertical gates may be configured to guide one or more carriers to a transfer region of the substrate.

[0106] In various embodiments, a method may deploy a third planar gate on a substrate, where the third planar gate is configured to guide one or more carriers to a third sense node when the third planar gate is activated. The method may deploy a fourth planar gate on the substrate, where the fourth planar gate is configured to guide one or more carriers to a fourth sense node when the fourth planar gate is activated.

[0107] In various embodiments, a method may electrically couple a third planar gate input terminal to the third planar gate to receive a third planar gate control signal. The method may electrically couple a fourth planar gate input terminal to the fourth planar gate to receive a fourth planar gate control signal. In various embodiments, the first, second, third, and fourth planar gate signals may include periodic waveforms and be spaced at 90° phase shifts from each other.

[0108] It should be readily appreciated that, in addition to the ways explicitly described herein, various additional and alternative ways can be employed to configure embodiments of the systems, devices, and methods described herein.

[0109] Figure 8 An example light detection system 800 in accordance with one or more embodiments of the present disclosure is illustrated.

[0110] The light detection system 800 may include a computing device 810 and / or one or more light detection pixels 820 communicatively coupled to the computing device 810 using one or more wired and / or wireless communication technologies. Generally, the terms computing device, computer, system, device, entity, and / or similar terms that may be used interchangeably herein may refer to, for example, one or more computers, computing entities, desktops, mobile phones, tablets, notebooks, laptop computers, distributed systems, kiosks, input terminals, servers or server networks, blade servers, gateways, switches, processing devices, processing entities, controllers, control systems, set-top boxes, repeaters, routers, network access points, base stations, etc. and / or any combination of devices or entities suitable for performing the functions, operations, and / or processes described herein. Such functions, operations, and / or processes may include, for example, sending, receiving, operating, processing, displaying, storing, determining, creating / generating, monitoring, evaluating, comparing, and / or similar terms that may be used interchangeably herein. In one embodiment, these functions, operations, and / or processes may be performed on data, content, information, and / or similar terms that may be used interchangeably herein. The computing device 810 may include any computing device, including, for example, a light detection processing device configured to perform one or more steps / operations of one or more light detection techniques described herein. In some examples, the computing device 810 may determine indirect time of flight (iToF) as described herein. In some examples, the computing device 810 may detect a 2D image as described herein. In some embodiments, the computing device 810 may include one or more mobile devices, (one or more) desktop computers, (one or more) laptop computers, (one or more) servers, and / or (one or more) cloud computing platforms, etc., and / or be associated therewith. In some example embodiments, the computing device 810 may be configured to receive and / or send light detection instructions, data, etc. between one or more light detection pixels 820 to perform one or more steps / operations of one or more light detection techniques described herein.

[0111] The computing device 810 may include one or more processing elements 802 (also referred to as processors, processing circuitry, digital circuitry, and / or similar terms that may be used interchangeably herein), or communicate with one or more processing elements 802, which communicate with other elements within the computing device 810 via, for example, a bus. As will be appreciated, the processing element 802 may be implemented in a variety of different ways.

[0112] For example, the processing element 802 may be implemented as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, coprocessing entities, application-specific instruction set processors (ASIPs), microcontrollers, and / or controllers. Additionally, the processing element 802 may be implemented as one or more other processing devices or circuitry. The term circuitry may refer to a fully hardware embodiment or a combination of hardware and a computer program product. Thus, the processing element 802 may be implemented as an integrated circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, and / or digital circuitry, among others.

[0113] Thus, as will be appreciated, the processing element 802 may be configured for a particular purpose or configured to execute instructions stored in volatile or non-volatile media or otherwise accessible to the processing element 802. Accordingly, whether configured by hardware or a computer program product, or by a combination thereof, the processing element 802, after being correspondingly configured, is capable of performing the steps or operations according to embodiments of the present disclosure.

[0114] In one embodiment, the computing device 810 may further include one or more memory elements 104, or communicate with one or more memory elements 804. The one or more memory elements 104 may include non-volatile and / or volatile media. For example, the memory element 804 may include non-volatile media (also referred to as non-volatile storage devices, memories, memory storage devices, memory circuitry, and / or similar terms that may be used interchangeably herein). In one embodiment, the non-volatile storage device or memory may include one or more non-volatile storage device or memory media, including but not limited to: hard disks, ROMs, PROMs, EPROMs, EEPROMs, flash memories, MMCs, SD memory cards, memory sticks, CBRAMs, PRAMs, FeRAMs, NVRAMs, MRAMs, RRAMs, SONOSs, FJG RAMs, Millipede memories, and / or racetrack memories, among others.

[0115] As will be appreciated, non-volatile storage devices or memory media can store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, and / or executable instructions, etc. The terms database, database instance, database management system, and / or similar terms that may be used interchangeably herein can refer to a collection of records or data stored in a computer-readable storage medium using one or more database models (such as hierarchical database models, network models, relational models, entity-relationship models, object models, document models, semantic models, and / or graph models, etc.).

[0116] Additionally or alternatively, the memory element 804 can include volatile memory. For example, the computing device 810 can also include a volatile medium (also referred to as volatile memory, memory storage, memory circuitry, and / or similar terms that may be used interchangeably herein) or communicate with the volatile medium. In one embodiment, the volatile storage device or memory can also include one or more volatile storage devices or memory media, including but not limited to: RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, and / or register memory, etc.

[0117] As will be appreciated, the volatile storage device or memory media can be used to store at least a portion of databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, and / or executable instructions, etc. executed by, for example, the processing element 802. Thus, databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, and / or executable instructions, etc. can be used to control certain aspects of the operation of the computing device 810 with the help of the processing element 802 and the operating system.

[0118] As indicated, in one embodiment, computing device 810 may also include one or more communication interfaces 808 for communicating with various computing entities, such as by transmitting data, content, information, and / or similar terms that may be used interchangeably herein, which may be sent, received, manipulated, processed, displayed, and / or stored. Such communication may be performed using wired data transmission protocols (such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Cable Data Service Interface Specification (DOCSIS), or any other wired transmission protocol). Similarly, computing device 810 may be configured to communicate via a wireless external communication network using any of a variety of protocols, such as General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Time Division-Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), Ultra Wideband (UWB), Infrared (IR) protocol, Near Field Communication (NFC) protocol, Wibree, Bluetooth protocol, Wireless Universal Serial Bus (USB) protocol, and / or any other wireless protocol.

[0119] The light detection system 800 may include input / output circuitry for communicating with one or more users or other systems or devices. For example, the input / output circuitry may include one or more interfaces for providing and / or receiving information to / from one or more users of the light detection system 800 or other systems or devices, or vice versa. The input / output circuitry may be configured to receive user input or input from various other systems or devices through one or more interfaces of the light detection system 800.

[0120] Conclusion

[0121] Those skilled in the art will think of many modifications and other embodiments of the disclosure described herein after benefiting from the above description and the teachings presented in the associated drawings. Although the figures only show certain components of the devices and systems described herein, it should be understood that various other components can be used in combination with the systems. Therefore, it should be understood that the present disclosure is not limited to the specific embodiments disclosed, and it is intended that modifications and other embodiments be included within the scope of the appended claims. The steps in the above methods do not necessarily occur in the order depicted in the drawings, and in some cases, one or more of the depicted steps may occur substantially simultaneously, or may involve additional steps. Although specific terms are employed herein, they are used in a general and descriptive sense only and not for purposes of limitation.

[0122] Although various embodiments in accordance with the principles disclosed herein have been shown and described above, those skilled in the art can make modifications thereto without departing from the spirit and teachings of the present disclosure. The embodiments described herein are merely representative and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of the present disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of (one or more) embodiments are also within the scope of the present disclosure. Accordingly, the scope of protection is not limited by the above description.

[0123] In addition, the section headings used herein are provided to be consistent with the recommendations of 37 C.F.R. 1.77 or to otherwise provide organizational cues. These headings should not limit or characterize the disclosure(s) set forth in any claims that may issue from the present disclosure.

[0124] The use of broader terms such as "comprising," "including," and "having" should be understood to support narrower terms such as "consisting of," "consisting essentially of," and "substantially consisting of." The use of terms such as "optionally," "can," "might," "may," etc. for any element of an embodiment indicates that the element is not required, or alternatively, that the element is required, both options being within the scope of (one or more) embodiments. Additionally, the reference to examples is for illustrative purposes only and is not intended to be exclusive.

[0125] Although this detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the foregoing embodiments in various modifications and improvements.

Claims

1. A pixel comprising: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers to a transfer region of the substrate; as well as A first planar gate and a second planar gate are disposed on the substrate, wherein the first planar gate and the second planar gate are configured to guide the one or more carriers from the transfer region to the first sensing node or the second sensing node.

2. The pixel according to claim 1, comprising: a first vertical gate input terminal electrically coupled to the first vertical gate and configured to receive a first vertical gate control signal; a second vertical gate input terminal electrically coupled to the second vertical gate and configured to receive a second vertical gate control signal; a first planar gate input terminal electrically coupled to the first planar gate and configured to receive a first planar gate control signal; as well as A second planar gate input terminal is electrically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first planar vertical gate and the second planar vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node using the first planar gate control signal and the second planar gate control signal.

3. The pixel of claim 2, wherein: The first vertical gate and the second vertical gate are configured to be activated using a first vertical gate control signal and a second vertical gate control signal and to direct the one or more carriers to the transfer region when activated; The first planar gate is configured to be activated using a first planar gate control signal and to direct the one or more carriers to the first sensing node when activated; as well as The second planar gate is configured to be activated using a second planar gate control signal and to direct the one or more carriers to the second sensing node when activated.

4. A pixel as claimed in claim 3, wherein: The first vertical gate and the second vertical gate are configured to be activated concurrently; the first planar gate is configured to be activated when the second planar gate is deactivated; as well as The second planar gate is configured to be activated when the first planar gate is deactivated. 5 . The pixel of claim 4 , wherein the first vertical gate control signal and the second vertical gate control signal are DC voltages, and the first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

6. The pixel of claim 2, further comprising: A third vertical gate is disposed inside the substrate; a fourth vertical gate disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to guide the one or more carriers to the transfer region; a third vertical gate input terminal electrically coupled to the third vertical gate and configured to receive a DC third gate control signal; a fourth vertical gate input terminal electrically coupled to the fourth vertical gate and configured to receive a DC fourth vertical gate control signal; a third planar gate disposed on the substrate and configured to guide the one or more carriers to a third sensing node when the third planar gate is activated; a fourth planar gate disposed on the substrate, wherein the fourth planar gate is configured to direct the one or more carriers to a fourth sensing node when the fourth planar gate is activated; a third planar gate input terminal electrically coupled to the third planar gate and configured to receive a third planar gate control signal; as well as A fourth planar gate input terminal is electrically coupled to the fourth planar gate and configured to receive a fourth planar gate control signal, wherein the first planar gate control signal, the second planar gate control signal, the third planar gate control signal and the fourth planar gate control signal include periodic waveforms and are spaced apart from each other by a 90° phase shift.

7. The pixel of claim 1, further comprising: a first deep isolation trench on a first side of the substrate; as well as A second deep isolation trench is located on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

8. The pixel of claim 1, wherein: The first planar gate and the second planar gate are configured to be alternately activated using a first planar gate control signal and a second planar gate control signal, wherein at a given time, the first planar gate control signal is the complement of the second planar gate control signal; The first vertical gate and the second vertical gate are configured to be activated using a first vertical gate control signal and a second vertical gate control signal; and The pixels are configured to determine an indirect time of flight, iToF.

9. The pixel of claim 1, wherein: The first vertical gate and the second vertical gate are configured to be deactivated simultaneously, and the first planar gate and the second planar gate are configured to be deactivated simultaneously for a first time period; the first vertical gate and the second vertical gate are configured to be activated, and the first planar gate or the second planar gate is configured to be activated for a second time period; as well as The pixels are configured to provide two-dimensional imaging.

10. A pixel comprising: a substrate configured to generate one or more carriers in response to an incident light beam; A first vertical gate and a second vertical gate are disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers toward the first vertical gate and the second vertical gate; a first planar gate input terminal is electrically coupled to the first planar gate and configured to receive a first planar gate control signal; as well as A second planar gate input terminal is electrically coupled to the second planar gate and configured to receive a second planar gate control signal, wherein the first planar gate and the second planar gate are configured to guide the one or more carriers to the first capacitor or the second capacitor using the first gate control signal and the second gate control signal.

11. The pixel of claim 10, wherein: a first planar gate configured to be activated using a first gate control signal and to direct the one or more carriers to the first capacitor when activated; as well as The second planar gate is configured to be activated using a second planar gate control signal and to direct the one or more carriers to the second capacitor when activated, The first planar gate and the second planar gate as well as the first vertical gate and the second vertical gate are disposed near the same surface of the substrate.

12. The pixel of claim 11, wherein: When the second planar gate is activated, the first planar gate is deactivated; when the first planar gate is activated, the second planar gate is deactivated; as well as The first planar gate control signal and the second planar gate control signal include periodic waveforms and are complementary to each other.

13. A method comprising: disposing a first vertical gate and a second vertical gate within the substrate, wherein the first vertical gate and the second vertical gate are configured to direct one or more carriers to a transfer region of the substrate, wherein the one or more carriers are generated within the substrate in response to an incident light beam; as well as A first planar gate and a second planar gate are disposed on the substrate, wherein the first planar gate and the second planar gate are configured to guide the one or more carriers from the transfer region to the first sensing node or the second sensing node.

14. The method of claim 13, comprising: configuring a first vertical gate input terminal to receive a first vertical gate control signal, wherein the first vertical gate input terminal is electrically coupled to the first vertical gate; configuring the second vertical gate input terminal to receive a second vertical gate control signal, wherein the second vertical gate input terminal is electrically coupled to the second vertical gate; configuring the first planar gate input terminal to receive a first planar gate control signal, wherein the first planar gate input terminal is electrically coupled to the first planar gate; The second planar gate input is configured to receive a second planar gate control signal, wherein the second planar gate input is electrically coupled to the second planar gate, wherein the first planar gate and the second planar gate are configured to guide the one or more carriers to the first sensing node or the second sensing node using the first planar gate control signal and the second planar gate control signal.

15. The method of claim 14, comprising: configuring the first vertical gate and the second vertical gate to be activated using a first vertical gate control signal and a second vertical gate control signal, wherein when the first vertical gate and the second vertical gate are activated, the first vertical gate and the second vertical gate guide the one or more carriers to the transfer region; configuring the first planar gate to be activated using the first planar gate control signal, and guiding the one or more carriers to the first sensing node when the first planar gate is activated; as well as The second planar gate is configured to be activated using a second planar gate control signal and to direct the one or more carriers to the second sensing node when the second planar gate is activated.

16. The method of claim 15, comprising: configuring the first planar gate to be deactivated when the second planar gate is activated; The second planar gate is configured to be deactivated when the first planar gate is activated.

17. The method of claim 14, comprising: disposing a first deep isolation trench on a first side of a substrate; as well as A second deep isolation trench is disposed on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

18. The method of claim 14, comprising: activating the first vertical gate using a first vertical gate control signal, wherein the first vertical gate control signal is a DC voltage; and The second vertical gate is activated using a second vertical gate control signal, wherein the second vertical gate control signal is a DC voltage.

19. The method of claim 18, comprising: electrically coupling the first sensing node to the first supplement capacitor; electrically coupling the second sensing node to the second supplement capacitor; as well as The first supplement capacitor and the second supplement capacitor are configured to determine an indirect time-of-flight or two-dimensional density image using a first charge value of the first supplement capacitor and a second charge value of the second supplement capacitor.

20. The method of claim 14, comprising: A third vertical gate is disposed inside the substrate; a fourth vertical gate is disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate and the fourth vertical gate are configured to guide the one or more carriers to the transfer region of the substrate; a third planar gate is disposed on the substrate, wherein the third planar gate is configured to guide the one or more carriers to the third sensing node when the third planar gate is activated; a fourth planar gate is disposed on the substrate, wherein the fourth planar gate is configured to guide the one or more carriers to the fourth sensing node when the fourth planar gate is activated; electrically coupling a third planar gate input terminal to the third planar gate to receive a third planar gate control signal; as well as electrically coupling a fourth planar gate input terminal to the fourth planar gate to receive a fourth planar gate control signal, The first planar gate control signal, the second planar gate control signal, the third planar gate control signal and the fourth planar gate control signal comprise periodic waveforms and are spaced apart from each other by a 90° phase shift.

Images