Solar cell, cell module and photovoltaic system

Abstract

The invention is applicable to the field of photovoltaic technology, and provides a solar cell, a cell module and a photovoltaic system, the solar cell comprises a silicon substrate, the silicon substrate comprises a first area and a second area, a P-type polycrystalline silicon layer is arranged in the first area, and an N-type polycrystalline silicon layer is arranged in the second area; the P-type polycrystalline silicon layer comprises a plurality of P-type crystal grains, the N-type polycrystalline silicon layer comprises a plurality of N-type crystal grains, and the number of the P-type crystal grains in unit area in the first region is larger than that of the N-type crystal grains in unit area in the second region. Therefore, separation and collection of holes and electrons are facilitated, transmission efficiency of the solar cell is improved, recombination of carriers is reduced, short-circuit current of the solar cell is improved, response of the cell to the whole solar spectrum is optimized, and photoelectric conversion efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaics, and particularly relates to a solar cell, a battery module, and a photovoltaic system. Background Art

[0002] As one of the most abundant renewable energy sources, solar energy has great development potential and application prospects. A solar cell is the core device for directly converting solar energy into electrical energy and is a key technology for the efficient utilization of solar energy. The photoelectric conversion efficiency refers to the proportion of incident light energy converted into electrical energy by a solar cell and is the core index for measuring the performance of a solar cell. Improving the photoelectric conversion efficiency can increase the electrical energy output per unit area and reduce the power generation cost.

[0003] Currently, the photoelectric conversion efficiency of commercial silicon-based solar cells is about 20% - 25%. Improving the photoelectric conversion efficiency of solar cells is an important part of solar cell research and development. Improving the photoelectric conversion efficiency can increase the electrical energy output per unit area, reduce the power generation cost, thereby shortening the investment recovery period, enhancing market competitiveness, and promoting the rapid development of the photovoltaic industry. Therefore, improving the photoelectric conversion efficiency of solar cells not only has important economic, environmental, and technical significance but also is the key to promoting the sustainable development of the photovoltaic industry. Summary of the Invention

[0004] An embodiment of the present invention provides a solar cell, aiming to improve the photoelectric conversion efficiency of the solar cell and solve the problem of low photoelectric conversion efficiency of the solar cell.

[0005] The embodiment of the present invention is implemented as follows. A solar cell includes:

[0006] A silicon substrate, the silicon substrate includes a first region and a second region, a P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region;

[0007] The P-type polysilicon layer includes a plurality of P-type grains, the N-type polysilicon layer includes a plurality of N-type grains, and the number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region.

[0008] Optionally, the silicon substrate has a light-facing surface and a backlight surface disposed opposite to each other, and both the first region and the second region are disposed on the backlight surface.

[0009] Optionally, the total perimeter of the P-type grains per unit area is greater than the total perimeter of the N-type grains per unit area.

[0010] Optionally, at least one of the first region and the second region is a textured surface.

[0011] Optionally, both the first region and the second region are suede surfaces.

[0012] Optionally, both the first region and the second region are polished surfaces.

[0013] Optionally, the roughness of the P-type polysilicon layer is less than the roughness of the N-type polysilicon layer.

[0014] An embodiment of the present invention further provides a battery module, including the above-mentioned solar cell.

[0015] An embodiment of the present invention further provides a photovoltaic system, including the above-mentioned battery module.

[0016] The beneficial effects achieved by the present invention are as follows: by respectively providing a first region and a second region on the silicon substrate, a P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains. The number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region. This is respectively beneficial to the separation and collection of holes and electrons, improves the transmission efficiency of the solar cell, reduces the recombination of carriers, increases the short-circuit current of the solar cell, optimizes the response of the battery to the entire solar spectrum, and thus improves the photoelectric conversion efficiency of the solar cell. Description of the Drawings

[0017] Figure 1 is a first perspective enlarged schematic view of the suede P-type polysilicon layer 200K provided by an embodiment of the present invention;

[0018] Figure 2 is a first perspective enlarged schematic view of the suede N-type polysilicon layer 200K provided by an embodiment of the present invention;

[0019] Figure 3 is a first perspective enlarged schematic view of the polished P-type polysilicon layer 200K provided by an embodiment of the present invention;

[0020] Figure 4 is a first perspective enlarged schematic view of the polished N-type polysilicon layer 200K provided by an embodiment of the present invention;

[0021] Figure 5 is a second perspective enlarged schematic view of the polished P-type polysilicon layer 200K provided by an embodiment of the present invention;

[0022] Figure 6 is a second perspective enlarged schematic view of the polished N-type polysilicon layer 200K provided by an embodiment of the present invention.

[0023] Description of the Reference Numerals:

[0024] 101. P-type crystal grains; 102. First grain boundary; 201. N-type crystal grains; 202. Second grain boundary;

[0025] 30. Protrusion; 40. Depression. Detailed implementation manners

[0026] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present invention and cannot be construed as a limitation of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0027] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation of the present invention.

[0028] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0029] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection, an electrical connection or a connection capable of mutual communication; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include direct contact between the first and second features, or may include the first and second features not being in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0031] The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0032] The present invention separately sets a first region and a second region on a silicon substrate. A P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains. The number of P-type grains per unit area in the first region is greater than the number of N-type grains per unit area in the second region. This is respectively beneficial to the separation and collection of holes and electrons, improves the transmission efficiency of the solar cell, reduces the recombination of carriers, increases the short-circuit current of the solar cell, optimizes the response of the cell to the entire solar spectrum, and thereby improves the photoelectric conversion efficiency of the solar cell.

[0033] Embodiment

[0034] As Figures 1 to 4 shown, this embodiment provides a solar cell, which is characterized by comprising:

[0035] A silicon substrate, the silicon substrate includes a first region and a second region, a P-type polysilicon layer is provided in the first region, and an N-type polysilicon layer is provided in the second region;

[0036] The P-type polysilicon layer includes a plurality of P-type grains 101, the N-type polysilicon layer includes a plurality of N-type grains 201, and the number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region.

[0037] Two different regions, a first region and a second region, are arranged on a silicon substrate. The first region and the second region can be arranged on the same surface of the silicon substrate or on two opposite surfaces of the silicon substrate, which is not limited herein. A P-type polysilicon layer is arranged in the first region, and an N-type polysilicon layer is arranged in the second region. The P-type polysilicon layer and the N-type polysilicon layer form regions with different electrical characteristics, supporting the formation of a PN junction and the separation of carriers.

[0038] The P-type polysilicon layer can cover the entire first region or only a part of the first region. P-type polysilicon is a polysilicon material that has undergone specific doping treatment. The doping element therein is usually an element that can provide holes (equivalent to positive charge carriers), such as boron (B), etc.

[0039] The P-type polysilicon layer is composed of a number of P-type grains 101. Grains are the basic units in the microstructure of polysilicon materials. The atomic arrangement within each P-type grain 101 has a certain regularity, but the orientations between different grains may be different, resulting in different shapes and sizes for each P-type grain 101. The shape of the P-type grain 101 can be approximately square, triangular, trapezoidal, approximately other polygons, or irregular, which is not limited herein. In the first region, these P-type grains 101 are distributed throughout the P-type polysilicon layer.

[0040] The N-type polysilicon layer can cover the entire second region or only a part of the second region. N-type polysilicon is formed by doping elements that can provide electrons (negative charge carriers), such as common doping elements like phosphorus (P), etc.

[0041] The N-type polysilicon layer is also composed of a number of N-type grains 201. Similar to the P-type grains 101, the atomic arrangement within the N-type grains 201 is regular, but there are differences in the orientations between the grains, resulting in different shapes and sizes for each N-type grain 201. The shape of the N-type grain 201 can be approximately square, triangular, trapezoidal, approximately other polygons, or irregular, which is not limited herein. In the second region, these N-type grains 201 are distributed throughout the N-type polysilicon layer.

[0042] The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region. Unit area means a preset specific region, and the side length, area, and shape of this specific region are all fixed. The specific shape of this specific region can be square, circular, or other shapes, which is not limited herein.

[0043] When the specific region is set within the first region, the specific region can be set at any position within the first region, and the number of P-type grains 101 falling within the specific region is a; when the specific region is set within the second region, the specific region can be set at any position within the second region, and the number of N-type grains 201 falling within the specific region is b, where a > b.

[0044] The number of P-type grains 101 per unit area is greater than the number of N-type grains 201, which means that the average area of P-type grains 101 is smaller than the average area of N-type grains 201. This is because within the same area, if the number of a certain type of grain is smaller, then the area occupied by each grain is relatively larger. For example, if there are more P-type grains 101 in a unit area, then the average area occupied by each P-type grain 101 will be smaller than the average area of N-type grains 201 with a smaller number.

[0045] It can be understood that although the average area of P-type grains 101 is smaller than the average area of N-type grains 201, this does not exclude the existence of one or more P-type grains 101 in the first region whose area is larger than the area of any N-type grain 201 in the second region. These larger P-type grains 101 may be due to local conditions during the material growth process, non-uniform doping distribution, or other factors. The average area is a statistical value that reflects the overall trend rather than the specific situation of each individual. In an actual material, the grain sizes may have a certain distribution range, some P-type grains 101 may be larger, and some N-type grains 201 may be smaller.

[0046] On the one hand, when the solar cell is illuminated, the silicon substrate absorbs photon energy to generate electron-hole pairs. In this structure with polysilicon layers of different doping types, the P-type polysilicon layer is rich in holes, and the N-type polysilicon layer is rich in electrons. The main function of the P-type polysilicon layer is to transport holes. More P-type grains can provide more transport channels, and holes can move more efficiently towards the corresponding electrodes of the battery through these channels. Because the hole migration within each grain is relatively smooth, and the network structure formed by numerous grains can reduce the hindrance during hole transport, lower the recombination probability of holes, and improve the hole collection efficiency. Since more photo-generated carriers are generated in the P-type region, under the action of the P-N junction, these carriers will diffuse towards the N-type region. At this time, although the number of grains per unit area in the N-type region is relatively small, it can form a good match with the carriers generated in the P-type region. The N-type region has enough space and ability to receive the electrons diffused from the P-type region, and its synergistic effect with the P-type region avoids the increase in recombination caused by excessive carrier concentration, ensuring the effective separation and transport of carriers.

[0047] On the other hand, the relatively large number of P-type grains in the P-type polysilicon layer means that there are more grain boundaries. These interfaces can serve as effective regions for light absorption. When light irradiates the solar cell, more P-type grains can interact with the light, increasing the probability of light absorption. After the light is absorbed, more electron-hole pairs, i.e., photo-generated carriers, are excited, thereby improving the generation efficiency of photo-generated carriers. The numerous P-type grains form a complex microstructure, and the light will be scattered multiple times between these grains. The propagation path of the scattered light inside the cell becomes longer, providing more opportunities for absorption, further increasing the amount of light absorbed, and thus increasing the generation of photo-generated carriers.

[0048] On the other hand, due to the different doping types and microstructures of the P-type polysilicon layer and the N-type polysilicon layer, they have different absorption and response characteristics to light of different wavelengths. The different numbers of grains per unit area in the first region and the second region enable the solar cell to achieve effective light absorption and carrier generation in a wider spectral range. For example, the P-type polysilicon layer may have an advantage in light absorption at certain specific wavelengths, while the N-type polysilicon layer performs better in light absorption at other wavelengths. By reasonably setting the number of grains per unit area, the response of the cell to the entire solar spectrum can be optimized, improving the power generation ability of the cell under different lighting conditions.

[0049] In this embodiment, a first region and a second region are respectively provided on the silicon substrate. A P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains 101; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains 201. The number of P-type grains 101 per unit area in the first region is greater than the number of N-type grains 201 per unit area in the second region. This is respectively beneficial to the separation and collection of holes and electrons, improves the transmission efficiency of the solar cell, reduces the recombination of carriers, increases the short-circuit current of the solar cell, optimizes the response of the cell to the entire solar spectrum, and thus improves the photoelectric conversion efficiency of the solar cell.

[0050] In some embodiments, the silicon substrate has a light-facing surface and a backlight-facing surface that are oppositely arranged, and both the first region and the second region are disposed on the backlight-facing surface.

[0051] The silicon substrate has two main surfaces, a light-facing surface and a backlight-facing surface. The light-facing surface directly faces the sunlight and is directly exposed to the light, while the backlight-facing surface is on the other side, and the two surfaces are oppositely arranged.

[0052] Both the first region and the second region are disposed on the backlight surface, that is, both the P-type polysilicon layer and the N-type polysilicon layer are disposed on the backlight surface. Usually, the first region and the second region are arranged alternately. Specifically, a plurality of first regions and a plurality of second regions are arranged alternately along the first direction, and both the first region and the second region extend along the second direction, and the second direction intersects with the first direction. The first region and the second region may be arranged alternately along the lateral direction of the silicon substrate and both extend along the longitudinal direction. That is, the first direction may be the lateral direction of the back contact battery, and the second direction may be the longitudinal direction of the back contact battery, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction may also be other directions. For example, the two may be the diagonal directions of the silicon substrate respectively, and specific details are not limited herein.

[0053] In this embodiment, the P-type polysilicon layer and the N-type polysilicon layer are disposed on the backlight surface. The polysilicon layer on the backlight surface can effectively collect and transport carriers, and at the same time reduce the reflection loss of photons on the backlight surface, which can optimize the collection and transport of carriers and improve the photoelectric conversion efficiency of the solar cell.

[0054] In some embodiments, the total perimeter of the P-type grains 101 per unit area is greater than the total perimeter of the N-type grains 201 per unit area.

[0055] The perimeter refers to the total length of the boundary line of a geometric figure. For a grain, the perimeter refers to the total length of the grain boundary. The total perimeter refers to the sum of the perimeters of all individual grains per unit area.

[0056] The total perimeter of the grains per unit area is mainly affected by two factors: the number of grains, the more the number of grains per unit area, the greater the total perimeter usually is; the ruggedness of the grain boundary, the more rugged the grain boundary (that is, the more complex the shape), the greater the perimeter of a single grain, and thus the greater the total perimeter.

[0057] Specific examples are given to illustrate the influence of the number of grains and the ruggedness of the grain boundary on the total perimeter of the grains per unit area:

[0058] The first example: Assume that the unit area is 1 square centimeter, and 20 first grains are arranged in the unit area. The boundary of each grain is smooth and flat, and the perimeter of a single grain is 0.1 centimeter. Then the total perimeter is: 20×0.1 = 2 centimeters.

[0059] 10 second grains are arranged in the unit area. The boundary of each grain is very rugged, and the perimeter of a single grain is 0.2 centimeter. Then the total perimeter is: 10×0.2 = 2 centimeters.

[0060] The number of the second grains is less, but the boundaries are rugged, and the total perimeter is 2 cm. The number of the first grains is more, but the boundaries are smooth, and the total perimeter is also 2 cm. In this example, although the number of the second grains is less than that of the first grains, due to the rugged boundaries of the second grains, the perimeter of a single grain is larger, and finally the total perimeters of both are equal.

[0061] Second example: Assume that the unit area is 1 square centimeter, and 20 first grains are set in the unit area. The boundary of each grain is smooth and flat, and the perimeter of a single grain is 0.1 cm. Then the total perimeter is: 20×0.1 = 2 cm.

[0062] 10 second grains are set in the unit area. The boundary of each grain is very rugged, and the perimeter of a single grain is 0.3 cm. Then the total perimeter is: 10×0.3 = 3 cm.

[0063] The number of the second grains is less, but the boundaries are rugged, and the total perimeter is 3 cm. The number of the first grains is more, but the boundaries are smooth, and the total perimeter is 2 cm, which is greater than the total perimeter of the second grains in the unit area. In this example, the total perimeter of the second grains is greater than that of the first grains. Although the number of the second grains is less, the ruggedness of their boundaries significantly increases the perimeter of a single grain, thus making the total perimeter larger.

[0064] Third example: Assume that the unit area is 1 square centimeter, and 20 first grains are set in the unit area. The boundary of each grain is smooth and flat, and the perimeter of a single grain is 0.1 cm. Then the total perimeter is: 20×0.1 = 2 cm.

[0065] 10 second grains are set in the unit area. The boundary of each grain is rugged, and the perimeter of a single grain is 0.15 cm. Then the total perimeter is: 10×0.15 = 1.5 cm.

[0066] The number of the second grains is less, but the boundaries are rugged, and the total perimeter is 1.5 cm. The number of the first grains is more, but the boundaries are smooth, and the total perimeter is 2 cm. The number of the second grains is less than that of the first grains, and the ruggedness of the boundaries of the second grains is greater than that of the first grains. However, the influence of the ruggedness of the second grains on the total perimeter increment is less than the influence of the number of the first grains on the total perimeter increment, making the total perimeter of the second grains less than that of the first grains, that is, the total perimeter of the first grains is greater than that of the second grains.

[0067] Fourth example: Assume that the unit area is 1 square centimeter, and 20 first grains are set in the unit area. The ruggedness of the boundary of each grain is similar to that of the second grains, and the perimeter of a single grain is also 0.2 cm. Then the total perimeter is: 20×0.2 = 4 cm.

[0068] 10 second grains are arranged per unit area, and the perimeter of a single grain is 0.2 cm, so the total perimeter is: 10 × 0.2 = 2 cm.

[0069] The number of second grains is less than that of the first grains, and the ruggedness of the boundaries of the second grains is similar to that of the boundaries of the first grains. The perimeters of single grains are the same, so that the total perimeter of the second grains is less than that of the first grains. It can be understood that when the ruggedness of the second grains is less than that of the first grains, it also holds that the total perimeter of the second grains is less than that of the first grains, that is, the total perimeter of the first grains is greater than that of the second grains.

[0070] In this embodiment, the total perimeter of the P-type grains 101 per unit area is greater than the total perimeter of the second grains per unit area, which can be similar to the third example or similar to the fourth example. A smaller total perimeter indicates that there are more boundaries of the P-type grains 101, that is, there are fewer boundaries of the N-type grains 201, which can reduce the recombination of carriers at the grain boundaries, is beneficial to improving the transport efficiency of carriers, and improving the photoelectric conversion efficiency of the solar cell.

[0071] Such as Figure 5 and Figure 6 As shown, in some embodiments, the number of protruding P-type grains 101 per unit area in the first region is less than the number of protruding N-type grains 201 per unit area in the second region.

[0072] The protrusion is relative to the reference plane, and the part of some P-type grains 101 or N-type grains 201 that is higher than the reference plane in height. For the P-type polysilicon layer, the reference plane usually refers to the plane where most of the P-type polysilicon layer is located in the first region. For the N-type polysilicon layer, the reference plane usually refers to the plane where most of the N-type polysilicon layer is located in the second region.

[0073] In the first region, P-type grains 101 protrude from the reference plane of the first region at multiple positions. Specifically, one P-type grain 101 can be respectively arranged to protrude from the reference plane of the first region at multiple positions, multiple adjacent P-type grains 101 can be respectively arranged to protrude from the reference plane of the first region at multiple positions, or one P-type grain 101 can be respectively arranged to protrude from the reference plane of the first region at some of the multiple positions, and multiple adjacent P-type grains 101 can be respectively arranged to protrude from the reference plane of the first region at the other part of the positions.

[0074] Similarly, in the second region, N-type grains 201 protrude from the reference plane of the second region at multiple positions. Specifically, one N-type grain 201 can protrude from the reference plane of the second region at each of multiple positions, multiple adjacent N-type grains 201 can protrude from the reference plane of the second region at each of multiple positions, or one N-type grain 201 can protrude from the reference plane of the second region at some of the multiple positions, and multiple adjacent N-type grains 201 can protrude from the reference plane of the second region at the other positions.

[0075] The number of P-type grains 101 protruding per unit area in the first region is less than the number of N-type grains 201 protruding per unit area in the second region. The unit area is a preset specific region, and the side length, area, and shape of this specific region are all fixed. The specific shape of this specific region can be square, circular, or other shapes, which are not limited here.

[0076] When the specific region is set in the first region, the specific region can be set at any position in the first region, and the number of P-type grains 101 protruding in this specific region is a; when the specific region is set in the second region, the specific region can be set at any position in the second region, and the number of N-type grains 201 protruding in this specific region is b, and a < b.

[0077] The P-type polysilicon layer is mainly responsible for the transport of holes, while the N-type polysilicon layer is mainly responsible for the transport of electrons. The protruding grains will increase the effective surface area, thus affecting the transport and recombination of carriers. The less protrusion of P-type grains 101 in the first region can reduce surface defects and carrier recombination, and improve the hole transport efficiency. The protruding grains can increase the scattering and absorption of light and reduce the reflection loss of light.

[0078] In this embodiment, the first region and the second region are respectively set on the silicon substrate. A P-type polysilicon layer is set in the first region, and the P-type polysilicon layer includes several P-type grains 101; an N-type polysilicon layer is set in the second region, and the N-type polysilicon layer includes several N-type grains 201. The number of P-type grains 101 protruding per unit area in the first region is less than the number of N-type grains 201 protruding per unit area in the second region, which can ensure a higher hole transport efficiency in the first region and a higher electron collection efficiency in the second region. By increasing the light absorption and reducing the carrier recombination, the photoelectric conversion efficiency of the solar cell is significantly improved.

[0079] In some embodiments, the protruding height of the P-type grains 101 is less than the protruding height of the N-type grains 201.

[0080] The description of the average state is that the protruding height of the P-type grains 101 is less than that of the N-type grains 201. That is, the average protruding height of the P-type grains 101 per unit area is less than that of the N-type grains 201 per unit area. There may be individual P-type grains 101 with a protruding height greater than that of the N-type grains 201, but the impact on the average trend is weak and will not be discussed separately.

[0081] Understandably, the protruding height of the P-type grains 101 refers to the distance between the highest protruding point of the P-type grains 101 and the reference plane of the first region. The protruding height of the N-type grains 201 refers to the distance between the highest protruding point of the N-type grains 201 and the reference plane of the second region.

[0082] On the one hand, the higher protruding height of the N-type grains 201 can play a better light scattering role. When light irradiates the battery surface, the higher N-type grains 201 will cause the light to scatter multiple times on their surfaces, extending the propagation path of the light inside the battery. This increases the chance of the light being absorbed by the P-type semiconductor because the P-type semiconductor is mainly responsible for absorbing photons and generating electron-hole pairs. And the P-type grains 101 are lower and will not overly obstruct the propagation of light, ensuring that the light can effectively reach the P-type region for photoelectric conversion. The higher N-type grains 201 can change the incident angle of the light, enabling more light to enter the battery interior rather than being reflected out, thereby improving the light utilization rate.

[0083] On the other hand, electrons and holes need to be effectively separated and collected after being generated under light irradiation. The higher N-type grains 201 can provide a larger surface area, which is beneficial to the rapid collection of electrons. As the majority carriers in the N-type semiconductor, electrons can reach the electrode faster through the N-type grains 201. And the P-type grains 101 are lower, reducing the recombination probability of holes during transmission because when holes are transmitted in the P-type semiconductor, if they pass through too many interfaces and obstacles, they are prone to recombine with electrons and be lost. The lower P-type grains 101 enable the holes to be transmitted to the electrode more smoothly, thereby improving the carrier collection efficiency.

[0084] In this embodiment, the protruding height of the P-type grains 101 is less than that of the N-type grains 201, which can optimize the carrier transmission and collection efficiency.

[0085] In some embodiments, the protruding height of the P-type grains 101 is 1 - 10 nm.

[0086] The specific height value can precisely control the carrier transmission path and recombination rate, further optimizing the battery performance. For example, the P-type grains 101 with a height of 1 - 10 nm can reduce surface recombination and increase the carrier lifetime.

[0087] In some embodiments, the protruding height of the N-type grains 201 is 1-15 nm.

[0088] The specific height value can precisely control the electron collection efficiency and further optimize the performance of the battery. For example, the N-type grains 201 with a height of 1-15 nm can enhance electron collection and increase the short-circuit current of the battery.

[0089] In some embodiments, the thickness of a single P-type grain 101 and / or a single N-type grain 201 is non-uniform.

[0090] Specifically, it can be that at least one P-type grain 101 has a non-uniform thickness while all N-type grains 201 have a uniform thickness, or at least one N-type grain 201 has a non-uniform thickness while all P-type grains 101 have a uniform thickness, or at least one P-type grain 101 has a non-uniform thickness and at least one N-type grain 201 has a non-uniform thickness.

[0091] The non-uniform thickness of a single grain means that there are differences in the thickness at different positions within the area occupied by each grain. Specifically, the thickness of a grain refers to the vertical distance between the top surface of the grain and the reference plane (i.e., the plane where most regions of the P-type polysilicon layer or N-type polysilicon layer are located).

[0092] Within a certain area of a single grain, the thickness may be thicker in one area and thinner in another area. This non-uniformity of thickness can be a continuous gradual change or a step-like abrupt change.

[0093] Grains with non-uniform thickness can optimize the carrier transport path and recombination rate. Thicker regions can enhance the carrier collection efficiency, while thinner regions can reduce carrier recombination, thereby improving the overall battery performance. At the same time, grains with non-uniform thickness can increase light scattering and absorption and reduce light reflection loss. Thicker regions can more effectively utilize incident light and improve the photoelectric conversion efficiency.

[0094] In this embodiment, the non-uniform thickness of a single P-type grain 101 and / or a single N-type grain 201 is beneficial to improving the carrier collection efficiency and reducing carrier recombination.

[0095] As Figures 1 to 4 shown, in some embodiments, the undulation degree of the P-type grains 101 is greater than that of the N-type grains 201.

[0096] The surface morphologies of the P-type grains 101 and the N-type grains 201 are different, and the undulation degree of the P-type grains 101 is greater than that of the N-type grains 201.

[0097] The undulation degree refers to the degree of height undulation of the material surface relative to a certain reference plane, reflecting the complexity and irregularity of the material surface morphology. Specifically, the undulation degree can be quantified by measuring the height differences of each point on the surface relative to the reference plane. The reference plane is a preset reference plane, which can be an idealized and completely flat reference plane or a plane that most areas of the material surface approach. The undulation degree is measured relative to the reference plane, and the choice of the reference plane directly affects the calculation result of the undulation degree. If the reference plane is selected as the plane that most areas of the material surface approach, then the measurement of the undulation degree will mainly reflect the height undulation of the surface relative to this plane. This method is more intuitive and can be judged by observing the surface morphology.

[0098] By measuring the height of each point on the surface relative to the reference plane, the undulation degree can be calculated. The undulation degree of the P-type grain 101 is greater than that of the N-type grain 201, which means that compared with the surface of the N-type grain 201, the surface morphology of the P-type grain 101 is more complex, with more protrusions 30 and / or depressions 40.

[0099] The fact that the undulation degree of the P-type grain 101 is greater than that of the N-type grain 201 means that there are more protrusions 30 and / or depressions 40 on the surface of the P-type grain 101 than on the surface of the N-type grain 201 ( Figures 1 to 4 in which the protrusions 30 are white positions and the depressions 40 are black positions). Specifically, it can be that there are more protrusions 30 on the surface of the P-type grain 101 than on the surface of the N-type grain 201, and the number of depressions 40 on the surface of the P-type grain 101 is equal to the number of depressions 40 on the surface of the N-type grain 201; it can be that the number of protrusions 30 on the surface of the P-type grain 101 is greater than the number of protrusions 30 on the surface of the N-type grain 201 (assuming the number is a), and the number of depressions 40 on the surface of the P-type grain 101 is less than the number of depressions 40 on the surface of the N-type grain 201 (assuming the number is b), and a > b; it can be that there are more protrusions 30 on the surface of the P-type grain 101 than on the surface of the N-type grain 201, and the number of depressions 40 on the surface of the P-type grain 101 is equal to the number of depressions 40 on the surface of the N-type grain 201; it can be that the number of depressions 40 on the surface of the P-type grain 101 is greater than the number of depressions 40 on the surface of the N-type grain 201 (assuming the number is c), and the number of protrusions 30 on the surface of the P-type grain 101 is less than the number of protrusions 30 on the surface of the N-type grain 201 (assuming the number is d), and c > d; it can also be that the number of depressions 40 on the surface of the P-type grain 101 is greater than the number of depressions 40 on the surface of the N-type grain 201, and the number of protrusions 30 on the surface of the P-type grain 101 is greater than the number of protrusions 30 on the surface of the N-type grain 201.

[0100] It can be understood that the undulation degree of the P-type grains 101 being greater than that of the N-type grains 201 is a description of the average state, that is, the average undulation degree of the P-type grains 101 is greater than that of the N-type grains 201. Since the growth of the grains is affected by many factors, there may be some P-type grains 101 with an undulation degree smaller than that of some N-type grains 201, but this does not affect the overall trend of the average undulation degree of the grains.

[0101] The undulation degree of the material surface is positively correlated not only with the number of depressions 40 and / or protrusions 30 on the material surface, but also with the depth of the depressions 40 and the depth of the protrusions 30. The deeper the depth of the depressions 40 and the higher the height of the protrusions 30, the greater the undulation degree of the material surface. However, on the grain surface, due to the relatively small grain size itself, the sizes of the depressions 40 and / or protrusions 30 on the grains are even smaller. The influence of the number of depressions 40 and / or protrusions 30 on the undulation degree is much greater than the influence of the depth of the depressions 40 and the depth of the protrusions 30 on the undulation degree. Therefore, in this embodiment, the influence of the depth of the depressions 40 and the depth of the protrusions 30 on the undulation degree is ignored and not discussed in detail.

[0102] It can be understood that the surface of the P-type grains 101 has more protrusions 30 and / or depressions 40 than the surface of the N-type grains 201. The larger undulation degree may increase the surface area of the grain surface, thereby affecting light absorption and the generation and transport of carriers. A larger undulation degree means more light scattering and reflection. The surface of the P-type grains 101 has a larger undulation degree, and light will be reflected and scattered multiple times on the grain surface, increasing the path length of photons in the P-type region and the residence time of photons in the P-type region, thereby increasing the light absorption rate. While the undulation degree of the N-type grains 201 is smaller, that is, the surface of the N-type grains 201 is relatively flat. The smaller undulation degree helps to reduce surface defects and improve the transport efficiency of carriers. The combined effect helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0103] In this embodiment, by respectively setting a first region and a second region on the silicon substrate, a P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains 101; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains 201, and the undulation degree of the P-type grains 101 is greater than that of the N-type grains 201. The absorption efficiency of photons in the first region is increased, and the transport efficiency of carriers in the second region is improved, thereby improving the overall photoelectric conversion efficiency of the solar cell.

[0104] In some embodiments, the number of depressions 40 on the P-type grains 101 is greater than the number of depressions 40 on the N-type grains 201.

[0105] The depression 40 refers to the tiny concave areas on the surface of the crystal grains. The fact that the number of depressions 40 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201 is a description of the average state, that is, the average number of depressions 40 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201. There may be individual P-type crystal grains 101 with the number of depressions 40 less than that of the N-type crystal grains 201, but the impact on the average trend is weak and will not be discussed separately.

[0106] The position of the depression 40 affects the scattering and absorption of light. More depressions 40 increase the light scattering ability on the surface of the P-type crystal grains 101, enabling the incident light to be more effectively captured and absorbed within the P-type region. This helps to improve the photoelectric conversion efficiency of the P-type region, thereby enhancing the performance of the entire solar cell.

[0107] In this embodiment, the number of depressions 40 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201. The existence of the depressions 40 causes the light to undergo multiple reflections and scatterings on the surface of the crystal grains, increasing the path length of photons within the P-type region, thereby improving the light absorption efficiency.

[0108] In some embodiments, the number of protrusions 30 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201.

[0109] The protrusion 30 refers to the tiny convex areas on the surface of the crystal grains. Similar to the depression 40, the fact that the number of protrusions 30 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201 is a description of the average state, that is, the average number of protrusions 30 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201. There may be individual P-type crystal grains 101 with the number of protrusions 30 less than that of the N-type crystal grains 201, but the impact on the average trend is weak and will not be discussed separately.

[0110] The position of the protrusion 30 also affects the scattering and absorption of light. A larger number of protrusions 30 further enhances the light scattering effect on the surface of the P-type crystal grains 101, increasing the residence time of photons within the P-type region and improving the light absorption efficiency. This helps to enhance the overall performance of the solar cell.

[0111] In this embodiment, the number of protrusions 30 on the P-type crystal grains 101 is greater than that on the N-type crystal grains 201. The existence of the protrusions 30 causes the light to undergo multiple reflections and scatterings on the surface of the crystal grains, increasing the path length of photons within the P-type region, thereby improving the light absorption efficiency.

[0112] In some embodiments, the difference between the highest and lowest positions on the P-type crystal grains 101 is 1 - 15 nm.

[0113] Multiple different samples were tested. The experimental results show that when the difference between the highest and lowest positions on the P-type grain 101 is 1 - 15 nm, the light absorption efficiency increases rapidly.

[0114] In some embodiments, the difference between the highest and lowest positions on the N-type grain 201 is 1 - 20 nm.

[0115] Multiple different samples were tested. The experimental results show that when the difference between the highest and lowest positions on the N-type grain 201 is 1 - 20 nm, the light absorption efficiency increases rapidly.

[0116] In some embodiments, a number of P-type grains 101 cover the surface of the entire first region.

[0117] A number of P-type grains 101 cover the entire first region and are arranged on the plane of the first region in a non-overlapping manner to ensure that the entire first region is completely covered. It does not exclude the existence of gaps between adjacent grains (grain boundaries formed due to the repulsive force between adjacent grains).

[0118] The fully covered P-type grains 101 ensure that there are no unutilized areas within the first region, maximizing the light absorption efficiency. This helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0119] In this embodiment, a number of P-type grains 101 cover the surface of the entire first region. The fully covered P-type grains 101 enable each part within the first region to effectively absorb light, thereby improving the overall light absorption efficiency.

[0120] In some embodiments, a number of N-type grains 201 cover the surface of the entire second region.

[0121] A number of N-type grains 201 cover the entire second region and are arranged on the plane of the second region in a non-overlapping manner to ensure that the entire second region is completely covered. It does not exclude the existence of gaps between adjacent grains (grain boundaries formed due to the repulsive force between adjacent grains).

[0122] The fully covered N-type grains 201 ensure that there are no unutilized areas within the second region, maximizing the light absorption efficiency. This helps to improve the overall photoelectric conversion efficiency of the solar cell.

[0123] In this embodiment, a number of N-type grains 201 cover the surface of the entire second region. The fully covered N-type grains 201 enable each part within the second region to effectively absorb light, thereby improving the overall light absorption efficiency.

[0124] Such as Figures 1 to 4As shown, in some embodiments, there is a first grain boundary 102 between adjacent P-type grains 101, and a second grain boundary 202 between adjacent N-type grains 201, and the width of the first grain boundary 102 is less than the width of the second grain boundary 202.

[0125] A grain boundary is the interface between adjacent grains in a polycrystalline material. In a polycrystalline material, due to the different growth directions and crystal structures of the grains, grain boundaries are formed between adjacent grains. Grain boundaries are recombination centers for charge carriers (electrons or holes), which can affect the conductivity and carrier lifetime of the material. Grain boundaries can impede the movement of dislocations, improving the strength and hardness of the material, but too many grain boundaries may also increase the brittleness of the material.

[0126] The description that the width of the first grain boundary 102 is less than the width of the second grain boundary 202 is a description of the average state, that is, the average width of the first grain boundary 102 is on average less than the average width of the second grain boundary 202. The specific value of the average width can be obtained by the mean method. That is, the same number of grain boundaries is arbitrarily selected in the first region and the second region respectively, and the widths of the grain boundaries in each region are added up and then divided by the number of grain boundaries to calculate the average width. It can be understood that the number of selected grain boundaries should not be too small, as it is likely to cause a large deviation in the results. In theory, the more grain boundaries are selected, the more accurate the calculation result will be, and the specific number can be selected according to the actual situation.

[0127] There may be individual P-type grains 101 with a grain boundary width greater than that of N-type grains 201, but the influence on the average trend is weak and will not be discussed separately.

[0128] There are a large number of lattice defects and impurities at the grain boundaries. These defects and impurities form energy traps. When electrons move in the silicon material, they may be trapped by these traps when encountering the grain boundaries, thus hindering the normal transmission path of the electrons. Electrons need to spend more time and energy to bypass these traps or escape from the traps, which slows down the migration speed of the electrons and reduces the transmission efficiency.

[0129] For example, originally electrons could move quickly from one position to another along a relatively smooth path. However, after the grain boundary becomes wider, the electrons interact frequently with defects and impurities at the grain boundary, constantly changing their movement directions, resulting in a longer actual transmission time and a decrease in the overall transmission efficiency.

[0130] On the one hand, the P-type grains 101 are doped with P-type impurities (such as boron) and have hole conductivity. There are a large number of free electrons in the silicon material, and the electrons become the majority carriers (majority carriers). Although the widening of the second grain boundary 202 will reduce the electron transport efficiency, due to the large number of electrons in the N-type silicon, even if some electrons are hindered at the grain boundary, there are still a large number of electrons that can successfully complete the transport process and participate in the photoelectric conversion of the battery. That is to say, the overall supply of electrons is sufficient, and the loss of a small number of electrons at the second grain boundary 202 has little impact on the total amount of electron transport in the entire N region.

[0131] From a macroscopic perspective, the overall efficiency of the solar cell mainly depends on the number of carriers that can effectively participate in the photoelectric conversion and the transport efficiency. In the N region, due to the abundant number of electrons, the reduction in electron transport efficiency caused by the widening of the second grain boundary 202 will not have a significant impact on the number of electrons that can finally reach the battery electrode, so it has little impact on the overall efficiency of the solar cell.

[0132] The P-type grains 101 are doped with P-type impurities (such as boron) and have hole conductivity. In P-type silicon, holes are the majority carriers, while electrons are the minority carriers. For the overall carrier balance in the P region, holes can be regarded as the key "minor participants" in the photoelectric conversion process to a certain extent (here, compared with the large number of hole generation mechanisms in the P region, the number of holes participating in the effective photoelectric conversion process is limited). When the first grain boundary 102 widens, the situation is very different from that in the N region. Since holes are relatively the key minority carriers (minority carriers) participating in the effective photoelectric conversion process in the P region, their number is relatively small. The increase in defects and impurities at the grain boundary caused by the widening of the first grain boundary 102 will greatly increase the probability of holes being trapped and recombined.

[0133] Once the holes encounter traps at the grain boundary during the transport process, they are easily recombined and thus cannot reach the battery electrode to participate in the photoelectric conversion. Moreover, due to the limited number of holes, the loss of each hole has a relatively large impact on the carrier transport and photoelectric conversion processes in the entire P region. Compared with the large number of electrons in the N region, the number of holes in the P region is small, and the hole loss caused by the widening of the first grain boundary 102 will significantly reduce the number of holes that can participate in the photoelectric conversion, thereby seriously affecting the overall efficiency of the solar cell. Therefore, a narrower first grain boundary 102 can reduce the recombination of holes at the grain boundary, thereby increasing the hole lifetime and the battery efficiency.

[0134] On the other hand, usually, the P region is slightly larger than the N region. This is because in the design of solar cells, the P region is mainly responsible for absorbing photons and generating photo-generated carriers (electron-hole pairs). A larger P region area can increase the light absorption area, thereby increasing the number of photo-generated carriers generated, which is beneficial to improving the photoelectric conversion efficiency of solar cells. There are phenomena such as lattice distortion and impurity enrichment at grain boundaries, which will generate certain stress. Since the P region is slightly larger than the N region and the width of the first grain boundary is smaller than that of the second grain boundary, this makes the stress distribution of the entire silicon wafer more balanced.

[0135] In the larger P region, the stress generated by the narrower first grain boundary is relatively small. Although the grain boundary in the N region is wider, its area is relatively small, and the stress generated by it can also balance the stress in the P region. When the internal stress distribution of the silicon wafer is uneven, an internal stress gradient will be generated, and this internal stress gradient will cause the silicon wafer to bend and deform. The bending of the silicon wafer will have a serious impact on subsequent cell manufacturing processes (such as photolithography, coating, etc.), which may lead to a decrease in process accuracy, problems such as pattern alignment deviation and uneven film thickness, thereby reducing the performance and yield of solar cells.

[0136] When the grain boundary in the P region is smaller than that in the N region, making the overall stress more balanced, the possibility of the silicon wafer bending will be greatly reduced. The flat state of the silicon wafer is conducive to the precise implementation of subsequent processes, reducing process defects caused by the bending of the silicon wafer, thereby improving the manufacturing yield of solar cells, reducing production costs, and improving the quality and reliability of products.

[0137] In this embodiment, a first region and a second region are respectively provided on the silicon substrate. A P-type polysilicon layer is provided in the first region, and the P-type polysilicon layer includes a plurality of P-type grains 101; an N-type polysilicon layer is provided in the second region, and the N-type polysilicon layer includes a plurality of N-type grains 201. There is a first grain boundary 102 between adjacent P-type grains 101, and there is a second grain boundary 202 between adjacent N-type grains 201. The width of the first grain boundary 102 is smaller than the width of the second grain boundary 202. The recombination of holes at the grain boundary is reduced, the electron transport efficiency is enhanced, and the photoelectric conversion efficiency of the solar cell is improved. At the same time, the overall stress of the silicon wafer can be made more balanced, reducing the possibility of the silicon wafer bending, and finally improving the manufacturing yield of solar cells.

[0138] In some embodiments, the width of the first grain boundary 102 is less than 10 nm.

[0139] Multiple samples with different widths of the first grain boundary 102 were tested. The experimental results show that when the width of the first grain boundary 102 is less than 10 nm, the carrier lifetime is significantly improved. For example, when the width of the first grain boundary 102 is 7 nm, the carrier lifetime is 200 μs; while when the width of the first grain boundary 102 is 12 nm, the carrier lifetime is only 100 μs. By statistically analyzing the experimental data, it can be determined that when the width of the first grain boundary 102 is less than 10 nm, the recombination of carriers at the grain boundary can be effectively reduced, thereby increasing the carrier lifetime.

[0140] Furthermore, when the width of the first grain boundary 102 is in the range of 7 - 8 nm, the transport and recombination rate of carriers can be further optimized, significantly reducing the recombination of carriers at the grain boundary and increasing the carrier lifetime.

[0141] In some embodiments, the width of the second grain boundary 202 is greater than 10 nm.

[0142] In an N-type semiconductor, due to the doping of pentavalent impurities (such as phosphorus), there are differences in the size and electronic structure between the impurity atoms and silicon atoms. When the width of the second grain boundary is greater than 10 nm, there is more space at the second grain boundary 202 to accommodate the lattice distortion caused by the mismatch between the impurity atoms and silicon atoms. The lattice around the impurity atoms will undergo stretching or compression, and the cumulative effect of this distortion is more obvious in the grain boundary region, thereby generating a large stress.

[0143] Multiple samples with different widths of the first grain boundary 102 were tested. The experimental results show that when the width of the second grain boundary 202 is greater than 10, a good balance with the stress in the P region can be achieved, and the stress concentration phenomenon inside the silicon wafer will be alleviated. This is beneficial to improving the stability of the silicon wafer during subsequent processing. For example, in processes such as lithography and etching, it can reduce pattern deformation and size deviation caused by stress. At the same time, it also helps to improve the long-term stability and reliability of the solar cell, reducing material fatigue and performance degradation problems caused by stress.

[0144] Furthermore, the width of the second grain boundary 202 is in the range of 10 - 22 nm. If the width of the second grain boundary is too large and exceeds the stress balance range that the silicon wafer can withstand, it may also cause stress imbalance inside the silicon wafer, increasing the risk of silicon wafer breakage and reducing the manufacturing yield of the solar cell. Setting the width of the second grain boundary 202 in the range of 10 - 22 nm can better achieve stress balance, reduce material fatigue and performance degradation problems caused by stress, and improve the overall performance of the battery.

[0145] In some embodiments, the depth of the first grain boundary 102 is less than the depth of the second grain boundary 202.

[0146] The grain boundary not only has a width but also has a depth. The grain boundary depth refers to the vertical distance that the grain boundary extends inside the material, usually measured from the surface and extending into the material. The depth of the grain boundary can be measured by observing the cross-section of the sample using a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0147] The grain boundary depth affects the transport path of carriers in the material. A deeper grain boundary may form a more complex transport channel, affecting the flow efficiency of carriers. The grain boundary depth is also closely related to the defect distribution at the grain boundary. A deeper grain boundary may contain more defects, increasing the probability of carrier recombination. At the same time, the grain boundary depth affects the distribution of the local electric field. A deeper grain boundary may form a stronger local electric field, affecting the separation and collection of carriers.

[0148] The depth of the first grain boundary 102 is less than the depth of the second grain boundary 202. Holes are the main carriers in the P-type grain 101, and holes are prone to recombine with electrons at the grain boundary. The relatively shallow depth of the first grain boundary 102 can reduce the residence time of holes at the grain boundary and lower the recombination rate. In the N-type grain 201, electrons are the main carriers, and electrons require a longer transport path at the grain boundary. The larger depth of the second grain boundary 202 can enhance the transport efficiency of electrons and reduce the loss during the transport process.

[0149] The grain boundary is the interfacial region between different grains, with irregular atomic arrangements, a large number of lattice defects such as dislocations and vacancies, and may also be enriched with impurity atoms. When the grain boundary becomes deeper, it means that the region with these defects and impurities expands in the direction perpendicular to the grain surface.

[0150] When electrons transport in an N-type semiconductor, they need to move freely in the lattice. After the grain boundary becomes deeper, electrons will encounter these defects and impurities more frequently during movement. Defects and impurities form energy traps, and electrons may be trapped by the traps, deviate from the original movement path, or even be bound in the traps. This leads to a decrease in the mobility of electrons. The electrons that could originally move quickly in a directed manner to form a current now need to spend more time and energy to overcome these obstacles, thus reducing the transport efficiency of electrons.

[0151] In the second region, the number of free electrons far exceeds the number of holes, and electrons are the majority carriers (majority carriers). Even if the increase in the depth of the second grain boundary 202 hinders the transport of some electrons, compared to the large number of electrons, the affected electrons are only a small part, so the impact on the overall efficiency is not significant.

[0152] In the first region, holes are the majority carriers, while electrons are the minority carriers. However, here we are discussing the holes that participate in conduction and energy conversion during the interaction with the second region. These holes are relatively few in number and are minority carriers.

[0153] When the first grain boundary 102 becomes deeper, the defects and impurities at the first grain boundary 102 increase, and holes are more likely to be trapped and recombined by these traps during transmission. Since the number of holes itself is small, the loss of each hole has a relatively large impact on the overall carrier transmission. In a solar cell, the smooth transmission of holes is crucial for converting light energy into electrical energy. The deepening of the first grain boundary 102 leads to a significant reduction in the hole transmission efficiency, resulting in a significant decrease in the number of holes reaching the electrode, thus seriously affecting the current output and photoelectric conversion efficiency of the cell, so it has a great impact on the overall efficiency.

[0154] In this embodiment, the depth of the first grain boundary 102 is less than the depth of the second grain boundary 202, which can reduce recombination, improve the transmission efficiency, and thus improve the photoelectric conversion efficiency of the cell.

[0155] In some embodiments, the depth of the first grain boundary 102 is less than 15 nm.

[0156] A shallower depth of the first grain boundary 102 can reduce the defect density at the grain boundary. The shallow grain boundary can limit the formation and expansion of defects, reduce the number of hole recombination centers, thereby reducing the recombination rate of holes at the grain boundary, and further increasing the hole lifetime.

[0157] Multiple samples with different depths of the first grain boundary 102 were tested. The experimental results show that when the depth of the first grain boundary 102 is less than 15 nm, the hole lifetime is significantly increased. For example, when the depth of the first grain boundary 102 is 10 nm, the hole lifetime is 250 μs; while when the depth of the first grain boundary 102 is 18 nm, the hole lifetime is only 120 μs. By statistically analyzing the experimental data, it can be determined that when the depth of the first grain boundary 102 is less than 15 nm, the hole lifetime is longer.

[0158] Furthermore, when the depth of the first grain boundary 102 is in the range of 8 - 14 nm, the hole lifetime reaches the optimal value, thereby improving the overall performance of the device.

[0159] In some embodiments, the depth of the second grain boundary 202 is greater than 10 nm.

[0160] In an N-type semiconductor, due to the doping of pentavalent impurities (such as phosphorus), there are differences in the size and electronic structure between the impurity atoms and silicon atoms. When the depth of the second grain boundary is greater than 10 nm, there is more space at the second grain boundary 202 to accommodate the lattice distortion caused by the mismatch between the impurity atoms and silicon atoms. The lattice around the impurity atoms will undergo stretching or compression, and the cumulative effect of this distortion is more obvious in the grain boundary region, thus generating a large stress.

[0161] A number of samples with different second grain boundary 202 depths were tested, and the experimental results showed that when the second grain boundary 202 depth is greater than 10nm, a good balance with the stress in the P region can be achieved, and the stress concentration phenomenon inside the silicon wafer will be alleviated. This is conducive to improving the stability of the silicon wafer in subsequent processing, such as reducing pattern deformation and dimensional deviation caused by stress in processes such as lithography and etching. At the same time, it also helps to improve the long-term stability and reliability of solar cells and reduce material fatigue and performance degradation caused by stress.

[0162] Furthermore, the depth of the second grain boundary 202 is within the range of 15 to 24 nm. If the depth of the second grain boundary is too large, exceeding the stress balance range that the silicon wafer can withstand, it may also cause stress imbalance inside the silicon wafer, increase the risk of silicon wafer cracking, and reduce the manufacturing yield of the solar cell. Setting the depth of the second grain boundary 202 within the range of 15 to 24 nm can better achieve stress balance, reduce material fatigue and performance degradation caused by stress, and improve the overall performance of the battery.

[0163] In some embodiments, at least one of the first region and the second region is suede.

[0164] The suede structure is a surface treatment technology that increases the scattering and absorption of light by forming tiny concave and convex structures on the surface of the material. The suede surface is usually formed by methods such as chemical etching or mechanical polishing. Chemical etching uses a specific etchant to form a tiny concave and convex structure on the surface of the material, while mechanical polishing forms a similar concave and convex structure on the surface of the material through mechanical force.

[0165] Specifically, the first region and the second region are both velvet, that is, the P-type polysilicon layer and the N-type polysilicon layer are both velvet layers. Alternatively, the first region is a velvet surface, and the second region is a polished surface, that is, the P-type polysilicon layer is a velvet layer, and the N-type polysilicon layer is a polished surface layer. Alternatively, the first region is a polished surface, and the second region is a velvet surface, that is, the P-type polysilicon layer is a polished surface layer, and the N-type polysilicon layer is a velvet layer.

[0166] The velvet structure can increase the scattering and reflection of light, extend the path of light in the material, and thus improve the light absorption efficiency. At least one of the first area and the second area is set as a velvet surface, which can improve the photoelectric conversion efficiency of the solar cell.

[0167] In some embodiments, both the first region and the second region are suede.

[0168] Specifically, both the P-type polysilicon layer and the N-type polysilicon layer are velvet layers. The double velvet structure can increase light scattering and absorption in the P-type polysilicon layer and the N-type polysilicon layer at the same time, optimize light absorption efficiency, and further improve the photoelectric conversion efficiency of the solar cell.

[0169] In some embodiments, both the first region and the second region are acid-etched facets.

[0170] An acid-etched facet is a type of matte surface, which is a microscopic structure formed on the surface of a silicon wafer through acid etching technology. Specifically, by adjusting the concentration, temperature, and time of the acid, the etching depth and surface topography can be controlled to meet different application requirements.

[0171] The acid-etched facet forms an irregular concavo-convex structure. This concavo-convex structure causes light to undergo multiple reflections and scatterings on the surface, extending the path length of photons within the silicon wafer, thereby improving the light absorption efficiency. The irregular structure can effectively reduce the reflection loss of light, allowing more light energy to enter the interior of the silicon wafer.

[0172] The acid etching treatment also increases the surface area of the silicon wafer, provides more carrier transport channels, improves the charge separation and collection efficiency, and the microscopic structure of the acid-etched facet can capture carriers, reducing their recombination loss on the surface, thereby improving the photoelectric conversion efficiency.

[0173] In this embodiment, both the first region and the second region are treated with acid-etched facets, which can ensure uniform light absorption and carrier transport performance across the entire surface of the cell, avoiding local performance differences.

[0174] In some embodiments, both the first region and the second region are polished surfaces.

[0175] A polished surface is a surface treatment technology that uses mechanical or chemical methods to make the material surface extremely smooth. Mechanical polishing usually uses a polishing agent and a polishing pad to make the material surface extremely smooth through mechanical force. Chemical polishing uses specific chemical reagents to form a smooth surface on the material surface.

[0176] In this embodiment, both the first region and the second region are polished surfaces, that is, both the P-type polysilicon layer and the N-type polysilicon layer are polished layers. The polished surface can reduce surface defects and impurities and improve the carrier transport efficiency. By setting both the first region and the second region as polished surfaces, the carrier transport efficiency of the solar cell can be improved, and carrier recombination can be reduced, thereby improving the photoelectric conversion efficiency.

[0177] In some embodiments, the roughness of the P-type polysilicon layer is less than that of the N-type polysilicon layer.

[0178] Roughness is a parameter that measures the flatness of a material surface. The higher the roughness, the lower the flatness of the material surface, and the lower the roughness, the higher the flatness of the material surface.

[0179] P-type polysilicon is usually formed by doping acceptor impurities such as boron (B). Boron atoms have a small size, cause less damage to the lattice structure during the doping process, are more likely to form a smooth surface, and P-type polysilicon is more likely to form a uniform grain structure during deposition and annealing. N-type polysilicon is usually formed by doping donor impurities such as phosphorus (P) or arsenic (As). Phosphorus and arsenic atoms have a large size, are likely to cause lattice distortion during the doping process, and due to the influence of doping atoms, the grain growth of N-type polysilicon may be uneven, resulting in an increase in surface roughness. The roughness of the P-type polysilicon layer is less than that of the N-type polysilicon layer, and it is easier to achieve in processing with lower processing difficulty.

[0180] In terms of performance, the surface of the P-type polysilicon layer with smaller roughness is smoother, reducing surface defects and trap states at grain boundaries, thereby reducing the recombination probability of carriers (electrons and holes) at the surface and grain boundaries. A lower carrier recombination rate can improve the carrier lifetime and efficiency of the device. At the same time, the interface quality between the P-type polysilicon layer and the N-type polysilicon layer is crucial for device performance. The smaller roughness of the P-type polysilicon layer than that of the N-type polysilicon layer can form a more uniform and stable interface, reducing the interface state density, thereby improving the electrical characteristics of the device.

[0181] Specifically, the root mean square roughness (RMS) of the material surface can be detected by an atomic force microscope (AFM). AFM uses a tiny probe (tip) to interact with the sample surface. When the probe approaches the sample surface, it is subject to various forces, such as van der Waals forces and electrostatic forces. By detecting the change in the force between the probe and the sample surface, AFM can accurately measure the height change of the probe when scanning the sample surface. During the scanning process, the probe moves point by point along the sample surface, recording the height value of each point relative to the reference plane. By statistically analyzing these height values, the root mean square roughness can be calculated.

[0182] The larger the value of RMS, the higher the surface roughness of the material; the smaller the value of RMS, the smaller the surface roughness of the material.

[0183] For example, the RMS value of the surface of the detected P-type polysilicon layer sample is 1.736 nm, and the RMS value of the surface of the detected N-type polysilicon layer sample is 6.928 nm. 1.736 nm < 6.928 nm, indicating that the roughness of the P-type polysilicon layer is less than that of the N-type polysilicon layer.

[0184] In this embodiment, based on the differences in processing characteristics and physical characteristics between P-type and N-type polysilicon, the smaller roughness of the P-type polysilicon layer than that of the N-type polysilicon layer can significantly reduce carrier recombination, improve carrier mobility, optimize interface characteristics, reduce leakage current, and improve the consistency and yield of the device.

[0185] In some embodiments, the surface of the N-type grain 201 has dense small holes.

[0186] The small holes refer to the tiny holes on the surface of the grain. The small holes on the surface of the N-type grain 201 are blind holes, and the small holes are densely distributed on the surface of the N-type grain 201. The small holes and the depressions 40 are two different surface structure features:

[0187] The size of the small holes is usually small, and the diameter may be between nanometers and micrometers (for example, 0.1 micrometer to 1 micrometer), and the distribution of the small holes is very dense, and the number of holes per unit area is large (for example, there are hundreds of small holes per square micrometer). Compared with the small holes, the size of the depressions 40 is usually large, and the diameter may be between micrometers and millimeters (for example, 1 micrometer to 100 micrometers), and the distribution of the depressions 40 is relatively sparse, and the number of depressions 40 per unit area is small (for example, there are dozens of depressions 40 per square micrometer).

[0188] The depth of the small holes is relatively shallow, usually equivalent to or slightly smaller than the diameter (for example, 0.1 micrometer to 1 micrometer), and the depth uniformity of the small holes is relatively high, and the overall surface is relatively flat. While the depth of the depressions 40 is relatively large, it may be much larger than its diameter (for example, 1 micrometer to 10 micrometers), and the depth of the depressions 40 is uneven, and may show an obvious undulating state.

[0189] The small holes are usually regular or irregular circles or ellipses. The presence of the small holes makes the surface present a porous structure, similar to a sponge or honeycomb. While the depressions 40 are usually irregular in shape, and may be in the shape of a long strip, a circle or an irregular polygon. The presence of the depressions 40 makes the surface present an uneven state, similar to a gully or a pothole.

[0190] The presence of the small holes causes the light to be reflected and scattered multiple times on the surface of the grain, increasing the path length of the photons in the N-type region, increasing the light scattering ability of the surface of the N-type grain, increasing the residence time of the photons in the N-type region, improving the light absorption efficiency, and helping to improve the overall performance of the solar cell.

[0191] In this embodiment, the surface of the N-type grain 201 has dense small holes, increasing the surface area and enhancing the light scattering, and improving the light absorption efficiency.

[0192] Furthermore, the aperture of the small holes is 0.1 - 2 nm.

[0193] This embodiment also provides a battery assembly, including the solar cell in the above embodiment.

[0194] The beneficial effects of the battery assembly are similar to those of the solar cell, and will not be elaborated here.

[0195] The battery module may include a plurality of back-contact solar cells. The plurality of back-contact solar cells in the battery module may be connected in series in sequence to form a battery string. Each battery string may be connected in series, parallel, or in a series-parallel combination to achieve the current collection and output. For example, the connection between each solar cell may be realized by welding a solder tape, and the connection between each battery string may be realized by a bus bar.

[0196] The battery module may further include a metal frame, a backsheet, a photovoltaic glass, and an encapsulant film (not shown in the figures). The encapsulant film may be filled between the light-facing surface of the solar cell and the photovoltaic glass, the backlight surface and the backsheet, and adjacent solar cells, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the encapsulant film may adopt an EVA encapsulant film or a POE encapsulant film, and the specific selection may be made according to the actual situation and is not limited herein.

[0197] The photovoltaic glass may cover the encapsulant film on the light-facing surface of the solar cell. The photovoltaic glass may be ultra-white glass, which has a high light transmittance, high transparency, and excellent physical, mechanical, and optical properties. For example, the light transmittance of the ultra-white glass can reach more than 92%, and it can protect the solar cell without affecting the efficiency of the solar cell as much as possible. At the same time, the encapsulant film may bond the photovoltaic glass and the solar cell together, and the presence of the encapsulant film can seal and insulate the solar cell and prevent water and moisture.

[0198] The backsheet may be attached to the encapsulant film on the backlight surface of the solar cell. The backsheet can protect and support the solar cell, and has reliable insulation, water resistance, and aging resistance. The backsheet can have multiple choices and is usually tempered glass, plexiglass, aluminum alloy TPT composite film, etc., and its specific setting can be made according to the specific situation and is not limited herein. The whole composed of the backsheet, the solar cell, the encapsulant film, and the photovoltaic glass may be arranged on the metal frame. The metal frame is the main external support structure of the entire battery module and can stably support and install the battery module. For example, the battery module can be installed at the required installation position through the metal frame.

[0199] This embodiment further provides a photovoltaic system, including the battery module in the above embodiment.

[0200] The beneficial effects of the photovoltaic system are similar to those of the battery module and will not be elaborated herein.

[0201] Photovoltaic systems can be applied in photovoltaic power stations, such as ground power stations, rooftop power stations, water surface power stations, etc., and can also be applied to devices or apparatuses that use solar energy for power generation, such as user solar power supplies, solar street lights, solar cars, solar buildings, and so on. Of course, it can be understood that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be applied in all fields that require solar power generation. Taking a photovoltaic power generation system network as an example, a photovoltaic system can include a photovoltaic array, a combiner box, and an inverter. The photovoltaic array can be an array combination of multiple battery components. For example, multiple battery components can form multiple photovoltaic arrays. The photovoltaic arrays are connected to the combiner box, and the combiner box can collect the current generated by the photovoltaic arrays. After the collected current flows through the inverter and is converted into alternating current required by the mains power grid, it is connected to the mains network to achieve solar power supply.

[0202] It can be understood that those skilled in the art can, under the guidance of the above embodiments, combine various implementation manners in the above various embodiments to obtain technical solutions of multiple implementation manners.

[0203] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate, the silicon substrate comprising a first region and a second region, a P-type polysilicon layer is disposed in the first region, and an N-type polysilicon layer is disposed in the second region; The P-type polysilicon layer includes a plurality of P-type crystal grains, the N-type polysilicon layer includes a plurality of N-type crystal grains, and the number of the P-type crystal grains per unit area in the first region is greater than the number of the N-type crystal grains per unit area in the second region.

2. The solar cell according to claim 1, characterized in that The silicon substrate has a light-facing surface and a backlight surface that are arranged opposite to each other, and the first area and the second area are both located on the backlight surface.

3. The solar cell according to claim 1, characterized in that The sum of the perimeters of the P-type grains within a unit area is greater than the sum of the perimeters of the N-type grains within a unit area.

4. The solar cell according to claim 1, characterized in that At least one of the first region and the second region is suede.

5. The solar cell according to claim 4, characterized in that: The first area and the second area are both suede.

6. The solar cell according to claim 1, characterized in that: Both the first region and the second region are polished surfaces.

7. The solar cell according to claim 1, characterized in that The roughness of the P-type polysilicon layer is smaller than the roughness of the N-type polysilicon layer.

8. A battery assembly, characterized in that: Comprising the solar cell described in any one of claims 1 to 7.

9. A photovoltaic system, characterized in that: A battery assembly comprising the battery assembly of claim 8.

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