LED chip and preparation method thereof
By introducing a transition layer between the AlInP restriction layer and the GaP current expansion layer in the LED chip, the lattice mismatch problem is solved, lattice defects are reduced, crystal quality and current diffusion uniformity are improved, and the photoelectric performance and stability of LED devices are improved.
Patent Information
- Application Number
- CN202510277922.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-05-30
AI Technical Summary
The lattice mismatch between the AlInP restriction layer and the GaP current expansion layer in the LED chip leads to lattice defects, affecting the uniformity of current diffusion and device stability.
A transition layer is introduced between the AlInP restriction layer and the GaP current expansion layer. The transition layer includes an alternately stacked first transition layer and a second transition layer. The first transition layer gradually introduces Ga components and reduces In components through the GayIn(1-y)P and GaAsnP(1-n) layers. The second transition layer gradually reduces As components and increases P components through the GaAszP(1-z)/GaP superlattice structure to achieve a transition between the material and the lattice.
The lattice defects between the AlInP restriction layer and the GaP current expansion layer are reduced, the crystal quality of the GaP current expansion layer and the epitaxial structure of the LED chip are improved, the uniformity of current diffusion is improved, and the photoelectric performance and stability of the LED devices are improved.
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Figure CN120076502A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to an LED chip and a method for manufacturing the same. Background Art
[0002] Currently, most of the AlGaInP-based light emitting diodes (LEDs) on the market have a same-side electrode structure. For this kind of chip structure, a relatively thick GaP current spreading layer needs to be grown on the AlInP confinement layer in the epitaxial structure. However, the lattice constant of the GaP material is 5.45, and the lattice constant of the AlInP material is 5.66, that is, there is a large difference in lattice constants between the AlInP confinement layer and the GaP current spreading layer, which will lead to a large lattice mismatch between the AlInP confinement layer and the GaP current spreading layer. Therefore, lattice defects will be formed at the interface between the AlInP confinement layer and the GaP current spreading layer. These lattice defects will cause uneven current diffusion, and the current will concentrate at the defects, ultimately resulting in an increase in the junction temperature and damage to the device.
[0003] Therefore, how to improve the lattice mismatch between the AlInP confinement layer and the GaP current spreading layer in the LED chip is an urgent problem to be solved. Summary of the Invention
[0004] To solve the above technical problems, embodiments of this application provide an LED chip and a method for manufacturing the same, so as to improve the lattice mismatch between the AlInP confinement layer and the GaP current spreading layer in the LED chip, reduce the lattice defects generated at the interface between the AlInP confinement layer and the GaP current spreading layer, improve the crystal quality of the epitaxial structure of the LED chip, and further improve the optoelectronic performance and stability of the device.
[0005] To achieve the above object, embodiments of this application provide the following technical solutions:
[0006] In a first aspect, an LED chip is provided, which includes a first-type confinement layer, an active layer, a second-type confinement layer, a transition layer, and a second-type current spreading layer that are stacked in sequence. The second-type confinement layer is an Al m In (1-m) P layer, where 0 < m < 1, the second-type current spreading layer is a GaP layer, and the transition layer includes a first transition layer and a second transition layer that are stacked in sequence along the direction from the second-type confinement layer to the second-type current spreading layer;
[0007] The first transition layer includes a first sub-layer and a second sub-layer that are alternately stacked. The first sub-layer is a Ga y In (1-y) P layer, and the second sub-layer is a GaAs n P (1-n)Layer, along the direction from the second-type confinement layer to the second-type current spreading layer, the Ga composition y of each of the first sub-layers gradually increases, and the In composition (1 - y) of each of the first sub-layers gradually decreases, where 0 < y < 1 and 0 < n < 1;
[0008] The second transition layer includes alternately stacked third sub-layers and fourth sub-layers, and the third sub-layer is GaAs z P (1-z) Layer, where z ≤ n, the fourth sub-layer is a GaP layer. Along the direction from the second-type confinement layer to the second-type current spreading layer, the As composition z of each of the third sub-layers gradually decreases to 0, and the P composition (1 - z) of each of the third sub-layers gradually increases to 1.
[0009] Optionally, the transition layer further includes a third transition layer located between the second-type confinement layer and the first transition layer. The third transition layer is (Al x Ga 1-x ) m In (1-m) P layer. Along the direction from the second-type confinement layer to the second-type current spreading layer, the Al composition x of the third transition layer gradually decreases from 1 to 0, and the Ga composition (1 - x) of the third transition layer gradually increases from 0 to 1;
[0010] In the first transition layer, the Ga composition y of each of the first sub-layers satisfies y ≥ m.
[0011] Optionally, m = 0.5 and n = 0.5;
[0012] The second-type confinement layer is an Al 0.5 In 0.5 P layer, and the third transition layer is (Al x Ga 1-x ) 0.5 In 0.5 P layer;
[0013] In the first transition layer, the Ga composition y of each of the first sub-layers satisfies: 0.5 ≤ y ≤ 0.8, and the In composition (1 - y) of each of the first sub-layers satisfies: 0.2 ≤ (1 - y) ≤ 0.5. The second sub-layer is a GaAs 0.5 P 0.5 layer.
[0014] Optionally, the layer of the first transition layer closest to the second transition layer is the first sub-layer, and the layer of the second transition layer closest to the first transition layer is the third sub-layer.
[0015] Optionally, the layer closest to the second transition layer in the first transition layer is the second sub-layer, and the layer closest to the first transition layer in the second transition layer is the fourth sub-layer.
[0016] Optionally, in the first transition layer, the thickness of the first sub-layer ranges from 2 nm to 15 nm, including the end values;
[0017] In the first transition layer, the thickness of the second sub-layer ranges from 2 nm to 15 nm, including the end values.
[0018] Optionally, in the first transition layer, one layer of the first sub-layer and an adjacent layer of the second sub-layer form a first periodic structure, and the number of periods of the first periodic structure in the first transition layer is 3 to 10, including the end values.
[0019] Optionally, in the second transition layer, the thickness of the third sub-layer ranges from 2 nm to 15 nm, including the end values;
[0020] In the second transition layer, the thickness of the fourth sub-layer ranges from 2 nm to 15 nm, including the end values.
[0021] Optionally, in the second transition layer, one layer of the third sub-layer and an adjacent layer of the fourth sub-layer form a second periodic structure, and the number of periods of the second periodic structure in the second transition layer is 3 to 10, including the end values.
[0022] Optionally, the first type of confinement layer is an N-type confinement layer, the second type of confinement layer is a P-type confinement layer, and the transition layer and the second type of current spreading layer are both P-type doped layers.
[0023] In a second aspect, a method for manufacturing an LED chip is provided, including:
[0024] Forming a first type of confinement layer, an active layer, and a second type of confinement layer stacked in sequence, where the second type of confinement layer is an Al m In (1-m) P layer, 0 < m < 1;
[0025] Forming a transition layer on a side of the second type of confinement layer facing away from the active layer, where the process of forming the transition layer includes:
[0026] Forming a first transition layer on a side of the second type of confinement layer facing away from the active layer, where the first transition layer includes the first sub-layer and the second sub-layer stacked alternately, and the first sub-layer is a Ga y In (1-y) P layer, and the second sub-layer is a GaAs n P (1-n)Layer, along the direction from the second-type confinement layer to the second-type current spreading layer, the Ga composition y of each of the first sub-layers gradually increases, and the In composition (1 - y) of each of the first sub-layers gradually decreases, where 0 < y < 1 and 0 < n < 1;
[0027] A second transition layer is formed on the side of the first transition layer away from the second-type confinement layer. The second transition layer includes alternately stacked third sub-layers and fourth sub-layers, and the third sub-layer is GaAs z P (1-z) Layer, z ≤ n, the fourth sub-layer is a GaP layer. Along the direction from the second-type confinement layer to the second-type current spreading layer, the As composition z of each of the third sub-layers gradually decreases to 0, and the P composition (1 - z) of each of the third sub-layers gradually increases to 1;
[0028] A second-type current spreading layer is formed on the side of the transition layer away from the second-type confinement layer. The second-type current spreading layer is a GaP layer.
[0029] Optionally, before forming the first transition layer, the formation process of the transition layer further includes:
[0030] A third transition layer is formed on the side of the second-type confinement layer away from the active layer. The third transition layer is an (Al x Ga 1-x ) m In (1-m) P layer. Along the direction away from the second-type confinement layer, the Al composition x of the third transition layer gradually decreases from 1 to 0, and the Ga composition (1 - x) of the third transition layer gradually increases from 0 to 1;
[0031] Subsequently, the first transition layer is formed on the side of the third transition layer away from the second-type confinement layer. In the first transition layer, the Ga composition y of each of the first sub-layers is y ≥ m.
[0032] Compared with the prior art, the above technical solution has the following advantages:
[0033] The LED chip provided by the embodiment of the present application includes a first-type confinement layer, an active layer, a second-type confinement layer, a transition layer, and a second-type current spreading layer stacked in sequence. The second-type confinement layer is an Al m In (1-m) P layer, 0 < m < 1, and the second-type current spreading layer is a GaP layer, that is, if directly on the second-type confinement layer (Al m In (1-m)If a second-type current spreading layer (GaP layer) is grown on the P layer, there will be a large lattice mismatch between them. Based on this, a transition layer is added between the second-type confinement layer and the second-type current spreading layer. Specifically, the transition layer includes a first transition layer and a second transition layer stacked in sequence along the direction from the second-type confinement layer to the second-type current spreading layer. Among them, the first transition layer includes a first sub-layer and a second sub-layer stacked alternately. The first sub-layer is a Ga y In (1-y) P layer. The Ga component y of the first sub-layer closest to the second-type confinement layer in the first transition layer can be controlled to make its lattice constant close to that of the second-type confinement layer. The second sub-layer is a GaAs n P (1-n) layer. And along the direction from the second-type confinement layer to the second-type current spreading layer, the Ga component y of each first sub-layer gradually increases, and the In component (1 - y) of each first sub-layer gradually decreases, where 0 < y < 1 and 0 < n < 1. In this way, the Ga component is introduced through the first transition layer, and the In component gradually decreases, thus transitioning to the second-type current spreading layer (GaP layer) in terms of materials. The second transition layer includes a third sub-layer and a fourth sub-layer stacked alternately. The third sub-layer is a GaAs z P (1-z) layer, z ≤ n, and the fourth sub-layer is a GaP layer. And along the direction from the second-type confinement layer to the second-type current spreading layer, the As component z of each third sub-layer gradually decreases to 0, and the P component (1 - z) of each third sub-layer gradually increases to 1. In this way, the second transition layer gradually reduces the As component and gradually increases the P component on the basis of the first transition layer, and transitions to the second-type current spreading layer (GaP layer) in terms of materials. At the same time, the first sub-layer and the second sub-layer stacked alternately in the first transition layer form a Ga y In (1-y) P / GaAs n P (1-n) superlattice structure, and the third sub-layer and the fourth sub-layer stacked alternately in the second transition layer form a GaAs z P (1-z) / GaP superlattice structure. Since the superlattice grows alternately, it can offset the stress, thereby reducing the dislocation generated at the interface due to the sudden change in lattice size, and at the same time reducing the defect diffusion caused by stress concentration, realizing the lattice transition from the second-type confinement layer (Al m In (1-m) P layer) to the second-type current spreading layer (GaP layer), and improving the crystal quality of the second-type current spreading layer (GaP layer).
[0034] Moreover, the elements of the second transition layer 42 are Ga, As, and P. Among them, both elements As and P are group V elements, and the element Ga is a group III element. When growing the second transition layer 42, the As source and the P source are in excess, and only the Ga source contributes to the growth rate. Therefore, by controlling only the flow rate of the Ga source, the growth rate of the second transition layer 42 can be better controlled, thereby better controlling the growth quality of the second transition layer 42, which is further conducive to improving the crystal quality of the second type current spreading layer 50 (GaP layer).
[0035] That is to say, for the LED chip provided by the embodiment of the present application, by arranging a transition layer between the second type confinement layer (Al m In (1-m) P layer) and the second type current spreading layer (GaP layer), the lattice mismatch between the AlInP confinement layer and the GaP current spreading layer in the LED chip is improved, the lattice defects generated at the interface between the AlInP confinement layer and the GaP current spreading layer are reduced, the crystal quality of the GaP current spreading layer and the epitaxial structure of the LED chip is improved, the current diffusion is made more uniform, and thus the optoelectronic performance and stability of the LED device are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0037] Figure 1 FIG. is a schematic cross-sectional structure diagram of an LED chip provided by an embodiment of the present application;
[0038] Figure 2 FIG. is a schematic cross-sectional structure diagram of the second type confinement layer 30, the transition layer 40, and the second type current spreading layer 50 in the LED chip provided by an embodiment of the present application;
[0039] Figure 3 FIG. is another schematic cross-sectional structure diagram of the second type confinement layer 30, the transition layer 40, and the second type current spreading layer 50 in the LED chip provided by an embodiment of the present application;
[0040] Figure 4 FIG. is still another schematic cross-sectional structure diagram of the second type confinement layer 30, the transition layer 40, and the second type current spreading layer 50 in the LED chip provided by an embodiment of the present application.
[0041] Reference Numerals:
[0042] 10 - Type I confinement layer; 20 - active layer; 30 - Type II confinement layer; 40 - transition layer; 50 - Type II current spreading layer; 41 - first transition layer; 411 - first sub - layer; 412 - second sub - layer; 42 - second transition layer; 421 - third sub - layer; 422 - fourth sub - layer; 101 - substrate; 102 - buffer layer; 103 - etch stop layer; 104 - ohmic contact layer; 105 - Type I current spreading layer; T1 - first periodic structure; T2 - second periodic structure. Detailed implementation manners
[0043] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
[0044] The terms "first", "second", etc. in the specification and claims of the present application and the above - mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non - exclusive inclusion, so that a process, method, system, product or device including a series of units does not necessarily have to be limited to those units, but may include other units that are not clearly listed or are inherent to these processes, methods, products or devices.
[0045] Secondly, the present application will be described in detail in conjunction with the schematic diagrams. When detailing the embodiments of the present application, for the convenience of description, the accompanying drawings showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present application here. In addition, in actual production, three - dimensional spatial dimensions including length, width and depth should be included.
[0046] As described in the background art section, how to improve the lattice mismatch between the AlInP confinement layer and the GaP Type II current spreading layer in an LED chip is an urgent problem to be solved.
[0047] In view of this, the embodiments of the present application provide an LED chip. Figure 1 The cross - sectional structure schematic diagram of an LED chip provided by the embodiments of the present application is shown, as Figure 1 shown, the LED chip includes a Type I confinement layer 10, an active layer 20, a Type II confinement layer 30, a transition layer 40, and a Type II current spreading layer 50 stacked in sequence. The Type II confinement layer 30 is Al mIn (1-m) The P layer, where 0 < m < 1, and the second-type current spreading layer 50 is a GaP layer. If the second-type current spreading layer 50 (GaP layer) is directly grown on the second-type confinement layer 30 (Al m In (1-m) P layer), there will be a large lattice mismatch between them. For example, when m = 0.5, the second-type confinement layer 30 is Al 0.5 In 0.5 P layer, the lattice constant of the second-type confinement layer 30 (Al 0.5 In 0.5 P layer) is 5.66 Å, while the lattice constant of the second-type current spreading layer 50 (GaP layer) is 5.45 Å, resulting in a large lattice mismatch between them.
[0048] Based on this, as Figure 1 shown, a transition layer 40 is added between the second-type confinement layer 30 and the second-type current spreading layer 50 to improve the lattice mismatch between the second-type confinement layer 30 (Al m In (1-m) P layer) and the second-type current spreading layer 50 (GaP layer).
[0049] Figure 2 FIG. shows a schematic cross-sectional structure of the second-type confinement layer 30, the transition layer 40, and the second-type current spreading layer 50 in the LED chip provided by the embodiment of the present application. As Figure 2 shown, the transition layer 40 includes a first transition layer 41 and a second transition layer 42 stacked in sequence along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50.
[0050] Among them, the first transition layer 41 includes a first sub-layer 411 and a second sub-layer 412 stacked alternately. The first sub-layer 411 is a Ga y In (1-y) P layer, and the second sub-layer 412 is a GaAs n P (1-n) layer. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the Ga component y of each first sub-layer 411 gradually increases, and the In component (1 - y) of each first sub-layer 411 gradually decreases, where 0 < y < 1 and 0 < n < 1;
[0051] The second transition layer 42 includes a third sub-layer 421 and a fourth sub-layer 422 stacked alternately. The third sub-layer 421 is a GaAs z P (1-z) layer, where z ≤ n, and the fourth sub-layer 422 is a GaP layer. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the As component z of each third sub-layer 421 gradually decreases to 0, and the P component (1 - z) of each third sub-layer gradually increases to 1.
[0052] It is understandable that the second type of confinement layer 30 is Al m In (1-m) P layer, where 0 < m < 1, the second type of current spreading layer 50 is a GaP layer, and the transition layer 40 needs to achieve the transition in terms of materials and lattice between the second type of confinement layer 30 and the second type of current spreading layer 50. Specifically,
[0053] For the first transition layer 41 closer to the second type of confinement layer 30 in the transition layer 40, its first sublayer 411 is Ga y In (1-y) P layer, where 0 < y < 1. The Ga composition y of the first sublayer 411 closest to the second type of confinement layer 30 in the first transition layer 41 can be set such that the lattice constant of the first sublayer 411 closest to the second type of confinement layer 30 in the first transition layer 41 is close to the lattice constant of the second type of confinement layer 30. For example, the Ga composition y of the first sublayer 411 closest to the second type of confinement layer 30 in the first transition layer 41 can be set to y = 0.5, that is, the first sublayer 411 closest to the second type of confinement layer 30 in the first transition layer 41 is Ga 0.5 In 0.5 P layer, and the lattice constant of the Ga 0.5 In 0.5 P layer is close to the lattice constant of the second type of confinement layer 30 (such as Al 0.5 In 0.5 P layer).
[0054] Moreover, through the first sublayer 411 (Ga y In (1-y) P layer) of the first transition layer 41, the Ga composition is introduced, and by setting the direction from the second type of confinement layer 30 to the second type of current spreading layer 50, the Ga composition y of each first sublayer 411 gradually increases, and the In composition (1 - y) of each first sublayer 411 gradually decreases, so that the In composition gradually decreases, thereby achieving the transition in terms of materials to the second type of current spreading layer 50 (GaP layer).
[0055] It should be noted that in the first transition layer 41, along the direction from the second type of confinement layer 30 to the second type of current spreading layer 50, the Ga composition y of each first sublayer 411 gradually increases, and the In composition (1 - y) of each first sublayer 411 gradually decreases, which means that along the direction from the second type of confinement layer 30 to the second type of current spreading layer 50, the Ga composition of the (i + 1)-th first sublayer 411 is greater than that of the i-th first sublayer 411, and the In composition of the (i + 1)-th first sublayer 411 is less than that of the i-th first sublayer 411.
[0056] It should also be noted that in the first transition layer 41, along the direction from the second type confinement layer 30 to the second type current spreading layer 50, the Ga component y of each first sub-layer 411 gradually increases, and the In component (1 - y) of each first sub-layer 411 gradually decreases. Then, the lattice constant of each first sub-layer 411 will gradually increase, while the lattice transition from the second type confinement layer 30 to the second type current spreading layer 50 requires a gradual decrease in the lattice constant. In order to reduce the lattice mismatch caused by material transition in the first transition layer 41, the first transition layer 41 is set to include alternately stacked first sub-layers 411 (Ga y In (1-y) P layer) and second sub-layers 412 (GaAs n P (1-n) layer). For example, when n = 0.5, the second sub-layer 412 is GaAs 0.5 P 0.5 layer. At this time, the lattice constant of the second sub-layer 412 (GaAs 0.5 P 0.5 layer) is 5.55 Å. That is, in the first transition layer 41, the lattice constant of the first sub-layer 411 is large, and the lattice constant of the second sub-layer 412 is small. The equivalent lattice constant of the first transition layer 41 is the lattice transition from the second type confinement layer 30 to the second type current spreading layer 50.
[0057] It should be further noted that the alternately stacked first sub-layers 411 (Ga y In (1-y) P layer) and second sub-layers 412 (GaAs n P (1-n) layer) in the first transition layer 41 form a Ga y In (1-y) P / GaAs n P (1-n) superlattice structure. The alternate growth of the superlattice can offset the stress, thereby reducing the dislocation generated at the interface due to the sudden change in lattice size. At the same time, it can also reduce the defect diffusion caused by stress concentration, and improve the crystal quality of the subsequent grown film layer.
[0058] For the second transition layer 42 in the transition layer 40 that is closer to the second type current spreading layer 50, its third sub-layer 421 is GaAs z P (1-z) layer, z ≤ n, the fourth sub-layer 422 is a GaP layer. And, along the direction from the second type confinement layer 30 to the second type current spreading layer 50, the As component z of each third sub-layer 421 gradually decreases to 0, and the P component (1 - z) of each third sub-layer 421 gradually increases to 1. That is, in the second transition layer 42, the third sub-layer 421 (GaAs z P (1-z) layer) in the first transition layer 41 is the second sub-layer 412 (GaAs nP (1-n) On the basis of the (layer), the As component gradually decreases and the P component gradually increases, transitioning both in terms of material and crystal lattice to the second-type current spreading layer 50 (GaP layer).
[0059] It should be noted that in the second transition layer 42, along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the As component z of each third sub-layer 421 gradually decreases to 0, and the P component (1 - z) of each third sub-layer gradually increases to 1, which means that along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the As component of the (j + 1)-th third sub-layer 421 is less than that of the j-th third sub-layer 421, and the P component of the (j + 1)-th third sub-layer 421 is greater than that of the j-th third sub-layer 421.
[0060] It should also be noted that the third sub-layers 421 (GaAs z P (1-z) layers) and the fourth sub-layers 422 (GaP layers) stacked alternately in the second transition layer 42 form a GaAs z P (1-z) / GaP superlattice structure. The alternate growth of the superlattice can offset stress, thereby reducing the dislocations generated at the interface due to the sudden change in lattice size, and at the same time can also reduce the defect diffusion caused by stress concentration, realizing the lattice transition to the second-type current spreading layer 50 (GaP layer) and improving the crystal quality of the second-type current spreading layer 50 (GaP layer).
[0061] Moreover, the elements in the second transition layer 42 are Ga, As, and P. Among them, both elements As and P are group V elements, and the element Ga is a group III element. When growing the second transition layer 42, both the As source and the P source are in excess, and only the Ga source contributes to the growth rate. Therefore, by only controlling the flow rate of the Ga source, the growth rate of the second transition layer 42 can be better controlled, thereby better controlling the growth quality of the second transition layer 42, which is further conducive to improving the crystal quality of the second-type current spreading layer 50 (GaP layer).
[0062] Thus, it can be seen that the LED chip provided by the embodiment of the present application improves the lattice mismatch between the AlInP confinement layer and the GaP current spreading layer in the LED chip by setting a transition layer 40 between the second-type confinement layer 30 (Al m In (1-m) P layer) and the second-type current spreading layer 50 (GaP layer), reduces the lattice defects generated at the interface between the AlInP confinement layer and the GaP current spreading layer, improves the crystal quality of the GaP current spreading layer and the epitaxial structure of the LED chip, makes the current diffusion more uniform, and further improves the optoelectronic performance and stability of the LED device.
[0063] Figure 3Fig. shows another schematic cross-sectional structure of the second-type confinement layer 30, the transition layer 40, and the second-type current spreading layer 50 in the LED chip provided by the embodiments of the present application, as Figure 3 shown, the transition layer 40 further includes a third transition layer 43 located between the second-type confinement layer 30 and the first transition layer 41. The third transition layer 43 is an (Al x Ga 1-x ) m In (1-m) P layer. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the Al component x of the third transition layer 43 gradually decreases from 1 to 0, and the Ga component (1 - x) of the third transition layer gradually increases from 0 to 1.
[0064] This is because, as known from the foregoing, the Ga component y of the first sub-layer 411 closest to the second-type confinement layer 30 in the first transition layer 41 can be set so that the lattice constant of the first sub-layer 411 closest to the second-type confinement layer 30 in the first transition layer 41 is close to the lattice constant of the second-type confinement layer 30. However, in order to introduce the Ga component in the first transition layer 41, the first sub-layer 411 thereof is a Ga y In (1-y) P layer, and its second sub-layer 412 is a GaAs n P (1-n) layer, while the second-type confinement layer 30 is an Al m In (1-m) P layer. That is, when changing from the second-type confinement layer 30 to the first transition layer 41, the Al component is directly changed to the Ga component. In actual processes, even if the Al source is replaced with a Ga source, since there is still residual Al source in the reaction chamber and pipelines, it may cause Al impurities during the growth of the first transition layer 41.
[0065] In order to achieve a good transition from the second-type confinement layer 30 (Al m In (1-m) P layer) to the first transition layer 41, in this embodiment, a third transition layer 43 is added between the second-type confinement layer 30 and the first transition layer 41. The third transition layer 43 is an (Al x Ga 1-x ) m In (1-m) P layer, which not only increases the Ga component but also retains the Al component. Moreover, the third transition layer 43 is a graded layer. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the Al component x of the third transition layer 43 gradually decreases from 1 to 0, and the Ga component (1 - x) of the third transition layer gradually increases from 0 to 1. That is, the material of the third transition layer 43 gradually changes from Al m In (1-m) P to Ga m In (1-m)P such that the Al component gradually decreases and the Ga component gradually increases, achieving a smooth transition from the second-type confinement layer 30 (Al m In (1-m) P layer) to the first transition layer 41.
[0066] Moreover, the lattice constant of the third transition layer 43 is close to that of the second-type confinement layer 30. For example, when m = 0.5, along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the material of the third transition layer 43 changes from Al 0.5 In 0.5 P to Ga 0.5 In 0.5 P. The lattice constant is basically 5.66 Å, which is basically the same as that of the second-type confinement layer 30. That is, the third transition layer 43 is a lattice-matching layer for the second-type confinement layer 30. Without introducing lattice mismatch, the Al component gradually decreases and the Ga component gradually increases, which is beneficial to the growth quality of the subsequent first transition layer 41 and second transition layer 42.
[0067] It can be understood that in this embodiment, for each first sublayer 411 (Ga y In (1-y) P layer) in the first transition layer 41, the Ga component y ≥ m. That is to say, in the first transition layer 41, on the basis of the third transition layer 43, along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the Ga component y of each first sublayer 411 gradually increases. For example, when m = 0.5, then, along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the material of the third transition layer 43 changes from Al 0.5 In 0.5 P to Ga 0.5 In 0.5 P. In the first transition layer 41, for each first sublayer 411 (Ga y In (1-y) P layer), the Ga component further gradually increases on the basis of 0.5.
[0068] Based on the above embodiment, optionally, in some embodiments of the present application, when m = 0.5, then the second-type confinement layer 30 is an Al 0.5 In 0.5 P layer, the third transition layer 43 is an (Al x Ga 1-x ) 0.5 In 0.5 P layer. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the Al component x of the third transition layer 43 gradually decreases from 1 to 0, and the Ga component (1 - x) of the third transition layer 43 gradually increases from 0 to 1. The material of the third transition layer 43 changes from Al0.5 In 0.5 P is gradually transformed into Ga 0.5 In 0.5 For InP, the lattice constants of both the third transition layer 43 and the second confinement layer 30 are 5.66 Å. That is, the third transition layer 43 is a lattice-matched layer for the second confinement layer 30. Without introducing lattice mismatch, the Al component in the third transition layer 43 gradually decreases, and the Ga component gradually increases.
[0069] Moreover, in the first transition layer 41, for each first sub-layer 411 (Ga y In (1-y) P layer), the Ga component y satisfies: 0.5 ≤ y ≤ 0.8, and the In component (1 - y) of each first sub-layer 411 (Ga y In (1-y) P layer) satisfies: 0.2 ≤ (1 - y) ≤ 0.5. That is to say, in the first transition layer 41, along the direction from the second confinement layer 30 to the second current spreading layer 50, for each first sub-layer 411 (Ga y In (1-y) P layer), the Ga component y gradually changes from 0.5 to 0.8, and the In component (1 - y) of each first sub-layer 411 (Ga y In (1-y) P layer) gradually changes from 0.5 to 0.2. As the Ga component of each first sub-layer 411 (Ga y In (1-y) P layer) increases, its lattice constant gradually changes to 5.78 Å; and, n = 0.5, each second sub-layer 412 (GaAs n P (1-n) layer) in the first transition layer 41 is a GaAs 0.5 P 0.5 layer, and the lattice constant of each second sub-layer 412 is 5.55, which is between the lattice constant (5.66 Å) of the second confinement layer 30 (Al 0.5 In 0.5 P) and the lattice constant (5.45 Å) of the second current spreading layer 50 (GaP layer).
[0070] Thus, on the basis of the third transition layer 43, for each first sub-layer 411 of the first transition layer 41, along the direction from the second confinement layer 30 to the second current spreading layer 50, the Ga component y gradually increases from 0.5 to 0.8, and the In component gradually decreases from 0.5 to 0.2, thereby making a transition in terms of materials to the second current spreading layer 50 (GaP layer); moreover, although the lattice constant of each first sub-layer 411 (Ga y In (1-y) P layer) in the first transition layer 41 gradually increases as the Ga component increases, each second sub-layer 412 (GaAsn P (1-n) The lattice constant of the (layer) is between the lattice constant of the second-type confinement layer 30 (Al 0.5 In 0.5 P) and the lattice constant of the second-type current spreading layer 50 (GaP layer), so that the equivalent lattice constant of the first transition layer 41 is a lattice transition from the second-type confinement layer 30 to the second-type current spreading layer 50; meanwhile, the first sub-layer 411 (Ga y In (1-y) P layer) and the second sub-layer 412 (GaAs n P (1-n) layer) that are alternately stacked in the first transition layer 41 form a Ga y In (1-y) P / GaAs n P (1-n) superlattice structure. The alternate growth of the superlattice can offset the stress, thereby reducing the dislocations generated at the interface due to the sudden change in lattice size, and at the same time reducing the defect diffusion caused by stress concentration, and improving the crystal quality of the subsequent grown film layer.
[0071] In the second transition layer 42, along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, for each third sub-layer 421 (GaAs z P (1-z) layer), the As component z gradually decreases from 0.5 to 0, and the P component (1 - z) of each third sub-layer 421 (GaAs z P (1-z) layer) gradually increases to 1. Each fourth sub-layer 422 is a GaP layer, and both in terms of material and lattice, it transitions to the second-type current spreading layer 50 (GaP layer). Moreover, the third sub-layer 421 (GaAs z P (1-z) layer) and the fourth sub-layer 422 (GaP layer) that are alternately stacked in the second transition layer 42 form a GaAs z P (1-z) / GaP superlattice structure. The alternate growth of the superlattice can offset the stress, thereby reducing the dislocations generated at the interface due to the sudden change in lattice size, and at the same time reducing the defect diffusion caused by stress concentration, achieving a lattice transition to the second-type current spreading layer 50 (GaP layer) and improving the crystal quality of the second-type current spreading layer 50 (GaP layer).
[0072] Based on any of the above embodiments, optionally, as Figure 2 and Figure 3 shown, in some embodiments of the present application, the layer of the first transition layer 41 closest to the second transition layer 42 is the first sub-layer 411, that is, Ga y In (1-y)The P layer, the layer in the second transition layer 42 closest to the first transition layer 41 is the third sub-layer 421, i.e., GaAs z P (1-z) layer. Thus, the layer in the first transition layer 41 closest to the second transition layer 42 and the layer in the second transition layer 42 closest to the first transition layer 41 are similar to the first sub-layer 411 and the second sub-layer 412 in the first transition layer 41, enabling the first transition layer 41 to transition well to the second transition layer 42.
[0073] Optionally, in some other embodiments of the present application, as Figure 4 shown, the layer in the first transition layer 41 closest to the second transition layer 42 is the second sub-layer 412, i.e., GaAs n P (1-n) layer. The layer in the second transition layer 42 closest to the first transition layer 41 is the fourth sub-layer 422, i.e., GaP layer. Thus, the layer in the first transition layer 41 closest to the second transition layer 42 and the layer in the second transition layer 42 closest to the first transition layer 41 are similar to the third sub-layer 421 and the fourth sub-layer 422 in the second transition layer 42, enabling the first transition layer 41 to transition well to the second transition layer 42.
[0074] It should be noted that the present application does not limit whether the layer in the first transition layer 41 closest to the second-type confinement layer 30 is the first sub-layer 411 or the second sub-layer 412, i.e., the layer in the first transition layer 41 closest to the second-type confinement layer 30 can be the first sub-layer 411 or the second sub-layer 412.
[0075] The present application does not limit whether the layer in the second transition layer 42 closest to the second-type current spreading layer 50 is the third sub-layer 421 or the fourth sub-layer 422. Even if the layer in the second transition layer 42 closest to the second-type current spreading layer 50 is the third sub-layer 421 (Ga z P (1-z) layer), since z will eventually decrease to 0, i.e., the third sub-layer 421 in the second transition layer 42 closest to the second-type current spreading layer 50 is also a GaP layer, so that the second-type current spreading layer 50 grows on the GaP layer, resulting in good growth quality of the second-type current spreading layer 50.
[0076] As known from the foregoing, the first sub-layer 411 (Ga y In (1-y) P layer) and the second sub-layer 412 (GaAs n P (1-n) layer) alternately stacked in the first transition layer 41 constitute Ga y In (1-y) P / GaAs n P (1-n)For a superlattice structure, the thicknesses of the first sub-layer 411 and the second sub-layer 412 need to be small. Optionally, in the first transition layer 41, the thickness of the first sub-layer 411 ranges from 2 nm to 15 nm, including the end values; the thickness of the second sub-layer 412 ranges from 2 nm to 15 nm, including the end values, so as to facilitate the formation of a Ga y In (1-y) P layer) and the second sub-layer 412 (GaAs n P (1-n) layer) to form a Ga y In (1-y) P / GaAs n P (1-n) superlattice structure.
[0077] It should be noted that in the first transition layer 41, the thicknesses of the first sub-layers 411 can be equal, or at least two of the first sub-layers 411 can have different thicknesses. This application does not limit whether the thicknesses of the first sub-layers 411 are equal, as long as the thicknesses of the first sub-layers 411 are within a certain range (such as 2 nm - 15 nm).
[0078] Similarly, in the first transition layer 41, the thicknesses of the second sub-layers 412 can be equal, or at least two of the second sub-layers 412 can have different thicknesses. This application does not limit whether the thicknesses of the second sub-layers 412 are equal, as long as the thicknesses of the second sub-layers 412 are within a certain range (such as 2 nm - 15 nm).
[0079] It can be understood that, as Figures 2 - 4 shown, in the first transition layer 41, one first sub-layer 411 and an adjacent second sub-layer 412 form a first periodic structure T1. The number of periods of the first periodic structure T1 in the first transition layer 41 can be 3 - 10, including the end values.
[0080] Similar to the first transition layer 41, in the second transition layer 42, the third sub-layer 421 (GaAs z P (1-z) layer) and the fourth sub-layer 422 (GaP layer) form a GaAs z P (1-z) / GaP superlattice structure. Then, the thicknesses of the third sub-layer 421 and the fourth sub-layer 422 need to be small. Optionally, in the second transition layer 42, the thickness of the third sub-layer 421 ranges from 2 nm to 15 nm, including the end values; the thickness of the fourth sub-layer 422 ranges from 2 nm to 15 nm, including the end values, so as to facilitate the formation of an alternating stack of the third sub-layer 421 (GaAs z P (1-z) layer) and the fourth sub-layer 422 (GaP layer) to form a GaAs z P(1-z) / GaP superlattice structure.
[0081] It should be noted that in the second transition layer 42, the thicknesses of the third sub-layers 421 may be equal, or at least two of the third sub-layers 421 may have different thicknesses. This application does not limit whether the thicknesses of the third sub-layers 421 are equal, as long as the thicknesses of the third sub-layers 421 are within a certain range (such as 2 nm - 15 nm).
[0082] Similarly, in the second transition layer 42, the thicknesses of the fourth sub-layers 422 may be equal, or at least two of the fourth sub-layers 422 may have different thicknesses. This application does not limit whether the thicknesses of the fourth sub-layers 422 are equal, as long as the thicknesses of the fourth sub-layers 422 are within a certain range (such as 2 nm - 15 nm).
[0083] It can be understood that as Figures 2 - 4 shown, in the second transition layer 42, one third sub-layer 421 and an adjacent fourth sub-layer 422 form a second periodic structure T2. The number of periods of the second periodic structure T2 in the second transition layer 42 can be 3 - 10, including the end values.
[0084] Based on any of the above embodiments, optionally, in some embodiments of this application, referring to Figure 1 shown, the first type of confinement layer 10 is an N-type confinement layer, the second type of confinement layer 30 is a P-type confinement layer, the transition layer 40 and the second type of current spreading layer 50 are both P-type doped layers. The doping element for P-type doping in the transition layer 40 can be Mg or Zn, and the doping element for P-type doping in the second type of current spreading layer 50 can be Mg, Zn or C.
[0085] Specifically, referring to Figure 1 shown, a buffer layer 102, an etch stop layer 103, an ohmic contact layer 104, a first type of current spreading layer 105, a first type of confinement layer 10, an active layer 20, a second type of confinement layer 30, a transition layer 40, and a second type of current spreading layer 50 are sequentially grown on a substrate 101 to obtain Figure 1 the epitaxial structure of the LED chip shown. Among them, the substrate 101 can be a GaAs 15° substrate; the buffer layer 102 can be a GaAs layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm -3 ; the etch stop layer 103 can be a GaInP layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm -3 ; the ohmic contact layer 104 can be a GaAs layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm -3; The first-type current spreading layer 105 can be an AlGaInP layer, the doping element can be Si / Te, and the doping concentration can be 1E18~5E18 cm -3 ; The first-type confinement layer 10 can be an N-type AlInP layer, the doping element can be Si / Te, and the doping concentration can be 1E18~3E18 cm -3 ; The active layer 20 is an undoped layer; the second-type confinement layer 30 can be a P-type AlInP layer, the doping element can be Mg / Zn, and the doping concentration can be 1E18~5E18 cm -3 .
[0086] Correspondingly, the embodiment of the present application also provides a method for manufacturing an LED chip. Referring to Figure 1 and Figure 2 shown, the method for manufacturing the LED chip includes:
[0087] S100: Form a first-type confinement layer 10, an active layer 20, and a second-type confinement layer 30 stacked in sequence. The second-type confinement layer 30 is an Al m In (1-m) P layer, 0 < m < 1.
[0088] S200: Form a transition layer 40 on the side of the second-type confinement layer 30 away from the active layer 20. The formation process of the transition layer 40 includes:
[0089] S210: Form a first transition layer 41 on the side of the second-type confinement layer 30 away from the active layer 20. The first transition layer 41 includes alternately stacked first sub-layers 411 and second sub-layers 412. The first sub-layers 411 are Ga y In (1-y) P layers, and the second sub-layers 412 are GaAs n P (1-n) layers. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the Ga component y of each first sub-layer 411 gradually increases, and the In component (1 - y) of each first sub-layer 411 gradually decreases, 0 < y < 1, 0 < n < 1;
[0090] S220: Form a second transition layer 42 on the side of the first transition layer 41 away from the second-type confinement layer 30. The second transition layer 42 includes alternately stacked third sub-layers 421 and fourth sub-layers 422. The third sub-layers 421 are GaAs z P (1-z) layers, z ≤ n, and the fourth sub-layers 422 are GaP layers. Along the direction from the second-type confinement layer 30 to the second-type current spreading layer 50, the As component z of each third sub-layer 421 gradually decreases to 0, and the P component (1 - z) of each third sub-layer 421 gradually increases to 1.
[0091] S300: Form a second-type current spreading layer 50 on the side of the transition layer 40 away from the second-type confinement layer 30. The second-type current spreading layer 50 is a GaP layer.
[0092] Optionally, as shown in Figure 3 and Figure 4 Before forming the first transition layer 41, the formation process of the transition layer 40 further includes:
[0093] S230: Form a third transition layer 43 on the side of the second-type confinement layer 30 away from the active layer 20. The third transition layer 43 is an (Al x Ga 1-x ) m In (1-m) P layer. Along the direction away from the second-type confinement layer 30, the Al component x of the third transition layer 43 gradually decreases from 1 to 0, and the Ga component (1 - x) of the third transition layer 43 gradually increases from 0 to 1.
[0094] In the subsequent step S210, form a first transition layer 41 on the side of the third transition layer 43 away from the second-type confinement layer 30. In the first transition layer 41, the Ga component y of each first sub-layer 411 ≥ m.
[0095] Specifically, as shown in Figures 1 - 4 , the method for manufacturing an LED chip provided by the embodiment of the present application includes:
[0096] 1. Provide a substrate 101, place the substrate 101 in a reaction chamber. The substrate 101 can be a GaAs 15° substrate;
[0097] 2. After heating, grow a buffer layer 102 on the substrate 101. The buffer layer 102 can be a GaAs layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm -3 ;
[0098] 3. Grow a corrosion stop layer 103 on the buffer layer 102. The corrosion stop layer 103 can be a GaInP layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm -3 ;
[0099] 4. Grow an ohmic contact layer 104 on the corrosion stop layer 103. The ohmic contact layer 104 can be a GaAs layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm -3 ;
[0100] 5. Grow a first-type current spreading layer 105 on the ohmic contact layer 104. The first-type current spreading layer 105 can be an AlGaInP layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 5E18 cm-3 ;
[0101] 6. Grow a first-type confinement layer 10 on the first-type current spreading layer 105. The first-type confinement layer 10 can be an N-type AlInP layer, the doping element can be Si / Te, and the doping concentration can be 1E18 - 3E18 cm -3 ;
[0102] 7. Grow an active layer 20 on the first-type confinement layer 10. The active layer 20 is an undoped layer;
[0103] 8. Grow a second-type confinement layer 30 on the active layer 20. The second-type confinement layer 30 can be a P-type AlInP layer, the doping element can be Mg / Zn, and the doping concentration can be 1E18 - 5E18 cm -3 ;
[0104] 9. Grow a transition layer 40 on the second-type confinement layer 30. The transition layer 40 is a P-type doped layer. The doping element for P-type doping in the transition layer 40 can be Mg or Zn. The transition layer 40 has been described before and will not be elaborated here.
[0105] 10. Grow a second-type current spreading layer 50 on the transition layer 40. The second-type current spreading layer 50 is a P-type GaP layer. The doping element for P-type doping in the second-type current spreading layer 50 can be Mg, Zn or C.
[0106] For the LED chip prepared by the method provided in the embodiments of the present application, by setting a transition layer 40 between the second-type confinement layer 30 (Al m In (1-m) P layer) and the second-type current spreading layer 50 (GaP layer), the lattice mismatch between the AlInP confinement layer and the GaP current spreading layer in the LED chip is improved, the lattice defects generated at the interface between the AlInP confinement layer and the GaP current spreading layer are reduced, the crystal quality of the GaP current spreading layer and the epitaxial structure of the LED chip is improved, the current diffusion becomes more uniform, and thus the optoelectronic performance and stability of the LED device are improved.
[0107] Specifically, the specific implementation manners of the transition layer 40 have been elaborated in detail in the foregoing embodiments and can be referred to the foregoing, and will not be elaborated here.
[0108] In this specification, each part is described in a combined manner of parallel and progressive. The key point of each part is to illustrate the differences from other parts. For the same or similar parts among each part, reference can be made to each other.
[0109] Regarding the above description of the disclosed embodiments, the features described in each embodiment in this specification can be replaced or combined with each other, enabling those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but rather will conform to the broadest scope consistent with the principles and novel features disclosed herein.
Claims
1. An LED chip, characterized in that: It includes a first-type confinement layer, an active layer, a second-type confinement layer, a transition layer, and a second-type current spreading layer stacked in sequence. The second-type confinement layer is Al m In (1-m) P layer, where 0 < m < 1. The second-type current spreading layer is a GaP layer. The transition layer includes a first transition layer and a second transition layer stacked in sequence along the direction from the second-type confinement layer to the second-type current spreading layer; The first transition layer includes a first sublayer and a second sublayer stacked alternately, wherein the first sublayer is Ga y In (1-y) P layer, the second sublayer is GaAs n P (1-n) layer, along the direction from the second type confinement layer to the second type current spreading layer, the Ga component y of each of the first sub-layers gradually increases, and the In component (1-y) of each of the first sub-layers gradually decreases, <y<1,0<n<1; The second transition layer includes a third sublayer and a fourth sublayer alternately stacked, wherein the third sublayer is GaAs z P (1-z) layer, z≤n, the fourth sublayer is a GaP layer, and along the direction from the second-type confinement layer to the second-type current spreading layer, the As component z of each of the third sublayers gradually decreases to 0, and the P component (1-z) of each of the third sublayers gradually increases to 1.
2. The LED chip according to claim 1, characterized in that: The transition layer further includes a third transition layer located between the second type restriction layer and the first transition layer, wherein the third transition layer is (Al x Ga 1-x ) m In (1-m) P layer, along the direction from the second type confinement layer to the second type current spreading layer, the Al component x of the third transition layer gradually decreases from 1 to 0, and the Ga component (1-x) of the third transition layer gradually increases from 0 to 1; In the first transition layer, the Ga composition of each of the first sub-layers is y≥m.
3. The LED chip according to claim 2, characterized in that: m=0.5, n=0.5; The second type confinement layer is Al 0.5 In 0.5 P layer, the third transition layer is (Al x Ga 1-x ) 0.5 In 0.5 P layer; In the first transition layer, the Ga component y of each of the first sub-layers satisfies: 0.5≤y≤0.8, the In component (1-y) of each of the first sub-layers satisfies: 0.2≤(1-y)≤0.5, and the second sub-layer is GaAs 0.5 P 0.5 layer.
4. The LED chip according to claim 1, characterized in that: The layer of the first transition layer closest to the second transition layer is the first sublayer, and the layer of the second transition layer closest to the first transition layer is the third sublayer.
5. The LED chip according to claim 1, characterized in that: The layer of the first transition layer closest to the second transition layer is the second sub-layer, and the layer of the second transition layer closest to the first transition layer is the fourth sub-layer.
6. The LED chip according to any one of claims 1 to 5, characterized in that: In the first transition layer, the thickness of the first sublayer ranges from 2 nm to 15 nm, including end points; In the first transition layer, the thickness of the second sub-layer ranges from 2 nm to 15 nm, including end points.
7. The LED chip according to any one of claims 1 to 5, characterized in that: In the first transition layer, one layer of the first sublayer and an adjacent layer of the second sublayer form a first periodic structure, and the number of periods of the first periodic structure in the first transition layer is 3-10, including endpoint values.
8. The LED chip according to any one of claims 1 to 5, characterized in that: In the second transition layer, the thickness of the third sublayer ranges from 2 nm to 15 nm, including end points; In the second transition layer, the thickness of the fourth sublayer ranges from 2 nm to 15 nm, including end points.
9. The LED chip according to any one of claims 1 to 5, characterized in that: In the second transition layer, one layer of the third sublayer and an adjacent layer of the fourth sublayer form a second periodic structure, and the number of periods of the second periodic structure in the second transition layer is 3-10, including endpoint values.
10. The LED chip according to any one of claims 1 to 5, characterized in that: The first-type confinement layer is an N-type confinement layer, the second-type confinement layer is a P-type confinement layer, and both the transition layer and the second-type current spreading layer are P-type doped layers.
11. A method for preparing an LED chip, characterized in that: include: A first-type confinement layer, an active layer, and a second-type confinement layer are formed in sequence, wherein the second-type confinement layer is Al m In (1-m) P layer, 0 <m<1; A transition layer is formed on the side of the second-type confinement layer away from the active layer, and the formation process of the transition layer includes: A first transition layer is formed on the side of the second type confinement layer away from the active layer. The first transition layer includes a first sublayer and a second sublayer alternately stacked. The first sublayer is Ga y In (1-y) P layer, the second sublayer is GaAs n P (1-n) layer, along the direction from the second type confinement layer to the second type current spreading layer, the Ga component y of each of the first sub-layers gradually increases, and the In component (1-y) of each of the first sub-layers gradually decreases, <y<1,0<n<1; A second transition layer is formed on the side of the first transition layer away from the second type restriction layer. The second transition layer includes a third sublayer and a fourth sublayer stacked alternately. The third sublayer is GaAs z P (1-z) layer, z≤n, the fourth sublayer is a GaP layer, along the direction from the second type confinement layer to the second type current spreading layer, the As component z of each of the third sublayers gradually decreases to 0, and the P component (1-z) of each of the third sublayers gradually increases to 1; A second-type current spreading layer is formed on a side of the transition layer away from the second-type confinement layer, and the second-type current spreading layer is a GaP layer.
12. The method for preparing an LED chip according to claim 11, characterized in that: Before forming the first transition layer, the process of forming the transition layer further includes: A third transition layer is formed on the side of the second type confinement layer away from the active layer, and the third transition layer is (Al x Ga 1-x ) m In (1-m) P layer, along the direction away from the second type confinement layer, the Al component x of the third transition layer gradually decreases from 1 to 0, and the Ga component (1-x) of the third transition layer gradually increases from 0 to 1; Subsequently, the first transition layer is formed on the side of the third transition layer away from the second type restriction layer, and in the first transition layer, the Ga composition of each of the first sub-layers is y≥m.