Display panel and preparation method thereof

Abstract

The invention provides a display panel and a preparation method thereof. A first light-emitting array chip and a driving array chip are provided; carrying out bonding processing on the first light emitting array chip and the driving array chip to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are in contact and are in inverted connection; carrying out bonding processing on the first bonding structure and a second light-emitting array chip to obtain a second bonding structure; and forming a red pixel unit array on one side of the second light-emitting array chip in the second bonding structure to obtain the display panel. The driving array chip is arranged between the first light-emitting array chip and the second light-emitting array chip, and the driving unit drives the light-emitting units through the interlayer connection technology, so that the process difficulty of electric connection can be reduced, a huge transfer technology is not adopted any more, the manufacturing cost can be reduced, the yield of the display panel can be improved, and the display quality of the display panel can be improved. And full-color display is realized, and the display effect of the display panel is better.

Description

Technical Field

[0001] The present application relates to the field of display panels, and particularly to a display panel and a manufacturing method thereof. Background Art

[0002] With the increasing demand for the performance of display devices, a miniature light-emitting diode (LED) display technology has gradually developed. The integration of RGB pixels and full-color display of miniature LEDs are major difficulties, and the related technologies to solve these difficulties are mainly monolithic integration technology and mass transfer technology.

[0003] Regarding the monolithic integration technology, due to the differences between the red miniature LED epitaxial materials and the blue-green miniature LED epitaxial materials, it is impossible to directly grow and fabricate a full-color miniature LED display panel on the same epitaxial layer. Therefore, the mass transfer technology has become the most direct way to manufacture a full-color miniature LED display panel. However, the mass transfer technology requires accurately transferring millions of micron-scale RGB three-color LED chips from the growth substrate to the target substrate respectively, but there are problems such as high manufacturing cost, low yield, low production efficiency, great difficulty in detection and repair, and poor reliability. Therefore, providing a suitable manufacturing method for the display panel has become a technical problem that urgently needs to be solved currently. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a display panel and a manufacturing method thereof, which can reduce the process difficulty of electrical connection, achieve full-color display, and the display effect of the display panel is better. The specific solutions are as follows: On the one hand, the present application provides a manufacturing method for a display panel, including: Providing a first light-emitting array chip and a driving array chip; the first light-emitting array chip includes a first light-emitting array layer and a first wiring layer stacked in sequence along a first direction, the first light-emitting array layer includes a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer stacked in sequence along the first direction, the driving unit layer includes a plurality of driving units, and one driving unit is used to drive one first light-emitting unit to emit light; Bonding the first light-emitting array chip and the driving array chip to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are in contact with each other, and the two are flip-chip connected; Bond the first bonding structure to the second light-emitting array chip to obtain a second bonding structure; the second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked in sequence along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is used to drive one of the second light-emitting units to emit light; in the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, the second wiring layer is in contact with the driving unit layer, and the second wiring layer and the driving wiring layer are interlayer connected; Form a red pixel unit array on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel; the red pixel unit array includes a plurality of red pixel units.

[0005] In a possible implementation, provide a first light-emitting array chip, including: Provide a first epitaxial wafer; the first epitaxial wafer includes a first substrate and a first light-emitting layer stacked in sequence along the first direction, and the first light-emitting layer includes a first buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a p-type GaN layer stacked in sequence along the first direction; Based on the first array arrangement pattern of the plurality of first light-emitting units, etch the area to be removed of the first epitaxial wafer until the n-type GaN layer to obtain a plurality of light-emitting structures arranged in an array; Form a first p-electrode on the p-type GaN layer of the light-emitting structure, and form a first n-electrode on the n-type GaN layer to obtain a plurality of the first light-emitting units arranged in an array; Deposit a first passivation layer; Form a first wiring layer and a second passivation layer on the first passivation layer in sequence; Form a first through hole in the second passivation layer, and form a first bonding solder layer in the first through hole; the first bonding solder layer is connected to the first wiring layer.

[0006] In a possible implementation, the first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in the first through hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, the surface of the first bonding solder layer is higher than the surface of the second passivation layer, and the first bonding solder layer has a convex structure; the driving array chip includes a fifth passivation layer covering the driving wiring layer, and the fifth passivation layer has a concave hole for exposing a part of the driving wiring layer; Bond the first light-emitting array chip and the driving array chip to obtain a first bonding structure, including: Align the convex structure of the first light-emitting array chip with the concave holes of the driving array chip, and perform thermocompression bonding under the conditions of meeting the preset temperature range and preset pressure range to obtain the first bonding structure.

[0007] In a possible implementation, the driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip, the GaN / AlGaN-based HEMT is an enhancement structure, and the driving array chip is a 1T structure; Provide a driving array chip, including: Provide a second epitaxial wafer; the second epitaxial wafer includes a second substrate and a driving layer stacked in sequence along a second direction, and the driving layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction; the second direction is opposite to the first direction; Based on the second array arrangement pattern of multiple driving units, etch the area to be removed of the second epitaxial wafer until the second buffer layer, and then etch until the AlGaN barrier layer to obtain multiple driving structures arranged in an array; Form a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure, and form a gate electrode on the p-type GaN cap layer to obtain multiple driving units arranged in an array; Deposit a third passivation layer; In the area to be removed of the second epitaxial wafer, etch the third passivation layer and the driving layer to obtain a second through hole; Form a fourth passivation layer and a via metal layer in sequence in the second through hole; Form the driving wiring layer and the fifth passivation layer in sequence.

[0008] In a possible implementation, bonding the first bonding structure with a second light-emitting array chip to obtain a second bonding structure, including: Thin the first bonding structure until the surface of the via metal layer is exposed to obtain a first via metal connection area; Bond the second wiring layer of the second light-emitting array chip with the first via metal connection area to obtain the second bonding structure.

[0009] In a possible implementation, the first light-emitting array chip includes a first bonding solder layer and a second passivation layer. The first bonding solder layer is located in the first through hole of the second passivation layer. The first bonding solder layer is connected to the first wiring layer, and the surface of the first bonding solder layer is flush with the surface of the second passivation layer; The driving array chip includes a fifth passivation layer covering the driving wiring layer and a second bonding solder layer located in a third through hole of the fifth passivation layer; the second bonding solder layer is connected to the driving wiring layer; Bond the first light-emitting array chip and the driving array chip to obtain a first bonding structure, including: Align the first bonding solder layer of the first light-emitting array chip with the second bonding solder layer of the driving array chip, and perform thermocompression bonding under the conditions of meeting a preset temperature range and a preset pressure range to obtain the first bonding structure.

[0010] In a possible implementation, the driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip, the GaN / AlGaN-based HEMT is an enhancement structure, and the driving array chip is a 2T1C structure; the driving unit layer includes a plurality of driving units and a plurality of switching units, and one switching unit is used to control the conduction and cut-off of one driving unit; Provide a driving array chip, including: Provide a second epitaxial wafer; the second epitaxial wafer includes a second substrate and a driving layer stacked in sequence along the second direction, and the driving layer includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction; Based on a third array arrangement pattern of the plurality of driving units and the plurality of switching units, etch the area to be removed of the second epitaxial wafer to the AlGaN barrier layer, and then perform ion implantation on the area to be isolated until the second buffer layer to obtain a plurality of driving structures and a plurality of switching structures arranged in an array; Form source and drain electrodes on the AlGaN barrier layer of the driving structure; form source and drain electrodes on the AlGaN barrier layer of the switching structure; Deposit a third passivation layer; form gate electrodes at the positions of the p-type GaN cap layers of the driving structures on the third passivation layer to obtain a plurality of the driving units arranged in an array; form gate electrodes at the positions of the p-type GaN cap layers of the switching structures on the third passivation layer to obtain a plurality of the switching units arranged in an array; Form the driving wiring layer and the fifth passivation layer on the third passivation layer; the driving wiring layer includes a capacitor; Form a third through hole in the fifth passivation layer, and form a second bonding solder layer in the third through hole; the second bonding solder layer is connected to the driving wiring layer.

[0011] In a possible implementation, bonding the first bonding structure to a second light-emitting array chip to obtain a second bonding structure includes: Etching through holes in the first bonding structure to obtain fourth through holes; Successively forming a fourth passivation layer and a through-hole metal layer in the fourth through holes to obtain a second through-hole metal connection region; Bonding the second wiring layer of the second light-emitting array chip to the second through-hole metal connection region to obtain the second bonding structure.

[0012] In a possible implementation, the display panel further includes a color filter layer, the color filter layer includes a plurality of color filter units, and the color filter units are configured to allow red, blue, or green light to pass through; The color filter layer is located on a side of the red pixel unit array away from the second light-emitting array chip.

[0013] In another aspect, an embodiment of the present application further provides a display panel, including: A first light-emitting array chip, a driving array chip, a second light-emitting array chip, and a red pixel unit array stacked in sequence along a first direction; the first light-emitting array layer includes a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer stacked in sequence along the first direction, the driving unit layer includes a plurality of driving units, and one driving unit is configured to drive one of the first light-emitting units to emit light; the first wiring layer and the driving wiring layer are in contact with each other and are flip-chip connected; The second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked in sequence along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is configured to drive one of the second light-emitting units to emit light; the second wiring layer is in contact with the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer connected; The red pixel unit array includes a plurality of red pixel units.

[0014] An embodiment of the present application provides a display panel and a manufacturing method thereof, providing a first light-emitting array chip and a driving array chip; the first light-emitting array chip includes a first light-emitting array layer and a first wiring layer stacked in sequence along a first direction, the first light-emitting array layer includes a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer stacked in sequence along the first direction, the driving unit layer includes a plurality of driving units, and one driving unit is used to drive one first light-emitting unit to emit light; bonding the first light-emitting array chip and the driving array chip to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are in contact and are flip-chip connected; bonding the first bonding structure with a second light-emitting array chip to obtain a second bonding structure; the second light-emitting array chip includes a second wiring layer and a second light-emitting array layer stacked in sequence along the first direction, the second light-emitting array layer includes a plurality of second light-emitting units, and one driving unit is used to drive one second light-emitting unit to emit light; in the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, the second wiring layer is in contact with the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer connected; forming a red pixel unit array on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel; the red pixel unit array includes a plurality of red pixel units.

[0015] It can be seen that by arranging the driving array chip between the first light-emitting array chip and the second light-emitting array chip, and realizing the driving of the first light-emitting unit by the driving unit through the flip-chip connection technology, and realizing the driving of the second light-emitting unit by the driving unit through the interlayer connection technology. Since the interlayer connection forms a vertical connection between different chips, the process difficulty of electrical connection can be reduced, the mass transfer technology is no longer used, the manufacturing cost can be reduced, the yield of the display panel can be improved, and full-color display is realized, and the display effect of the display panel is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 The flowchart shows a manufacturing method of a display panel provided by an embodiment of the present application; Figure 2 The partial structural diagram shows a first light-emitting array chip provided by an embodiment of the present application; Figure 3AShows a partial structural schematic diagram of a driving array chip provided by an embodiment of the present application; Figure 3B Shows another partial structural schematic diagram of a driving array chip provided by an embodiment of the present application; Figure 4 Shows another partial structural schematic diagram of a driving array chip provided by an embodiment of the present application; Figure 5 Shows another partial structural schematic diagram of a driving array chip provided by an embodiment of the present application; Figure 6 Shows a partial structural schematic diagram of a second light-emitting array chip provided by an embodiment of the present application; Figure 7 Shows a partial structural schematic diagram of a first bonding structure provided by an embodiment of the present application; Figure 8 Shows a partial structural schematic diagram of a preparation of a first via metal connection region provided by an embodiment of the present application; Figure 9 Shows a partial structural schematic diagram of a second bonding structure provided by an embodiment of the present application; Figure 10 Shows another partial structural schematic diagram of a second bonding structure provided by an embodiment of the present application; Figure 11 Shows another partial structural schematic diagram of a second bonding structure provided by an embodiment of the present application; Figure 12 Shows a partial structural schematic diagram of a preparation of a filter layer provided by an embodiment of the present application; Figure 13 Shows a partial structural schematic diagram of a display panel provided by an embodiment of the present application; Figure 14 Shows another partial structural schematic diagram of a preparation of a first light-emitting array chip provided by an embodiment of the present application; Figure 15 Shows another partial structural schematic diagram of a driving array chip provided by an embodiment of the present application; Figure 16 Shows another partial structural schematic diagram of a second light-emitting array chip provided by an embodiment of the present application; Figure 17 Shows another partial structural schematic diagram of a second bonding structure provided by an embodiment of the present application; Figure 18 Shows a partial structural schematic diagram of a preparation of a second via metal connection region provided by an embodiment of the present application; Figure 19Shows a partial structural schematic diagram of another method for preparing a second via metal connection region provided by an embodiment of the present application; Figure 20 Shows a partial structural schematic diagram of another method for preparing a second via metal connection region provided by an embodiment of the present application; Figure 21 Shows a partial structural schematic diagram of another second bonding structure provided by an embodiment of the present application; Figure 22 Shows a partial structural schematic diagram of another second bonding structure provided by an embodiment of the present application; Figure 23 Shows a partial structural schematic diagram of another method for preparing a light filtering layer provided by an embodiment of the present application; Figure 24 Shows a partial structural schematic diagram of a method for preparing a red pixel unit array provided by an embodiment of the present application; Figure 25 Shows a partial structural schematic diagram of another display panel provided by an embodiment of the present application; Figure 26 Shows a circuit schematic diagram of a periodically arranged pixel unit provided by an embodiment of the present application. Detailed implementation manners

[0018] To make the above objects, features, and advantages of the present application more apparent and understandable, the following describes the detailed implementation manners of the present application with reference to the accompanying drawings.

[0019] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0020] Secondly, the present application is described in detail with reference to the schematic diagrams. When detailing the embodiments of the present application, for ease of explanation, the cross-sectional views showing the device structures are enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0021] Next, a brief description is given of the reference numerals used in the present application.

[0022] 101 - First substrate, 102 - First light-emitting layer, 103 - First p electrode, 104 - First n electrode, 105 - First passivation layer, 106 - First wiring layer, 107 - First bonding solder layer, 108 - First light-emitting unit; 201 - Second substrate, 202 - Driving layer, 203 - Driving structure, 204 - Gate, 205 - Source-drain electrode, 206 - Third passivation layer, 207 - Driving wiring layer, 208 - Second bonding solder layer, 209 - Driving unit, 210 - Second via hole, 211 - Switching structure, 212 - Switching unit; 301 - Third substrate, 302 - Second light-emitting layer, 303 - Second p electrode, 304 - Second n electrode, 305 - Seventh passivation layer, 306 - Second wiring layer, 307 - Third bonding solder layer, 308 - Second light-emitting unit; 401 - Red pixel unit; 501 - Fourth passivation layer, 502 - Via metal layer, 503 - Fifth passivation layer, 504 - Eighth passivation layer, 505 - First via metal connection area, 506 - Fourth via hole, 507 - Second via metal connection area; 601 - Glass substrate; 602 - Blue color filter unit, 603 - Green color filter unit, 604 - Red color filter unit, 605 - Passivation layer of color filter layer.

[0023] For ease of understanding, a display panel and a method for manufacturing the same provided by an embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0024] Reference Figure 1 As shown in the figure, it is a schematic flow chart of a method for manufacturing a display panel provided by an embodiment of the present application, and the method may include the following steps.

[0025] S101, provide a first light-emitting array chip and a driving array chip.

[0026] The first light-emitting array chip may include a first light-emitting array layer and a first wiring layer 106 stacked in sequence along a first direction. The first direction may be a direction from bottom to top, that is, the first light-emitting array layer is at the bottom and the first wiring layer 106 is at the top. The first light-emitting array layer may include a plurality of first light-emitting units 108. The first light-emitting unit 108 may be a micro-LED or an ordinary LED. The first light-emitting unit 108 is used for emitting light, and may emit blue light or green light. For ease of description, in the following, it is taken as an example that the first light-emitting unit 108 emits blue light. At this time, the first light-emitting array chip is also a blue LED array chip. The first wiring layer 106 may include a large number of metal traces to connect the first light-emitting unit 108 to the driving unit 209. The manufacturing size of the first light-emitting unit 108 may be greater than 0 μm and less than 500 μm.

[0027] The driving array chip is used to provide a driving effect for the first light-emitting array chip. The driving array chip may include a driving wiring layer 207 and a driving unit layer stacked in sequence along a first direction, that is, the driving unit layer may be located above the driving wiring layer 207. The driving unit layer may include a plurality of driving units 209. One driving unit 209 is used to drive one first light-emitting unit 108 to emit light. The driving unit 209 may be, for example, a thin film transistor (TFT). There are a large number of metal traces in the driving wiring layer 207, and through the metal traces, the driving unit 209 and the first light-emitting unit 108 can be electrically connected.

[0028] S102, bond the first light-emitting array chip and the driving array chip to obtain a first bonding structure.

[0029] Specifically, the first wiring layer 106 in the first light-emitting array chip and the driving wiring layer 207 in the driving array chip can be bonded (Bonding) to obtain a first bonding structure. In the first bonding structure, the first wiring layer 106 and the driving wiring layer 207 are in contact, and the two are in a flip chip (FC) structure. In this way, a vertical connection can be achieved between the first light-emitting array chip and the driving array chip, which can reduce the connection distance and improve the current transmission efficiency.

[0030] S103, bond the first bonding structure and the second light-emitting array chip to obtain a second bonding structure.

[0031] The second light-emitting array chip may include a second wiring layer 306 and a second light-emitting array layer stacked in sequence along the first direction, that is, the second light-emitting array layer may be located above the second wiring layer 306. The second light-emitting array layer may include a plurality of second light-emitting units 308. The second light-emitting units 308 may emit blue light or green light. For the convenience of description, in the following, it is taken as an example that the second light-emitting units 308 emit green light. At this time, the second light-emitting array chip is also a green LED array chip. The second wiring layer 306 may include a large number of metal traces to connect the second light-emitting units 308 and the driving units 209. The preparation size of the second light-emitting units 308 may be greater than 0 μm and less than 500 μm.

[0032] One driving unit 209 is used to drive one second light-emitting unit 308 to emit light. That is to say, in the driving array chip, a part of the driving units 209 are used to drive the first light-emitting units 108, and a part of the driving units 209 are used to drive the second light-emitting units 308.

[0033] Specifically, during the bonding process of the first bonding structure and the second light-emitting array chip, the driving array chip and the second light-emitting array chip can be brought into contact to obtain the second bonding structure. That is, in the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, and the second wiring layer 306 in the second light-emitting array chip is in contact with the driving unit layer in the driving array chip.

[0034] The second wiring layer 306 and the driving wiring layer 207 are interlayer connections (Through-Silicon Via, TSV). That is to say, the second wiring layer 306 can be electrically connected to the driving wiring layer 207 through the vias in the driving unit layer. In short, in the second bonding structure, there are a first light-emitting array layer, a first wiring layer 106, a driving wiring layer 207, a driving unit layer, a second wiring layer 306, and a second light-emitting array layer stacked in sequence along the first direction.

[0035] In this way, on the one hand, the driving unit layer in the driving array chip can supply power to the first light-emitting unit 108 downward through the flip-chip connection between the driving wiring layer 207 and the first wiring layer 106, and on the other hand, it can supply power to the second light-emitting unit 308 upward through the interlayer connection between the driving wiring layer 207 and the second wiring layer 306, realizing the display of blue light and green light.

[0036] S104, form a red pixel unit array on one side of the second light-emitting array chip in the second bonding structure to obtain a display panel.

[0037] By setting two light-emitting array chips, the display panel can emit blue light and green light. To achieve full-color display, a red pixel unit array can be formed on the surface of the second light-emitting array chip.

[0038] The red pixel unit array can include a plurality of red pixel units 401 arranged in an array, and the red pixel units 401 are used to emit red light. The red pixel unit 401 can be a red color conversion film, which can emit red light under the excitation of blue light. The red color conversion film can be quantum dot photoresist or red phosphor, etc. The preparation size of the red pixel unit 401 can be the same as or slightly larger than the size of the first light-emitting unit 108 that provides the blue light source for this unit to ensure that the light-emitting area of the red pixel unit 401 is large enough.

[0039] In this way, by disposing the driving array chip between the first light-emitting array chip and the second light-emitting array chip, and realizing the driving of the first light-emitting unit 108 by the driving unit 209 through flip-chip technology, and realizing the driving of the second light-emitting unit 308 by the driving unit 209 through interlayer connection technology. Since the interlayer connection forms a vertical connection between different chips, the process difficulty of electrical connection can be reduced. Without using the mass transfer technology, the manufacturing cost can be reduced, the yield of the display panel can be improved, and full-color display of red, green, and blue is achieved, and the display effect of the display panel is better.

[0040] In a possible implementation manner, the display panel may further include a color filter layer. The color filter layer may include a plurality of color filter units. The color filter units are used to allow red light, blue light, or green light to pass through. Specifically, when the first light-emitting unit 108 emits blue light and the second light-emitting unit 308 emits green light, the blue color filter unit 602 may be disposed above the first light-emitting unit 108, so that blue light passes through and stray light is filtered. Similarly, the green color filter unit 603 is disposed above the second light-emitting unit 308, so that green light passes through and stray light is filtered. The red color filter unit 604 is disposed above the red pixel unit 401, so that red light passes through and stray light is filtered.

[0041] The color filter layer may be located on a side of the red pixel unit array away from the second light-emitting array chip. The material of the color filter unit includes but is not limited to colored glass, organic light-absorbing materials, perovskite, etc.

[0042] In a possible implementation manner, providing the first light-emitting array chip in S101 may specifically include S201-S206. Refer to Figure 2 As shown, it is a schematic diagram of a first light-emitting array chip provided by an embodiment of the present application.

[0043] S201, provide a first epitaxial wafer.

[0044] The first epitaxial wafer may include a first substrate 101 and a first light-emitting layer 102 stacked in sequence along a first direction. The first substrate 101 may be a sapphire substrate. The sapphire substrate is a transparent substrate, so that double-sided light emission of the display panel can be realized and the display effect can be improved. The first substrate 101 may also be a silicon substrate or the like.

[0045] The first light-emitting layer 102 may include a first buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer, and a p-type GaN layer stacked in sequence along the first direction. Figure 2 Each film layer is not specifically shown therein.

[0046] S202, etch the to-be-removed area of the first epitaxial wafer until the n-type GaN layer based on the first array arrangement pattern of the plurality of first light-emitting units 108 to obtain a plurality of light-emitting structures arranged in an array.

[0047] The first array arrangement pattern can be a preset arrangement pattern of a plurality of first light-emitting units 108, which can be used to determine the formation positions of the respective first light-emitting units 108. According to the first array arrangement pattern, the area to be removed on the first epitaxial wafer can be etched. The area to be removed is the area where the first array arrangement pattern is not located, that is, the position where the first light-emitting units 108 will not be formed. Etching is performed on the area to be removed until reaching the n-type GaN layer, that is, in the area to be removed, the multi-quantum well layer, the electron blocking layer, and the p-type GaN layer are etched away, exposing the surface of the n-type GaN layer, and a plurality of array-arranged light-emitting structures are obtained. Among them, the light-emitting structures are not specifically marked in Figure 2 and there are two light-emitting structures in Figure 2 Among them, the etching method can be inductively coupled plasma etching (ICP) to achieve high precision, high selectivity, high speed, and low damage.

[0048] S203, form a first p-electrode 103 on the p-type GaN layer of the light-emitting structure, and form a first n-electrode 104 on the n-type GaN layer to obtain a plurality of first light-emitting units 108 arranged in an array.

[0049] For each light-emitting structure, a p-electrode can be formed on the exposed surface of the p-type GaN layer, denoted as the first p-electrode 103 (which is the anode). The material of the first p-electrode 103 can be indium tin oxide. An n-electrode is formed on the exposed surface of the n-type GaN layer by etching, denoted as the first n-electrode 104 (which is the cathode). The material of the first n-electrode 104 can be titanium aluminum nickel gold. In this way, a plurality of first light-emitting units 108 can be obtained, and 2 first light-emitting units 108 are shown in Figure 2 Among them.

[0050] S204, deposit a first passivation layer 105.

[0051] Deposit a first passivation layer 105 on the first light-emitting layer 102. The first passivation layer 105 can passivate and fill the first light-emitting layer 102, and cover and isolate the first p-electrode 103 and the first n-electrode 104, thereby protecting the first light-emitting units 108 from being damaged. The deposition process can be plasma enhanced chemical vapor deposition (PECVD) to improve the flatness and deposition rate of the passivation layer. The material of the first passivation layer 105 can be silicon dioxide, and the materials of subsequent other passivation layers can also be silicon dioxide, which will not be elaborated here.

[0052] After the first passivation layer 105 is formed, since the first passivation layer 105 covers the first p-electrode 103 and the first n-electrode 104, the positions of the first p-electrode 103 and the first n-electrode 104 can be etched in the first passivation layer 105 to form a p-electrode hole and an n-electrode hole, so as to realize the extraction of the two electrodes.

[0053] S205, form the first wiring layer 106 and the second passivation layer on the first passivation layer 105 in sequence.

[0054] Form the first wiring layer 106 on the surface of the first passivation layer 105. The first wiring layer 106 includes a large number of metal traces. Part of the metal traces are used to realize the extraction of the electrodes, and their positions are above the positions of the first p-electrode 103 and the first n-electrode 104. Specifically, metal can be deposited inside and around the through holes of the first passivation layer 105 to form metal traces. The first wiring layer 106 can be electrically connected to the first p-electrode 103 and the first n-electrode 104 through the p-electrode hole and the n-electrode hole respectively.

[0055] After the first wiring layer 106 is formed, the second passivation layer needs to be deposited to form a flat surface. The second passivation layer can isolate adjacent metal traces. In addition, the number of layers of the first wiring layer 106 is not limited here. It can be one layer or multiple layers. The number of layers of the second passivation layer is set correspondingly according to the number of layers of the first wiring layer 106. In Figure 2 it, the first wiring layer 106 includes two layers, and the second passivation layer also includes two layers.

[0056] The first wiring layer 106 mainly includes three circuit connection layouts. The first circuit connection layout is used to realize the circuit connection between the first light-emitting unit 108 and the driving unit 209, that is, connect the anode of the first light-emitting unit 108 to the source electrode of the driving unit 209, so that the current in the driving unit 209 can flow through the source electrode to the first light-emitting unit 108 to ensure normal light emission.

[0057] The second circuit connection layout is mainly used to realize the circuit connection between the first light-emitting unit 108 and the second light-emitting unit 308, that is, connect the cathodes of these two types of light-emitting units, so that all the light-emitting units can share a negative electrode and achieve common grounding. In this way, the circuit connection can be simplified without each light-emitting unit being grounded separately.

[0058] The third circuit connection layout is mainly the circuit connection layout of the pads required when the driving array chip is connected to the external circuit. The external circuit is used to realize power supply. For example, connect the source-drain 205 of the transistor to the column line of the external circuit, and connect the gate 204 of the transistor to the row line of the external circuit.

[0059] S206. Form a first through hole in the second passivation layer and form a first bonding solder layer 107 in the first through hole.

[0060] Specifically, in order to lead out the first wiring layer 106, a first through hole can be formed in the second passivation layer. The first through hole is located above the metal trace in the first wiring layer 106, and the first through hole is not specifically marked in Figure 2 the figure. A first bonding solder layer 107 is formed in the first through hole, and the first bonding solder layer 107 is connected to the first wiring layer 106. The material of the first bonding solder layer 107 can be indium metal or other materials. The first bonding solder layer 107 is used to realize subsequent bonding with the driving array chip. The materials of the first bonding solder layer 107 and the subsequent third bonding solder layer 307 include but are not limited to Au series, Sn series, In series, Ag series, Cu series, Al series, Cu series and metal oxides.

[0061] In this way, by setting the specific positions of the first light-emitting units 108 and the first wiring layer 106 in the first light-emitting array chip, the simplicity of the preparation of the first light-emitting array chip is realized, the preparation cost is lower, and the quality of the chip is better.

[0062] In a possible implementation manner, the driving array chip can be a GaN / AlGaN-based high electron mobility transistors (HEMT) active addressing driving chip. This type of driving array chip not only realizes the light emission control of the light-emitting units through transistors, but also one transistor can drive one light-emitting unit to emit light, that is, each light-emitting unit is independently controlled, and thus the addressing of the light-emitting units can be realized, and the display effect of the display panel is more diverse, and the light-emitting units in the specified partial area can be made to emit light. In addition, this type of chip is transparent. By integrating it on the display panel, the display panel can have the advantages of thin thickness, good transparency and high integration, improving the integration of full-color active addressing driving display, and having the advantages of full-color light emission and transparency on the light-emitting surface. Especially in the fields of virtual reality (VR) and augmented reality (AR) displays, it has significant advantages and broad application prospects, and can effectively solve many technical problems such as the difficulty of transferring full-color display chips and the influence of driving chips on full-color micro-LED displays, greatly improving the display effect of the display panel.

[0063] Specifically, the driving array chip can be of a 1T structure or a 2T1C structure. The 1T structure can be understood as one transistor controlling one light-emitting unit. In this structure, the number of transistors required is less, which can simplify the process steps and manufacturing costs. The 2T1C structure can be understood as two transistors and one capacitor controlling one light-emitting unit. In this structure, more precise control of the light-emitting unit can be achieved.

[0064] When the driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip, the GaN / AlGaN-based HEMT is of an enhancement structure and is of a 1T structure, S101 provides the driving array chip, which can specifically include S301 - S307.

[0065] S301 provides a second epitaxial wafer.

[0066] The second epitaxial wafer can include a second substrate 201 and a driving layer 202 stacked in sequence along a second direction. The second direction can be a direction opposite to the first direction. For example, if the first direction is from bottom to top, then the second direction is from top to bottom. The second substrate 201 can be a sapphire substrate, and the driving layer 202 can include a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction. Refer to Figure 3A As shown, from top to bottom, it includes the stacked second substrate 201 and driving layer 202. The layers of the driving layer 202 are not specifically shown. The second buffer layer of the driving layer 202 is in contact with the second substrate 201. The p-type GaN cap layer is used to make the transistor in the off state under normal conditions. The GaN channel layer can form a two-dimensional electron gas, that is, carriers, under the action of the AlGaN barrier layer. The AlN insertion layer is used to make the lattice match between the GaN channel layer and the AlGaN barrier layer.

[0067] S302, based on the second array arrangement pattern of multiple driving units 209, etches the area to be removed on the second epitaxial wafer until the second buffer layer, and then etches until the AlGaN barrier layer to obtain multiple driving structures 203 arranged in an array.

[0068] The second array arrangement pattern can be understood as a preset arrangement pattern of multiple driving units 209, which can be used to determine the formation positions of each driving unit 209. According to the second array arrangement pattern, the area to be removed on the second epitaxial wafer can be etched. Among them, the area to be removed can be the position where the driving unit 209 is not formed. The area to be removed is etched until the second buffer layer is exposed. Then, a part of the p-type GaN cap layer needs to be etched until the AlGaN barrier layer is exposed, and a part of the p-type GaN cap layer is retained, so as to obtain multiple driving structures 203 arranged in an array. The driving structure 203 is not specifically marked in Figure 3A it.

[0069] S303. Form source / drain electrodes 205 on the AlGaN barrier layer of the driving structure 203, and form gate electrodes 204 on the p-type GaN cap layer to obtain multiple driving units 209 arranged in an array.

[0070] Next, for each driving structure 203, form source / drain electrodes 205 on the exposed AlGaN barrier layer. The material of the source / drain electrodes 205 can be metal or the like. For the sake of easy representation, the source / drain electrodes 205 include a source electrode and a drain electrode, and the source electrode and the drain electrode are not distinguished by marks. If the left metal is the drain electrode, then the right metal is the source electrode. The material of the source / drain electrodes 205 can be titanium-aluminum-nickel-gold. In addition, it is also necessary to form gate electrodes 204 on the surface of the exposed p-type GaN cap layer. The gate electrodes 204 can specifically be nickel-gold gate electrodes 204, thereby obtaining a complete transistor structure (i.e., a GaN / AlGaN-based HEMT), that is, obtaining a driving unit 209. Source / drain / gate electrodes are formed on each driving structure 203, thereby obtaining multiple driving units 209. Figure 3A Three driving units 209 are shown in . In addition, the sizes of the driving units 209 and the subsequent switching units 212 can be greater than 0 μm and less than 50 μm.

[0071] S304. Deposit a third passivation layer 206.

[0072] Form a third passivation layer 206 on the multiple driving units 209. The third passivation layer 206 can cover and isolate the GaN / AlGaN-based HEMT to protect each transistor from being damaged. The material of the third passivation layer 206 can be, for example, silicon dioxide or the like.

[0073] S305. Etch the third passivation layer 206 and the driving layer 202 in the area to be removed on the second epitaxial wafer to obtain a second via 210.

[0074] In order to enable the GaN / AlGaN-based HEMT to drive and control the second light-emitting unit 308 located above it, it is necessary to electrically connect the GaN / AlGaN-based HEMT and the second light-emitting unit 308.

[0075] The GaN / AlGaN-based HEMT is not provided in the area to be removed on the second epitaxial wafer. Therefore, the third passivation layer 206 and the driving layer 202 located in this area can be etched to obtain a second via 210. The etching stop layer can be the second buffer layer or other film layers. The etching process can be an ICP process. As shown in Figure 3B , a second via 210 is formed in the third passivation layer 206 and the driving layer 202.

[0076] S306. Form a fourth passivation layer 501 and a via metal layer 502 in the second via 210 in sequence.

[0077] Specifically, a layer of the fourth passivation layer 501 can be deposited in the second via 210. Then, metal such as copper is sputtered in the second via 210, and the metal is electroplated to form the via metal layer 502, and the via metal layer 502 completely fills the second via 210. Refer to Figure 4 As shown, the fourth passivation layer 501 is provided on the sidewall and the bottom wall of the second via 210, and the via metal layer 502 completely fills the inside of the second via 210.

[0078] S307. Form a driving wiring layer 207 and a fifth passivation layer 503 in sequence.

[0079] Next, the driving wiring layer 207 can be formed on the surface of the third passivation layer 206. The driving wiring layer 207 can be, for example, a metal wiring layer. The driving wiring layer 207 mainly includes two circuit connection layouts. The first circuit connection layout is mainly used to realize the electrical connection between the driving unit 209 and the first light-emitting unit 108, that is, to connect the source electrode of the driving unit 209 to the anode of the first light-emitting unit 108. The second circuit connection layout is mainly used to realize the electrical connection between the driving unit 209 and the second light-emitting unit 308, that is, to connect the source electrode of the driving unit 209 to the anode of the second light-emitting unit 308. Specifically, when realizing the electrical connection, openings need to be made at the corresponding positions of the source-drain electrode 205 and the gate electrode 204 so that the metal traces can be connected to them. Refer to Figure 5 As shown, the driving wiring layer 207 and the fifth passivation layer 503 are formed.

[0080] In this way, for the prepared GaN / AlGaN-based HEMT active site selection driving chip, the number of transistors is relatively small, the overall preparation process is relatively simple, and vertical electrical connections in both upward and downward directions can be realized, greatly reducing the process difficulty of electrical connection.

[0081] In a possible implementation manner, the first light-emitting array chip can include a first bonding solder layer 107 and a second passivation layer. The first bonding solder layer 107 is located in the first via of the second passivation layer. The first bonding solder layer 107 is connected to the first wiring layer 106. The surface of the first bonding solder layer 107 is higher than the surface of the second passivation layer, and the first bonding solder layer 107 has a convex structure.

[0082] Specifically, refer to Figure 2As shown, the first bonding solder layer 107 not only fills the first through-hole, but also forms a raised structure. In actual operation, before forming the first bonding solder layer 107, a photoresist layer can be first formed on the surface of the second passivation layer, and the photoresist layer is exposed and developed to form a patterned photoresist layer. The pattern of the photoresist layer is consistent with the pattern of the second passivation layer having the first through-hole. Then, a layer of solder layer material is deposited, and the photoresist layer is removed, thereby forming the first bonding solder layer 107 having a raised structure.

[0083] The driving array chip may include a fifth passivation layer 503 covering the driving wiring layer 207. The fifth passivation layer 503 has a concave hole for exposing a part of the driving wiring layer 207. Specifically, in order to lead out the driving wiring layer 207, a concave hole can be formed at the position where the metal traces of the driving wiring layer 207 are located, that is, the fifth passivation layer 503 is etched to form a concave hole. The etching process can be reactive ion etching (RIE), etc. In this way, the driving wiring layer 207 can be partially exposed at the bottom of the concave hole. The driving array chip having a concave hole is not specifically shown. The difference between the driving array chip having a concave hole and Figure 5 is mainly that a concave hole is formed at the corresponding position in the fifth passivation layer 503 for exposing the driving wiring layer 207.

[0084] S102 performs a bonding process on the first light-emitting array chip and the driving array chip to obtain a first bonding structure, which may specifically include S1021.

[0085] S1021 aligns the raised structure of the first light-emitting array chip with the concave hole of the driving array chip, and performs thermocompression bonding under the conditions of satisfying a preset temperature range and a preset pressure range to obtain a first bonding structure.

[0086] Specifically, when bonding the first light-emitting array chip and the driving array chip, the raised structure of the first bonding solder layer 107 can be aligned with the concave hole in the fifth passivation layer 503, so that the first bonding solder layer 107 can be connected to the driving wiring layer 207.

[0087] Specifically, thermocompression bonding can be performed under the conditions of satisfying a preset temperature range and a preset pressure range to obtain a first bonding structure. Among them, the preset temperature range is the suitable temperature range for bonding, which can be higher than the bonding temperature of the bonding material layer. For example, it can be 250 °C to 400 °C. The preset pressure range is the suitable pressure range for bonding. For example, it can be 10 kPa to 100 MPa. The time of thermocompression bonding can be 5 min to 60 min, so that the first light-emitting array chip and the driving array chip can be completely bonded to obtain a first bonding structure.

[0088] Refer toFigure 7 As shown, a first bonding structure obtained after bonding a first light-emitting array chip and a driving array chip is shown. There may be a tiny gap between the two chips, and underfill can be filled into this gap to improve the firmness of the first bonding structure. Of course, the two chips should be as close as possible to each other.

[0089] In this way, the first bonding structure is obtained through this concave-convex bonding method. During the bonding process, rapid alignment can be achieved according to the positions of the convex structures and the concave holes, greatly improving the bonding efficiency and ensuring the stability of bonding.

[0090] Next, the formation and bonding process of the second light-emitting array chip will be described in detail.

[0091] The formation process of the second light-emitting array chip is basically similar to that of the first light-emitting array chip. The main difference between the two lies in the composition of the multiple quantum well layer. The multiple quantum well layer includes alternately stacked gallium nitride (GaN) and indium gallium nitride (InGaN). The main difference between the first light-emitting array chip and the second light-emitting array chip lies in the different indium contents in the indium gallium nitride.

[0092] Refer to Figure 6 As shown, a schematic diagram of the second light-emitting array chip is shown. During the formation process, a second epitaxial wafer can be provided. The second epitaxial wafer may include a third substrate 301 and a second light-emitting layer 302 stacked in sequence along a second direction. The second light-emitting layer 302 includes a third buffer layer, an n-type GaN layer, a multiple quantum well layer, an electron blocking layer, and a p-type GaN layer stacked in sequence along the second direction. Based on the third array arrangement pattern of multiple second light-emitting units 308, the to-be-removed area of the second epitaxial wafer is etched until the n-type GaN layer to obtain multiple light-emitting structures arranged in an array; a second p electrode 303 is formed on the p-type GaN layer of the light-emitting structure, and a second n electrode 304 is formed on the n-type GaN layer to obtain multiple second light-emitting units 308 arranged in an array; a seventh passivation layer 305 is deposited; a second wiring layer 306 and an eighth passivation layer 504 are sequentially formed on the seventh passivation layer 305; a fifth through hole is formed in the eighth passivation layer 504, and a third bonding solder layer 307 is formed in the fifth through hole; the third bonding solder layer 307 is connected to the second wiring layer 306.

[0093] The second wiring layer 306 mainly includes two circuit connection layouts. The first circuit connection layout is mainly used to implement the circuit connection between the second light-emitting unit 308 and the driving unit 209, and the other circuit connection layout is mainly used to implement the circuit connection between the second light-emitting unit 308 and the first light-emitting unit 108, that is, connecting the negative electrode of the second light-emitting unit 308 to the negative electrode of the first light-emitting unit 108 to achieve common grounding. In actual processes, metal connection lines can be formed in the driving array chip to connect the negative electrodes of the two types of light-emitting units.

[0094] Although Figure 6 each film layer is located below the third substrate 301, in actual process, each film layer is formed in sequence above the third substrate 301. Figure 6 Inverting the prepared second light-emitting array chip for display is to facilitate the subsequent bonding process, that is, Figure 6 directly bonding the shown structure to the first bonding structure.

[0095] In one possible implementation, S103 bonds the first bonding structure and the second light-emitting array chip to obtain a second bonding structure, which may specifically include S1031 - S1032.

[0096] S1031, thinning the first bonding structure until the surface of the via metal layer 502 is exposed to obtain a first via metal connection area 505.

[0097] Specifically, in the first bonding structure, the second substrate 201 of the driving array chip can be removed by wire cutting or laser cutting, and the driving array chip can be thinned by a thinning and polishing process until the surface of the via metal layer 502 is exposed, thus obtaining the first via metal connection area 505. Refer to Figure 8 shown, the first via metal connection area 505 is obtained through the thinning process. The first via metal connection area 505 is the area where the via metal layer 502 is located. Since no light-emitting units are formed at the position where the first via metal connection area 505 is located, that is, this connection area is around the light-emitting units, it can avoid blocking the front light output, and the existence of the connection area can cut off the propagation of light in the gallium nitride layer, preventing weak light emission of adjacent light-emitting units when one light-emitting unit is lit, and preventing light crosstalk.

[0098] S1032, bonding the second wiring layer 306 of the second light-emitting array chip to the first via metal connection area 505 to obtain a second bonding structure.

[0099] Refer to Figure 9As shown, when integrating the second light-emitting array chip, the second wiring layer 306 and the first via metal connection area 505 can be connected through the third bonding solder layer 307 to obtain the second bonding structure.

[0100] During the bonding process, the preset temperature range can be 250 °C to 400 °C, the preset pressure range can be 10 kPa to 100 MPa, and the hot press welding time can be 5 min to 60 min, so that the second light-emitting array chip and the driving array chip are completely bonded.

[0101] Next, the bonding red pixel unit array will be described, mainly including processes such as peeling off the third substrate 301 of the second light-emitting array chip, preparing the red pixel unit array, preparing the filter layer, and integrating the filter layer.

[0102] Refer to Figure 10 As shown, a schematic diagram of peeling off the third substrate 301 of the second light-emitting array chip is shown. Specifically, the third substrate 301 of the bonded second light-emitting array chip can be removed by using laser lift-off technology to obtain Figure 10 the structure shown, and the second light-emitting array layer is exposed, which is beneficial to the top surface light emission of the three-dimensional stacked full-color active addressing driving display panel.

[0103] Then, prepare the red pixel unit array, refer to Figure 11 As shown. After peeling off the third substrate 301, the third buffer layer in the second light-emitting array layer is exposed. A photoresist can be coated on the third buffer layer, and according to the specific position of the first light-emitting unit 108 that provides light sources for the red pixel units 401, the photoresist is patterned exposed and developed to form a patterned photoresist array. Taking the red color conversion film as the red phosphor as an example for illustration, the red phosphor can be spin-coated, and after peeling off the photoresist, the patterned red pixel units 401 are formed, that is, the red pixel unit array is obtained.

[0104] Then prepare the filter layer, taking the filter layer located above the red pixel unit array as an example for illustration. At this time, the red pixel unit array can be formed separately. Refer to Figure 12 As shown, the blue filter unit 602, the green filter unit 603, and the red filter unit 604 can be prepared on the glass substrate 601, which are respectively located above the red, green, and blue micro-LED units; deposit the passivation layer 605 of the filter layer, and thus the filter layer with an array distribution is obtained.

[0105] Fix the filter layer on the red pixel unit array, refer to Figure 13As shown, a display panel with a first light-emitting array chip, a driving array chip, a second light-emitting array chip, a red pixel unit array, and a filter layer stacked in sequence is obtained. The light-emitting surface is the upper surface of the display panel. Since the filter layer is closest to the light-emitting side, the stray light of the emitted light can be minimized to the greatest extent, the emitted light color is more pure, and the displayed color is more vivid.

[0106] Next, a specific description of another implementation manner for forming the display panel is given. Refer to Figures 14 - 25 as shown.

[0107] Refer to Figure 14 as shown, which is a schematic diagram of another method for fabricating the first light-emitting array chip. The main difference from Figure 2 is that the first bonding solder layer 107 does not have a raised structure, that is, the surface of the first bonding solder layer 107 is flush with the surface of the second passivation layer.

[0108] In the process of forming the driving array chip, in a possible implementation manner, the driving array chip is a GaN / AlGaN-based HEMT active addressing driving chip. The GaN / AlGaN-based HEMT is an enhancement-mode structure, and the driving array chip can be a 2T1C structure. The driving unit layer can include a plurality of driving units 209 and a plurality of switching units 212. One switching unit 212 can be used to control the conduction and cutoff of one driving unit 209. The driving unit 209 and the switching unit 212 can be a Metal-Insulator-Semiconductor (MIS) structure, which can reduce the leakage current of the gate 204 and has better performance.

[0109] That is to say, for each light-emitting unit (the first light-emitting unit 108 or the second light-emitting unit 308), the light emission can be controlled by one driving unit 209, and the driving unit 209 is controlled to conduct and cutoff by the switching unit 212.

[0110] Then, S101 provides the driving array chip, which can specifically include S401 - S406.

[0111] S401 provides a second epitaxial wafer.

[0112] The second epitaxial wafer can include a second substrate 201 and a driving layer 202 stacked in sequence along the second direction. The driving layer 202 includes a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, and a p-type GaN cap layer stacked in sequence along the second direction. Refer to Figure 15 as shown.

[0113] S402. Based on the third array arrangement pattern of multiple drive units 209 and multiple switch units 212, etch the area to be removed on the second epitaxial wafer to the AlGaN barrier layer, and then perform ion implantation on the area to be isolated until the second buffer layer, to obtain multiple drive structures 203 and multiple switch structures 211 arranged in an array.

[0114] The third array arrangement pattern can be understood as a preset arrangement pattern of the drive units 209 and the switch units 212, which can reflect the positions of the respective drive units 209 and the positions of the respective switch units 212. The area to be removed on the second epitaxial wafer is the area outside the gates of the drive units 209 and the switch units 212, and this area can be etched until the AlGaN barrier layer is exposed. The area to be isolated on the second epitaxial wafer is the area where no drive units 209 and switch units 212 are provided, and this area can be implanted with fluorine ions until the second buffer layer, so as to obtain multiple drive structures 203 and multiple switch structures 211 arranged in an array.

[0115] S403. Form source and drain electrodes on the AlGaN barrier layer of the drive structure 203; form source and drain electrodes on the AlGaN barrier layer of the switch structure 211.

[0116] Specifically, for each drive structure 203, source-drain electrodes 205 can be formed on the exposed AlGaN barrier layer. The material of the source-drain electrodes 205 can be a metal or the like. For the sake of easy representation, the source-drain electrodes 205 are all represented by the same reference numeral in the figure. If the metal on the left is the drain electrode, then the metal on the right is the source electrode. The material of the source-drain electrodes 205 can be titanium-aluminum-nickel-gold. For each switch structure 211, source-drain electrodes 205 can be formed on the exposed AlGaN barrier layer.

[0117] In the actual process, the source-drain electrodes 205 of the switch units 212, as well as the source-drain electrodes 205 and the gates 204 of the drive units 209, are in the same film layer and can be formed simultaneously.

[0118] S404. Deposit the third passivation layer 206, and form gates 204 at the positions of the p-type GaN cap layers of the drive structures 203 on the third passivation layer 206 to obtain multiple drive units 209 arranged in an array; form gates 204 at the positions of the p-type GaN cap layers of the switch structures 211 on the third passivation layer 206 to obtain multiple switch units 212 arranged in an array.

[0119] Specifically, a third passivation layer 206 is formed on the multiple driving structures 203 and the multiple switching structures 211. The third passivation layer 206 can cover and isolate the driving unit 209 and the source-drain electrodes 205 of the switching structure 211, and can also serve as the insulating layer of the MIS-structured enhanced GaN / AlGaN-based HEMT. The material of the third passivation layer 206 can be, for example, alumina. For each driving structure 203, a gate 204 can be formed on the p-type GaN cap layer covered by the third passivation layer 206. The gate 204 can specifically be a nickel-gold gate 204, thereby obtaining a complete transistor structure that can be used for driving, that is, obtaining a driving unit 209. For each switching structure 211, a gate 204 can be formed on the p-type GaN cap layer covered by the third passivation layer 206, obtaining a switching unit 212.

[0120] In the actual process, the gates 204 of the switching unit 212 and the gates 204 of the driving unit 209 are in the same film layer and can be formed simultaneously. In Figure 15 , three groups of transistor structures are shown. Each group of transistor structures includes a switching unit 212 and a driving unit 209. The transistor on the left is the switching unit 212, and the transistor on the right is the driving unit 209. The source electrode of the switching unit 212 is electrically connected to the gate 204 of the driving unit 209, thereby realizing the control effect on the gate 204 of the driving unit 209. In addition, both the switching unit 212 and the driving unit 209 are MIS-structured enhanced GaN / AlGaN-based HEMTs.

[0121] S405, form a driving wiring layer 207 and a fifth passivation layer 503 on the third passivation layer 206.

[0122] A driving wiring layer 207 can be formed on the third passivation layer 206. The driving wiring layer 207 is used to lead out the source-drain electrodes 205 and the gates 204. Then, a fifth passivation layer 503 is deposited. The number of layers of the fifth passivation layer 503 and the driving wiring layer 207 is not limited. In Figure 15 , there are two layers of the fifth passivation layer 503 and two layers of the driving wiring layer 207.

[0123] The driving wiring layer 207 includes a capacitor, that is, during the formation of the driving wiring layer 207, some metal traces can form a capacitor. In Figure 15 , a planar capacitor is shown. The capacitor can also be a deep trench capacitor.

[0124] S406, form a third through-hole in the fifth passivation layer 503 and form a third bonding solder layer 307 in the third through-hole; the third bonding solder layer 307 is connected to the driving wiring layer 207.

[0125] A third through-hole (not specifically marked in the figure) may be formed in the fifth passivation layer 503. The third through-hole is used to expose a part of the metal trace, and a third bonding solder layer 307 is formed in the third through-hole. The third bonding solder layer 307 can be electrically connected to the driving wiring layer 207.

[0126] In this way, the prepared driving array chip has a switching unit 212 and a driving unit 209. The switching unit 212 can control the magnitude of the gate 204 current of the driving unit 209, and thus can more finely regulate the source-drain current of the driving unit 209, and further can finely regulate the light emission brightness of the light-emitting unit, and the display effect is more controllable.

[0127] In a possible implementation manner, the first light-emitting array chip may include a first bonding solder layer 107 and a second passivation layer. The first bonding solder layer 107 is located in a first through-hole of the second passivation layer. The first bonding solder layer 107 is connected to the first wiring layer 106, and the surface of the first bonding solder layer 107 is flush with the surface of the second passivation layer. The driving array chip may include a fifth passivation layer 503 covering the driving wiring layer 207, and a third bonding solder layer 307 located in a third through-hole of the fifth passivation layer 503; the third bonding solder layer 307 is connected to the driving wiring layer 207.

[0128] Then, S102 performs a bonding process on the first light-emitting array chip and the driving array chip to obtain a first bonding structure. Specifically, in S1022, the first bonding solder layer 107 of the first light-emitting array chip is aligned with the third bonding solder layer 307 of the driving array chip, and thermocompression bonding is performed under the conditions of a preset temperature range and a preset pressure range to obtain a first bonding structure.

[0129] Specifically, referring to Figure 17 As shown, when bonding, the first bonding solder layer 107 can be aligned with the third bonding solder layer 307 of the driving array chip. In this bonding process, since it is bonding between planes, not only can the bonding solder layers be bonded, but the passivation layers can also be bonded. Therefore, the bonding effect of the obtained first bonding structure is better, and the two can be more closely combined, avoiding gaps in the middle, and the bonding strength is higher. The preset temperature range and the preset pressure range can refer to the above description.

[0130] Next, the process of integrating the second light-emitting array chip will be specifically described.

[0131] First, it is the preparation process of the second light-emitting array chip. Referring to Figure 16 As shown, it is a schematic diagram of the prepared second light-emitting array chip, and its preparation process refers to the preparation process of the foregoing second light-emitting array chip. Figure 16 With Figure 6The main difference is that the third bonding solder layer 307 has no protruding structure, realizing plane-to-plane bonding.

[0132] In a possible implementation, S103 bonds the first bonding structure to the second light-emitting array chip to obtain a second bonding structure, which may specifically include S1033 - S1035.

[0133] S1033 performs via etching on the first bonding structure to obtain a fourth via 506.

[0134] Specifically, the second substrate 201 in the first bonding structure can be removed, and the driving unit layer can be thinned. The substrate can be removed by wire cutting or laser cutting, and the driving array chip can be thinned to 2um through a thinning and polishing process. Refer to Figure 18 As shown, it is the thinned first bonding structure.

[0135] Next, refer to Figure 19 As shown, via etching can be performed on the first bonding structure. The etching method can be ICP process, etching until the driving wiring layer 207 is exposed to obtain a fourth via 506.

[0136] S1034 sequentially forms a fourth passivation layer 501 and a via metal layer 502 in the fourth via 506 to obtain a second via metal connection region 507.

[0137] Next, a fourth passivation layer 501 is formed on the surface of the first bonding structure. The fourth passivation layer 501 covers the bottom wall and side wall of the fourth via 506, and the fourth passivation layer 501 on the bottom wall is removed. Refer to Figure 19 As shown. Then metal is formed in the fourth via 506 to obtain a via metal layer 502. The via metal layer 502 completely fills the inside of the fourth via 506. Thus, a second via metal connection region 507 can be obtained. Refer to Figure 20 As shown.

[0138] S1035 bonds the second wiring layer 306 of the second light-emitting array chip to the second via metal connection region 507 to obtain a second bonding structure.

[0139] Refer to Figure 21 As shown, align the second wiring layer 306 of the second light-emitting array chip with the second via metal connection region 507, and perform bonding under certain temperature and pressure conditions to obtain a second bonding structure.

[0140] Next, the formation of the filter layer and the red pixel unit array will be specifically described.

[0141] Refer to Figure 22As shown, the third substrate 301 in the second bonding structure can be removed, which is beneficial for light emission from the top surface of the three-dimensional stacked full-color active addressing driving display panel. Refer to Figure 23 As shown, a filter layer is prepared, and the specific process is the same as that in Figure 12 shown.

[0142] Refer to Figure 24 As shown, a red pixel unit array is formed on the filter layer. Taking the red pixel unit 401 as an example of quantum dot photoresist, a red quantum dot photoresist can be coated on the filter layer. According to the position corresponding to the first light-emitting unit 108 that provides light for the red pixel unit 401, the red quantum dot photoresist is pattern-exposed and developed to form a patterned red quantum dot photoresist array, obtaining a red color conversion film, that is, obtaining a red pixel unit array, and then a passivation layer is formed.

[0143] Refer to Figure 25 As shown, the structure integrating the filter layer and the red pixel unit array is fixed to the second bonding structure, thereby obtaining a display panel.

[0144] In this way, by forming a red pixel unit array on the filter layer, since the filter layer is relatively thin and the distance between the filter layer and the red pixel unit 401 is close enough, the alignment accuracy between the position of the filter layer and the position of the red pixel unit 401 can be higher, enabling the filter layer to better play the role of filtering light, making the red light redder, and the display effect of the display panel more delicate.

[0145] Refer to Figure 26 As shown, it is a circuit schematic diagram of a pixel unit arranged periodically provided by an embodiment of the present application, showing a 6-row and 6-column pixel unit. The pixel unit is an R pixel, a B pixel, and a G pixel. For a single pixel unit, it includes a switching unit (left transistor) and a driving unit (right transistor). The drain of the switching unit is connected to the column line, the gate of the switching unit is connected to the row line, a capacitor connects the drain of the driving unit to the gate 204, the source of the driving unit 209 is connected to the light-emitting diode, and the negative electrode of the light-emitting diode is grounded.

[0146] An embodiment of the present application also provides a display panel, which may include: A first light-emitting array chip, a driving array chip, a second light-emitting array chip, and a red pixel unit array stacked in sequence along a first direction; the first light-emitting array layer includes a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer stacked in sequence along the first direction, the driving unit layer includes a plurality of driving units, and one driving unit is used to drive one of the first light-emitting units to emit light; the first wiring layer and the driving wiring layer are in contact and are flip-chip connected; The second light-emitting array chip includes a second wiring layer and a second light-emitting array layer that are stacked in sequence along the first direction. The second light-emitting array layer includes a plurality of second light-emitting units, and one of the driving units is used to drive one of the second light-emitting units to emit light. The second wiring layer is in contact with the second light-emitting array layer, and the second wiring layer and the driving wiring layer are interlayer-connected; The red pixel unit array includes a plurality of red pixel units.

[0147] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiment of the display panel, since it is basically similar to the embodiment of the manufacturing method, the description is relatively simple, and the relevant parts can refer to the partial description of the embodiment of the manufacturing method.

[0148] The above are only the preferred embodiments of the present application. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the protection of the technical solution of the present application.

Claims

1. A method for preparing a display panel, characterized in that: include: Providing a first light-emitting array chip and a driving array chip; The first light-emitting array chip comprises a first light-emitting array layer and a first wiring layer sequentially stacked along a first direction, wherein the first light-emitting array layer comprises a plurality of first light-emitting units; the driving array chip comprises a driving wiring layer and a driving unit layer sequentially stacked along the first direction, wherein the driving unit layer comprises a plurality of driving units, wherein one driving unit is used to drive one of the first light-emitting units to emit light; The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure; in the first bonding structure, the first wiring layer and the driving wiring layer are in contact and are flip-chip connected; The first bonding structure is bonded to a second light-emitting array chip to obtain a second bonding structure; the second light-emitting array chip comprises a second wiring layer and a second light-emitting array layer sequentially stacked along the first direction, the second light-emitting array layer comprises a plurality of second light-emitting units, and one of the driving units is used to drive one of the second light-emitting units to emit light; In the second bonding structure, the driving array chip is located between the first light-emitting array chip and the second light-emitting array chip, the second wiring layer is in contact with the driving unit layer, and the second wiring layer and the driving wiring layer are interlayer connected; A red pixel unit array is formed on one side of the second light emitting array chip in the second bonding structure to obtain a display panel; the red pixel unit array includes a plurality of red pixel units.

2. The method according to claim 1, characterized in that A first light emitting array chip is provided, comprising: Providing a first epitaxial wafer; the first epitaxial wafer comprises a first substrate and a first light-emitting layer sequentially stacked along the first direction, the first light-emitting layer comprises a first buffer layer, an n-type GaN layer, a multi-quantum well layer, an electron blocking layer and a p-type GaN layer sequentially stacked along the first direction; Based on the first array arrangement pattern of the plurality of the first light-emitting units, etching the to-be-removed region of the first epitaxial wafer until reaching the n-type GaN layer to obtain a plurality of light-emitting structures arranged in an array; Forming a first p-electrode on the p-type GaN layer of the light-emitting structure, and forming a first n-electrode on the n-type GaN layer, to obtain a plurality of the first light-emitting units arranged in an array; depositing a first passivation layer; sequentially forming a first wiring layer and a second passivation layer on the first passivation layer; A first through hole is formed in the second passivation layer, and a first bonding solder layer is formed in the first through hole; the first bonding solder layer is connected to the first wiring layer.

3. The method according to claim 1, characterized in that The first light-emitting array chip comprises a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, the surface of the first bonding solder layer is higher than the surface of the second passivation layer, and the first bonding solder layer has a convex structure; the driving array chip comprises a fifth passivation layer covering the driving wiring layer, the fifth passivation layer has a concave hole, and the concave hole is used to expose a portion of the driving wiring layer; The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure, including: The protruding structure of the first light-emitting array chip is aligned with the concave hole of the driving array chip, and hot pressing welding is performed under the conditions of satisfying a preset temperature range and a preset pressure range to obtain the first bonding structure.

4. The method according to claim 1, characterized in that: The drive array chip is a GaN / AlGaN-based HEMT active site selection drive chip, the GaN / AlGaN-based HEMT is an enhanced structure, and the drive array chip is a 1T structure; Provide drive array chips, including: Providing a second epitaxial wafer; the second epitaxial wafer comprises a second substrate and a driving layer sequentially stacked along a second direction, the driving layer comprises a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a p-type GaN cap layer sequentially stacked along the second direction; the second direction is opposite to the first direction; Based on the second array arrangement pattern of the plurality of driving units, etching the to-be-removed area of ​​the second epitaxial wafer until the second buffer layer, and then etching until the AlGaN barrier layer, to obtain a plurality of driving structures arranged in an array; Forming a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure, and forming a gate electrode on the p-type GaN cap layer, to obtain a plurality of driving units arranged in an array; depositing a third passivation layer; In the to-be-removed area of ​​the second epitaxial wafer, etching the third passivation layer and the driving layer to obtain a second through hole; sequentially forming a fourth passivation layer and a through-hole metal layer in the second through-hole; The driving wiring layer and the fifth passivation layer are formed in sequence.

5. The method according to claim 4, characterized in that The first bonding structure is bonded to the second light emitting array chip to obtain a second bonding structure, comprising: Performing a thinning process on the first bonding structure until the surface of the through-hole metal layer is exposed to obtain a first through-hole metal connection area; The second wiring layer of the second light-emitting array chip is bonded to the first through-hole metal connection area to obtain the second bonding structure.

6. The method according to claim 1, characterized in that The first light-emitting array chip includes a first bonding solder layer and a second passivation layer, the first bonding solder layer is located in a first through hole of the second passivation layer, the first bonding solder layer is connected to the first wiring layer, and a surface of the first bonding solder layer is flush with a surface of the second passivation layer; The drive array chip comprises a fifth passivation layer covering the drive wiring layer, and a second bonding solder layer located in a third through hole of the fifth passivation layer; the second bonding solder layer is connected to the drive wiring layer; The first light-emitting array chip and the driving array chip are bonded to obtain a first bonding structure, including: The first bonding solder layer of the first light-emitting array chip is aligned with the second bonding solder layer of the driving array chip, and hot pressing welding is performed under the conditions of satisfying a preset temperature range and a preset pressure range to obtain the first bonding structure.

7. The method according to claim 1, characterized in that The drive array chip is a GaN / AlGaN-based HEMT active addressing drive chip, the GaN / AlGaN-based HEMT is an enhanced structure, and the drive array chip is a 2T1C structure; the drive unit layer includes a plurality of drive units and a plurality of switch units, and one of the switch units is used to control the conduction and cutoff of one of the drive units; Provide drive array chips, including: Providing a second epitaxial wafer; the second epitaxial wafer comprises a second substrate and a driving layer sequentially stacked along the second direction, the driving layer comprises a second buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer and a p-type GaN cap layer sequentially stacked along the second direction; Based on the third array arrangement pattern of the plurality of the driving units and the plurality of the switch units, etching the area to be removed of the second epitaxial wafer to the AlGaN barrier layer, and then performing ion implantation on the area to be isolated to the second buffer layer, to obtain a plurality of driving structures and a plurality of switch structures arranged in an array; forming a source electrode and a drain electrode on the AlGaN barrier layer of the driving structure; forming a source electrode and a drain electrode on the AlGaN barrier layer of the switch structure; Depositing a third passivation layer; forming a gate on the third passivation layer at the position of the p-type GaN cap layer of the driving structure to obtain a plurality of driving units arranged in an array; forming a gate on the third passivation layer at the position of the p-type GaN cap layer of the switch structure to obtain a plurality of switch units arranged in an array; forming the driving wiring layer and the fifth passivation layer on the third passivation layer; and including a capacitor in the driving wiring layer; A third through hole is formed in the fifth passivation layer, and a second bonding solder layer is formed in the third through hole; the second bonding solder layer is connected to the driving wiring layer.

8. The method according to claim 7, characterized in that The first bonding structure is bonded to the second light emitting array chip to obtain a second bonding structure, comprising: Performing through-hole etching on the first bonding structure to obtain a fourth through-hole; Sequentially forming a fourth passivation layer and a through-hole metal layer in the fourth through-hole to obtain a second through-hole metal connection area; The second wiring layer of the second light-emitting array chip is bonded to the second through-hole metal connection area to obtain the second bonding structure.

9. The method according to claim 1, characterized in that: The display panel further includes a filter layer, the filter layer includes a plurality of filter units, and the filter units are used to allow red light, blue light or green light to pass through; The filter layer is located on a side of the red pixel unit array away from the second light emitting array chip.

10. A display panel, characterized in that: include: A first light emitting array chip, a driving array chip, a second light emitting array chip and a red pixel unit array are sequentially stacked along a first direction; The first light-emitting array layer includes a plurality of first light-emitting units; the driving array chip includes a driving wiring layer and a driving unit layer sequentially stacked along the first direction, the driving unit layer includes a plurality of driving units, and one driving unit is used to drive one of the first light-emitting units to emit light; the first wiring layer and the driving wiring layer are in contact, and the two are flip-chip connected; The second light emitting array chip comprises a second wiring layer and a second light emitting array layer sequentially stacked along the first direction, the second light emitting array layer comprises a plurality of second light emitting units, and one of the driving units is used to drive one of the second light emitting units to emit light; The second wiring layer is in contact with the second light emitting array layer, and the second wiring layer is interlayer connected to the driving wiring layer; The red pixel unit array includes a plurality of red pixel units.

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