Display panel and display device

Abstract

The invention relates to a display panel and a display device, and relates to the technical field of display, the display panel comprises a driving substrate, a chip array and a first electric connection part; the chip array is located between the driving substrate and the first electric connection part, and the driving substrate comprises a second electric connection part; the chip array comprises a plurality of light-emitting elements, each light-emitting element comprises a first electrode and a second electrode, the first electrodes are located on the sides, away from the driving substrate, of the light-emitting elements and electrically connected with the first electric connecting parts, and the second electrodes are located on the sides, facing the driving substrate, of the light-emitting elements and electrically connected with the second electric connecting parts. Therefore, the binding of the light-emitting elements can be realized, the production cost is reduced, and the binding complexity of the light-emitting elements in the high-pixel-density display panel can be greatly reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Currently, the mainstream light-emitting chips of LED display panels are LED flip chips. In recent years, LED vertical chips have also been increasingly applied in display panels. LED vertical chips are usually connected to a driving substrate by means of gold wire bonding. However, gold wires are costly, prone to breakage, and have poor welding reliability. Especially in display panels with high pixel density, the connection between a large number of LED vertical chips and the driving substrate needs to be achieved through one-to-one welding of gold wires, resulting in high process difficulty and complexity.

[0003] How to improve the reliability of LED vertical chip bonding, reduce the process complexity and difficulty, and reduce the production cost has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a display panel and a display device, which are used to improve the reliability of LED vertical chip bonding, reduce the process complexity and difficulty, and reduce the production cost.

[0005] In a first aspect, the present disclosure provides a display panel, including: a driving substrate, a chip array, and a first electrical connection portion; the chip array is located between the driving substrate and the first electrical connection portion, and the driving substrate includes a second electrical connection portion;

[0006] The chip array includes a plurality of light-emitting elements. The light-emitting element includes a first electrode and a second electrode. The first electrode is located on the side of the light-emitting element away from the driving substrate and is electrically connected to the first electrical connection portion. The second electrode is located on the side of the light-emitting element facing the driving substrate and is electrically connected to the second electrical connection portion.

[0007] In a second aspect, the present disclosure provides a display device, including the display panel as described in the first aspect.

[0008] The technical solutions provided by the embodiments of the present disclosure have the following advantages compared with the prior art: by providing a first electrical connection portion on the side of the chip array facing away from the driving substrate, and connecting the first electrical connection portion to the first electrode of the light-emitting element, the binding to multiple light-emitting elements in the chip array can be achieved at one time through the first electrical connection portion, reducing the process complexity and difficulty. At the same time, the use of gold wires for bonding in the prior art can be reduced, the production cost can be reduced, and the production efficiency can be improved; the width of the first connection portion is much larger than the wire width of the gold wire, which can make the binding of the light-emitting elements more secure and improve the production yield. Description of the Drawings

[0009] The accompanying drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with the present disclosure, and are used together with the description to explain the principles of the present disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 The following shows a schematic connection diagram of an LED flip-chip and a driving substrate in the prior art provided by the present disclosure;

[0012] Figure 2 The following shows a schematic connection diagram of an LED vertical chip and a driving substrate in the prior art provided by the present disclosure;

[0013] Figure 3 The following shows a top view of a display panel provided by an embodiment of the present disclosure;

[0014] Figure 4 The following shows Figure 3 a cross-sectional view along A-A';

[0015] Figure 5 The following shows a schematic shape diagram of a first electrical connection part provided by an embodiment of the present disclosure;

[0016] Figure 6 The following shows a top view of a driving layer provided by an embodiment of the present disclosure;

[0017] Figure 7 The following shows a schematic diagram of the film layer structure of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 8 The following shows a schematic connection diagram of a mutual capacitance touch electrode unit provided by an embodiment of the present disclosure;

[0019] Figure 9 The following shows another schematic diagram of the film layer structure of a display panel provided by an embodiment of the present disclosure;

[0020] Figure 10 The following shows yet another schematic diagram of the film layer structure of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 11 The following shows a schematic connection diagram of a self-capacitance touch structure in a display panel provided by an embodiment of the present disclosure;

[0022] Figure 12The figure shows a schematic diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0023] In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0024] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0025] Figure 1 The figure shows a schematic diagram of the connection between an LED flip-chip and a driving substrate in the prior art provided by the present disclosure. Please refer to Figure 1 , the display panel 100' includes a substrate 10', a driving substrate 20', and a light-emitting element 30'. Among them, the light-emitting element 30' is located on the side of the driving substrate 20' away from the substrate 10'. The light-emitting element 30' is an LED flip-chip. The light-emitting element 30' includes a light-emitting layer 31', a first electrode 32', and a second electrode 33'. The first electrode 32' and the second electrode 33' are located on the same side of the light-emitting layer 31'. The first electrode 32' is connected to the driving substrate 20' through a first electrical connection portion 40'. The second electrode 33' is connected to the driving substrate 20' through a second electrical connection portion 50'. As can be seen from the figure, the first electrode 32' needs to pass through the light-emitting layer 31' to reach the same side as the second electrode 33'. Due to the sacrifice of the active layer, there is a current crowding phenomenon, which affects the display effect.

[0026] Figure 2 The figure shows a schematic diagram of the connection between an LED vertical chip and a driving substrate in the prior art provided by the present disclosure. Please refer to Figure 2, the display panel 100” includes a substrate 10”, a driving substrate 20”, and a light-emitting element 30”. Among them, the light-emitting element 30” is located on the side of the driving substrate 20” away from the substrate 10”. The light-emitting element 30” is an LED vertical chip, and the light-emitting element 30” includes a light-emitting layer 31”, a first electrode 32”, and a second electrode 33”. The first electrode 32” and the second electrode 33” are located on different sides of the light-emitting layer 31”. The first electrode 32” is connected to the driving substrate 20” through a metal wire 00” to the driving substrate 20”. The second electrode 33” is connected to the driving substrate 20” through a second electrical connection part 50”. As can be seen from the figure, the LED vertical chip in the prior art is limited by the position structure of the electrodes. Usually, the bonding of the LED vertical chip needs to be completed by welding gold wires. The gold wire welding needs to be carried out separately for each LED vertical chip. As the pixel density of the display panel increases and the size of the light-emitting element becomes smaller, the process complexity and difficulty of gold wire welding also become greater. In addition, the cost of gold wire welding is relatively high, and the reliability is poor. It is easy to break and separate, which is likely to reduce the production yield or cause display failures.

[0027] In view of the above problems, a display panel 100 provided by the present disclosure can improve the bonding reliability of the LED vertical chip and reduce the production cost. Figure 3 The following is a top view of a display panel provided by an embodiment of the present disclosure. Figure 4 As shown in Figure 3 the cross-sectional view along A-A’, please refer to Figure 3 and Figure 4 , the present disclosure provides a display panel 100, including: a driving substrate 20, a chip array 30, and a first electrical connection part 40; the chip array 30 is located in the display area AA of the display panel 100, and the chip array 30 is located between the driving substrate 20 and the first electrical connection part 40. The driving substrate 20 includes a second electrical connection part 50; the chip array 30 includes a plurality of light-emitting elements 34. The light-emitting element 34 includes a light-emitting layer 31, a first electrode 32, and a second electrode 33. The first electrode 32 is located on the side of the light-emitting layer 31 away from the driving substrate 20 and is electrically connected to the first electrical connection part 40. The second electrode 33 is located on the side of the light-emitting layer 31 facing the driving substrate 20 and is electrically connected to the second electrical connection part 50. It should be noted that to show the connection of the light-emitting element 34, Figure 3 the number of the light-emitting elements 34 in the chip array 30 is only for illustration and does not represent the actual number of the light-emitting elements 34 in the chip array 30. The present disclosure does not make specific limitations on this.

[0028] Specifically, the driving substrate 20 is used to drive the light-emitting elements 34 in the chip array 30 to emit light. In an optional embodiment provided by the present disclosure, the light-emitting element 34 may be an LED vertical chip, and the first electrode 32 and the second electrode 33 are respectively the cathode and anode of the LED vertical chip, or the first electrode 32 and the second electrode 33 are respectively the anode and cathode of the LED vertical chip. The present disclosure does not make specific limitations on this. The light-emitting element 34 includes a first electrode 32, a second electrode 33, and a light-emitting layer 31. In the direction perpendicular to the plane where the driving substrate 20 is located, the first electrode 32 and the second electrode 33 are respectively located on both sides of the light-emitting layer 31. The first electrode 32 of the LED vertical chip is connected to the first electrical connection portion 40, and the driving substrate 20 includes a second electrical connection portion 50. The second electrode 33 of the LED vertical chip is connected to the second electrical connection portion 50 on the driving substrate 20.

[0029] In this way, the bonding of the vertical LED chip can be realized by setting the first electrical connection portion 40 in the display panel 100 and the second electrical connection portion 50 in the driving substrate 20. Compared with the bonding method in the prior art of welding the electrodes of the LED vertical chip to the driving substrate 20 with a gold wire, directly setting the first electrical connection portion 40 in the display panel 100 to realize the bonding of the vertical LED chip can reduce the use of gold wire and lower the production cost. Secondly, the first electrical connection portion 40 is located on the side of the chip array 30 away from the driving substrate 20. In the actual process production, existing manufacturing processes such as coating, exposure, development, and etching can be used to manufacture the first electrical connection portion 40 without adding additional processes. In addition, as the pixel density of the display panel 100 increases, the size of the LED becomes smaller, and the process complexity and difficulty of gold wire welding also become greater. Compared with the one-to-one gold wire welding of the LED vertical chip and the driving substrate 20 in the prior art, the first electrical connection portion 40 in the present disclosure can be integrally formed and bonded to multiple vertical LED chips at the same time, reducing the bonding difficulty and complexity of the vertical LED chip.

[0030] Figure 5 The following shows a schematic diagram of the shape of a first electrical connection portion provided by an embodiment of the present disclosure. Please refer to Figures 3 to 5 , the first electrical connection portion 40 is in a grid shape.

[0031] Specifically, in an optional implementation provided by the present disclosure, the grid-shaped first electrical connection portion 40 is located on the side of the chip array 30 away from the driving substrate 20 and is parallel to the plane where the driving substrate 20 is located. Optionally, the first electrical connection portion 40 includes a plurality of branches 41, and at least some of the branches 41 are respectively connected to a first electrode 32 of a light-emitting element 34 in a one-to-one correspondence; in a direction parallel to the plane where the driving substrate 20 is located, each branch 41 is connected to an adjacent branch 41 to form a whole-surface grid-like structure, which is beneficial to the integral formation of the first electrical connection portion 40 in the manufacturing process; since the first electrical connection portion 40 needs to be connected to the first electrode 32 of the light-emitting element 34, the grid-shaped first electrical connection portion 40 with a whole-surface design can realize the connection with the first electrodes 32 of a plurality of light-emitting elements 34 on the driving substrate 20 at one time. Compared with the prior art in which a plurality of vertical LED chips need to be individually bonded to the driving substrate 20 through gold wires, the first electrical connection portion 40 provided by the present disclosure can reduce the manufacturing process and improve the production line efficiency.

[0032] The present disclosure does not specifically limit the shape of the branch 41, as long as at least some of the branches 41 overlap at least partially with the projection of the corresponding first electrode 32 on the driving substrate 20 in a direction perpendicular to the plane where the driving substrate 20 is located.

[0033] Optionally, the first electrical connection portion 40 can be made of a transparent conductive material or an opaque conductive material. The transparent conductive material includes indium tin oxide, indium zinc oxide, etc., and the present disclosure does not specifically limit the composition of the transparent conductive material; the opaque conductive material includes aluminum, etc., and the present disclosure does not specifically limit the composition of the opaque conductive material. It should be noted that when the first electrical connection portion 40 is made of an opaque conductive material, for example, made of aluminum, the grid-shaped first electrical connection portion 40 includes a hollow 42, and in a direction perpendicular to the plane where the driving substrate 20 is located, the branches 41 of the first electrical connection portion 40 need to avoid overlapping with the light-emitting element 34 so as not to block the light emission of the light-emitting element 34.

[0034] In this way, by setting the first electrical connection portion 40 in a grid shape, the integral formation of the first electrical connection portion 40 on the whole surface can be realized in the actual manufacturing process, and then the binding of the first electrical connection portion 40 to a plurality of light-emitting elements 34 can be realized at one time, which is beneficial to reducing the process steps. Especially in the display panel 100 with a high pixel density, the process complexity can be greatly reduced and the production efficiency can be improved.

[0035] It should be noted that Figure 4In the first electrical connection portion 40, the shapes of the branches 41 and the hollow portions 42 are only schematic. The branches 41 can be regular or irregular long strip shapes, arc shapes, square shapes, etc. The shapes of different branches 41 can be the same or different, or gradually increase, or change irregularly. The present disclosure does not specifically limit this, and it shall be subject to actual needs. The hollow portions 42 can be regular or irregular or gradually changing square shapes, rectangular shapes, diamond shapes, oval shapes, circular shapes, etc. The present disclosure does not specifically limit this.

[0036] Figure 6 The following is a top view of a driving layer provided by an embodiment of the present disclosure. Please refer to Figures 3 to 6 , the display panel 100 includes a touch control layer 60 located on the side of the chip array 30 away from the driving substrate 20, and the first electrical connection portion 40 is located in the touch control layer 60. In an optional implementation manner provided by the present disclosure, please combine Figure 3 . The first electrical connection portion 40 is disposed in the touch control layer 60. Without additionally providing a film layer, the touch control layer 60 can not only implement the touch control function but also connect to the first electrode 32 of the light-emitting element 34, without additionally increasing the film layer of the display panel 100, which is beneficial to the thinning of the display panel 100.

[0037] Figure 7 The following is a schematic diagram of a film layer structure of a display panel provided by an embodiment of the present disclosure. Please combine Figures 3 to 7 . The touch control layer 60 includes a first electrode layer 61 and a second electrode layer 62. The first electrode layer 61 is located on the side of the second electrode layer 62 facing the chip array 30, and the first electrical connection portion 40 is located in the first electrode layer 61.

[0038] Specifically, in an alternative embodiment provided by the present disclosure, the touch layer 60 includes a first electrode layer 61 and a second electrode layer 62. Among them, in the direction perpendicular to the plane where the driving substrate 20 is located, the first electrode layer 61 is located between the second electrode layer 62 and the chip array 30, and the first electrical connection portion 40 is located in the first electrode layer 61; that is, when the first electrical connection portion 40 is located in the touch layer 60, the first electrical connection portion 40 is specifically located in the first electrode layer 61 of the touch layer 60. Setting the first electrical connection portion 40 in the first electrode layer 61 of the touch layer 60, and the first electrode layer 61 is located on the side of the second electrode layer 62 facing the chip array 30, which is beneficial to the connection between the first electrical connection portion 40 in the first electrode layer 61 and the first electrode 32 of the light-emitting element 34 in the chip array 30. In this way, by setting the first electrical connection portion 40 in the first electrode layer 61 of the touch layer 60 closer to the chip array 30, it is beneficial to the connection between the first electrical connection portion 40 and the first electrode 32 in the light-emitting element 34, reducing film layer penetration and simplifying the process steps; in addition, the first electrical connection portion 40 can be formed simultaneously when the first electrode layer 61 is fabricated, without introducing a separate fabrication process for the first electrical connection portion 40, which is beneficial to simplifying the production process and improving production efficiency.

[0039] Figure 8 The following figure shows a connection schematic diagram of a mutual capacitance touch electrode unit provided by an embodiment of the present disclosure. Please refer to Figures 3 to 8 On the second electrode layer 62, touch electrode units 620 are provided, and on the first electrode layer 61, electrode connection portions 63 for connecting the touch electrode units 620 are provided. The electrode connection portions 63 are on the same layer as the first electrical connection portion 40 and are insulated.

[0040] Specifically, in an alternative embodiment provided by the present disclosure, the touch layer 60 includes a first electrode layer 61 and a second electrode layer 62. The first electrode layer 61 is located on the side of the second electrode layer 62 facing the chip array 30, and the first electrical connection portion 40 is located in the first electrode layer 61. The second electrode layer 62 includes touch electrode units 620 arranged in an array. Please refer to Figure 8, the touch electrode unit 620 includes a first touch electrode 621 and a second touch electrode 622. The first touch electrode 621 and the second touch electrode 622 each include a plurality of electrode blocks. The electrode blocks in the first touch electrode 621 are connected through the electrode connection part 63 of the first electrode layer 61, and the electrode blocks in the second touch electrode 622 are connected through the same-layer wire 623. The touch electrode unit 620 is connected to the touch chip 65 through the touch lead 64. That is, the electrode connection part 63 and the first electrical connection part 40 are both located in the first electrode layer 61, and are insulated from each other between the electrode connection part 63 and the first electrical connection part 40. That is, the touch layer 60 has a touch function. For example, the electrode connection part 63 located in the first electrode layer 61 is used to connect the electrode blocks in the first touch electrode 621 located in the second electrode layer 62. When the user touches the display panel 100, the sensing capacitance between the first touch electrode 621 and the second touch electrode 622 in the touch layer 60 changes, and the touch position and signal can be recognized; the first electrode layer 61 in the touch layer 60 also has the function of being a common cathode connected to the chip array 30. For example, the first electrical connection part 40 located in the first electrode layer 61 is used to connect the first electrode 32 of the light-emitting element 34 and is used as the entire surface common cathode of the chip array 30. Thus, by providing the mutually insulated first electrical connection part 40 and the electrode connection part 63 in the first electrode layer 61, the touch function of the touch layer 60 and the function of the common cathode connected to the chip array 30 can be realized simultaneously without additionally providing other film layers.

[0041] Please continue to refer to Figure 5 and Figure 6 , the first electrical connection part 40 includes a hollow 42, and the electrode connection part 63 is located in the hollow 42; along the direction parallel to the plane where the driving substrate 20 is located, the minimum distance R between the electrode connection part 63 and the first electrical connection part 40 is greater than 3 μm, and the minimum width L1 of the first electrical connection part 40 is greater than the maximum width L2 of the electrode connection part 63.

[0042] Specifically, in an alternative embodiment provided by the present disclosure, the first electrical connection portion 40 includes a hollow 42. As described above, when the first electrical connection portion 40 is a mesh structure, the hollow 42 refers to the voids of the mesh structure formed by the connection of multiple branches 41. The first electrical connection portion 40 is located in the first electrode layer 61, and the electrode connection portion 63 is located in the first electrode layer 61 and in the hollow 42 of the mesh-structured first electrical connection portion 40. The first direction D1 is a direction parallel to the plane where the driving substrate 20 is located, and the second direction D2 is a direction parallel to the plane where the driving substrate 20 is located. The first direction D1 intersects with the second direction D2. Optionally, the first direction D1 is the direction in which the hollow 42 extends in a certain direction, and the second direction D2 is the direction in which the hollow 42 extends in another direction, where the first direction D1 is different from the second direction D2. It should be noted that the "intersection" of the first direction D1 and the second direction D2 includes various situations such as perpendicular or non-perpendicular, and the present disclosure does not make specific limitations on this.

[0043] Along the first direction D1, in the same hollow 42, the minimum first spacing R1 between the electrode connection portion 63 and the first electrical connection portion 40 is greater than 3 μm; along the second direction D2, in the same hollow 42, the minimum second spacing R2 between the electrode connection portion 63 and the connection portion of the first electrode 32 is greater than 3 μm. That is to say, the electrode connection portion 63 of the first electrode layer 61 and the first electrical connection portion 40 are on the same layer and insulated, and regardless of the direction parallel to the plane where the driving substrate 20 is located, the minimum spacing R between the electrode connection portion 63 and the first electrical connection portion 40 in the same hollow 42 is greater than 3 μm. Thus, in the process manufacturing, when etching the electrode connection portion 63 and the first electrical connection portion 40 located on the same layer, the minimum spacing R between them is greater than 3 μm, which is beneficial to ensuring that the electrode connection portion 63 and the first electrical connection portion 40 located on the same layer are separated into two independent parts after etching, reducing process losses and improving the product yield.

[0044] Please continue to refer to Figure 6, along the first direction D1, the first width L21 of the electrode connection portion 63 located in the first electrode layer 61 is much smaller than the first width L11 of a certain branch 41 in the first electrical connection portion 40. Along the second direction D2, the second width L22 of the electrode connection portion 63 located in the first electrode layer 61 is much smaller than the second width L12 of the first electrical connection portion 40. In the actual manufacturing process, optionally, the line width of the electrode connection portion 63 is usually less than 10 μm. The trace width of the first electrical connection portion 40 (i.e., the width of the branch 41 mentioned above) is related to the size of the display panel 100 and is usually between 50 - 100 μm. For example, it can be 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm... Here, they are not listed one by one. Just know that the minimum width L1 of the first electrical connection portion 40 is greater than the maximum width L2 of the electrode connection portion 63. In this way, the electrode connection portion 63 and the first electrical connection portion 40 can be arranged on the same layer, and the electrode connection portion 63 is arranged in the hollow 42 of the first electrical connection portion 40, which can save layout space and is beneficial to the miniaturization of the display panel 100. In addition, compared with the prior art of bonding vertical LED chips with gold wires, connecting the light-emitting element 34 through the first electrical connection portion 40 can not only reduce the use of gold wires and lower the production cost, but also, since the width L1 of the first electrical connection portion 40 is much larger than the width of the gold wire, the contact area of the first electrical connection portion 40 connected to the light-emitting element 34 is much larger than the contact area of the gold wire connected to the light-emitting element 34. In this way, the reliability of the bonding of the light-emitting element 34 can be greatly improved, which is beneficial to improving the product yield.

[0045] Figure 9 The following is a schematic diagram of the film layer structure of another display panel provided by an embodiment of the present disclosure. Please refer to Figure 9 , the display panel 100 includes a touch layer 60 on the side of the chip array 30 away from the driving substrate 20, and the first electrical connection portion 40 is located between the touch layer 60 and the chip array 30.

[0046] Specifically, in an optional implementation manner provided by the present disclosure, the display panel 100 includes a driving substrate 20, a chip array 30, a first electrical connection portion 40, and a touch layer 60. Along the direction perpendicular to the plane where the driving substrate 20 is located, the driving substrate 20 is on the side of the chip array 30 away from the first electrical connection portion 40, and the touch layer 60 is on the side of the first electrical connection portion 40 away from the chip array 30. That is, in this embodiment, the first electrical connection portion 40 and the touch layer 60 are arranged in layers. The first electrical connection portion 40 is used to connect to the first electrode 32 of the light-emitting element 34 in the chip array 30, and the second electrical connection portion 50 in the driving substrate 20 is used to connect to the second electrode 33 of the light-emitting element 34 in the chip array 30. A eutectic layer is further included between the second electrode 33 and the second electrical connection portion 50 to realize the bonding of the light-emitting element 34. Optionally, please combine Figure 5, the first electrical connection portion 40 is designed as a full-surface grid-like structure, and the first electrical connection portion 40 is independent of the touch layer 60. That is, the first electrical connection portion 40 only has the function of being the common cathode of the light-emitting elements 34 in the chip array 30, and the touch layer 60 only has the touch function. The two do not interfere with each other, which can reduce the influence of the existence of the full-surface common cathode on the touch characteristics. The influence of the existence of the full-surface common cathode on the touch characteristics is specifically reflected as follows. Please refer to Figure 6 , when the first electrical connection portion 40 and the electrode connection portion 63 are arranged on the same layer, the existence of the full-surface first electrical connection portion 40 will increase the parasitic capacitance between the cathode metal and the electrode connection portion 63 (touch metal), which may affect the sensitivity and accuracy of touch. Therefore, by independently arranging the first electrical connection portion 40 in a film layer outside the touch layer 60, the parasitic capacitance between the first electrical connection portion 40 (full-surface cathode metal) and the touch metal can be reduced to reduce the influence on the touch function. At the same time, due to the functional separation of the touch layer 60 and the first electrical connection portion 40, the touch layer 60 can be freely designed in forms such as mutual capacitance or self-capacitance, without being restricted to the mutual capacitance form due to the same-layer limitation of the first electrical connection portion 40 and the touch layer 60. In this way, by independently arranging the first electrical connection portion 40 and the touch layer 60, the influence of the existence of the full-surface common cathode on the touch characteristics can be reduced, and the diversity of touch forms can be increased.

[0047] Figure 10 The following shows a schematic diagram of the film layer structure of another display panel provided by an embodiment of the present disclosure. Please refer to Figure 7 , Figure 9 and Figure 10 , the display panel 100 includes a packaging layer 70. The packaging layer 70 is used to package the light-emitting elements 34. The side of the packaging layer 70 facing away from the driving substrate 20 has an opening 71. The opening 71 exposes the first electrode 32. At least a part of the first electrical connection portion 40 is located in the opening 71.

[0048] Specifically, in an alternative embodiment provided by the present disclosure, the encapsulation layer 70 is used to encapsulate the light-emitting elements 34 in the chip array 30 to reduce the position offset of the light-emitting elements 34 during the manufacturing process. One side surface of the encapsulation layer 70 facing the first electrical connection portion 40 includes an opening 71. The opening 71 exposes the first electrode 32 of the light-emitting element 34. At least a part of the side of the first electrical connection portion 40 facing the chip array 30 is located in the opening 71 and is connected to the first electrode 32 of the light-emitting element 34 to achieve the bonding of the first electrical connection portion 40 and the light-emitting element 34. Optionally, the openings 71 corresponding to different light-emitting elements 34 can be formed at one time in the same process. In the manufacturing process, the first electrical connection portion 40 formed on the encapsulation layer 70 can achieve batch bonding with the entire chip array 30. In this way, by using the encapsulation layer 70 to encapsulate the light-emitting elements 34 and providing the opening 71 in the encapsulation layer 70, it is convenient for the first electrical connection portion 40 to be connected to the first electrode 32 in the light-emitting element 34, and the first electrical connection portion 40 can achieve batch bonding with multiple light-emitting elements 34 in the chip array 30 through multiple different openings 71, simplifying the process and improving production efficiency.

[0049] Please continue to refer to Figure 7 、 Figure 9 and Figure 10 , the driving substrate 20 further includes a power signal line 82, and the second electrical connection portion 50 is disposed on the same layer as the power signal line 82; the driving substrate 20 includes a substrate 10 and a transistor 21, and the power signal line 82 and the second electrical connection portion 50 are located on the side of the transistor 21 away from the substrate 10.

[0050] Specifically, in an alternative embodiment provided by the present disclosure, the display panel 100 includes a driving substrate 20, a chip array 30, and a first electrical connection portion 40. Along the direction perpendicular to the plane where the driving substrate 20 is located, the driving substrate 20 is located on the side of the chip array 30 away from the first electrical connection portion 40. The first electrical connection portion 40 is used to connect to the first electrode 32 of the light-emitting element 34 in the chip array 30; the driving substrate 20 includes a second electrical connection portion 50 and a power signal line 82. The second electrical connection portion 50 is used to connect to the second electrode 33 of the light-emitting element 34 in the chip array 30, and the second electrical connection portion 50 is disposed on the same layer as the power signal line 82, which can effectively utilize the film layer space and realize the dual functions of being the anode of the chip array 30 and the power signal line only by forming one film layer. Optionally, please refer to Figure 7 and Figure 9, the second electrical connection portion 50 and the power signal line 82 are located in the M4 metal layer of the driving member 20. The driving substrate 20 further includes a substrate 10 and a transistor 21. The substrate 10 is located on the side of the transistor 21 away from the power signal line and the second electrical connection portion 50. Optionally, the substrate 10 can be made of organic or inorganic materials, or rigid or flexible materials. The present disclosure does not specifically limit this and shall be subject to actual needs. The transistor 21 is used to control the light emission of the light-emitting element 34. It can be understood that the transistor 2 includes an active layer, a gate, a source, and a drain. Please refer to Figure 7 , Figure 9 and Figure 10 . The active layer of the transistor 21 is located in the poly layer, the gate is located in the M1 metal layer, and the source and drain are located in the M2 metal layer. The M2 metal layer is located on the side of the M1 metal layer away from the substrate 10. Among them, the gate line formed in the M1 metal layer is used to control the conduction of the transistor 21, and the data line formed in the M2 metal layer is used to transmit data signals to the light-emitting element 34. Optionally, the driving substrate 20 further includes an MC metal layer, and the MC metal layer can be used as part of a storage capacitor to help stabilize the circuit state, achieve more precise pixel control, and more uniform picture display.

[0051] In this way, by designing the second electrical connection portion 50 and the power signal line 82 on the same layer, the film layer space can be effectively utilized, the number of film layers of the display panel 100 can be reduced, which is beneficial to the thinning of the display panel 100.

[0052] It should be noted that the metal of the touch layer 60, the first electrical connection portion 40 in the display panel 100, and the M2 metal layer, M3 metal layer, and M4 metal layer in the driving substrate 20 can be used as bonding pads in the bonding area. The interconnection of the metal layers in the bonding area can be used for padding, facilitating the connection of the bonding pads to the driving chip or the flexible circuit board, and reducing the impedance. At the same time, the stacking of multiple layers of metal can improve the reliability of the bonding pads. Even if the upper metal layer is damaged, the lower metal layer can still be used.

[0053] Please continue to refer to Figure 7 and Figure 9 . The driving substrate 20 includes an auxiliary signal line 92. The auxiliary signal line 92 is located between the transistor 21 and the power signal line 82, and the auxiliary signal line 92 is electrically connected to the power signal line 82.

[0054] Specifically, in an alternative embodiment provided by the present disclosure, the display panel 100 includes a driving substrate 20, a chip array 30, and a first electrical connection portion 40. In a direction perpendicular to the plane where the driving substrate 20 is located, the driving substrate 20 is located on a side of the chip array 30 away from the first electrical connection portion 40. The first electrical connection portion 40 is used to connect to a first electrode 32 of a light-emitting element 34 in the chip array 30. The driving substrate 20 includes a substrate 10, a transistor 21, a second electrical connection portion 50, a power supply signal line 82, and an auxiliary signal line 92. Among them, the substrate 10 is located on a side of the transistor 21 away from the chip array 30, the auxiliary signal line 92 is located on a side of the transistor 21 away from the substrate 10, and the second electrical connection portion 50 and the power supply signal line 82 are located on a side of the auxiliary signal line 92 away from the transistor 21. The second electrical connection portion 50 and the power supply signal line 82 are provided on the same layer, and the auxiliary signal line 92 and the power supply signal line 82 are provided on different layers and are connected through vias. Optionally, the power supply signal line 82 and the second electrical connection portion 50 are located in the M4 metal layer, and the auxiliary signal line 92 is located in the M3 metal layer.

[0055] It can be understood that Figure 7 and Figure 9 in the M3 metal layer in is generally made of Mo / Al / Mo or Ti / Al / Ti, and is mainly used to form a PVDD mesh anode trace; the M4 metal layer can usually be made of Mo / Al / Mo or Ti / Al / Ti in the same way as the M3 metal layer. In this embodiment, the second electrical connection portion 50 in the M4 metal layer can be used as an arrayed anode structure connected to the first electrode 32 of the light-emitting element 34 in the chip array 30, and the power supply signal line 82 in the M4 metal layer can be used as a whole-surface PVDD trace; among them, the power supply signal line 82 in the M4 metal layer carrying the PVDD signal can be short-circuited with the auxiliary signal line 92 in the M3 metal layer below carrying the PVDD, that is, a double-layer PVDD trace is formed to reduce impedance and improve product uniformity.

[0056] In this way, by providing the auxiliary signal line 92 in the driving substrate 20 and connecting the power supply signal line 82 and the auxiliary signal line 92 through vias, the short circuit between the power supply signal line 82 and the auxiliary signal line 92 can be realized, and a double-layer PVDD structure is formed to reduce the voltage drop of the display panel 100.

[0057] Figure 10 An embodiment without forming a double-layer PVDD structure is also provided. Please refer to Figure 10 , the second electrical connection portion 50 and the power supply signal line 82 are provided on the same layer. At this time, no auxiliary signal line is provided. Optionally, the second electrical connection 50 and the power supply signal line 82 can be located in the M3 metal layer, that is, the driving substrate 20 only includes the transistor 21 and the M3 metal layer and does not include the M4 metal layer, which can reduce the number of film layers and is beneficial to the thinning of the display panel 100.

[0058] Figure 11 The following is a schematic connection diagram of a self - capacitance touch structure in a display panel provided by an embodiment of the present disclosure. Please refer to Figure 8 , Figure 9 and Figure 11 . The touch layer 60 is a self - capacitance or mutual - capacitance structure.

[0059] Specifically, in an alternative embodiment provided by the present disclosure, please refer to Figure 9 . When the touch layer 60 does not include the first electrical connection portion 40, the first electrical connection portion 40 and the touch layer 60 are located on different layers. At this time, the touch layer 60 can be set as a self - capacitance structure or a mutual - capacitance structure. Please refer to Figure 8 . When the touch layer 60 is a mutual - capacitance touch layer 60, the touch layer 60 includes a first electrode layer 61 and a second electrode layer 62. Among them, the second electrode layer 62 includes touch electrode units 620. The touch electrode units 620 include touch electrodes arranged along the first direction D1 and sensing electrodes arranged along the second direction D2, or the second electrode layer 62 includes touch electrodes arranged along the first direction D1 and sensing electrodes arranged along the second direction D2. The present disclosure does not specifically limit the arrangement manner of the touch electrodes and the sensing electrodes. The first electrode layer 61 includes electrode connection portions 63. That is to say, the mutual - capacitance touch layer 60 can respectively set touch electrodes and sensing electrodes in different directions on the second electrode layer 62, and the arrangement directions of the touch electrodes and the sensing electrodes intersect. Adjacent touch electrodes can be connected through the electrode connection portions 63 in the first electrode layer 61, and adjacent sensing electrodes are connected through the wires 623 in the second electrode layer 62, or adjacent sensing electrodes can be connected through the electrode connection portions 63 in the first electrode layer 61, and adjacent touch electrodes are connected through the wires 623 in the second electrode layer 62. The present disclosure does not specifically limit the connection manner of the touch electrodes and the sensing electrodes. Since the wires 623 of the second electrode layer 62 and the electrode connection portions 63 in the first electrode layer 61 are located on different layers, in the direction perpendicular to the plane where the driving substrate 20 is located, a capacitance node is formed at the intersection of the wires 623 and the electrode connection portions 63; when current flows through the wires 623 in the second electrode layer 62, if there is a signal of capacitance change in the external environment, it will cause a change in the capacitance node in the electrode connection portions 63 on the first electrode layer 61, and touch positioning can be performed according to the measured sensing signal.

[0060] Please refer to Figure 9 and Figure 11, when the touch control layer 60 is a self-capacitance touch control layer 60, the touch control layer 60 includes a first electrode layer 61 and a second electrode layer 62. Among them, the first electrode layer 61 includes a plurality of self-capacitance touch control electrodes 68 arranged in an array, and the plurality of self-capacitance touch control electrodes 68 are insulated from each other. The second electrode layer 62 includes a plurality of touch leads 66, and the touch leads 66 are connected to a touch control chip 65. The touch control chip 65 is configured to send or receive touch signals to / from the self-capacitance touch control electrodes 68 through the touch leads 66. The self-capacitance touch control electrodes 68 of the first electrode layer 61 and the touch leads 66 of the second electrode layer 62 are arranged and connected in one-to-one correspondence, and the position of the contact point 67 can be confirmed by monitoring the capacitance change between the self-capacitance touch control electrode 68 and the ground.

[0061] In this way, when the first electrical connection part 40 and the touch control layer 60 are arranged in a layered manner, the touch control layer 60 can be freely designed into a mutual-capacitance or self-capacitance structure, which is beneficial to increasing the diversity of the structure of the display panel 100.

[0062] Figure 12 The following is a schematic diagram of a display device provided by an embodiment of the present disclosure. Please refer to Figure 12 , the present disclosure provides a display device 200, including the display panel 100 as described above. The display device 200 provided by the embodiment of the present disclosure may be any electronic device with a display function such as a touch display screen, a mobile phone, a tablet computer, a notebook computer, an e-reader or a television. The display device 200 provided by the embodiment of the present disclosure has the beneficial effects of the display panel 100 provided by the embodiment of the present disclosure. For specific descriptions of the display panel 100, reference may be made to the above embodiments, and details are not described herein again.

[0063] It can be understood that Figure 12 only the shape of the display device 200 is schematically shown by taking a rounded rectangle structure as an example. In some other embodiments of the present disclosure, the display device 200 may also be embodied as a circular shape, an oval shape or any other feasible shape, and the present disclosure does not specifically limit this.

[0064] In summary, a display panel and a display device provided by the present disclosure can realize the bonding of vertical LED chips by arranging a first electrical connection part and a second electrical connection part located on a driving substrate in the display panel, reduce the use of bonding gold wires in the prior art, and lower the production cost. By arranging the first electrical connection part in a whole-surface grid-like structure, the bonding of the first electrical connection part with multiple light-emitting elements can be realized at one time in the actual manufacturing process, which is beneficial to reducing the process steps, especially greatly reducing the process complexity in a high pixel density display panel and improving the production efficiency. By arranging the first electrical connection part in the touch control layer, without additionally arranging a film layer, the touch control layer can not only realize the touch control function but also realize the connection with the first electrode of the light-emitting element, which is beneficial to the thinning of the display panel. By arranging the first electrical connection part in the first electrode layer of the touch control layer closer to the chip array, it is beneficial to the connection between the first electrical connection part and the first electrode in the light-emitting element, reduce the film layer penetration, and simplify the process steps. By arranging mutually insulated first electrical connection parts and electrode connection parts in the first electrode layer, the touch control function of the first electrode layer in the touch control layer and the function of the common cathode connected to the chip array can be realized simultaneously without additionally arranging a film layer. In the process manufacturing, when etching the electrode connection part and the first electrical connection part located on the same layer, the minimum distance between the two is greater than 3 μm, which is beneficial to ensuring that the electrode connection part and the first electrical connection part located on the same layer are separated into two independent parts after etching, reducing the process loss and improving the product yield. The minimum width of the first electrical connection part is greater than the maximum width of the electrode connection part. In this way, the electrode connection part can be arranged in the hollow of the first electrical connection part, saving the layout space and being beneficial to the miniaturization of the display panel.

[0065] By arranging the first electrical connection part independently of the touch control layer, the influence of the existence of the whole-surface common cathode on the touch control characteristics can be reduced, and the diversity of the touch control forms can be increased. By encapsulating the light-emitting element with an encapsulation layer and arranging an opening in the encapsulation layer, it is convenient for the connection between the first electrical connection part and the first electrode in the light-emitting element, and the first electrical connection part can realize the batch bonding with multiple light-emitting elements in the chip array through multiple different openings, simplifying the process and improving the production efficiency. By designing the second electrical connection part on the same layer as the power signal line, the film layer space can be effectively utilized, the number of film layers of the display panel can be reduced, and it is beneficial to the thinning of the display panel. By arranging an auxiliary signal line in the driving substrate and connecting the power signal line and the auxiliary signal line through a via hole, the parallel connection of the power signal line and the auxiliary signal line can be realized, forming a double-layer PVDD structure to reduce the voltage drop of the display panel. When the first electrical connection part and the touch control layer are arranged in layers, the touch control layer can be freely designed into a mutual capacitance or self-capacitance structure, which is beneficial to increasing the diversity of the display panel structure.

[0066] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: A driving substrate, a chip array, and a first electrical connection portion; the chip array is located between the driving substrate and the first electrical connection portion, and the driving substrate includes a second electrical connection portion; The chip array includes a plurality of light-emitting elements, each of which includes a first electrode and a second electrode. The first electrode is located on a side of the light-emitting element away from the driving substrate and is electrically connected to the first electrical connection portion. The second electrode is located on a side of the light-emitting element facing the driving substrate and is electrically connected to the second electrical connection portion.

2. The display panel according to claim 1, wherein: The first electrical connection portion is in a grid shape.

3. The display panel according to claim 2, wherein: The display panel includes a touch layer located on a side of the chip array away from the driving substrate, and the first electrical connection portion is located on the touch layer.

4. The display panel according to claim 3, wherein: The touch control layer includes a first electrode layer and a second electrode layer. The first electrode layer is located on a side of the second electrode layer facing the chip array. The first electrical connection portion is located on the first electrode layer.

5. The display panel according to claim 4, wherein: A touch electrode unit is disposed on the second electrode layer, and an electrode connecting portion for connecting the touch electrode unit is disposed on the first electrode layer. The electrode connecting portion is in the same layer as the first electrical connecting portion and is insulated.

6. The display panel according to claim 5, wherein: The first electrical connection portion includes a hollow, and the electrode connection portion is located in the hollow; Along a direction parallel to the plane where the drive substrate is located, a minimum spacing between the electrode connecting portion and the first electrical connecting portion is greater than 3 μm, and a minimum width of the first electrical connecting portion is greater than a maximum width of the electrode connecting portion.

7. The display panel according to claim 1, wherein: The display panel includes a touch layer located on a side of the chip array away from the drive substrate, and the first electrical connection portion is located between the touch layer and the chip array.

8. The display panel according to claim 1, wherein: The display panel includes an encapsulation layer, the encapsulation layer is used to encapsulate the light emitting element, the encapsulation layer has an opening on a side away from the driving substrate, the opening exposes the first electrode, and at least a part of the first electrical connection portion is located in the opening.

9. The display panel according to claim 1, wherein: The driving substrate further includes a power signal line, and the second electrical connection portion is arranged on the same layer as the power signal line; The driving substrate includes a substrate and a transistor, and the power signal line and the second electrical connection portion are located on a side of the transistor away from the substrate.

10. The display panel according to claim 9, wherein: The driving substrate includes an auxiliary signal line, the auxiliary signal line is located between the transistor and the power signal line, and the auxiliary signal line is electrically connected to the power signal line.

11. The display panel according to claim 7, wherein: The touch control layer is a self-capacitive or mutual-capacitive structure.

12. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-11.

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