Photoelectric sensing substrate and photoelectric sensing device

Abstract

The invention provides a photoelectric sensing substrate and a photoelectric sensing device, is applied to the technical field of photoelectric devices, and aims to reduce the resistance and capacitance load of the photoelectric sensing substrate, and the photoelectric sensing substrate comprises a substrate which comprises a display area and a non-display area surrounding part or all of the edge of the display area; the pixel electrode is located in the display area; the first conductive layer and the pixel electrode are arranged on the same layer; the first electrode is located on the side, away from the substrate, of the pixel electrode, and the first electrode is connected with the pixel electrode; the organic semiconductor material layer is located on the side, away from the substrate, of the first electrode; the second electrode is located on the side, away from the substrate, of the organic semiconductor material layer, and the orthographic projection of the second electrode on the substrate is overlapped with the display area and the non-display area; the second conducting layer is located on the side, away from the substrate, of the second electrode, the orthographic projection of the second conducting layer on the substrate is located in the non-display area, and the orthographic projection of the second conducting layer on the substrate is overlapped with the orthographic projection of the first conducting layer and the orthographic projection of the second electrode on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the technical field of optoelectronic devices, and particularly to a photoinductive substrate and a photoinductive device. Background Art

[0002] Currently, in conventional photoinductive devices, an organic photodiode generally includes a p-type semiconductor layer, an intrinsic layer, and an n-type semiconductor layer. The p-type semiconductor layer and the n-type semiconductor layer are connected to signal lines to control the state of the organic photodiode. However, in current photoinductive devices, the organic photodiode has problems of easy film peeling and load delay. Summary of the Invention

[0003] Based on the content of the background art, the present disclosure provides a photoinductive substrate and a preparation method thereof.

[0004] In the first aspect of the present disclosure, a photoinductive substrate is provided, including:

[0005] A substrate, the substrate including a display area and a non-display area surrounding part or all of the edges of the display area;

[0006] A pixel electrode, located in the display area;

[0007] A first conductive layer, located in the non-display area and arranged on the same layer as the pixel electrode;

[0008] A first electrode, located on the side of the pixel electrode away from the substrate, the first electrode being connected to the pixel electrode;

[0009] An organic semiconductor material layer, located on the side of the first electrode away from the substrate;

[0010] A second electrode, located on the side of the organic semiconductor material layer away from the substrate, and the orthographic projection of the second electrode on the substrate overlaps with the display area and the non-display area;

[0011] A second conductive layer, located on the side of the second electrode away from the substrate, the orthographic projection of the second conductive layer on the substrate is located in the non-display area and overlaps with the orthographic projections of the first conductive layer and the second electrode on the substrate;

[0012] Wherein, the second conductive layer is respectively connected to the second electrode and the first conductive layer.

[0013] Optionally, the display area is a polygon, the non-display area is a frame structure surrounding the polygon, and the second conductive layer is distributed in at least two adjacent borders of the non-display area.

[0014] Optionally, the positive projection of the second conductive layer on the substrate is in an inverted U shape or an inverted L shape.

[0015] Optionally, the display area is polygonal, the non-display area encloses the display area, and includes two relatively arranged first areas and two relatively arranged second areas. The photoinductive substrate further includes a fan-out structure and a gate driving circuit on one side of the substrate; the fan-out structure is located in at least one of the first areas, and the gate driving circuit is located in the second area;

[0016] Wherein, the first conductive layer is located in the first area, or in at least one of the second areas.

[0017] Optionally, the first conductive layer is located in the second area, and the positive projection of the gate driving circuit on the substrate is located within the positive projection of the first conductive layer on the substrate.

[0018] Optionally, the distance between the edge of the positive projection of the gate driving circuit on the substrate and the edge of the positive projection of the first conductive layer on the substrate is 5-200 μm.

[0019] Optionally, the first conductive layer is located in the first area, and the first conductive layer and the fan-out structure are respectively located in two of the first areas,

[0020] Or, both of the two first areas include the fan-out structure, and the positive projection of the first conductive layer on the substrate is located between the positive projections of the two fan-out structures on the substrate.

[0021] Optionally, the positive projection of the gate driving circuit on the substrate does not overlap with the positive projection of the second conductive layer on the substrate.

[0022] Optionally, the positive projection of the second conductive layer on the substrate is located between the positive projections of multiple fan-out structures on the substrate.

[0023] Optionally, in one of the first areas, the distance between the positive projection of the second conductive layer on the substrate and the positive projection of the fan-out structure on the substrate is greater than the distance between the positive projection of the second conductive layer on the substrate and the positive projection of the display area on the substrate.

[0024] Optionally, the distance between the edge of the positive projection of the second conductive layer on the substrate and the edge of the positive projection of the second electrode on the substrate is 5-300 μm.

[0025] In a second aspect of the present disclosure, there is provided a photoinductive device, including: the photoinductive substrate as described in the first aspect above.

[0026] The photoinductive substrate provided by the present disclosure includes: a substrate, the substrate including a display area and a non-display area surrounding part or all of the edges of the display area; a pixel electrode located in the display area; a first conductive layer located in the non-display area and arranged on the same layer as the pixel electrode; a first electrode located on a side of the pixel electrode facing away from the substrate, the first electrode being connected to the pixel electrode; an organic semiconductor material layer located on a side of the first electrode facing away from the substrate; a second electrode located on a side of the organic semiconductor material layer facing away from the substrate, a positive projection of the second electrode on the substrate overlapping with the display area and the non-display area; a second conductive layer located on a side of the second electrode facing away from the substrate, a positive projection of the second conductive layer on the substrate being located in the non-display area and overlapping with positive projections of the first conductive layer and the second electrode on the substrate; wherein the second conductive layer is respectively connected to the second electrode and the first conductive layer;

[0027] Thus, in the present disclosure, by arranging the second conductive layer in the non-display area and connecting the second conductive layer to the second electrode in the non-display area, the second conductive layer does not need to cover the display area of the photoinductive substrate, reducing the area of the second conductive layer, thereby reducing the resistance-capacitance load of the organic photodiode.

[0028] The above description is only an overview of the technical solution of the present disclosure. In order to be able to understand the technical means of the present disclosure more clearly, it can be implemented according to the content of the specification. And in order to make the above and other objects, features and advantages of the present disclosure more obvious and understandable, the following specifically gives the specific embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. It should be noted that the ratios in the drawings are only for illustration and do not represent the actual ratios.

[0030] Figure 1 The top view of the photoinductive substrate provided in the first example of the present disclosure is shown;

[0031] Figure 2A Shown is Figure 1 The cross-sectional view of the photoinductive substrate shown along A-A';

[0032] Figure 2B shows Figure 1 A sectional view taken along B-B' of the photoelectric induction substrate shown;

[0033] Figure 3 shows a top view of the photoelectric induction substrate provided in Example 3 of the present disclosure;

[0034] Figure 4 shows a top view of the photoelectric induction substrate provided in Example 4 of the present disclosure;

[0035] Figure 5 shows a top view of the photoelectric induction substrate provided in Example 5 of the present disclosure;

[0036] Figure 6 shows a top view of the photoelectric induction substrate provided in Example 6 of the present disclosure;

[0037] Figure 7 shows a top view of the photoelectric induction substrate provided in Example 2 of the present disclosure;

[0038] Figure 8 shows Figure 7 An enlarged view of the S area in. Detailed implementation manners

[0039] To make the above objects, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0040] Biometric technologies have been widely penetrated into all aspects of social life, such as 3D face recognition, fingerprint recognition, etc. These biometric technologies that utilize the shapes and features of the human body surface have potential risks such as being vulnerable to the environment, loss of media, being replicated, and data source security. The working principle of vein recognition is as follows: Light is difficult to penetrate the human body, and only infrared light within a specific wavelength range can penetrate most human tissues. However, since hemoglobin flowing through veins can fully absorb infrared light, vein images can be obtained using this characteristic. The entire recognition process includes three parts: image acquisition, image processing, and image recognition.

[0041] Vein recognition technology uses the vein characteristics inside the human body for recognition, which has uniqueness and is difficult to steal, and has the characteristics of high precision, high speed, and high anti-counterfeiting. The internal information of the human body is not affected by the roughness of the epidermis and the external environment (temperature and humidity); the internal living body information is difficult to copy and steal; the usage habit is similar to fingerprint recognition, users accept it quickly, and the publicity and learning cost is low; therefore, it has the highest security level. The current vein recognition technologies mainly include finger vein recognition and palm vein recognition. These two recognition technologies are different from the common fingerprint recognition technology, and their usual collection area is less than 1 centimeter; on the contrary, the finger vein recognition technology requires a collection area of more than 3*1 centimeters, while the palm vein requires a larger collection area to obtain effective feature information such as patterns and textures.

[0042] The light source corresponding to the vein recognition technology is a near-infrared light source, and OPD (Organic Photo Diode) materials have good EQE performance in the near-infrared band. In addition, the current demand for near-infrared sensors in the fields of automotive, industrial sensing, security, etc. is particularly urgent. Although silicon-based sensors still have light response in the near-infrared band, CIS (Contact Image Sensor) generally has a small size and it is difficult to achieve 1:1 imaging. After adding a lens to focus the image information, the thickness of the entire module is relatively thick, which affects the development of silicon-based CIS in the direction of ultra-thin, flexible, and better terminal compatibility.

[0043] In related technologies, the preparation scheme of OPD sensors mainly uses small-piece processes, which have problems such as poor device performance, low device reliability, easy failure, and low yield. This problem stems from the fact that the HIL (Hole Inject Layer) line acting as a wire in the OPD device is coated over the entire surface, or there is only one electrode layer of the HIL electrode, resulting in problems such as easy peeling of the film layer and too large RC loading.

[0044] In view of this, the present disclosure proposes a photoinductive substrate, by restricting the HIL line to the non-display area, so that the HIL line does not need to be coated over the entire surface, reducing the resistance and thus solving the signal delay problem caused by a large load.

[0045] Refer to Figure 1 - Figure 2, Figure 1 which shows a top view of the photoinductive substrate provided by an embodiment of the present disclosure, Figure 2A shows Figure 1 a cross-sectional view of the photoinductive substrate shown along A-A', Figure 2B shows Figure 1 a cross-sectional view of the photoinductive substrate shown along B-B', as Figure 1 shown in -2, the photoinductive substrate specifically includes:

[0046] A substrate 100, comprising a display area 101 and a non-display area 102 surrounding part or all of the edges of the display area 101;

[0047] A pixel electrode 110, located in the display area 101;

[0048] A first conductive layer 120, located in the non-display area 102 and disposed on the same layer as the pixel electrode 110;

[0049] A first electrode 130, located on the side of the pixel electrode 110 facing away from the substrate 100, and the first electrode 130 is connected to the pixel electrode 110;

[0050] An organic semiconductor material layer 140, located on the side of the first electrode 130 facing away from the substrate 100;

[0051] A second electrode 150, located on the side of the organic semiconductor material layer 140 facing away from the substrate 100, and the orthographic projection of the second electrode 150 on the substrate 100 overlaps with the display area 101 and the non-display area 102;

[0052] A second conductive layer 160, located on the side of the second electrode 150 facing away from the substrate 100, and the orthographic projection of the second conductive layer 160 on the substrate 100 is located in the non-display area 102 and overlaps with the orthographic projections of the first conductive layer 120 and the second electrode 150 on the substrate 100;

[0053] Wherein, the second conductive layer 160 is respectively connected to the second electrode 150 and the first conductive layer 120.

[0054] In this embodiment, the substrate 100 may be a rigid glass substrate or a flexible substrate with a rigid glass carrier; the display area 101 of the substrate 100 includes a plurality of pixels, and each pixel includes a pixel electrode 110, and the pixel electrode 110 is connected to the first electrode 130 of the organic photodiode. In this way, when the organic photodiode generates an electrical signal in response to a light signal, the electrical signal can be transmitted to the pixel electrode, causing the corresponding pixel to emit light, thereby displaying an image in the display area 101.

[0055] The first conductive layer 120 can be a metal material, a transparent conductive material, a semiconductor material, etc. It serves as a conductive platform to connect with the chip traces. At the same time, the first conductive layer 120 is also connected to the second electrode 150 of the organic optoelectronic diode. In this way, the signal output by the chip can be transmitted to the second electrode 160 through the first conductive layer 120 and the second conductive layer 160, enabling the chip to control the voltage of the second electrode 160 and thus control the state of the organic optoelectronic diode. Among them, the first conductive layer 160 can be located on either side of the non-display area 102 as long as it can be connected to the second conductive layer 160.

[0056] In one example, the photoinductive substrate may further include a gate driving circuit to drive the pixels. To avoid mutual influence between the signals of the gate driving circuit and the control signals of the chip, the first conductive layer 120 can be disposed between the gate driving circuit and the second conductive layer 160. At this time, the first conductive layer 120 can act as a shielding material to avoid signal interference between the two. Among them, when the first conductive layer 120 is located between the gate driving circuit and the second conductive layer 160, the orthographic projection of the first conductive layer 120 on the substrate 100 can completely cover the orthographic projection of the gate driving circuit on the substrate 100. In this way, the signal interference between the gate driving circuit and the second conductive layer 160 can be shielded to the greatest extent.

[0057] Among them, the organic optoelectronic diode specifically includes a first electrode 130, an organic semiconductor material layer 140, and a second electrode 150. When the organic optoelectronic diode receives a light signal, the organic semiconductor material layer 140 absorbs the light to generate carriers, which are dissociated into free charges and transmitted to the electrodes, thereby generating a current and an electrical signal. Among them, the first electrode 130 is formed of an n-type semiconductor; the organic semiconductor material layer 140 is formed of an intrinsic semiconductor material; the second electrode 160 is formed of a p-type semiconductor.

[0058] The second conductive layer 160 can be a metal material, such as copper, aluminum, molybdenum, etc., or a transparent conductive material, such as ITO (Indium tin oxide). The second conductive layer 160 is located in the non-display area 102 without covering the display area 101. In this way, the orthographic projection area of the second conductive layer 160 on the substrate 100 can be reduced, thereby reducing the resistance of the second conductive layer 160 and avoiding signal delay.

[0059] The orthographic projection of the second conductive layer 160 on the substrate 100 can partially surround the orthographic projection of the second electrode 150 on the substrate 100, so that the second conductive layer 160 can be connected to the second electrode 150 in the non-display area 102; moreover, the orthographic projection of the second conductive layer 160 on the substrate 100 can partially overlap with the orthographic projection of the first conductive layer 120 on the substrate 100 to achieve the connection between the second conductive layer 160 and the first conductive layer 120; it can also be that the orthographic projection of the first conductive layer 120 on the substrate 100 is located within the orthographic projection of the second conductive layer 160 on the substrate 100 to ensure an effective electrical connection between the first conductive layer 120 and the second conductive layer 160. Among them, considering that the non-display area 102 also includes a fan-out structure, the second conductive layer 160 can be arranged away from the fan-out structure. For example, if the non-display area 102 is a frame structure and the fan-out structure is located on one of the side frames of the frame structure, then the orthographic projection of the second conductive layer 160 on the substrate 100 does not overlap with the orthographic projection of the side frame on the substrate 100. And if the fan-out structure is arranged on multiple side frames and it is difficult for the second conductive layer 160 to avoid the fan-out structure, it can be arranged to avoid the fan-out structure, such as arranging the second conductive layer 160 between multiple fan-out structures.

[0060] In this embodiment, in the photoinductive substrate, the first electrode 130, the organic semiconductor material layer 140, and the second electrode 140 can be prepared in the following specific ways: Coating an electron transport material on the substrate 100 including the pixel electrode 110 and the first conductive layer 120 to form the first electrode 130; then coating an organic semiconductor material on the first electrode 130 to form the organic semiconductor material layer 140; after that, coating a hole injection material on the organic semiconductor material layer 140 to form the second electrode 150; after forming the second electrode 150, etching the first electrode 130, the organic semiconductor material layer 140, and the second electrode 150 in the same etching process. Among them, after the etching is completed, the second conductive layer 160 can be formed by using a mask plate. In this way, the second conductive layer 160 does not need to be coated on the entire surface, reducing the orthographic projection area of the second conductive layer 160 on the substrate 100, thereby reducing its resistance.

[0061] Among them, the film-forming process of the first electrode 130, the organic semiconductor material layer 140, and the second electrode 150 can be spin coating by a spin coater or slit coating; the film-forming of the second conductive layer 160 can be spin coating by a spin coater, slit coating, evaporation, or sputter deposition; among them, the evaporation process itself includes a mask patterning process.

[0062] The photoinductive substrate provided by an embodiment of the present disclosure includes a substrate 100, a pixel electrode 110, a first conductive layer 120, a first electrode 130, an organic semiconductor material layer 140, a second electrode 150, and a second conductive layer 160. Among them, the orthographic projection of the second conductive layer 160 on the substrate 100 is located in the non-display area 102. Thus, the area occupied by the second conductive layer 160 is smaller than the case of coating the entire surface of the second electrode 150, reducing the resistance-capacitance load and avoiding the problem of signal delay.

[0063] In one embodiment, referring to Figure 1 or Figure 3 , Figure 3 shows a top view of the photoinductive substrate provided by another embodiment of the present disclosure. The display area 101 is a polygon, and the non-display area 102 is a frame-shaped structure enclosing the polygon. The second conductive layer 160 is distributed in at least two adjacent side frames of the non-display area 102.

[0064] In this embodiment, the shape of the display area 101 can be designed according to product requirements. Specifically, it can be a triangle, a quadrilateral, a pentagon, etc. Then, the non-display area 102 can be a frame-shaped structure enclosing a triangle, a frame-shaped structure enclosing a quadrilateral, or a frame-shaped structure enclosing a pentagon. Taking Figure 1 as an example, the display area 101 is a quadrilateral, and the non-display area 102 is a frame-shaped structure enclosing a quadrilateral, that is, a "square" shape composed of four side frames.

[0065] Among them, the second conductive layer 160 can be located in at least two adjacent side frames of the non-display area 102. In this way, the second electrode 150 can be electrically connected to the first conductive layer 120 through the second conductive layer 160, so that multiple photoinductive units distributed in the display area 101 can all be controlled by the chip. Specifically, when the display area 101 is a triangle, the second conductive layer 160 can be located in two of the side frames of the frame-shaped structure enclosing the triangle; when the display area 101 is a quadrilateral, the second conductive layer 160 can be located in two adjacent side frames of the frame-shaped structure enclosing the quadrilateral, or can be located in three adjacent side frames of the frame-shaped structure; when the display area 101 is a pentagon, the second conductive layer 160 can be located in two adjacent side frames of the frame-shaped structure enclosing the pentagon, or can be located in three adjacent side frames in sequence, etc. Taking Figure 1 as an example, when the display area 101 is a quadrilateral, the non-display area 102 is a frame-shaped structure enclosing a quadrilateral, and the second conductive layer 160 is located in three adjacent side frames.

[0066] In one embodiment, continuing to refer to Figure 1 or Figure 3 , the orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted U shape or an inverted L shape.

[0067] In this embodiment, the first conductive layer 160 is located in the frame structure surrounded by the non-display area 102. The first conductive layer 120 can be located on one side of the frame structure or on both sides of the frame structure. Among them, the shape of the orthographic projection of the second conductive layer 160 on the substrate 100 can be determined according to the distribution of the first conductive layer 120.

[0068] Specifically, if the first conductive layer 120 is located on one side of the frame structure of the non-display area 102, taking Figure 3 as an example, the orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted L shape. In the two mutually perpendicular parts of the inverted L shape, one part is connected to the first conductive layer 120, and the other part is connected to the second electrode 150, so that the second conductive layer 160 can be connected to both the first conductive layer 120 and the second electrode 150. If the first conductive layer 120 is located on both sides of the frame structure of the non-display area 102, taking Figure 1 as an example, the orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted U shape. At this time, both sides of the U shape in the inverted U shape are connected to the first conductive layer 120, and the remaining part is connected to the second electrode 150. Thus, the second conductive layer 160 is connected to both the first conductive layer 120 and the second electrode 150.

[0069] In one embodiment, referring to Figures 3 - 7 , among which, Figures 3 - 7 respectively show the top views of the photoinductive substrate in different positions of the first conductive layer 120. As shown in Figures 3 - 7 , the display area 101 is a polygon, the non-display area 102 encloses the display area 101 and includes two relatively arranged first regions 1021 and two relatively arranged second regions 1022. The photoinductive substrate further includes a fan-out structure 200 and a gate driving circuit 300 located on one side of the substrate; the fan-out structure 200 is located in at least one first region 1021, and the gate driving circuit 300 is located in the second region 1022;

[0070] Among them, the first conductive layer 120 is located in the first region 1021 or in at least one second region 1022.

[0071] Specifically, the non-display area 102 is a frame structure. The two first regions 1021 are two relatively arranged side frames respectively, and the two second regions 1022 are the remaining two relatively arranged side frames. The photoinductive substrate further includes a fan-out structure 200 and a gate driving circuit 300 so that the chips packaged on the photoinductive substrate can drive the pixels in the display area 101 of the photoinductive substrate. Among them, the fan-out structure 200 can be located in one of the two first regions 1021, or both regions include the fan-out structure 200; the gate driving circuit 300 can be located in the two second regions 1022. Taking Figure 3For example, the gate driving circuit 300 is located in two second regions 1022 (one side of which is blocked by the first conductive layer 120 and not shown). The first conductive layer 120 is located in the second region 1022. Then it can be located in one of the two second regions 1022, or both of the two second regions 1022 may include the first conductive layer 120. Taking Figure 5 or Figure 6 For example, the fan-out structure 200 can be located in one first region 1021 or in two first regions 1021. When the fan-out structure 200 is located in one first region 1021, the first conductive layer 120 can be disposed opposite to the fan-out structure 200. When the fan-out structure 200 is located in two first regions 1021, the orthographic projection of the first conductive layer 120 on the substrate 100 does not overlap with the orthographic projection of the fan-out structure 200 on the substrate 100.

[0072] In the present disclosure, the first conductive layer 120 can be located in the first region 1021 or in the second region 1022. When the first conductive layer 120 is located in the first region 1021, the overlapping portion of the orthographic projection of the first conductive layer 120 on the substrate 100 and the orthographic projection of the second conductive layer 160 on the substrate 100 is located in the first region 1021; when the first conductive layer 120 is located in the second region 1022, the overlapping portion of the orthographic projection of the first conductive layer 120 on the substrate 100 and the orthographic projection of the second conductive layer 160 on the substrate is located in the second region 1022.

[0073] It can be understood that the fan-out structure 200 is included in the first region 1021. To avoid signal interference between the chip traces and the second conductive layer 160, the first conductive layer 120 can be arranged to avoid the fan-out structure 200, so that the second conductive layer 160 connected to the first conductive layer 120 also avoids the fan-out structure 200. Similarly, the gate driving circuit is included in the second region 1022. To avoid signal interference between the gate driving circuit 300 and the second conductive layer 160, the first conductive layer 120 can be disposed between the gate driving circuit 300 and the second conductive layer 160 to play a role in signal shielding.

[0074] In one example, referring to Figure 3 、 Figure 4 and Figure 7 , the first conductive layer 120 is located in the second region 1022, and the orthographic projection of the gate driving circuit 300 on the substrate 100 is located within the orthographic projection of the first conductive layer 120 on the substrate 100.

[0075] In this embodiment, the first conductive layer 120 can be located in one second region 1022 or in two second regions 1022; among them, taking Figure 3 or Figure 4For example, when the first conductive layer 120 is located in a second region 1022, the orthographic projection of the gate driving circuit 300 on the same side on the substrate 100 is located within the orthographic projection of the first conductive layer 120 on the substrate 100, and the gate driving circuit 300 on the other side does not overlap with the first conductive layer 120 and the second conductive layer 160; at this time, the orthographic projection of the second conductive layer 160 on the substrate 100 may be an inverted L shape, and the orthographic projection of the first conductive layer 120 on the substrate 100 is located within the second conductive layer 160, so that the second conductive layer 160 can be connected to both the first conductive layer 120 and the second electrode 150; taking Figure 7 For another example, when the first conductive layer 120 is located in two second regions 1022, the orthographic projections of the gate driving circuits 300 on both sides on the substrate 100 are both located within the orthographic projection of the first conductive layer 120 on the substrate 100. At this time, the orthographic projection of the second conductive layer 160 on the substrate 100 may be an inverted U shape, and the orthographic projection of the first conductive layer 120 on the substrate 100 is located within the second conductive layer 160, so that the second conductive layer 160 can be connected to both the first conductive layer 120 and the second electrode 150.

[0076] It can be understood that when the orthographic projection of the gate driving circuit 300 on the substrate 100 is located within the orthographic projection of the first conductive layer 120 on the substrate 100, the first conductive layer 120 can help the second conductive layer 160 shield the signal of the gate driving circuit 300, and can also help the gate driving circuit 300 shield the signal of the second conductive layer 160, reduce the signal influence between the two, and improve the signal-to-noise ratio.

[0077] Among them, taking Figure 4 For example, when both of the two first regions 1021 include the fan-out structure 200, the second conductive layer 160 needs to be arranged away from the fan-out structure 200 to avoid mutual influence between the second conductive layer 160 and the traces. Therefore, the part of the second conductive layer 160 located in the first region 1021 can be arranged away from the fan-out structure 200 on the same side, that is, in the first region 1021, the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the fan-out structure 200 on the substrate 100 is greater than the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the display area 102 on the substrate 100.

[0078] In an embodiment, referring to Figure 8 , Figure 8 shows Figure 7 an enlarged view of the S region in Figure 8 As shown, the distance between the edge of the orthographic projection of the gate driving circuit 300 on the substrate 100 and the edge of the orthographic projection of the first conductive layer 120 on the substrate 100 is 5 - 200 μm.

[0079] In this embodiment, taking Figure 8 as an example, the distance between the edge of the orthographic projection of the gate driving circuit 300 on the substrate 100 and the edge of the orthographic projection of the first conductive layer 120 on the substrate 100 is A, and the value of A is 5 - 200 μm. Specifically, the distance between the edge of the orthographic projection of the gate driving circuit 300 on the substrate 100 and the edge of the orthographic projection of the first conductive layer 120 on the substrate 100 can be 5 μm, 10 μm, 50 μm, 100 μm, 150 μm, 200 μm, etc. Within this range, the orthographic projection of the gate driving circuit 300 on the substrate 100 can be completely wrapped by the orthographic projection of the first conductive layer 120 on the substrate 100, and moreover, the area of the required non-display area 102 is avoided from being too large.

[0080] In another example, referring to Figures 5 - 6 , the first conductive layer 120 is located in the first region 1021, and the first conductive layer 120 and the fan-out structure 200 are respectively located in two first regions 1021.

[0081] Or, both of the two first regions 1021 include the fan-out structure 200, and the orthographic projection of the first conductive layer 120 on the substrate 100 is located between the orthographic projections of the two fan-out structures 200 on the substrate 100.

[0082] In this embodiment, the fan-out structure 200 can be located in one first region 1021 or in two first regions 1021. Among them, to avoid the routing of the fan-out structure 200, the position of the first conductive layer 120 can be determined according to the position of the fan-out structure 200, so as to determine the position of the second conductive layer 160, and avoid the orthographic projection of the fan-out structure 200 on the substrate 100 from overlapping with the orthographic projection of the second conductive layer 160 on the substrate 100.

[0083] Specifically, when including one fan-out structure 200, referring to Figure 5 , the first conductive layer 120 is located on the opposite side of the fan-out structure 200, that is, the fan-out structure 200 and the first conductive layer 120 are respectively located in two first regions. In this way, the first conductive layer 120 is arranged on the opposite side of the fan-out structure 200, and the two do not affect each other.

[0084] When including two fan-out structures 200, referring to Figure 6, two fan-out structures 200 are respectively located in two first regions 1021. At this time, the orthographic projection of the first conductive layer 120 on the substrate 100 is located between the two fan-out structures 200, and the first conductive layer 120 is located in the non-display area 102. In this case, since fan-out structures 200 are included on both sides, to minimize the influence between traces, the orthographic projection of the first conductive layer 120 on the substrate 100 can be arranged between the two fan-out structures 200. In this way, there is no mutual influence between the first conductive layer 120 and the fan-out structures 200 either.

[0085] In one embodiment, continue to refer to Figure 5 or Figure 6 , the orthographic projection of the gate driving circuit 300 on the substrate 100 and the orthographic projection of the second conductive layer 160 on the substrate 100 do not overlap.

[0086] In this embodiment, considering that both the gate driving circuit 200 and the second conductive layer 160 have signal transmissions, to reduce the influence between the signals of the two, the orthographic projection of the gate driving circuit 300 on the substrate 100 and the orthographic projection of the second conductive layer 160 on the substrate 100 can be made non-overlapping, thereby reducing the signal influence between the gate driving circuit 300 and the second conductive layer 160.

[0087] In one embodiment, the orthographic projection of the second conductive layer 160 on the substrate 100 is located between the orthographic projections of the two fan-out structures 200 on the substrate 100.

[0088] Specifically, when the orthographic projection of the first conductive layer 120 on the substrate 100 is located between the orthographic projections of the two fan-out structures 200 on the substrate 100, the orthographic projection of the second conductive layer 160 on the substrate 100 is also located between the orthographic projections of the two fan-out structures 200 on the substrate 100. And because the orthographic projection of the second conductive layer 160 on the substrate 100 overlaps with the orthographic projection of the first conductive layer 120 on the substrate 100, the second conductive layer 160 is connected to the first conductive layer 120, and the second conductive layer 160 avoids the traces of the fan-out structures 200, reducing the signal influence between the second conductive layer 160 and the fan-out structures 200.

[0089] In one embodiment, refer to Figure 7 , in one first region 1021, the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the fan-out structure 200 on the substrate 100 is greater than the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the display area 101 on the substrate 100.

[0090] In this embodiment, in the first region 1021 where the second conductive layer 160 is located, the orthographic projection of the second conductive layer 160 on the substrate 100 is close to one side edge of the orthographic projection of the fan-out structure 200 on the substrate 100. The distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the side edge of the orthographic projection of the fan-out structure 200 on the substrate 100 close to the orthographic projection of the second conductive layer 160 on the substrate 100 is greater than the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the side edge of the orthographic projection of the display area 101 on the substrate 100 close to the orthographic projection of the second conductive layer 160 on the substrate 100. In this way, the second conductive layer 160 is arranged away from the fan-out structure 200 to avoid the overlap of the traces between the two.

[0091] In one embodiment, with continued reference to Figure 8 , the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the second electrode 150 on the substrate 100 is 5 - 300 μm.

[0092] Specifically, the distance C between the edge of the orthographic projection of the second conductive layer 160 on the substrate and the edge of the orthographic projection of the second electrode 150 on the substrate 100 is between 5 - 300 μm, so that the second conductive layer 160 can be effectively electrically connected to the second electrode 150.

[0093] Among them, the distance between the edge of the orthographic projection of the second electrode 150 on the substrate 100 and the edge of the orthographic projection of the second electrode 150 on the substrate 100 can be 5 μm, 25 μm, 50 μm, 100 μm, 200 μm, 300 μm, etc. When the distance between the two is within this range, the second conductive layer 160 can be effectively electrically connected to the second electrode 150, and it is convenient for preparation.

[0094] In this embodiment, the orthographic projection of the second electrode 150 on the substrate 100 is located in the display area 101 and the non-display area 102, so that the overlapping part of the orthographic projection of the second electrode 150 on the substrate 100 and the orthographic projection of the second conductive layer 160 on the substrate 100 is located in the non-display area 102. Thus, the edge of the orthographic projection of the second electrode 150 on the substrate 100 extends beyond the display area 101, specifically, it can extend beyond the display area edge by 5 - 300 μm. For Figure 8 example, the distance between the edge of the orthographic projection of the second electrode 150 on the substrate 100 and the edge of the orthographic projection of the display area 101 on the substrate 100 is B, and B can be 5 μm, 20 μm, 60 μm, 100 μm, 220 μm, 300 μm, etc.

[0095] The photoinductive substrate provided in this embodiment reduces the positive projection area of the second conductive layer 160 on the substrate 100 by disposing the second conductive layer 160 in the non-display area 102 and connecting it to the first conductive layer 120 and the second electrode 150 in the non-display area 102, thereby reducing the resistance of the second conductive layer 160 and reducing the rc loading. Moreover, when the gate driving circuit 300 and the first conductive layer 120 are on the same side, the positive projection of the first conductive layer 120 on the substrate 100 completely covers the positive projection of the gate driving circuit 300 on the substrate 100. Since the first conductive layer 120 can achieve signal shielding, the signal interference between the gate driving circuit 300 and the second conductive layer 160 is reduced, and the signal-to-noise ratio is improved. When both the first conductive layer 120 and the fan-out structure 200 are located in the first area 1021, the first conductive layer 120 and the fan-out structure 200 are respectively located in two first areas 1021, or the first conductive layer 120 is located between two fan-out structures 200. In this way, the second conductive layer 160 connected to the first conductive layer 120 can avoid the traces of the fan-out structure 200, reducing signal interference.

[0096] Next, the photoinductive substrate provided in the embodiments of the present disclosure will be introduced in combination with specific examples and drawings:

[0097] Example 1: Refer to Figure 1-2, The optoelectronic induction substrate includes a substrate 100, a pixel electrode 110, a first conductive layer 120, a first electrode 130, an organic semiconductor material layer 140, a second electrode 150, and a second electrode 160. Among them, the first conductive layer 120 is located in two second regions 1022, and the orthographic projection of the gate driving circuit 300 (covered by the first conductive layer 120, not shown) is located within the orthographic projection of the first conductive layer 120 on the substrate 100. And the distance between the edge of the orthographic projection of the gate driving circuit 300 on the substrate 100 and the edge of the orthographic projection of the first conductive layer 120 on the substrate 100 is 20 μm. The orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted U shape. The orthographic projection of the first conductive layer 120 on the substrate 100 is located within the orthographic projection of the second conductive layer 160 on the substrate 100, and the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the first conductive layer 120 on the substrate 100 is 200 μm. The orthographic projection of the second electrode 150 on the substrate 100 is located in the display area 101 and the non-display area 102. The second conductive layer 160 is respectively connected to the first conductive layer 120 and the second electrode 150. Among them, the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the second electrode 150 on the substrate 100 is 200 μm. Among them, one of the first regions 1021 in the non-display area 102 includes a fan-out structure 200. The fan-out structure 200 and the second conductive layer 120 are located in different first regions 1021. In this example, the second conductive layer 160 is only located in the non-display area 102 and does not need to be coated on the second electrode 150 as a whole, thereby reducing the resistance of the second conductive layer 160 and further reducing the capacitive resistance load.

[0098] Example 2: Refer to Figure 7 , the first region 1021 includes two fan-out structures 200, and the rest is the same as in Example 1. In the first region 1021, the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the fan-out structure 200 on the substrate 100 is greater than the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the display area 101 on the substrate 100. In this way, the part of the second conductive layer 160 located in the first region 1021 can avoid the traces of the fan-out structure 200 and prevent mutual influence between the two.

[0099] Example 3: Refer to Figure 3, the photoinductive substrate includes a substrate 100, a pixel electrode 110, a first conductive layer 120, a first electrode 130, an organic semiconductor material layer 140, a second electrode 150, and a second electrode 160; wherein, the first conductive layer 120 is located in a second region 1022 of the non-display area 102. In this second region 1022, the orthographic projection of the gate driving circuit 300 on the substrate 100 is located within the orthographic projection of the first conductive layer 120 on the substrate 100, and the orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted L shape. In this example, the second conductive layer 160 is only located in the non-display area 102 and does not need to be coated on the second electrode 150 entirely, thereby reducing the resistance of the second conductive layer 160 and further reducing the capacitive resistance load; and, the part of the second conductive layer 160 located in the first region 1021 is disposed opposite to the fan-out structure 200. By disposing the second conductive layer 160 and the fan-out structure 200 opposite to each other in two first regions 1021, the mutual influence between the two can be avoided.

[0100] Example 4: Refer to Figure 4 , including two fan-out structures 200, and the rest is the same as in Example 3. The distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the fan-out structure 200 on the substrate 100 is greater than the distance between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the display area 101 on the substrate. In this way, the overlapping of the traces of the second conductive layer 160 and the fan-out structure 200 can be avoided as much as possible.

[0101] Example 5: Refer to Figure 5 , the photoinductive substrate includes a substrate 100, a pixel electrode 110, a first conductive layer 120, a first electrode 130, an organic semiconductor material layer 140, a second electrode 150, and a second electrode 160; wherein, the first conductive layer 120 and the fan-out structure 200 are respectively located in two first regions 1021, and the orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted L shape. At this time, there is no overlap between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the gate driving circuit 300 on the substrate 100. In this example, the second conductive layer 160 is only located in the non-display area 102 and does not need to be coated on the second electrode 150 entirely, thereby reducing the resistance of the second conductive layer 160 and further reducing the capacitive resistance load; and, since there is no overlap between the orthographic projection of the second conductive layer 160 on the substrate 100 and the orthographic projection of the gate driving circuit 300 on the substrate 100, the mutual influence between the signal transmitted by the second conductive layer 160 and the signal transmitted by the gate driving circuit can be avoided.

[0102] Example 6: Refer to Figure 6, including two fan-out structures 200, which are respectively located in two first regions 1021, and the rest is the same as in Example 5. Among them, the orthographic projection of the first conductive layer 120 on the substrate 100 is located between the two fan-out structures 200, and the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the fan-out structure 200 on the substrate 100 is greater than the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the display area 101 on the substrate 100. The orthographic projection of the second conductive layer 160 on the substrate 100 is in an inverted L shape. In this example, the second conductive layer 160 is only located in the non-display area 102 and does not need to be coated on the entire second electrode 150, thereby reducing the resistance of the second conductive layer 160 and further reducing the capacitive resistance load. Moreover, the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the fan-out structure 200 on the substrate 100 is greater than the distance between the edge of the orthographic projection of the second conductive layer 160 on the substrate 100 and the edge of the orthographic projection of the display area 101 on the substrate 100. In this way, the overlap between the second conductive layer 160 and the traces of the fan-out structure 200 can be avoided as much as possible.

[0103] Based on the same inventive concept, an embodiment of the present disclosure further provides a photoinductive device, including the photoinductive substrate provided in any of the above embodiments.

[0104] In this embodiment, the photoinductive device may be a fingerprint acquisition device, a palmprint acquisition device, a fingerprint recognition device, a palmprint recognition device, etc. For example, it may be a screen including fingerprint recognition.

[0105] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0106] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to this process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, commodity or device including the said element.

[0107] The above has provided a detailed introduction to an optoelectronic induction substrate and an optoelectronic induction device provided by the present disclosure. Specific examples are used herein to elaborate on the principle and implementation manner of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

[0108] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other embodiments of the present disclosure. The present disclosure aims to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include the common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0109] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

[0110] As used herein, the terms "one embodiment", "an embodiment", or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. In addition, please note that the examples of the phrase "in one embodiment" herein do not necessarily all refer to the same embodiment.

[0111] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0112] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices can be embodied by the same hardware item. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A photoelectric sensing substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a non-display area surrounding a portion or all of an edge of the display area; A pixel electrode, located in the display area; A first conductive layer is located in the non-display area and is disposed in the same layer as the pixel electrode; A first electrode, located at a side of the pixel electrode away from the base substrate, the first electrode being connected to the pixel electrode; An organic semiconductor material layer is located on a side of the first electrode facing away from the substrate; A second electrode is located on a side of the organic semiconductor material layer away from the base substrate, and an orthographic projection of the second electrode on the base substrate overlaps the display area and the non-display area; A second conductive layer is located on a side of the second electrode away from the base substrate, the orthographic projection of the second conductive layer on the base substrate is located in the non-display area, and overlaps with the orthographic projections of the first conductive layer and the second electrode on the base substrate; The second conductive layer is connected to the second electrode and the first conductive layer respectively.

2. The photoelectric sensing substrate according to claim 1, characterized in that: The display area is a polygon, the non-display area is a frame structure enclosing the polygon, and the second conductive layer is distributed in at least two adjacent frames of the non-display area.

3. The photoelectric sensing substrate according to claim 2, characterized in that: The orthographic projection of the second conductive layer on the base substrate is in an inverted U shape or an inverted L shape.

4. The photoelectric sensing substrate according to claim 1, characterized in that: The display area is a polygon, the non-display area encloses the display area and includes two first areas and two second areas that are oppositely arranged, and the photoelectric sensing substrate also includes a fan-out structure and a gate driving circuit located on one side of the base substrate; the fan-out structure is located in at least one of the first areas, and the gate driving circuit is located in the second area; Wherein, the first conductive layer is located in the first region, or in at least one of the second regions.

5. The photoelectric sensing substrate according to claim 4, characterized in that: The first conductive layer is located in the second region, and the orthographic projection of the gate driving circuit on the base substrate is located within the orthographic projection of the first conductive layer on the base substrate.

6. The photoelectric sensing substrate according to claim 5, characterized in that: The distance between the edge of the orthographic projection of the gate driving circuit on the base substrate and the edge of the orthographic projection of the first conductive layer on the base substrate is 5-200 μm.

7. The photoelectric sensing substrate according to claim 4, characterized in that: The first conductive layer is located in the first region, and the first conductive layer and the fan-out structure are located in two first regions respectively. Alternatively, both of the two first regions include the fan-out structure, and the orthographic projection of the first conductive layer on the substrate is located between the orthographic projections of the two fan-out structures on the substrate.

8. The photoelectric sensing substrate according to claim 7, characterized in that: The orthographic projection of the gate driving circuit on the base substrate has no overlap with the orthographic projection of the second conductive layer on the base substrate.

9. The photoelectric sensing substrate according to claim 4 or 7, characterized in that: The second conductive layer is located at an opposite side of the fan-out structure, or the orthographic projection of the second conductive layer on the substrate is located between orthographic projections of a plurality of the fan-out structures on the substrate.

10. The photoelectric sensing substrate according to claim 9, characterized in that: In one of the first regions, a distance between an orthographic projection of the second conductive layer on the base substrate and an orthographic projection of the fan-out structure on the base substrate is greater than a distance between an orthographic projection of the second conductive layer on the base substrate and an orthographic projection of the display area on the base substrate.

11. The photoelectric sensing substrate according to claim 1, characterized in that: The distance between the edge of the orthographic projection of the second conductive layer on the base substrate and the edge of the orthographic projection of the second electrode on the base substrate is 5-300 μm.

12. A photoelectric sensing device, characterized in that: It comprises the photoelectric sensing substrate as described in any one of claims 1-11.

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